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January 2015

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[U-Boot] [PATCH 18/22] ppc4xx: cleanup CPCI4052 board
by Matthias Fuchs 13 Jan '15

13 Jan '15

- remove some obsolete code - switch to generic board Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- board/esd/common/auto_update.c | 478 ------ board/esd/common/auto_update.h | 40 - board/esd/cpci405/Makefile | 2 +- board/esd/cpci405/cpci405.c | 276 +--- board/esd/cpci405/fpgadata_cpci405.c | 683 --------- board/esd/cpci405/fpgadata_cpci405ab.c | 2569 -------------------------------- include/configs/CPCI4052.h | 2 + 7 files changed, 4 insertions(+), 4046 deletions(-) delete mode 100644 board/esd/common/auto_update.c delete mode 100644 board/esd/common/auto_update.h delete mode 100644 board/esd/cpci405/fpgadata_cpci405.c delete mode 100644 board/esd/cpci405/fpgadata_cpci405ab.c diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c deleted file mode 100644 index f3f70ff..0000000 --- a/board/esd/common/auto_update.c +++ /dev/null @@ -1,478 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Gary Jennejohn, DENX Software Engineering, garyj(a)denx.de. - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#include <command.h> -#include <image.h> -#include <asm/byteorder.h> -#include <fat.h> -#include <flash.h> -#include <part.h> - -#include "auto_update.h" - -#ifdef CONFIG_AUTO_UPDATE - -#if !defined(CONFIG_CMD_FAT) -#error "must define CONFIG_CMD_FAT" -#endif - -extern au_image_t au_image[]; -extern int N_AU_IMAGES; - -/* where to load files into memory */ -#define LOAD_ADDR ((unsigned char *)0x100000) -#define MAX_LOADSZ 0x1c00000 - -/* externals */ -long do_fat_read (const char *filename, void *buffer, - unsigned long maxsize, int dols); - -extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE]; - -int au_check_cksum_valid(int i, long nbytes) -{ - image_header_t *hdr; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - if ((au_image[i].type == AU_FIRMWARE) && - (au_image[i].size != image_get_data_size (hdr))) { - printf ("Image %s has wrong size\n", au_image[i].name); - return -1; - } - - if (nbytes != (image_get_image_size (hdr))) { - printf ("Image %s bad total SIZE\n", au_image[i].name); - return -1; - } - - /* check the data CRC */ - if (!image_check_dcrc (hdr)) { - printf ("Image %s bad data checksum\n", au_image[i].name); - return -1; - } - return 0; -} - -int au_check_header_valid(int i, long nbytes) -{ - image_header_t *hdr; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - /* check the easy ones first */ - if (nbytes < image_get_header_size ()) { - printf ("Image %s bad header SIZE\n", au_image[i].name); - return -1; - } - if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) { - printf ("Image %s bad MAGIC or ARCH\n", au_image[i].name); - return -1; - } - if (!image_check_hcrc (hdr)) { - printf ("Image %s bad header checksum\n", au_image[i].name); - return -1; - } - - /* check the type - could do this all in one gigantic if() */ - if (((au_image[i].type & AU_TYPEMASK) == AU_FIRMWARE) && - !image_check_type (hdr, IH_TYPE_FIRMWARE)) { - printf ("Image %s wrong type\n", au_image[i].name); - return -1; - } - if (((au_image[i].type & AU_TYPEMASK) == AU_SCRIPT) && - !image_check_type (hdr, IH_TYPE_SCRIPT)) { - printf ("Image %s wrong type\n", au_image[i].name); - return -1; - } - - return 0; -} - -int au_do_update(int i, long sz) -{ - image_header_t *hdr; - char *addr; - long start, end; - int off, rc; - uint nbytes; - int k; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - switch (au_image[i].type & AU_TYPEMASK) { - case AU_SCRIPT: - printf("Executing script %s\n", au_image[i].name); - - /* execute a script */ - if (image_check_type (hdr, IH_TYPE_SCRIPT)) { - addr = (char *)((char *)hdr + image_get_header_size ()); - /* stick a NULL at the end of the script, otherwise */ - /* parse_string_outer() runs off the end. */ - addr[image_get_data_size (hdr)] = 0; - addr += 8; - - /* - * Replace cr/lf with ; - */ - k = 0; - while (addr[k] != 0) { - if ((addr[k] == 10) || (addr[k] == 13)) { - addr[k] = ';'; - } - k++; - } - - run_command(addr, 0); - return 0; - } - - break; - - case AU_FIRMWARE: - case AU_NOR: - case AU_NAND: - start = au_image[i].start; - end = au_image[i].start + au_image[i].size - 1; - - /* - * do not update firmware when image is already in flash. - */ - if (au_image[i].type == AU_FIRMWARE) { - char *orig = (char*)start; - char *new = (char *)((char *)hdr + - image_get_header_size ()); - nbytes = image_get_data_size (hdr); - - while (--nbytes) { - if (*orig++ != *new++) { - break; - } - } - if (!nbytes) { - printf ("Skipping firmware update - " - "images are identical\n"); - break; - } - } - - /* unprotect the address range */ - if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) || - (au_image[i].type == AU_FIRMWARE)) { - flash_sect_protect (0, start, end); - } - - /* - * erase the address range. - */ - if (au_image[i].type != AU_NAND) { - printf ("Updating NOR FLASH with image %s\n", - au_image[i].name); - debug ("flash_sect_erase(%lx, %lx);\n", start, end); - flash_sect_erase (start, end); - } - - udelay(10000); - - /* strip the header - except for the kernel and ramdisk */ - if (au_image[i].type != AU_FIRMWARE) { - addr = (char *)hdr; - off = image_get_header_size (); - nbytes = image_get_image_size (hdr); - } else { - addr = (char *)((char *)hdr + image_get_header_size ()); - off = 0; - nbytes = image_get_data_size (hdr); - } - - /* - * copy the data from RAM to FLASH - */ - if (au_image[i].type != AU_NAND) { - debug ("flash_write(%p, %lx, %x)\n", - addr, start, nbytes); - rc = flash_write ((char *)addr, start, - (nbytes + 1) & ~1); - } else { - rc = -1; - } - if (rc != 0) { - printf ("Flashing failed due to error %d\n", rc); - return -1; - } - - /* - * check the dcrc of the copy - */ - if (au_image[i].type != AU_NAND) { - rc = crc32 (0, (uchar *)(start + off), - image_get_data_size (hdr)); - } - if (rc != image_get_dcrc (hdr)) { - printf ("Image %s Bad Data Checksum After COPY\n", - au_image[i].name); - return -1; - } - - /* protect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) || - (au_image[i].type == AU_FIRMWARE)) { - flash_sect_protect (1, start, end); - } - - break; - - default: - printf("Wrong image type selected!\n"); - } - - return 0; -} - -static void process_macros (const char *input, char *output) -{ - char c, prev; - const char *varname_start = NULL; - int inputcnt = strlen (input); - int outputcnt = CONFIG_SYS_CBSIZE; - int state = 0; /* 0 = waiting for '$' */ - /* 1 = waiting for '(' or '{' */ - /* 2 = waiting for ')' or '}' */ - /* 3 = waiting for ''' */ -#ifdef DEBUG_PARSER - char *output_start = output; - - printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", - strlen(input), input); -#endif - - prev = '\0'; /* previous character */ - - while (inputcnt && outputcnt) { - c = *input++; - inputcnt--; - - if (state != 3) { - /* remove one level of escape characters */ - if ((c == '\\') && (prev != '\\')) { - if (inputcnt-- == 0) - break; - prev = c; - c = *input++; - } - } - - switch (state) { - case 0: /* Waiting for (unescaped) $ */ - if ((c == '\'') && (prev != '\\')) { - state = 3; - break; - } - if ((c == '$') && (prev != '\\')) { - state++; - } else { - *(output++) = c; - outputcnt--; - } - break; - case 1: /* Waiting for ( */ - if (c == '(' || c == '{') { - state++; - varname_start = input; - } else { - state = 0; - *(output++) = '$'; - outputcnt--; - - if (outputcnt) { - *(output++) = c; - outputcnt--; - } - } - break; - case 2: /* Waiting for ) */ - if (c == ')' || c == '}') { - int i; - char envname[CONFIG_SYS_CBSIZE], *envval; - /* Varname # of chars */ - int envcnt = input - varname_start - 1; - - /* Get the varname */ - for (i = 0; i < envcnt; i++) { - envname[i] = varname_start[i]; - } - envname[i] = 0; - - /* Get its value */ - envval = getenv (envname); - - /* Copy into the line if it exists */ - if (envval != NULL) - while ((*envval) && outputcnt) { - *(output++) = *(envval++); - outputcnt--; - } - /* Look for another '$' */ - state = 0; - } - break; - case 3: /* Waiting for ' */ - if ((c == '\'') && (prev != '\\')) { - state = 0; - } else { - *(output++) = c; - outputcnt--; - } - break; - } - prev = c; - } - - if (outputcnt) - *output = 0; - -#ifdef DEBUG_PARSER - printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n", - strlen (output_start), output_start); -#endif -} - -/* - * this is called from board_init() after the hardware has been set up - * and is usable. That seems like a good time to do this. - * Right now the return value is ignored. - */ -int do_auto_update(void) -{ - block_dev_desc_t *stor_dev = NULL; - long sz; - int i, res, old_ctrlc; - char buffer[32]; - char str[80]; - int n; - - if (ide_dev_desc[0].type != DEV_TYPE_UNKNOWN) { - stor_dev = get_dev ("ide", 0); - if (stor_dev == NULL) { - debug ("ide: unknown device\n"); - return -1; - } - } - - if (fat_register_device (stor_dev, 1) != 0) { - debug ("Unable to register ide disk 0:1\n"); - return -1; - } - - /* - * Check if magic file is present - */ - if ((n = do_fat_read (AU_MAGIC_FILE, buffer, - sizeof(buffer), LS_NO)) <= 0) { - debug ("No auto_update magic file (n=%d)\n", n); - return -1; - } - -#ifdef CONFIG_AUTO_UPDATE_SHOW - board_auto_update_show (1); -#endif - puts("\nAutoUpdate Disk detected! Trying to update system...\n"); - - /* make sure that we see CTRL-C and save the old state */ - old_ctrlc = disable_ctrlc (0); - - /* just loop thru all the possible files */ - for (i = 0; i < N_AU_IMAGES; i++) { - /* - * Try to expand the environment var in the fname - */ - process_macros (au_image[i].name, str); - strcpy (au_image[i].name, str); - - printf("Reading %s ...", au_image[i].name); - /* just read the header */ - sz = do_fat_read (au_image[i].name, LOAD_ADDR, - image_get_header_size (), LS_NO); - debug ("read %s sz %ld hdr %d\n", - au_image[i].name, sz, image_get_header_size ()); - if (sz <= 0 || sz < image_get_header_size ()) { - puts(" not found\n"); - continue; - } - if (au_check_header_valid (i, sz) < 0) { - puts(" header not valid\n"); - continue; - } - sz = do_fat_read (au_image[i].name, LOAD_ADDR, - MAX_LOADSZ, LS_NO); - debug ("read %s sz %ld hdr %d\n", - au_image[i].name, sz, image_get_header_size ()); - if (sz <= 0 || sz <= image_get_header_size ()) { - puts(" not found\n"); - continue; - } - if (au_check_cksum_valid (i, sz) < 0) { - puts(" checksum not valid\n"); - continue; - } - puts(" done\n"); - - do { - res = au_do_update (i, sz); - /* let the user break out of the loop */ - if (ctrlc() || had_ctrlc ()) { - clear_ctrlc (); - break; - } - } while (res < 0); - } - - /* restore the old state */ - disable_ctrlc (old_ctrlc); - - puts("AutoUpdate finished\n\n"); -#ifdef CONFIG_AUTO_UPDATE_SHOW - board_auto_update_show (0); -#endif - - return 0; -} - -int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - do_auto_update(); - - return 0; -} -U_BOOT_CMD( - autoupd, 1, 1, auto_update, - "Automatically update images", - "" -); -#endif /* CONFIG_AUTO_UPDATE */ diff --git a/board/esd/common/auto_update.h b/board/esd/common/auto_update.h deleted file mode 100644 index be8f439..0000000 --- a/board/esd/common/auto_update.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _AUTO_UPDATE_H_ -#define _AUTO_UPDATE_H_ - -#define MBR_MAGIC 0x07081967 -#define MBR_MAGIC_ADDR 0x100 /* offset 0x100 should be free space */ - -#define AU_MAGIC_FILE "__auto_update" - -#define AU_TYPEMASK 0x000000ff -#define AU_FLAGMASK 0xffff0000 - -#define AU_PROTECT 0x80000000 - -#define AU_SCRIPT 0x01 -#define AU_FIRMWARE (0x02 | AU_PROTECT) -#define AU_NOR 0x03 -#define AU_NAND 0x04 - -struct au_image_s { - char name[80]; - ulong start; - ulong size; - ulong type; -}; - -typedef struct au_image_s au_image_t; - -int do_auto_update(void); -#ifdef CONFIG_AUTO_UPDATE_SHOW -void board_auto_update_show(int au_active); -#endif - -#endif /* #ifndef _AUTO_UPDATE_H_ */ diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile index b140571..7490b78 100644 --- a/board/esd/cpci405/Makefile +++ b/board/esd/cpci405/Makefile @@ -5,5 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y = cpci405.o flash.o ../common/misc.o ../common/auto_update.o +obj-y = cpci405.o flash.o ../common/misc.o obj-y += ../common/cmd_loadpci.o diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index e23ec55..bf5a4cb 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -24,13 +24,7 @@ extern void __ft_board_setup(void *blob, bd_t *bd); const unsigned char fpgadata[] = { #if defined(CONFIG_CPCI405_VER2) -# if defined(CONFIG_CPCI405AB) -# include "fpgadata_cpci405ab.c" -# else -# include "fpgadata_cpci4052.c" -# endif -#else -# include "fpgadata_cpci405.c" +# include "fpgadata_cpci4052.c" #endif }; @@ -38,37 +32,6 @@ const unsigned char fpgadata[] = * include common fpga code (for esd boards) */ #include "../common/fpga.c" -#include "../common/auto_update.h" - -#if defined(CONFIG_CPCI405AB) -au_image_t au_image[] = { - {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT}, - {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR}, - {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR}, - {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE}, - {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT}, -}; -#else -#if defined(CONFIG_CPCI405_VER2) -au_image_t au_image[] = { - {"cpci4052/preinst.img", 0, -1, AU_SCRIPT}, - {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR}, - {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR}, - {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE}, - {"cpci4052/postinst.img", 0, 0, AU_SCRIPT}, -}; -#else -au_image_t au_image[] = { - {"cpci405/preinst.img", 0, -1, AU_SCRIPT}, - {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR}, - {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR}, - {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE}, - {"cpci405/postinst.img", 0, 0, AU_SCRIPT}, -}; -#endif -#endif - -int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); /* Prototypes */ int cpci405_version(void); @@ -530,240 +493,3 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ - -#if defined(CONFIG_CPCI405AB) -#define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ - CONFIG_SYS_FPGA_MODE), \ - in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ - CONFIG_SYS_FPGA_MODE)) | \ - CONFIG_SYS_FPGA_MODE_1WIRE_DIR) - -#define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ - CONFIG_SYS_FPGA_MODE), \ - in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ - CONFIG_SYS_FPGA_MODE)) & \ - ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR) - -#define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ - CONFIG_SYS_FPGA_STATUS)) & \ - CONFIG_SYS_FPGA_MODE_1WIRE) - -/* - * Generate a 1-wire reset, return 1 if no presence detect was found, - * return 0 otherwise. - * (NOTE: Does not handle alarm presence from DS2404/DS1994) - */ -int OWTouchReset(void) -{ - int result; - - ONE_WIRE_CLEAR; - udelay(480); - ONE_WIRE_SET; - udelay(70); - - result = ONE_WIRE_GET; - - udelay(410); - return result; -} - -/* - * Send 1 a 1-wire write bit. - * Provide 10us recovery time. - */ -void OWWriteBit(int bit) -{ - if (bit) { - /* - * write '1' bit - */ - ONE_WIRE_CLEAR; - udelay(6); - ONE_WIRE_SET; - udelay(64); - } else { - /* - * write '0' bit - */ - ONE_WIRE_CLEAR; - udelay(60); - ONE_WIRE_SET; - udelay(10); - } -} - -/* - * Read a bit from the 1-wire bus and return it. - * Provide 10us recovery time. - */ -int OWReadBit(void) -{ - int result; - - ONE_WIRE_CLEAR; - udelay(6); - ONE_WIRE_SET; - udelay(9); - - result = ONE_WIRE_GET; - - udelay(55); - return result; -} - -void OWWriteByte(int data) -{ - int loop; - - for (loop = 0; loop < 8; loop++) { - OWWriteBit(data & 0x01); - data >>= 1; - } -} - -int OWReadByte(void) -{ - int loop, result = 0; - - for (loop = 0; loop < 8; loop++) { - result >>= 1; - if (OWReadBit()) - result |= 0x80; - } - - return result; -} - -int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short val; - int result; - int i; - unsigned char ow_id[6]; - char str[32]; - - /* - * Clear 1-wire bit (open drain with pull-up) - */ - val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + - CONFIG_SYS_FPGA_MODE)); - val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */ - out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + - CONFIG_SYS_FPGA_MODE), val); - - result = OWTouchReset(); - if (result != 0) - puts("No 1-wire device detected!\n"); - - OWWriteByte(0x33); /* send read rom command */ - OWReadByte(); /* skip family code ( == 0x01) */ - for (i = 0; i < 6; i++) - ow_id[i] = OWReadByte(); - OWReadByte(); /* read crc */ - - sprintf(str, "%02X%02X%02X%02X%02X%02X", - ow_id[0], ow_id[1], ow_id[2], ow_id[3], ow_id[4], ow_id[5]); - printf("Setting environment variable 'ow_id' to %s\n", str); - setenv("ow_id", str); - - return 0; -} -U_BOOT_CMD( - onewire, 1, 1, do_onewire, - "Read 1-write ID", - "" -); - -#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */ -#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */ - -/* - * Write backplane ip-address... - */ -int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char *buf; - ulong crc; - char str[32]; - char *ptr; - IPaddr_t ipaddr; - - buf = malloc(CONFIG_ENV_SIZE_2); - if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, - (uchar *)buf, CONFIG_ENV_SIZE_2)) - puts("\nError reading backplane EEPROM!\n"); - else { - crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4); - if (crc != *(ulong *)buf) { - printf("ERROR: crc mismatch %08lx %08lx\n", - crc, *(ulong *)buf); - return -1; - } - - /* - * Find bp_ip - */ - ptr = strstr(buf+4, "bp_ip="); - if (ptr == NULL) { - printf("ERROR: bp_ip not found!\n"); - return -1; - } - ptr += 6; - ipaddr = string_to_ip(ptr); - - /* - * Update whole ip-addr - */ - sprintf(str, "%pI4", &ipaddr); - setenv("ipaddr", str); - printf("Updated ip_addr from bp_eeprom to %s!\n", str); - } - - free(buf); - - return 0; -} -U_BOOT_CMD( - getbpip, 1, 1, do_get_bpip, - "Update IP-Address with Backplane IP-Address", - "" -); - -/* - * Set and print backplane ip... - */ -int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char *buf; - char str[32]; - ulong crc; - - if (argc < 2) { - puts("ERROR!\n"); - return -1; - } - - printf("Setting bp_ip to %s\n", argv[1]); - buf = malloc(CONFIG_ENV_SIZE_2); - memset(buf, 0, CONFIG_ENV_SIZE_2); - sprintf(str, "bp_ip=%s", argv[1]); - strcpy(buf+4, str); - crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4); - *(ulong *)buf = crc; - - if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, - 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) - puts("\nError writing backplane EEPROM!\n"); - - free(buf); - - return 0; -} -U_BOOT_CMD( - setbpip, 2, 1, do_set_bpip, - "Write Backplane IP-Address", - "" -); - -#endif /* CONFIG_CPCI405AB */ diff --git a/board/esd/cpci405/fpgadata_cpci405.c b/board/esd/cpci405/fpgadata_cpci405.c deleted file mode 100644 index 46c2fed..0000000 --- a/board/esd/cpci405/fpgadata_cpci405.c +++ /dev/null @@ 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enable this for 6U boards */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ -- 1.7.9.5

2 1

[U-Boot] [PATCH 17/22] ppc4xx: remove some CPCI405 variants
by Matthias Fuchs 13 Jan '15

13 Jan '15

only keep CPCI4052 Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- arch/powerpc/cpu/ppc4xx/Kconfig | 9 - board/esd/cpci405/Kconfig | 39 ---- configs/CPCI405AB_defconfig | 3 - configs/CPCI405DT_defconfig | 3 - configs/CPCI405_defconfig | 3 - doc/README.scrapyard | 3 + include/configs/CPCI405.h | 320 --------------------------------- include/configs/CPCI405AB.h | 373 -------------------------------------- include/configs/CPCI405DT.h | 376 --------------------------------------- 9 files changed, 3 insertions(+), 1126 deletions(-) delete mode 100644 configs/CPCI405AB_defconfig delete mode 100644 configs/CPCI405DT_defconfig delete mode 100644 configs/CPCI405_defconfig delete mode 100644 include/configs/CPCI405.h delete mode 100644 include/configs/CPCI405AB.h delete mode 100644 include/configs/CPCI405DT.h diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index e7163c1..a40ae3b 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -110,18 +110,9 @@ config TARGET_PPCHAMELEONEVB config TARGET_CPCI2DP bool "Support CPCI2DP" -config TARGET_CPCI405 - bool "Support CPCI405" - config TARGET_CPCI4052 bool "Support CPCI4052" -config TARGET_CPCI405AB - bool "Support CPCI405AB" - -config TARGET_CPCI405DT - bool "Support CPCI405DT" - config TARGET_PLU405 bool "Support PLU405" diff --git a/board/esd/cpci405/Kconfig b/board/esd/cpci405/Kconfig index bc56907..0df2755 100644 --- a/board/esd/cpci405/Kconfig +++ b/board/esd/cpci405/Kconfig @@ -1,16 +1,3 @@ -if TARGET_CPCI405 - -config SYS_BOARD - default "cpci405" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "CPCI405" - -endif - if TARGET_CPCI4052 config SYS_BOARD @@ -23,29 +10,3 @@ config SYS_CONFIG_NAME default "CPCI4052" endif - -if TARGET_CPCI405AB - -config SYS_BOARD - default "cpci405" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "CPCI405AB" - -endif - -if TARGET_CPCI405DT - -config SYS_BOARD - default "cpci405" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "CPCI405DT" - -endif diff --git a/configs/CPCI405AB_defconfig b/configs/CPCI405AB_defconfig deleted file mode 100644 index 6550fd1..0000000 --- a/configs/CPCI405AB_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_CPCI405AB=y diff --git a/configs/CPCI405DT_defconfig b/configs/CPCI405DT_defconfig deleted file mode 100644 index b61f65c..0000000 --- a/configs/CPCI405DT_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_CPCI405DT=y diff --git a/configs/CPCI405_defconfig b/configs/CPCI405_defconfig deleted file mode 100644 index 1638e2b..0000000 --- a/configs/CPCI405_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_CPCI405=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 69daaab..9172f6c 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,9 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +CPCI405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs(a)esd.eu> +CPCI405DT ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs(a)esd.eu> +CPCI405AB ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs(a)esd.eu> G2000 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> WUH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> VOH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h deleted file mode 100644 index 34252d4..0000000 --- a/include/configs/CPCI405.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#undef CONFIG_HAS_ETH1 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MII -#define CONFIG_CMD_EEPROM - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_LOOPW 1 /* enable loopw command */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */ - -#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ - -#if 1 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ - -#else /* Use EEPROM for environment variables */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (CompactFlash IDE) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (NVRAM) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */ -#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 5 (Quart) initialization */ -#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ -#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ - -/*----------------------------------------------------------------------- - * FPGA stuff - */ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -#if 1 /* test-only */ -#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#else -#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h deleted file mode 100644 index 7d58e9d..0000000 --- a/include/configs/CPCI405AB.h +++ /dev/null @@ -1,373 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ -#define CONFIG_CPCI405_VER2 1 /* ...version 2 */ -#define CONFIG_CPCI405AB 1 /* ...and special AB version */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#undef CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#undef CONFIG_HAS_ETH1 - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_CMDLINE_EDITING /* add command line history */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#undef CONFIG_AUTOBOOT_DELAY_STR -#define CONFIG_AUTOBOOT_STOP_STR " " - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */ - -#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -#define CONFIG_PRAM 0 /* use pram variable to overwrite */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC32) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom used! */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* Use EEPROM for environment variables */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC32 is 4096 bytes */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (CAN0, 1) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#define CONFIG_SYS_LED_ADDR 0xF0000380 - -/* Memory Bank 3 (CompactFlash IDE) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (NVRAM/RTC) initialization */ -/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ -#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ -#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 5 (optional Quart) initialization */ -#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ -#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 6 (FPGA internal) initialization */ -#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ -#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CONFIG_SYS_FPGA_MODE 0x00 -#define CONFIG_SYS_FPGA_STATUS 0x02 -#define CONFIG_SYS_FPGA_TS 0x04 -#define CONFIG_SYS_FPGA_TS_LOW 0x06 -#define CONFIG_SYS_FPGA_TS_CAP0 0x10 -#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 -#define CONFIG_SYS_FPGA_TS_CAP1 0x14 -#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 -#define CONFIG_SYS_FPGA_TS_CAP2 0x18 -#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a -#define CONFIG_SYS_FPGA_TS_CAP3 0x1c -#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 -#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002 -#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ -#define CONFIG_SYS_FPGA_MODE_1WIRE_DIR 0x0100 /* dir=1 -> output */ -#define CONFIG_SYS_FPGA_MODE_SIM_OK_DIR 0x0200 -#define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400 -#define CONFIG_SYS_FPGA_MODE_1WIRE 0x1000 -#define CONFIG_SYS_FPGA_MODE_SIM_OK 0x2000 /* wired-or net from all devices */ -#define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL 0x4000 - -/* FPGA Status Reg */ -#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 -#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 -#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 -#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 -#define CONFIG_SYS_FPGA_STATUS_1WIRE 0x1000 -#define CONFIG_SYS_FPGA_STATUS_SIM_OK 0x2000 - -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S30 */ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h deleted file mode 100644 index c2598a3..0000000 --- a/include/configs/CPCI405DT.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ -#define CONFIG_CPCI405_VER2 1 /* ...version 2 */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#undef CONFIG_HAS_ETH1 - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_LOOPW 1 /* enable loopw command */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/* Only interrupt boot if special string is typed */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Autobooting in %d seconds\n", bootdelay -#undef CONFIG_AUTOBOOT_DELAY_STR -#undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */ -#define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */ - -#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */ - -#else /* Use EEPROM for environment variables */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ -#endif - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (CAN0, 1) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#define CONFIG_SYS_LED_ADDR 0xF0000380 - -/* Memory Bank 3 (CompactFlash IDE) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (NVRAM/RTC) initialization */ -/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ -#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ -#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 5 (optional Quart) initialization */ -#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ -#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 6 (FPGA internal) initialization */ -#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ -#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CONFIG_SYS_FPGA_MODE 0x00 -#define CONFIG_SYS_FPGA_STATUS 0x02 -#define CONFIG_SYS_FPGA_TS 0x04 -#define CONFIG_SYS_FPGA_TS_LOW 0x06 -#define CONFIG_SYS_FPGA_TS_CAP0 0x10 -#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 -#define CONFIG_SYS_FPGA_TS_CAP1 0x14 -#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 -#define CONFIG_SYS_FPGA_TS_CAP2 0x18 -#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a -#define CONFIG_SYS_FPGA_TS_CAP3 0x1c -#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 -#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002 -#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 -#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 - -/* FPGA Status Reg */ -#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 -#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 -#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 -#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 -#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 - -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ -- 1.7.9.5

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[U-Boot] [PATCH 16/22] ppc4xx: remove G2000 board
by Matthias Fuchs 13 Jan '15

13 Jan '15

Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- arch/powerpc/cpu/ppc4xx/Kconfig | 4 - board/g2000/Kconfig | 9 - board/g2000/MAINTAINERS | 6 - board/g2000/Makefile | 8 - board/g2000/g2000.c | 245 ------------- board/g2000/strataflash.c | 774 --------------------------------------- configs/G2000_defconfig | 3 - doc/README.scrapyard | 1 + include/configs/G2000.h | 383 ------------------- 9 files changed, 1 insertion(+), 1432 deletions(-) delete mode 100644 board/g2000/Kconfig delete mode 100644 board/g2000/MAINTAINERS delete mode 100644 board/g2000/Makefile delete mode 100644 board/g2000/g2000.c delete mode 100644 board/g2000/strataflash.c delete mode 100644 configs/G2000_defconfig delete mode 100644 include/configs/G2000.h diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 6c4759a..e7163c1 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -13,9 +13,6 @@ config TARGET_CSB272 config TARGET_CSB472 bool "Support csb472" -config TARGET_G2000 - bool "Support G2000" - config TARGET_JSE bool "Support JSE" @@ -218,7 +215,6 @@ source "board/esd/plu405/Kconfig" source "board/esd/pmc405de/Kconfig" source "board/esd/pmc440/Kconfig" source "board/esd/vom405/Kconfig" -source "board/g2000/Kconfig" source "board/gdsys/405ep/Kconfig" source "board/gdsys/405ex/Kconfig" source "board/gdsys/dlvision/Kconfig" diff --git a/board/g2000/Kconfig b/board/g2000/Kconfig deleted file mode 100644 index 031fae9..0000000 --- a/board/g2000/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_G2000 - -config SYS_BOARD - default "g2000" - -config SYS_CONFIG_NAME - default "G2000" - -endif diff --git a/board/g2000/MAINTAINERS b/board/g2000/MAINTAINERS deleted file mode 100644 index 8171b10..0000000 --- a/board/g2000/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -G2000 BOARD -M: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> -S: Maintained -F: board/g2000/ -F: include/configs/G2000.h -F: configs/G2000_defconfig diff --git a/board/g2000/Makefile b/board/g2000/Makefile deleted file mode 100644 index 74c8053..0000000 --- a/board/g2000/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = g2000.o strataflash.o diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c deleted file mode 100644 index a64f946..0000000 --- a/board/g2000/g2000.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <command.h> - -#define MEM_MCOPT1_INIT_VAL 0x00800000 -#define MEM_RTR_INIT_VAL 0x04070000 -#define MEM_PMIT_INIT_VAL 0x07c00000 -#define MEM_MB0CF_INIT_VAL 0x00082001 -#define MEM_MB1CF_INIT_VAL 0x04082000 -#define MEM_SDTR1_INIT_VAL 0x00854005 -#define SDRAM0_CFG_ENABLE 0x80000000 - -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */ - -int board_early_init_f (void) -{ -#if 0 /* test-only */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000010); - mtdcr (UIC0PR, 0xFFFF7FF0); /* set int polarities */ - mtdcr (UIC0TR, 0x00000010); /* set int trigger levels */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ -#else - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFFF0); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ -#endif - -#if 1 /* test-only */ - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ -#endif - - return 0; -} - - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ -#if defined(CONFIG_CMD_NAND) - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE); -#endif - - return (0); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming G2000"); - } else { - puts(str); - } - - putc ('\n'); - - return 0; -} - - -/* ------------------------------------------------------------------------- - G2000 rev B is an embeded design. we don't read for spd of this version. - Doing static SDRAM controller configuration in the following section. - ------------------------------------------------------------------------- */ - -long int init_sdram_static_settings(void) -{ - /* disable memcontroller so updates work */ - mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL); - mtsdram(SDRAM0_RTR, MEM_RTR_INIT_VAL); - mtsdram(SDRAM0_PMIT, MEM_PMIT_INIT_VAL); - mtsdram(SDRAM0_B0CR, MEM_MB0CF_INIT_VAL); - mtsdram(SDRAM0_B1CR, MEM_MB1CF_INIT_VAL); - mtsdram(SDRAM0_TR, MEM_SDTR1_INIT_VAL); - - /* SDRAM have a power on delay, 500 micro should do */ - udelay(500); - mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE); - - return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */ - } - - -phys_size_t initdram (int board_type) -{ - long int ret; - -/* flzt, we can still turn this on in the future */ -/* #ifdef CONFIG_SPD_EEPROM - ret = spd_sdram (); -#else - ret = init_sdram_static_settings(); -#endif -*/ - - ret = init_sdram_static_settings(); - - return ret; -} - -#if 0 /* test-only !!! */ -int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong ap, cr; - - printf("\nEBC registers for PPC405GP:\n"); - mfebc(PB0AP, ap); mfebc(PB0CR, cr); - printf("0: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(PB1AP, ap); mfebc(PB1CR, cr); - printf("1: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(PB2AP, ap); mfebc(PB2CR, cr); - printf("2: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(PB3AP, ap); mfebc(PB3CR, cr); - printf("3: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(PB4AP, ap); mfebc(PB4CR, cr); - printf("4: AP=%08lx CP=%08lx\n", ap, cr); - printf("\n"); - - return 0; -} -U_BOOT_CMD( - dumpebc, 1, 1, do_dumpebc, - "Dump all EBC registers", - "" -); - - -int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int i; - - printf("\nDevice Configuration Registers (DCR's) for PPC405GP:"); - for (i=0; i<=0x1e0; i++) { - if (!(i % 0x8)) { - printf("\n%04x ", i); - } - printf("%08lx ", get_dcr(i)); - } - printf("\n"); - - return 0; -} -U_BOOT_CMD( - dumpdcr, 1, 1, do_dumpdcr, - "Dump all DCR registers", - "" -); - - -int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:"); - printf("\n%04x %08x ", 947, mfspr(947)); - printf("\n%04x %08x ", 9, mfspr(9)); - printf("\n%04x %08x ", 1014, mfspr(1014)); - printf("\n%04x %08x ", 1015, mfspr(1015)); - printf("\n%04x %08x ", 1010, mfspr(1010)); - printf("\n%04x %08x ", 957, mfspr(957)); - printf("\n%04x %08x ", 1008, mfspr(1008)); - printf("\n%04x %08x ", 1018, mfspr(1018)); - printf("\n%04x %08x ", 954, mfspr(954)); - printf("\n%04x %08x ", 950, mfspr(950)); - printf("\n%04x %08x ", 951, mfspr(951)); - printf("\n%04x %08x ", 981, mfspr(981)); - printf("\n%04x %08x ", 980, mfspr(980)); - printf("\n%04x %08x ", 982, mfspr(982)); - printf("\n%04x %08x ", 1012, mfspr(1012)); - printf("\n%04x %08x ", 1013, mfspr(1013)); - printf("\n%04x %08x ", 948, mfspr(948)); - printf("\n%04x %08x ", 949, mfspr(949)); - printf("\n%04x %08x ", 1019, mfspr(1019)); - printf("\n%04x %08x ", 979, mfspr(979)); - printf("\n%04x %08x ", 8, mfspr(8)); - printf("\n%04x %08x ", 945, mfspr(945)); - printf("\n%04x %08x ", 987, mfspr(987)); - printf("\n%04x %08x ", 287, mfspr(287)); - printf("\n%04x %08x ", 953, mfspr(953)); - printf("\n%04x %08x ", 955, mfspr(955)); - printf("\n%04x %08x ", 272, mfspr(272)); - printf("\n%04x %08x ", 273, mfspr(273)); - printf("\n%04x %08x ", 274, mfspr(274)); - printf("\n%04x %08x ", 275, mfspr(275)); - printf("\n%04x %08x ", 260, mfspr(260)); - printf("\n%04x %08x ", 276, mfspr(276)); - printf("\n%04x %08x ", 261, mfspr(261)); - printf("\n%04x %08x ", 277, mfspr(277)); - printf("\n%04x %08x ", 262, mfspr(262)); - printf("\n%04x %08x ", 278, mfspr(278)); - printf("\n%04x %08x ", 263, mfspr(263)); - printf("\n%04x %08x ", 279, mfspr(279)); - printf("\n%04x %08x ", 26, mfspr(26)); - printf("\n%04x %08x ", 27, mfspr(27)); - printf("\n%04x %08x ", 990, mfspr(990)); - printf("\n%04x %08x ", 991, mfspr(991)); - printf("\n%04x %08x ", 956, mfspr(956)); - printf("\n%04x %08x ", 284, mfspr(284)); - printf("\n%04x %08x ", 285, mfspr(285)); - printf("\n%04x %08x ", 986, mfspr(986)); - printf("\n%04x %08x ", 984, mfspr(984)); - printf("\n%04x %08x ", 256, mfspr(256)); - printf("\n%04x %08x ", 1, mfspr(1)); - printf("\n%04x %08x ", 944, mfspr(944)); - printf("\n"); - - return 0; -} -U_BOOT_CMD( - dumpspr, 1, 1, do_dumpspr, - "Dump all SPR registers", - "" -); -#endif diff --git a/board/g2000/strataflash.c b/board/g2000/strataflash.c deleted file mode 100644 index 1d29eb4..0000000 --- a/board/g2000/strataflash.c +++ /dev/null @@ -1,774 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp(a)seranoa.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for ppcboot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - -#define FLASH_MAN_CFI 0x01000000 - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CONFIG_SYS_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size(address, i); - address += CONFIG_SYS_FLASH_INCREMENT; - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i, - flash_info[0].size, flash_info[i].size<<20); - } - } - -#if 0 /* test-only */ - /* Monitor protection ON by default */ -#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#else - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - - CONFIG_SYS_MONITOR_LEN, - - 1, &flash_info[1]); -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { -#ifdef CONFIG_SYS_FLASH_EMPTY_INFO - int k; - int size; - int erased; - volatile unsigned long *flash; - - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; k<size; k++) - { - if (*flash++ != 0xffffffff) - { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - /* print empty and read-only info */ - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); -#endif - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;i<aln; ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - - for(; (i< info->portwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; i<info->portwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; i<info->sector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * -*/ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if(flash_detect_cfi(info)){ -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t cptr; - int flag; - - cptr.cp = (uchar *)dest; - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - if (len & 0x1) { /* test-only: unaligned size */ - puts("\nUnalgined size!!!\n"); /* test-only */ - cnt++; - } - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ diff --git a/configs/G2000_defconfig b/configs/G2000_defconfig deleted file mode 100644 index a01bc0f..0000000 --- a/configs/G2000_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_G2000=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index a385bde..69daaab 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +G2000 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> WUH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> VOH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> PMC405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs(a)esd.eu> diff --git a/include/configs/G2000.h b/include/configs/G2000.h deleted file mode 100644 index 0c66092..0000000 --- a/include/configs/G2000.h +++ /dev/null @@ -1,383 +0,0 @@ -/* - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_G2000 1 /* ...on a PLU405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#if 0 /* test-only */ -#define CONFIG_BAUDRATE 115200 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -#define CONFIG_PREBOOT - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "panic=1\0" \ - "flash_nfs=run nfsargs addip addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};" \ - "run nfsargs addip addmisc;bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/g2000/pImage\0" \ - "kernel_addr=ff800000\0" \ - "ramdisk_addr=ff900000\0" \ - "pciconfighost=yes\0" \ - "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY1_ADDR 1 /* PHY address */ - -#if 0 /* test-only */ -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#if 0 /* test-only */ -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------------*/ -/* adding Ethernet setting: FTS OUI 00:11:0B */ -/*----------------------------------------------------------------------------*/ -#define CONFIG_ETHADDR 00:11:0B:00:00:01 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:11:0B:00:00:02 -#define CONFIG_IPADDR 10.48.8.178 -#define CONFIG_IP1ADDR 10.48.8.188 -#define CONFIG_NETMASK 255.255.255.128 -#define CONFIG_SERVERIP 10.48.8.138 - -/*----------------------------------------------------------------------- - * RTC stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -#if 0 /* test-only */ -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ - -#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#endif - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#if 0 /* APC405 */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* test-only...*/ -#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* test-only */ -#else /* G2000 */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* test-only...*/ -#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* test-only */ -#endif - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#if 1 /* test-only */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#else /* DEFAULT: environment in flash, using redundand flash sectors */ - -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CONFIG_ENV_ADDR 0xFFFA0000 /* environment starts before u-boot */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k bytes may be used for env vars*/ - -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -/* CAT24WC08/16... */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Intel Strata Flash) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFF87A000 /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 1 ( Power TAU) initialization */ -/* #define CONFIG_SYS_EBC_PB1AP 0x04041000 */ -/* #define CONFIG_SYS_EBC_PB1CR 0xF0018000 */ /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#define CONFIG_SYS_EBC_PB1AP 0x00000000 -#define CONFIG_SYS_EBC_PB1CR 0x00000000 - -/* Memory Bank 2 (Intel Flash) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x00000000 -#define CONFIG_SYS_EBC_PB2CR 0x00000000 - -/* Memory Bank 3 (NAND) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x92015480 -#define CONFIG_SYS_EBC_PB3CR 0xF40B8000 /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */ - -/* Memory Bank 4 (FPGA regs) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x00000000 -#define CONFIG_SYS_EBC_PB4CR 0x00000000 /* leave it blank */ - -#define CONFIG_SYS_NAND_BASE 0xF4000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - * - * following GPIO setting changed for G20000, 080304 - */ -#define CONFIG_SYS_GPIO0_OSRL 0x40005555 -#define CONFIG_SYS_GPIO0_OSRH 0x40000110 -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014 - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 1 -#define PLLMR0_DEFAULT PLLMR0_266_66_33_33 -#define PLLMR1_DEFAULT PLLMR1_266_66_33_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ -- 1.7.9.5

2 1

[U-Boot] [PATCH 15/22] ppc4xx: remove WUH405 board
by Matthias Fuchs 13 Jan '15

13 Jan '15

Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- arch/powerpc/cpu/ppc4xx/Kconfig | 4 - board/esd/wuh405/Kconfig | 12 - board/esd/wuh405/MAINTAINERS | 6 - board/esd/wuh405/Makefile | 10 - board/esd/wuh405/flash.c | 85 - board/esd/wuh405/fpgadata.c | 3636 --------------------------------------- board/esd/wuh405/wuh405.c | 171 -- configs/WUH405_defconfig | 3 - doc/README.scrapyard | 1 + include/configs/WUH405.h | 346 ---- 10 files changed, 1 insertion(+), 4273 deletions(-) delete mode 100644 board/esd/wuh405/Kconfig delete mode 100644 board/esd/wuh405/MAINTAINERS delete mode 100644 board/esd/wuh405/Makefile delete mode 100644 board/esd/wuh405/flash.c delete mode 100644 board/esd/wuh405/fpgadata.c delete mode 100644 board/esd/wuh405/wuh405.c delete mode 100644 configs/WUH405_defconfig delete mode 100644 include/configs/WUH405.h diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 9884894..6c4759a 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -137,9 +137,6 @@ config TARGET_PMC440 config TARGET_VOM405 bool "Support VOM405" -config TARGET_WUH405 - bool "Support WUH405" - config TARGET_DLVISION_10G bool "Support dlvision-10g" @@ -221,7 +218,6 @@ source "board/esd/plu405/Kconfig" source "board/esd/pmc405de/Kconfig" source "board/esd/pmc440/Kconfig" source "board/esd/vom405/Kconfig" -source "board/esd/wuh405/Kconfig" source "board/g2000/Kconfig" source "board/gdsys/405ep/Kconfig" source "board/gdsys/405ex/Kconfig" diff --git a/board/esd/wuh405/Kconfig b/board/esd/wuh405/Kconfig deleted file mode 100644 index 8a7df4d..0000000 --- a/board/esd/wuh405/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_WUH405 - -config SYS_BOARD - default "wuh405" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "WUH405" - -endif diff --git a/board/esd/wuh405/MAINTAINERS b/board/esd/wuh405/MAINTAINERS deleted file mode 100644 index 782c72a..0000000 --- a/board/esd/wuh405/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -WUH405 BOARD -M: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> -S: Maintained -F: board/esd/wuh405/ -F: include/configs/WUH405.h -F: configs/WUH405_defconfig diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile deleted file mode 100644 index b9beeff..0000000 --- a/board/esd/wuh405/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = wuh405.o flash.o \ - ../common/misc.o \ - ../common/esd405ep_nand.o \ diff --git a/board/esd/wuh405/flash.c b/board/esd/wuh405/flash.c deleted file mode 100644 index 23e8164..0000000 --- a/board/esd/wuh405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Setup offsets */ - flash_get_offsets (-size_b0, &flash_info[0]); - - /* Re-do sizing to get full correct info */ - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b0 = -size_b0; - switch (size_b0) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - } - pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(EBC0_CFGDATA, pbcr); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} diff --git a/board/esd/wuh405/fpgadata.c b/board/esd/wuh405/fpgadata.c deleted file mode 100644 index a964f9f..0000000 --- a/board/esd/wuh405/fpgadata.c +++ /dev/null @@ -1,3636 +0,0 @@ -0x1f, 0x8b, 0x08, 0x08, 0xe2, 0x44, 0xc5, 0x42, -0x00, 0x03, 0x77, 0x75, 0x68, 0x34, 0x30, 0x35, -0x5f, 0x31, 0x2e, 0x62, 0x69, 0x74, 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0x4b, 0x4b, 0xeb, 0xbf, -0x28, 0x5f, 0xfc, 0xd1, 0x24, 0xf8, 0xe7, 0x79, -0x1f, 0xb8, 0xf8, 0xce, 0x53, 0xdc, 0x07, 0xf6, -0xb9, 0xdf, 0x27, 0xd4, 0x3f, 0x6b, 0xf8, 0x50, -0x25, 0xd1, 0x39, 0x1f, 0x9f, 0x7e, 0xb6, 0xdf, -0xbf, 0x00, 0x34, 0x34, 0xbf, 0x69, 0xee, 0x33, -0x01, 0x00, diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c deleted file mode 100644 index 71d16e4..0000000 --- a/board/esd/wuh405/wuh405.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <command.h> -#include <malloc.h> - -/* ------------------------------------------------------------------------- */ - -#if 0 -#define FPGA_DEBUG -#endif - -/* fpga configuration data - gzip compressed and generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ - - return 0; -} - -int misc_init_r (void) -{ - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - - /* - * Reset external DUARTs - */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST); - udelay(10); /* wait 10us */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); - udelay(1000); /* wait 1ms */ - - /* - * Enable interrupts in exar duart mcr[3] - */ - out_8((void *)(DUART0_BA + 4), 0x08); - out_8((void *)(DUART1_BA + 4), 0x08); - out_8((void *)(DUART2_BA + 4), 0x08); - out_8((void *)(DUART3_BA + 4), 0x08); - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming WUH405"); - } else { - puts(str); - } - - putc ('\n'); - - return 0; -} diff --git a/configs/WUH405_defconfig b/configs/WUH405_defconfig deleted file mode 100644 index dadea20..0000000 --- a/configs/WUH405_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_WUH405=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index dfab3d5..a385bde 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +WUH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> VOH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> PMC405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs(a)esd.eu> PCI405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs(a)esd.eu> diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h deleted file mode 100644 index e4f0d19..0000000 --- a/include/configs/WUH405.h +++ /dev/null @@ -1,346 +0,0 @@ -/* - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_IDENT_STRING " $Name: $" - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_WUH405 1 /* ...on a WUH405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 - -#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ - -#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* test-only */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART0_BA 0xF0000400 /* DUART Base Address */ -#define DUART1_BA 0xF0000408 /* DUART Base Address */ -#define DUART2_BA 0xF0000410 /* DUART Base Address */ -#define DUART3_BA 0xF0000418 /* DUART Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define CONFIG_SYS_NAND_BASE 0xF4000000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -#define CONFIG_SYS_GPIO0_OSRL 0x40000550 -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 - -#define CONFIG_SYS_DUART_RST (0x80000000 >> 14) - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 1 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ -- 1.7.9.5

2 1

[U-Boot] [PATCH 14/22] ppc4xx: remove VOH405 board
by Matthias Fuchs 13 Jan '15

13 Jan '15

Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- arch/powerpc/cpu/ppc4xx/Kconfig | 4 - board/esd/voh405/Kconfig | 12 - board/esd/voh405/MAINTAINERS | 6 - board/esd/voh405/Makefile | 10 - board/esd/voh405/flash.c | 85 - board/esd/voh405/fpgadata.c | 4021 --------------------------------- board/esd/voh405/logo_320_240_4bpp.c | 153 -- board/esd/voh405/logo_640_480_24bpp.c | 3443 ---------------------------- board/esd/voh405/voh405.c | 377 ---- configs/VOH405_defconfig | 3 - doc/README.scrapyard | 1 + include/configs/VOH405.h | 407 ---- 12 files changed, 1 insertion(+), 8521 deletions(-) delete mode 100644 board/esd/voh405/Kconfig delete mode 100644 board/esd/voh405/MAINTAINERS delete mode 100644 board/esd/voh405/Makefile delete mode 100644 board/esd/voh405/flash.c delete mode 100644 board/esd/voh405/fpgadata.c delete mode 100644 board/esd/voh405/logo_320_240_4bpp.c delete mode 100644 board/esd/voh405/logo_640_480_24bpp.c delete mode 100644 board/esd/voh405/voh405.c delete mode 100644 configs/VOH405_defconfig delete mode 100644 include/configs/VOH405.h diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index eddaee1..9884894 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -134,9 +134,6 @@ config TARGET_PMC405DE config TARGET_PMC440 bool "Support PMC440" -config TARGET_VOH405 - bool "Support VOH405" - config TARGET_VOM405 bool "Support VOM405" @@ -223,7 +220,6 @@ source "board/esd/cpci405/Kconfig" source "board/esd/plu405/Kconfig" source "board/esd/pmc405de/Kconfig" source "board/esd/pmc440/Kconfig" -source "board/esd/voh405/Kconfig" source "board/esd/vom405/Kconfig" source "board/esd/wuh405/Kconfig" source "board/g2000/Kconfig" diff --git a/board/esd/voh405/Kconfig b/board/esd/voh405/Kconfig deleted file mode 100644 index d9fe9d2..0000000 --- a/board/esd/voh405/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_VOH405 - -config SYS_BOARD - default "voh405" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "VOH405" - -endif diff --git a/board/esd/voh405/MAINTAINERS b/board/esd/voh405/MAINTAINERS deleted file mode 100644 index 0039f5d..0000000 --- a/board/esd/voh405/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -VOH405 BOARD -M: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> -S: Maintained -F: board/esd/voh405/ -F: include/configs/VOH405.h -F: configs/VOH405_defconfig diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile deleted file mode 100644 index 3d82399..0000000 --- a/board/esd/voh405/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = voh405.o flash.o \ - ../common/misc.o \ - ../common/esd405ep_nand.o \ diff --git a/board/esd/voh405/flash.c b/board/esd/voh405/flash.c deleted file mode 100644 index 23e8164..0000000 --- a/board/esd/voh405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Setup offsets */ - flash_get_offsets (-size_b0, &flash_info[0]); - - /* Re-do sizing to get full correct info */ - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b0 = -size_b0; - switch (size_b0) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - } - pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(EBC0_CFGDATA, pbcr); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} diff --git a/board/esd/voh405/fpgadata.c b/board/esd/voh405/fpgadata.c deleted file mode 100644 index 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0xec, 0x87, 0x01, 0xfa, 0xef, 0xa5, 0x6f, -0x44, 0x0a, 0x1a, 0x00, 0x00, 0x00, 0x28, 0x84, -0xb6, 0xcd, 0x09, 0x36, 0x05, 0xbd, 0xe6, 0x21, -0xd3, 0x4b, 0x04, 0x00, 0x00, 0x00, 0x42, 0x07, -0xf5, 0xb6, 0xd0, 0xe5, 0x6f, 0x0e, 0xd0, 0x7f, -0x1f, 0xf8, 0xf2, 0xff, 0x07, 0x66, 0x87, 0xe4, -0x0f, 0x36, 0x10, 0x0e, 0x00, diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c deleted file mode 100644 index 3cc2206..0000000 --- a/board/esd/voh405/voh405.c +++ /dev/null @@ -1,377 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <command.h> -#include <malloc.h> - -/* ------------------------------------------------------------------------- */ - -#if 0 -#define FPGA_DEBUG -#endif - -extern void lxt971_no_sleep(void); - -/* fpga configuration data - gzip compressed and generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -/* logo bitmap data - gzip compressed and generated by bin2c */ -unsigned char logo_bmp_320[] = -{ -#include "logo_320_240_4bpp.c" -}; - -unsigned char logo_bmp_640[] = -{ -#include "logo_640_480_24bpp.c" -}; - - -/* - * include common lcd code (for esd boards) - */ -#include "../common/lcd.c" - -#include "../common/s1d13704_320_240_4bpp.h" -#include "../common/s1d13806_320_240_4bpp.h" -#include "../common/s1d13806_640_480_16bpp.h" - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFFB5); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ - - return 0; -} - -int misc_init_r (void) -{ - unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); - unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); - unsigned short *lcd_contrast = - (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4); - unsigned short *lcd_backlight = - (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6); - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - char *str; - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_INIT pin - */ - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */ - udelay(1000); /* wait 1ms */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */ - udelay(1000); /* wait 1ms */ - - /* - * Reset external DUARTs - */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */ - udelay(10); /* wait 10us */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */ - udelay(1000); /* wait 1ms */ - - /* - * Set NAND-FLASH GPIO signals to default - */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE); - - /* - * Setup EEPROM write protection - */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP); - - /* - * Enable interrupts in exar duart mcr[3] - */ - out_8(duart0_mcr, 0x08); - out_8(duart1_mcr, 0x08); - - /* - * Init lcd interface and display logo - */ - str = getenv("bd_type"); - if (strcmp(str, "voh405_bw") == 0) { - lcd_setup(0, 1); - lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, - regs_13704_320_240_4bpp, - sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), - logo_bmp_320, sizeof(logo_bmp_320)); - } else if (strcmp(str, "voh405_bwbw") == 0) { - lcd_setup(0, 1); - lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, - regs_13704_320_240_4bpp, - sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), - logo_bmp_320, sizeof(logo_bmp_320)); - lcd_setup(1, 1); - lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, - regs_13806_320_240_4bpp, - sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]), - logo_bmp_320, sizeof(logo_bmp_320)); - } else if (strcmp(str, "voh405_bwc") == 0) { - lcd_setup(0, 1); - lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, - regs_13704_320_240_4bpp, - sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), - logo_bmp_320, sizeof(logo_bmp_320)); - lcd_setup(1, 0); - lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, - regs_13806_640_480_16bpp, - sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), - logo_bmp_640, sizeof(logo_bmp_640)); - } else { - printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); - return 0; - } - - /* - * Set invert bit in small lcd controller - */ - out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2), - in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2)) | 0x01); - - /* - * Set default contrast voltage on epson vga controller - */ - out_be16(lcd_contrast, 0x4646); - - /* - * Enable backlight - */ - out_be16(lcd_backlight, 0xffff); - - /* - * Enable external I2C bus - */ - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_IIC_ON); - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming VOH405"); - } else { - puts(str); - } - - if (getenv_f("bd_type", str, sizeof(str)) != -1) { - printf(" (%s)", str); - } else { - puts(" (Missing bd_type!)"); - } - - putc ('\n'); - - return 0; -} - -#ifdef CONFIG_IDE_RESET -#define FPGA_MODE (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL) -void ide_set_reset(int on) -{ - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { /* assert RESET */ - out_be16((void *)FPGA_MODE, - in_be16((void *)FPGA_MODE) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET); - } else { /* release RESET */ - out_be16((void *)FPGA_MODE, - in_be16((void *)FPGA_MODE) | CONFIG_SYS_FPGA_CTRL_CF_RESET); - } -} -#endif /* CONFIG_IDE_RESET */ - -#if defined(CONFIG_RESET_PHY_R) -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} -#endif - -#if defined(CONFIG_SYS_EEPROM_WREN) -/* Input: <dev_addr> I2C address of EEPROM device to enable. - * <state> -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if <state> was -1. - */ -int eeprom_write_enable (unsigned dev_addr, int state) -{ - if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO0. */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO0. */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in_be32((void*)GPIO0_OR) & CONFIG_SYS_EEPROM_WP)); - break; - } - } - return state; -} - -int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); - if (state < 0) { - puts ("Query of write access state failed.\n"); - } else { - printf ("Write access for device 0x%0x is %sabled.\n", - CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); - } - if (state < 0) { - puts ("Setup of write access state failed.\n"); - } - } - - return state; -} - -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - "" -); -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/configs/VOH405_defconfig b/configs/VOH405_defconfig deleted file mode 100644 index 1fbe91a..0000000 --- a/configs/VOH405_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_VOH405=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 24a5d93..dfab3d5 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +VOH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> PMC405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs(a)esd.eu> PCI405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs(a)esd.eu> OCRTC ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs(a)esd.eu> diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h deleted file mode 100644 index d4a4b68..0000000 --- a/include/configs/VOH405.h +++ /dev/null @@ -1,407 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_VOH405 1 /* ...on a VOH405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_HAS_ETH1 - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 - -#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ - -#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CONFIG_SYS_NAND_QUIET 1 - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0010 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFF80000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */ - -#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) -# define CONFIG_SYS_RAMBOOT 1 -#else -# undef CONFIG_SYS_RAMBOOT -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -#define CONFIG_SYS_EEPROM_WREN 1 - -/* CAT24WC32/64... */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART0_BA 0xF0000400 /* DUART Base Address */ -#define DUART1_BA 0xF0000408 /* DUART Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define VGA_BA 0xF1000000 /* Epson VGA Base Address */ -#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (Epson VGA) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ -#define CONFIG_SYS_EBC_PB4CR VGA_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */ - -/*----------------------------------------------------------------------- - * LCD Setup - */ - -#define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ -#define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ -#define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ -#define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ - -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20) - -/*----------------------------------------------------------------------- - * FPGA stuff - */ - -#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ - -/* FPGA internal regs */ -#define CONFIG_SYS_FPGA_CTRL 0x000 - -/* FPGA Control Reg */ -#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001 -#define CONFIG_SYS_FPGA_CTRL_WDI 0x0002 -#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020 - -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO - */ -#define CONFIG_SYS_GPIO0_OSRL 0x00000550 -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1H 0x15555440 -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0x777E0017 - -#define CONFIG_SYS_DUART_RST (0x80000000 >> 14) -#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7) -#define CONFIG_SYS_IIC_ON (0x80000000 >> 8) -#define CONFIG_SYS_LCD0_RST (0x80000000 >> 30) -#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31) -#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0) - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 1 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ -- 1.7.9.5

2 1

[U-Boot] [PATCH 13/22] ppc4xx: remove PMC405 board
by Matthias Fuchs 13 Jan '15

13 Jan '15

Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- arch/powerpc/cpu/ppc4xx/Kconfig | 4 - board/esd/pmc405/Kconfig | 12 -- board/esd/pmc405/MAINTAINERS | 6 - board/esd/pmc405/Makefile | 13 -- board/esd/pmc405/pmc405.c | 142 ----------------- configs/PMC405_defconfig | 3 - doc/README.scrapyard | 1 + include/configs/PMC405.h | 318 --------------------------------------- 8 files changed, 1 insertion(+), 498 deletions(-) delete mode 100644 board/esd/pmc405/Kconfig delete mode 100644 board/esd/pmc405/MAINTAINERS delete mode 100644 board/esd/pmc405/Makefile delete mode 100644 board/esd/pmc405/pmc405.c delete mode 100644 configs/PMC405_defconfig delete mode 100644 include/configs/PMC405.h diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 0e8cbf3..eddaee1 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -128,9 +128,6 @@ config TARGET_CPCI405DT config TARGET_PLU405 bool "Support PLU405" -config TARGET_PMC405 - bool "Support PMC405" - config TARGET_PMC405DE bool "Support PMC405DE" @@ -224,7 +221,6 @@ source "board/dave/PPChameleonEVB/Kconfig" source "board/esd/cpci2dp/Kconfig" source "board/esd/cpci405/Kconfig" source "board/esd/plu405/Kconfig" -source "board/esd/pmc405/Kconfig" source "board/esd/pmc405de/Kconfig" source "board/esd/pmc440/Kconfig" source "board/esd/voh405/Kconfig" diff --git a/board/esd/pmc405/Kconfig b/board/esd/pmc405/Kconfig deleted file mode 100644 index 3738c68..0000000 --- a/board/esd/pmc405/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_PMC405 - -config SYS_BOARD - default "pmc405" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "PMC405" - -endif diff --git a/board/esd/pmc405/MAINTAINERS b/board/esd/pmc405/MAINTAINERS deleted file mode 100644 index 148a596..0000000 --- a/board/esd/pmc405/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PMC405 BOARD -M: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> -S: Maintained -F: board/esd/pmc405/ -F: include/configs/PMC405.h -F: configs/PMC405_defconfig diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile deleted file mode 100644 index ad98207..0000000 --- a/board/esd/pmc405/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# Objects for Xilinx JTAG programming (CPLD) -CPLD = ../common/xilinx_jtag/lenval.o \ - ../common/xilinx_jtag/micro.o \ - ../common/xilinx_jtag/ports.o - -obj-y = pmc405.o ../common/misc.o ../common/cmd_loadpci.o $(CPLD) diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c deleted file mode 100644 index e67ff30..0000000 --- a/board/esd/pmc405/pmc405.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, DENX Software Engineering, sr(a)denx.de. - * - * (C) Copyright 2005-2009 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <command.h> -#include <malloc.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern void lxt971_no_sleep(void); - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: - * set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); - - /* - * Setup GPIO pins - */ - mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_FPGA_INIT | - CONFIG_SYS_FPGA_DONE | - CONFIG_SYS_XEREADY | - CONFIG_SYS_NONMONARCH | - CONFIG_SYS_REV1_2) << 5)); - - if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) { - /* rev 1.2 boards */ - mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_INTA_FAKE | - CONFIG_SYS_SELF_RST) << 5)); - } - - out_be32((void *)GPIO0_OR, CONFIG_SYS_VPEN); - /* setup for output */ - out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | - CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN); - - /* - * - check if rev1_2 is low, then: - * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST - * in TCR to assert INTA# or SELFRST# - */ - return 0; -} - -int misc_init_r (void) -{ - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* deassert EREADY# */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_XEREADY); - return (0); -} - -ushort pmc405_pci_subsys_deviceid(void) -{ - ulong val; - - val = in_be32((void *)GPIO0_IR); - if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */ - /* check monarch# signal */ - if (val & CONFIG_SYS_NONMONARCH) - return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH; - return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH; - } - return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH; -} - -/* - * Check Board Identity - */ -int checkboard (void) -{ - ulong val; - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) - puts ("### No HW ID - assuming PMC405"); - else - puts(str); - - val = in_be32((void *)GPIO0_IR); - if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */ - puts(" rev1.2 ("); - if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */ - puts("non-"); - puts("monarch)"); - } else - puts(" <=rev1.1"); - - putc ('\n'); - - return 0; -} - -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} diff --git a/configs/PMC405_defconfig b/configs/PMC405_defconfig deleted file mode 100644 index d82117c..0000000 --- a/configs/PMC405_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_PMC405=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index a41d942..24a5d93 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +PMC405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs(a)esd.eu> PCI405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs(a)esd.eu> OCRTC ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs(a)esd.eu> HUB405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h deleted file mode 100644 index c68d9a6..0000000 --- a/include/configs/PMC405.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_PMC405 1 /* ...on a PMC405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -/* Only interrupt boot if space is pressed. */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#undef CONFIG_AUTOBOOT_DELAY_STR -#define CONFIG_AUTOBOOT_STOP_STR " " - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CFG_BOOTM_LEN 0x1000000 /* support booting of huge images */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_HAS_ETH1 - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PING -#define CONFIG_CMD_UNIVERSE -#define CONFIG_CMD_EEPROM - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible */ -#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */ -#define CONFIG_SYS_BASE_BAUD 806400 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 - -/* - * PCI stuff - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid() - -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* Processor/PPC */ - -#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */ -#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ - -#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* 128 kB for malloc() */ - -#define CONFIG_PRAM 0 /* use pram variable to overwrite */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * FLASH organization - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */ -#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}} -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT} -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on fli */ - -/* - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ - -/* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_OFFSET 0x000 -#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ - -/* - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24W16 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24W16 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ - -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * External Bus Controller (EBC) Setup - */ -#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ -#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ -#define CAN_BA 0xF0000000 /* CAN Base Addres */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -/* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */ -#define CONFIG_SYS_EBC_PB0CR (FLASH0_BA | 0x9A000) - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -/* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/ -#define CONFIG_SYS_EBC_PB1CR (FLASH1_BA | 0x9A000) - -/* Memory Bank 2 (CAN0, 1, RTC) initialization */ -/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ -#define CONFIG_SYS_EBC_PB2AP 0x03000440 -/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#define CONFIG_SYS_EBC_PB2CR (CAN_BA | 0x18000) - -/* Memory Bank 3 -> unused */ - -/* Memory Bank 4 (NVRAM) initialization */ -/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ -#define CONFIG_SYS_EBC_PB4AP 0x03000440 -/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#define CONFIG_SYS_EBC_PB4CR (NVRAM_BA | 0x18000) - -/* - * FPGA stuff - */ -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO pin (output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI pin (input) */ - -/* pass Ethernet MAC to VxWorks */ -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 - -/* - * GPIOs - */ -#define CONFIG_SYS_VPEN (0x80000000 >> 3) /* GPIO3 */ -#define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO14 */ -#define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */ -#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */ -#define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */ -#define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */ - -/* - * Definitions for initial stack pointer and data area (in data cache) - */ - -/* use on chip memory (OCM) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -/* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR - -/* End of used area in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP - -#endif /* __CONFIG_H */ -- 1.7.9.5

2 1

[U-Boot] [PATCH 12/22] ppc4xx: remove PCI405 board
by Matthias Fuchs 13 Jan '15

13 Jan '15

Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- arch/powerpc/cpu/ppc4xx/Kconfig | 4 - board/esd/pci405/Kconfig | 12 - board/esd/pci405/MAINTAINERS | 6 - board/esd/pci405/Makefile | 9 - board/esd/pci405/cmd_pci405.c | 97 --- board/esd/pci405/flash.c | 85 --- board/esd/pci405/fpgadata.c | 1492 --------------------------------------- board/esd/pci405/pci405.c | 366 ---------- board/esd/pci405/pci405.h | 16 - board/esd/pci405/writeibm.S | 205 ------ configs/PCI405_defconfig | 3 - doc/README.scrapyard | 1 + include/configs/PCI405.h | 294 -------- 13 files changed, 1 insertion(+), 2589 deletions(-) delete mode 100644 board/esd/pci405/Kconfig delete mode 100644 board/esd/pci405/MAINTAINERS delete mode 100644 board/esd/pci405/Makefile delete mode 100644 board/esd/pci405/cmd_pci405.c delete mode 100644 board/esd/pci405/flash.c delete mode 100644 board/esd/pci405/fpgadata.c delete mode 100644 board/esd/pci405/pci405.c delete mode 100644 board/esd/pci405/pci405.h delete mode 100644 board/esd/pci405/writeibm.S delete mode 100644 configs/PCI405_defconfig delete mode 100644 include/configs/PCI405.h diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index ea4227e..0e8cbf3 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -125,9 +125,6 @@ config TARGET_CPCI405AB config TARGET_CPCI405DT bool "Support CPCI405DT" -config TARGET_PCI405 - bool "Support PCI405" - config TARGET_PLU405 bool "Support PLU405" @@ -226,7 +223,6 @@ source "board/csb472/Kconfig" source "board/dave/PPChameleonEVB/Kconfig" source "board/esd/cpci2dp/Kconfig" source "board/esd/cpci405/Kconfig" -source "board/esd/pci405/Kconfig" source "board/esd/plu405/Kconfig" source "board/esd/pmc405/Kconfig" source "board/esd/pmc405de/Kconfig" diff --git a/board/esd/pci405/Kconfig b/board/esd/pci405/Kconfig deleted file mode 100644 index 0a6524d..0000000 --- a/board/esd/pci405/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_PCI405 - -config SYS_BOARD - default "pci405" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "PCI405" - -endif diff --git a/board/esd/pci405/MAINTAINERS b/board/esd/pci405/MAINTAINERS deleted file mode 100644 index cf9c1c9..0000000 --- a/board/esd/pci405/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PCI405 BOARD -M: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> -S: Maintained -F: board/esd/pci405/ -F: include/configs/PCI405.h -F: configs/PCI405_defconfig diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile deleted file mode 100644 index 9e659c7..0000000 --- a/board/esd/pci405/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = pci405.o flash.o ../common/misc.o cmd_pci405.o -obj-y += writeibm.o diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c deleted file mode 100644 index 29c688a..0000000 --- a/board/esd/pci405/cmd_pci405.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <malloc.h> -#include <net.h> -#include <asm/io.h> -#include <pci.h> -#include <asm/4xx_pci.h> -#include <asm/processor.h> - -#include "pci405.h" - -#if defined(CONFIG_CMD_BSP) - -/* - * Command loadpci: wait for signal from host and boot image. - */ -int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned int *ptr; - int count = 0; - int count2 = 0; - int i; - char addr[16]; - char str[] = "\\|/-"; - char *local_args[2]; - - /* - * Mark sync address - */ - ptr = 0; - /* cppcheck-suppress nullPointer */ - *ptr = 0xffffffff; - puts("\nWaiting for image from pci host -"); - - /* - * Wait for host to write the start address - */ - /* cppcheck-suppress nullPointer */ - while (*ptr == 0xffffffff) { - count++; - if (!(count % 100)) { - count2++; - putc(0x08); /* backspace */ - putc(str[count2 % 4]); - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - udelay(1000); - } - - if (*ptr == PCI_RECONFIG_MAGIC) { - /* - * Save own pci configuration in PRAM - */ - memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN); - ptr = (unsigned int *)PCI_REGS_ADDR + 1; - for (i=0; i<0x40; i+=4) { - pci_read_config_dword(PCIDEVID_405GP, i, ptr++); - } - ptr = (unsigned int *)PCI_REGS_ADDR; - *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4); - - printf("\nStoring PCI Configuration Regs...\n"); - } else { - sprintf(addr, "%08x", *ptr); - - /* - * Boot image via bootm - */ - printf("\nBooting Image at addr 0x%s ...\n", addr); - setenv("loadaddr", addr); - - local_args[0] = argv[0]; - local_args[1] = NULL; - do_bootm (cmdtp, 0, 1, local_args); - } - - return 0; -} -U_BOOT_CMD( - loadpci, 1, 1, do_loadpci, - "Wait for pci-image and boot it", - "" -); -#endif diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c deleted file mode 100644 index 113111d..0000000 --- a/board/esd/pci405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Setup offsets */ - flash_get_offsets (-size_b0, &flash_info[0]); - - /* Re-do sizing to get full correct info */ - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b0 = -size_b0; - switch (size_b0) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - } - pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(EBC0_CFGDATA, pbcr); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -monitor_flash_len, - 0xffffffff, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} diff --git a/board/esd/pci405/fpgadata.c b/board/esd/pci405/fpgadata.c deleted file mode 100644 index d145826..0000000 --- a/board/esd/pci405/fpgadata.c +++ /dev/null @@ -1,1492 +0,0 @@ -0x1f, 0x8b, 0x08, 0x08, 0xcd, 0x78, 0x61, 0x3f, -0x00, 0x03, 0x70, 0x63, 0x69, 0x34, 0x30, 0x35, -0x5f, 0x31, 0x5f, 0x30, 0x34, 0x2e, 0x62, 0x69, -0x74, 0x00, 0xed, 0x9c, 0x7f, 0x78, 0x14, 0xc7, -0x99, 0xe7, 0xdf, 0xae, 0xee, 0x11, 0x2d, 0xcd, -0x88, 0x69, 0x89, 0x11, 0x1e, 0x3b, 0x32, 0xdb, -0x1a, 0x09, 0x3c, 0xc1, 0x23, 0x69, 0x18, 0x61, -0x85, 0x60, 0x79, 0xd4, 0x8c, 0x04, 0x19, 0x1b, -0xd9, 0x4c, 0x6c, 0x27, 0x61, 0xf3, 0xf8, 0xc9, -0x8e, 0x1d, 0x92, 0x23, 0x59, 0x92, 0x47, 0x90, -0xdc, 0x2e, 0x49, 0x9c, 0x6c, 0x8d, 0x24, 0xd0, -0x00, 0xb2, 0x19, 0x30, 0x97, 0xb0, 0x59, 0xce, -0x3b, 0x60, 0x12, 0x0b, 0x9b, 0x64, 0x07, 0x61, -0x1b, 0x61, 0x88, 0xdd, 0x92, 0x85, 0x23, 0x40, -0x06, 0x85, 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0xf7, 0xb6, 0xf9, 0xf4, 0xfa, 0xf4, -0xfa, 0xf4, 0xfa, 0xf4, 0xfa, 0xf4, 0xfa, 0xf4, -0xfa, 0xff, 0xe5, 0xd2, 0xf6, 0x49, 0xa2, 0xed, -0x93, 0xea, 0x7f, 0x76, 0x5f, 0x3e, 0xbd, 0x3e, -0xbd, 0x3e, 0xbd, 0x3e, 0xbd, 0x3e, 0xbd, 0x3e, -0xbd, 0xfe, 0x33, 0xae, 0x20, 0xfb, 0x73, 0x09, -0x50, 0xf9, 0x6b, 0xe3, 0xef, 0xff, 0xf3, 0x41, -0x50, 0xa6, 0xfd, 0xeb, 0xbf, 0xaf, 0xfd, 0x9e, -0x23, 0x08, 0x69, 0xce, 0x6a, 0xbf, 0x3b, 0x35, -0xb5, 0xaf, 0xff, 0x13, 0x87, 0x7b, 0xf6, 0xdd, -0xd4, 0x60, 0x00, 0x00, diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c deleted file mode 100644 index 566f6f7..0000000 --- a/board/esd/pci405/pci405.c +++ /dev/null @@ -1,366 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <command.h> -#include <malloc.h> -#include <pci.h> -#include <asm/4xx_pci.h> -#include <asm/io.h> - -#include "pci405.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* Prototypes */ -unsigned long fpga_done_state(void); -unsigned long fpga_init_state(void); - -#if 0 -#define FPGA_DEBUG -#endif - -/* predefine these here */ -#define FPGA_DONE_STATE (fpga_done_state()) -#define FPGA_INIT_STATE (fpga_init_state()) - -/* fpga configuration data - generated by bin2cc */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - -#define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE) -#define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12) - -#define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT) -#define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12) - - -int board_revision(void) -{ - unsigned long CPC0_CR0Reg; - unsigned long value; - - /* - * Get version of PCI405 board from GPIO's - */ - - /* - * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000); - out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200); - udelay(1000); /* wait some time before reading input */ - value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */ - - /* - * Restore GPIO settings - */ - mtdcr(CPC0_CR0, CPC0_CR0Reg); - - switch (value) { - case 0x00100200: - /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */ - return 1; - case 0x00000200: - /* CS2==0 && IRQ5==1 -> version 1.2 */ - return 2; - case 0x00000000: - /* CS2==0 && IRQ5==0 -> version 1.3 */ - return 3; -#if 0 /* not yet manufactured ! */ - case 0x00100000: - /* CS2==1 && IRQ5==0 -> version 1.4 */ - return 4; -#endif - default: - /* should not be reached! */ - return 0; - } -} - - -unsigned long fpga_done_state(void) -{ - if (gd->board_type < 2) { - return FPGA_DONE_STATE_V11; - } else { - return FPGA_DONE_STATE_V12; - } -} - - -unsigned long fpga_init_state(void) -{ - if (gd->board_type < 2) { - return FPGA_INIT_STATE_V11; - } else { - return FPGA_INIT_STATE_V12; - } -} - - -int board_early_init_f (void) -{ - unsigned long CPC0_CR0Reg; - - /* - * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board) - */ - out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */ - out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ - out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ - out_be32((void*)GPIO0_OR, 0); /* pull prg low */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive - * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive - * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive - * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive - * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * Setup GPIO pins (IRQ4/GPIO21 as GPIO) - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000); - - /* - * Setup GPIO pins (CS6+CS7 as GPIO) - */ - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us - */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ - - return 0; -} - -int misc_init_r (void) -{ - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - unsigned int *ptr; - unsigned int *magic; - - /* - * On PCI-405 the environment is saved in eeprom! - * FPGA can be gzip compressed (malloc) and booted this late. - */ - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - - /* - * Check if magic for pci reconfig is written - */ - magic = (unsigned int *)0x00000004; - if (*magic == PCI_RECONFIG_MAGIC) { - /* - * Rewrite pci config regs (only after soft-reset with magic set) - */ - ptr = (unsigned int *)PCI_REGS_ADDR; - if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) { - puts("Restoring PCI Configurations Regs!\n"); - ptr = (unsigned int *)PCI_REGS_ADDR + 1; - for (i=0; i<0x40; i+=4) { - pci_write_config_dword(PCIDEVID_405GP, i, *ptr++); - } - } - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - *magic = 0; /* clear pci reconfig magic again */ - } - - /* - * Decrease PLB latency timeout and reduce priority of the PCI bridge master - */ -#define PCI0_BRDGOPT1 0x4a - pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20); - - /* - * Enable fairness and high bus utilization - */ - mtdcr(PLB0_ACR, 0x98000000); - - free(dst); - return (0); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming PCI405"); - } else { - puts (str); - } - - gd->board_type = board_revision(); - printf(" (Rev 1.%ld", gd->board_type); - - if (gd->board_type >= 2) { - unsigned long CPC0_CR0Reg; - unsigned long value; - - /* - * Setup GPIO pins (Trace/GPIO1 to GPIO) - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000); - out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000); - udelay(1000); /* wait some time before reading input */ - value = in_be32((void*)GPIO0_IR) & 0x40000000; /* get config bits */ - if (value) { - puts(", 33 MHz PCI"); - } else { - puts(", 66 MHz PCI"); - } - } - - puts(")\n"); - - return 0; -} - -/* ------------------------------------------------------------------------- */ -#define UART1_MCR 0xef600404 -int wpeeprom(int wp) -{ - int wp_state = wp; - - if (wp == 1) { - out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02); - } else if (wp == 0) { - out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02); - } else { - if (in_8((void *)UART1_MCR) & 0x02) { - wp_state = 0; - } else { - wp_state = 1; - } - } - return wp_state; -} - -int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int wp = -1; - if (argc >= 2) { - if (argv[1][0] == '1') { - wp = 1; - } else if (argv[1][0] == '0') { - wp = 0; - } - } - - wp = wpeeprom(wp); - printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED"); - return 0; -} - -U_BOOT_CMD( - wpeeprom, 2, 1, do_wpeeprom, - "Check/Enable/Disable I2C EEPROM write protection", - "wpeeprom\n" - " - check I2C EEPROM write protection state\n" - "wpeeprom 1\n" - " - enable I2C EEPROM write protection\n" - "wpeeprom 0\n" - " - disable I2C EEPROM write protection" -); diff --git a/board/esd/pci405/pci405.h b/board/esd/pci405/pci405.h deleted file mode 100644 index a62c9c2..0000000 --- a/board/esd/pci405/pci405.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PCI405_H_ -#define _PCI405_H_ - -#define PCI_REGS_LEN 0x100 -#define PCI_REGS_ADDR ((unsigned long)0x01000000 - PCI_REGS_LEN) - -#define PCI_RECONFIG_MAGIC 0x07081967 - -#endif /* _PCI405_H_ */ diff --git a/board/esd/pci405/writeibm.S b/board/esd/pci405/writeibm.S deleted file mode 100644 index 03eaf97..0000000 --- a/board/esd/pci405/writeibm.S +++ /dev/null @@ -1,205 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ -/*----------------------------------------------------------------------------- */ -/* Function: ext_bus_cntlr_init */ -/* Description: Initializes the External Bus Controller for the external */ -/* peripherals. IMPORTANT: For pass1 this code must run from */ -/* cache since you can not reliably change a peripheral banks */ -/* timing register (pbxap) while running code from that bank. */ -/* For ex., since we are running from ROM on bank 0, we can NOT */ -/* execute the code that modifies bank 0 timings from ROM, so */ -/* we run it from cache. */ -/* Bank 0 - Flash and SRAM */ -/* Bank 1 - NVRAM/RTC */ -/* Bank 2 - Keyboard/Mouse controller */ -/* Bank 3 - IR controller */ -/* Bank 4 - not used */ -/* Bank 5 - not used */ -/* Bank 6 - not used */ -/* Bank 7 - FPGA registers */ -/*----------------------------------------------------------------------------- */ -#include <asm/ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - - - .globl write_without_sync -write_without_sync: - /* - * Write one values to host via pci busmastering - * ptr = 0xc0000000 -> 0x01000000 (PCI) - * *ptr = 0x01234567; - */ - addi r31,0,0 - lis r31,0xc000 - -start1: - lis r0,0x0123 - ori r0,r0,0x4567 - stw r0,0(r31) - - /* - * Read one value back - * ptr = (volatile unsigned long *)addr; - * val = *ptr; - */ - - lwz r0,0(r31) - - /* - * One pci config write - * ibmPciConfigWrite(0x2e, 2, 0x1234); - */ - /* subsystem id */ - - li r4,0x002C - oris r4,r4,0x8000 - lis r3,0xEEC0 - stwbrx r4,0,r3 - - li r5,0x1234 - ori r3,r3,0x4 - stwbrx r5,0,r3 - - b start1 - - blr /* never reached !!!! */ - - .globl write_with_sync -write_with_sync: - /* - * Write one values to host via pci busmastering - * ptr = 0xc0000000 -> 0x01000000 (PCI) - * *ptr = 0x01234567; - */ - addi r31,0,0 - lis r31,0xc000 - -start2: - lis r0,0x0123 - ori r0,r0,0x4567 - stw r0,0(r31) - - /* - * Read one value back - * ptr = (volatile unsigned long *)addr; - * val = *ptr; - */ - - lwz r0,0(r31) - - /* - * One pci config write - * ibmPciConfigWrite(0x2e, 2, 0x1234); - */ - /* subsystem id */ - - li r4,0x002C - oris r4,r4,0x8000 - lis r3,0xEEC0 - stwbrx r4,0,r3 - sync - - li r5,0x1234 - ori r3,r3,0x4 - stwbrx r5,0,r3 - sync - - b start2 - - blr /* never reached !!!! */ - - .globl write_with_less_sync -write_with_less_sync: - /* - * Write one values to host via pci busmastering - * ptr = 0xc0000000 -> 0x01000000 (PCI) - * *ptr = 0x01234567; - */ - addi r31,0,0 - lis r31,0xc000 - -start2b: - lis r0,0x0123 - ori r0,r0,0x4567 - stw r0,0(r31) - - /* - * Read one value back - * ptr = (volatile unsigned long *)addr; - * val = *ptr; - */ - - lwz r0,0(r31) - - /* - * One pci config write - * ibmPciConfigWrite(0x2e, 2, 0x1234); - */ - /* subsystem id */ - - li r4,0x002C - oris r4,r4,0x8000 - lis r3,0xEEC0 - stwbrx r4,0,r3 - sync - - li r5,0x1234 - ori r3,r3,0x4 - stwbrx r5,0,r3 -/* sync */ - - b start2b - - blr /* never reached !!!! */ - - .globl write_with_more_sync -write_with_more_sync: - /* - * Write one values to host via pci busmastering - * ptr = 0xc0000000 -> 0x01000000 (PCI) - * *ptr = 0x01234567; - */ - addi r31,0,0 - lis r31,0xc000 - -start3: - lis r0,0x0123 - ori r0,r0,0x4567 - stw r0,0(r31) - sync - - /* - * Read one value back - * ptr = (volatile unsigned long *)addr; - * val = *ptr; - */ - - lwz r0,0(r31) - sync - - /* - * One pci config write - * ibmPciConfigWrite(0x2e, 2, 0x1234); - */ - /* subsystem id (PCIC0_SBSYSVID)*/ - - li r4,0x002C - oris r4,r4,0x8000 - lis r3,0xEEC0 - stwbrx r4,0,r3 - sync - - li r5,0x1234 - ori r3,r3,0x4 - stwbrx r5,0,r3 - sync - - b start3 - - blr /* never reached !!!! */ diff --git a/configs/PCI405_defconfig b/configs/PCI405_defconfig deleted file mode 100644 index 48f19fe..0000000 --- a/configs/PCI405_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_PCI405=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 0b449d1..a41d942 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +PCI405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs(a)esd.eu> OCRTC ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs(a)esd.eu> HUB405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> HH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h deleted file mode 100644 index 0989407..0000000 --- a/include/configs/PCI405.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * (C) Copyright 2007 - * Matthias Fuchs, esd gmbh, matthias.fuchs(a)esd-electronics.com - * - * (C) Copyright 2001-2004 - * Stefan Roese, DENX Software Engineering, sr(a)denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_PCI405 1 /* ...on a PCI405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFD0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ - -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 0 /* autoboot after 0 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mem_linux=14336k\0" \ - "optargs=panic=0\0" \ - "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \ - "addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \ - "" -#define CONFIG_BOOTCOMMAND "run ramargs;run addcons;loadpci" - -#define CONFIG_PREBOOT /* enable preboot variable */ - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_ITEST -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */ - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#undef CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */ -#undef CONFIG_PCI_PNP /* no pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ - -#define CONFIG_SYS_PCI_PTM2LA 0xef600000 /* point to internal regs */ -#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFD0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/ - /* total size of a CAT24WC08 is 1024 bytes */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (NVRAM/RTC) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */ -#define CONFIG_SYS_EBC_PB1CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (CAN0, 1) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -/*#define CONFIG_SYS_EBC_PB2AP 0x038056C0 / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (FPGA internal) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF041C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */ -#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CONFIG_SYS_FPGA_MODE 0x00 -#define CONFIG_SYS_FPGA_STATUS 0x02 -#define CONFIG_SYS_FPGA_TS 0x04 -#define CONFIG_SYS_FPGA_TS_LOW 0x06 -#define CONFIG_SYS_FPGA_TS_CAP0 0x10 -#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 -#define CONFIG_SYS_FPGA_TS_CAP1 0x14 -#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 -#define CONFIG_SYS_FPGA_TS_CAP2 0x18 -#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a -#define CONFIG_SYS_FPGA_TS_CAP3 0x1c -#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 -#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 - -/* FPGA Status Reg */ -#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 -#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 -#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 -#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 -#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 - -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ -/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support) */ -#define CONFIG_SYS_FPGA_INIT_V12 0x00008000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE_V12 0x00010000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ -- 1.7.9.5

2 1

[U-Boot] [PATCH 11/22] ppc4xx: remove OCRTC board
by Matthias Fuchs 13 Jan '15

13 Jan '15

Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- arch/powerpc/cpu/ppc4xx/Kconfig | 4 - board/esd/ocrtc/Kconfig | 12 -- board/esd/ocrtc/MAINTAINERS | 6 - board/esd/ocrtc/Makefile | 8 -- board/esd/ocrtc/cmd_ocrtc.c | 68 ---------- board/esd/ocrtc/flash.c | 140 ------------------- board/esd/ocrtc/ocrtc.c | 78 ----------- board/esd/ocrtc/ocrtc.h | 28 ---- configs/OCRTC_defconfig | 3 - doc/README.scrapyard | 1 + include/configs/OCRTC.h | 285 --------------------------------------- 11 files changed, 1 insertion(+), 632 deletions(-) delete mode 100644 board/esd/ocrtc/Kconfig delete mode 100644 board/esd/ocrtc/MAINTAINERS delete mode 100644 board/esd/ocrtc/Makefile delete mode 100644 board/esd/ocrtc/cmd_ocrtc.c delete mode 100644 board/esd/ocrtc/flash.c delete mode 100644 board/esd/ocrtc/ocrtc.c delete mode 100644 board/esd/ocrtc/ocrtc.h delete mode 100644 configs/OCRTC_defconfig delete mode 100644 include/configs/OCRTC.h diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index cab8f25..ea4227e 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -125,9 +125,6 @@ config TARGET_CPCI405AB config TARGET_CPCI405DT bool "Support CPCI405DT" -config TARGET_OCRTC - bool "Support OCRTC" - config TARGET_PCI405 bool "Support PCI405" @@ -229,7 +226,6 @@ source "board/csb472/Kconfig" source "board/dave/PPChameleonEVB/Kconfig" source "board/esd/cpci2dp/Kconfig" source "board/esd/cpci405/Kconfig" -source "board/esd/ocrtc/Kconfig" source "board/esd/pci405/Kconfig" source "board/esd/plu405/Kconfig" source "board/esd/pmc405/Kconfig" diff --git a/board/esd/ocrtc/Kconfig b/board/esd/ocrtc/Kconfig deleted file mode 100644 index 44b402d..0000000 --- a/board/esd/ocrtc/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_OCRTC - -config SYS_BOARD - default "ocrtc" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "OCRTC" - -endif diff --git a/board/esd/ocrtc/MAINTAINERS b/board/esd/ocrtc/MAINTAINERS deleted file mode 100644 index 85c1a12..0000000 --- a/board/esd/ocrtc/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -OCRTC BOARD -M: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> -S: Maintained -F: board/esd/ocrtc/ -F: include/configs/OCRTC.h -F: configs/OCRTC_defconfig diff --git a/board/esd/ocrtc/Makefile b/board/esd/ocrtc/Makefile deleted file mode 100644 index 44b7d5d..0000000 --- a/board/esd/ocrtc/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = ocrtc.o flash.o ../common/misc.o cmd_ocrtc.o diff --git a/board/esd/ocrtc/cmd_ocrtc.c b/board/esd/ocrtc/cmd_ocrtc.c deleted file mode 100644 index 6dcbd8b..0000000 --- a/board/esd/ocrtc/cmd_ocrtc.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <pci.h> -#include <pci_ids.h> -#include <asm/4xx_pci.h> - - -#if defined(CONFIG_CMD_BSP) - -/* - * Set device number on pci board - */ -int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int idx = 1; /* start at 1 (skip device 0) */ - pci_dev_t bdf = 0; - u32 addr; - - while (bdf >= 0) { - if ((bdf = pci_find_device(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_405GP, idx++)) < 0) { - break; - } - printf("Found device nr %d at %x!\n", idx-1, bdf); - pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr); - addr &= ~0xf; - *(u32 *)addr = (bdf & 0x0000f800) >> 11; - printf("Wrote %x at %x!\n", (bdf & 0x0000f800) >> 11, addr); - } - - return 0; -} -U_BOOT_CMD( - setdevice, 1, 1, do_setdevice, - "Set device number on pci adapter boards", - "" -); - - -/* - * Get device number on pci board - */ -int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - u32 device; - char str[32]; - - device = *(u32 *)0x0; - device = 0x16 - device; /* calculate vxworks bp slot id */ - sprintf(str, "%d", device); - setenv("slot", str); - printf("Variabel slot set to %x\n", device); - - return 0; -} -U_BOOT_CMD( - getdevice, 1, 1, do_getdevice, - "Get device number and set slot env variable", - "" -); - -#endif diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c deleted file mode 100644 index 279746e..0000000 --- a/board/esd/ocrtc/flash.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - base_b0 = FLASH_BASE0_PRELIM; - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - base_b1 = FLASH_BASE1_PRELIM; - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - mtdcr (EBC0_CFGADDR, PB0CR); - pbcr = mfdcr (EBC0_CFGDATA); - mtdcr (EBC0_CFGADDR, PB0CR); - base_b1 = -size_b1; - switch (size_b1) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - } - pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17); - mtdcr (EBC0_CFGDATA, pbcr); - /* printf("PB1CR = %x\n", pbcr); */ - } - - if (size_b0) { - mtdcr (EBC0_CFGADDR, PB1CR); - pbcr = mfdcr (EBC0_CFGDATA); - mtdcr (EBC0_CFGADDR, PB1CR); - base_b0 = base_b1 - size_b0; - switch (size_b1) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - } - pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr (EBC0_CFGDATA, pbcr); - /* printf("PB0CR = %x\n", pbcr); */ - } - - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - flash_get_offsets (base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - flash_get_offsets (base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b1 + size_b1 - monitor_flash_len, - base_b1 + size_b1 - 1, &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - flash_protect (FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c deleted file mode 100644 index b815961..0000000 --- a/board/esd/ocrtc/ocrtc.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include "ocrtc.h" -#include <asm/processor.h> -#include <i2c.h> -#include <command.h> - - -extern void lxt971_no_sleep(void); - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: clear EBTC -> high-Z ebc signals between - * transfers, set device-paced timeout to 256 cycles - */ - mtebc (EBC0_CFG, 0x20400000); - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (i == -1) { -#ifdef CONFIG_OCRTC - puts ("### No HW ID - assuming OCRTC"); -#endif -#ifdef CONFIG_ORSG - puts ("### No HW ID - assuming ORSG"); -#endif - } else { - puts (str); - } - - putc ('\n'); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return (0); -} diff --git a/board/esd/ocrtc/ocrtc.h b/board/esd/ocrtc/ocrtc.h deleted file mode 100644 index 029e27e..0000000 --- a/board/esd/ocrtc/ocrtc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/configs/OCRTC_defconfig b/configs/OCRTC_defconfig deleted file mode 100644 index f2fd0c5..0000000 --- a/configs/OCRTC_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_OCRTC=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index d8bb3aa..0b449d1 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +OCRTC ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs(a)esd.eu> HUB405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> HH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> DU440 ppc4xx 440epx - - Matthias Fuchs <matthias.fuchs(a)esd.eu> diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h deleted file mode 100644 index 4680afe..0000000 --- a/include/configs/OCRTC.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_OCRTC 1 /* ...on a OCRTC board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFD0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "go fff00100" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_ELF -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0410 /* PCI Device ID: OCRTC */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFD0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ -#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */ - -#else /* Use EEPROM for environment variables */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (PLD - FPGA-boot) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (PLD - OSL) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 4 (Spartan2 1) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/ - -/* Memory Bank 5 (Spartan2 2) initialization */ -#define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/ - -/* Memory Bank 6 (Virtex 1) initialization */ -#define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 7 (Virtex 2) initialization */ -#define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/ - - -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ -- 1.7.9.5

2 1

[U-Boot] [PATCH 10/22] ppc4xx: remove HUB405 board
by Matthias Fuchs 13 Jan '15

13 Jan '15

Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- arch/powerpc/cpu/ppc4xx/Kconfig | 4 - board/esd/hub405/Kconfig | 12 -- board/esd/hub405/MAINTAINERS | 6 - board/esd/hub405/Makefile | 10 -- board/esd/hub405/flash.c | 85 ---------- board/esd/hub405/hub405.c | 208 ----------------------- configs/HUB405_defconfig | 3 - doc/README.scrapyard | 1 + include/configs/HUB405.h | 351 --------------------------------------- 9 files changed, 1 insertion(+), 679 deletions(-) delete mode 100644 board/esd/hub405/Kconfig delete mode 100644 board/esd/hub405/MAINTAINERS delete mode 100644 board/esd/hub405/Makefile delete mode 100644 board/esd/hub405/flash.c delete mode 100644 board/esd/hub405/hub405.c delete mode 100644 configs/HUB405_defconfig delete mode 100644 include/configs/HUB405.h diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 8ce66d6..cab8f25 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -125,9 +125,6 @@ config TARGET_CPCI405AB config TARGET_CPCI405DT bool "Support CPCI405DT" -config TARGET_HUB405 - bool "Support HUB405" - config TARGET_OCRTC bool "Support OCRTC" @@ -232,7 +229,6 @@ source "board/csb472/Kconfig" source "board/dave/PPChameleonEVB/Kconfig" source "board/esd/cpci2dp/Kconfig" source "board/esd/cpci405/Kconfig" -source "board/esd/hub405/Kconfig" source "board/esd/ocrtc/Kconfig" source "board/esd/pci405/Kconfig" source "board/esd/plu405/Kconfig" diff --git a/board/esd/hub405/Kconfig b/board/esd/hub405/Kconfig deleted file mode 100644 index 2b9556a..0000000 --- a/board/esd/hub405/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_HUB405 - -config SYS_BOARD - default "hub405" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "HUB405" - -endif diff --git a/board/esd/hub405/MAINTAINERS b/board/esd/hub405/MAINTAINERS deleted file mode 100644 index e84a1d9..0000000 --- a/board/esd/hub405/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -HUB405 BOARD -M: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> -S: Maintained -F: board/esd/hub405/ -F: include/configs/HUB405.h -F: configs/HUB405_defconfig diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile deleted file mode 100644 index 99e18b5..0000000 --- a/board/esd/hub405/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = hub405.o flash.o \ - ../common/misc.o \ - ../common/esd405ep_nand.o \ diff --git a/board/esd/hub405/flash.c b/board/esd/hub405/flash.c deleted file mode 100644 index 23e8164..0000000 --- a/board/esd/hub405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Setup offsets */ - flash_get_offsets (-size_b0, &flash_info[0]); - - /* Re-do sizing to get full correct info */ - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b0 = -size_b0; - switch (size_b0) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - } - pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(EBC0_CFGDATA, pbcr); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c deleted file mode 100644 index 1423744..0000000 --- a/board/esd/hub405/hub405.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <command.h> -#include <malloc.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern void lxt971_no_sleep(void); - -int board_revision(void) -{ - unsigned long osrl_reg; - unsigned long isr1l_reg; - unsigned long tcr_reg; - unsigned long value; - - /* - * Get version of HUB405 board from GPIO's - */ - - /* - * Setup GPIO pin(s) (IRQ6/GPIO23) - */ - osrl_reg = in_be32((void *)GPIO0_OSRH); - isr1l_reg = in_be32((void *)GPIO0_ISR1H); - tcr_reg = in_be32((void *)GPIO0_TCR); - out_be32((void *)GPIO0_OSRH, osrl_reg & ~0x00030000); /* output select */ - out_be32((void *)GPIO0_ISR1H, isr1l_reg | 0x00030000); /* input select */ - out_be32((void *)GPIO0_TCR, tcr_reg & ~0x00000100); /* select input */ - - udelay(1000); /* wait some time before reading input */ - value = in_be32((void *)GPIO0_IR) & 0x00000100; /* get config bits */ - - /* - * Restore GPIO settings - */ - out_be32((void *)GPIO0_OSRH, osrl_reg); /* output select */ - out_be32((void *)GPIO0_ISR1H, isr1l_reg); /* input select */ - out_be32((void *)GPIO0_TCR, tcr_reg); /* enable output driver for outputs */ - - if (value & 0x00000100) { - /* Revision 1.1 or 1.2 detected */ - return 1; - } - - /* Revision 1.0 */ - return 0; -} - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ - - return 0; -} - -#define LED_REG (DUART0_BA + 0x20) -int misc_init_r (void) -{ - unsigned long val; - int delay, flashcnt; - char *str; - char hw_rev[4]; - - /* - * Enable interrupts in exar duart mcr[3] - */ - out_8((void *)(DUART0_BA + 4), 0x08); - out_8((void *)(DUART1_BA + 4), 0x08); - out_8((void *)(DUART2_BA + 4), 0x08); - out_8((void *)(DUART3_BA + 4), 0x08); - - /* - * Set RS232/RS422 control (RS232 = high on GPIO) - */ - val = in_be32((void *)GPIO0_OR); - val &= ~(CONFIG_SYS_UART2_RS232 | CONFIG_SYS_UART3_RS232 | - CONFIG_SYS_UART4_RS232 | CONFIG_SYS_UART5_RS232); - - str = getenv("phys0"); - if (!str || (str && (str[0] == '0'))) - val |= CONFIG_SYS_UART2_RS232; - - str = getenv("phys1"); - if (!str || (str && (str[0] == '0'))) - val |= CONFIG_SYS_UART3_RS232; - - str = getenv("phys2"); - if (!str || (str && (str[0] == '0'))) - val |= CONFIG_SYS_UART4_RS232; - - str = getenv("phys3"); - if (!str || (str && (str[0] == '0'))) - val |= CONFIG_SYS_UART5_RS232; - - out_be32((void *)GPIO0_OR, val); - - /* - * check board type and setup AP power - */ - str = getenv("bd_type"); /* this is only set on non prototype hardware */ - if (str != NULL) { - if ((strcmp(str, "swch405") == 0) || ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) { - unsigned char led_reg_default = 0; - str = getenv("ap_pwr"); - if (!str || (str && (str[0] == '1'))) - led_reg_default = 0x04 | 0x02 ; /* U2_LED | AP_PWR */ - - /* - * Flash LEDs - */ - for (flashcnt = 0; flashcnt < 3; flashcnt++) { - /* LED_A..D off */ - out_8((void *)LED_REG, led_reg_default); - for (delay = 0; delay < 100; delay++) - udelay(1000); - /* LED_A..D on */ - out_8((void *)LED_REG, led_reg_default | 0xf0); - for (delay = 0; delay < 50; delay++) - udelay(1000); - } - out_8((void *)LED_REG, led_reg_default); - } - } - - /* - * Reset external DUARTs - */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */ - udelay(10); /* wait 10us */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */ - udelay(1000); /* wait 1ms */ - - /* - * Store hardware revision in environment for further processing - */ - sprintf(hw_rev, "1.%ld", gd->board_type); - setenv("hw_rev", hw_rev); - return (0); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming HUB405"); - } else { - puts(str); - } - - if (getenv_f("bd_type", str, sizeof(str)) != -1) { - printf(" (%s", str); - } else { - puts(" (Missing bd_type!"); - } - - gd->board_type = board_revision(); - printf(", Rev 1.%ld)\n", gd->board_type); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return 0; -} diff --git a/configs/HUB405_defconfig b/configs/HUB405_defconfig deleted file mode 100644 index a39712e..0000000 --- a/configs/HUB405_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_HUB405=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 1775987..d8bb3aa 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +HUB405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> HH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> DU440 ppc4xx 440epx - - Matthias Fuchs <matthias.fuchs(a)esd.eu> DU405 ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs(a)esd.eu> diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h deleted file mode 100644 index 1783b9f..0000000 --- a/include/configs/HUB405.h +++ /dev/null @@ -1,351 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_HUB405 1 /* ...on a HUB405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/* Ethernet stuff */ -#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ -#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 - -#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ - -#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CONFIG_SYS_NAND_QUIET 1 - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#undef CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* test-only */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: UART) initialization */ -#if 0 -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#else -#define CONFIG_SYS_EBC_PB2AP 0x92015480 -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#endif - -#define DUART0_BA 0xF0000000 /* DUART Base Address */ -#define DUART1_BA 0xF0000008 /* DUART Base Address */ -#define DUART2_BA 0xF0000010 /* DUART Base Address */ -#define DUART3_BA 0xF0000018 /* DUART Base Address */ -#define CONFIG_SYS_NAND_BASE 0xF4000000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -#define CONFIG_SYS_GPIO0_OSRL 0x40000550 -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 - -#define CONFIG_SYS_DUART_RST (0x80000000 >> 14) -#define CONFIG_SYS_UART2_RS232 (0x80000000 >> 5) -#define CONFIG_SYS_UART3_RS232 (0x80000000 >> 6) -#define CONFIG_SYS_UART4_RS232 (0x80000000 >> 7) -#define CONFIG_SYS_UART5_RS232 (0x80000000 >> 8) - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 1 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ -- 1.7.9.5

2 1

[U-Boot] [PATCH 09/22] ppc4xx: remove HH405 board
by Matthias Fuchs 13 Jan '15

13 Jan '15

Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- arch/powerpc/cpu/ppc4xx/Kconfig | 4 - board/esd/hh405/Kconfig | 12 - board/esd/hh405/MAINTAINERS | 6 - board/esd/hh405/Makefile | 11 - board/esd/hh405/flash.c | 85 - board/esd/hh405/fpgadata.c | 5034 -------------------- board/esd/hh405/hh405.c | 895 ---- board/esd/hh405/logo_1024_768_8bpp.c | 5087 -------------------- board/esd/hh405/logo_320_240_4bpp.c | 454 -- board/esd/hh405/logo_320_240_8bpp.c | 1042 ----- board/esd/hh405/logo_640_480_24bpp.c | 8417 ---------------------------------- configs/HH405_defconfig | 3 - doc/README.scrapyard | 1 + include/configs/HH405.h | 479 -- 14 files changed, 1 insertion(+), 21529 deletions(-) delete mode 100644 board/esd/hh405/Kconfig delete mode 100644 board/esd/hh405/MAINTAINERS delete mode 100644 board/esd/hh405/Makefile delete mode 100644 board/esd/hh405/flash.c delete mode 100644 board/esd/hh405/fpgadata.c delete mode 100644 board/esd/hh405/hh405.c delete mode 100644 board/esd/hh405/logo_1024_768_8bpp.c delete mode 100644 board/esd/hh405/logo_320_240_4bpp.c delete mode 100644 board/esd/hh405/logo_320_240_8bpp.c delete mode 100644 board/esd/hh405/logo_640_480_24bpp.c delete mode 100644 configs/HH405_defconfig delete mode 100644 include/configs/HH405.h diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 723b268..8ce66d6 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -125,9 +125,6 @@ config TARGET_CPCI405AB config TARGET_CPCI405DT bool "Support CPCI405DT" -config TARGET_HH405 - bool "Support HH405" - config TARGET_HUB405 bool "Support HUB405" @@ -235,7 +232,6 @@ source "board/csb472/Kconfig" source "board/dave/PPChameleonEVB/Kconfig" source "board/esd/cpci2dp/Kconfig" source "board/esd/cpci405/Kconfig" -source "board/esd/hh405/Kconfig" source "board/esd/hub405/Kconfig" source "board/esd/ocrtc/Kconfig" source "board/esd/pci405/Kconfig" diff --git a/board/esd/hh405/Kconfig b/board/esd/hh405/Kconfig deleted file mode 100644 index 8a8623a..0000000 --- a/board/esd/hh405/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_HH405 - -config SYS_BOARD - default "hh405" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "HH405" - -endif diff --git a/board/esd/hh405/MAINTAINERS b/board/esd/hh405/MAINTAINERS deleted file mode 100644 index b695c7b..0000000 --- a/board/esd/hh405/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -HH405 BOARD -M: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> -S: Maintained -F: board/esd/hh405/ -F: include/configs/HH405.h -F: configs/HH405_defconfig diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile deleted file mode 100644 index fba21a3..0000000 --- a/board/esd/hh405/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = hh405.o flash.o \ - ../common/misc.o \ - ../common/esd405ep_nand.o \ - ../common/auto_update.o diff --git a/board/esd/hh405/flash.c b/board/esd/hh405/flash.c deleted file mode 100644 index 23e8164..0000000 --- a/board/esd/hh405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Setup offsets */ - flash_get_offsets (-size_b0, &flash_info[0]); - - /* Re-do sizing to get full correct info */ - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b0 = -size_b0; - switch (size_b0) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - } - pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(EBC0_CFGDATA, pbcr); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} diff --git a/board/esd/hh405/fpgadata.c b/board/esd/hh405/fpgadata.c deleted file mode 100644 index 620c714..0000000 --- a/board/esd/hh405/fpgadata.c +++ /dev/null @@ -1,5034 +0,0 @@ -0x1f, 0x8b, 0x08, 0x08, 0x7a, 0x8e, 0xc6, 0x43, -0x00, 0x03, 0x68, 0x68, 0x34, 0x30, 0x35, 0x5f, -0x31, 0x5f, 0x30, 0x36, 0x2e, 0x62, 0x69, 0x74, -0x00, 0xec, 0xfd, 0x7f, 0x7c, 0x14, 0x55, 0x9a, -0x2f, 0x8e, 0x3f, 0x75, 0xaa, 0x12, 0x4e, 0xba, -0x3a, 0xe9, 0x22, 0x09, 0x4e, 0x54, 0xc4, 0x4a, -0x27, 0x30, 0x4d, 0xec, 0x84, 0xa6, 0x83, 0x21, -0x42, 0x48, 0x2a, 0x9d, 0xe8, 0x44, 0x40, 0xe9, -0x71, 0xdc, 0x59, 0x76, 0xae, 0x77, 0xb6, 0x65, -0x98, 0xbd, 0x99, 0xb9, 0xe8, 0x46, 0xc7, 0xbb, -0x97, 0xf1, 0xce, 0x8f, 0x93, 0x4e, 0x80, 0x4e, -0x82, 0xd0, 0x20, 0x33, 0x46, 0x87, 0x71, 0x9b, -0x10, 0x35, 0x2a, 0x33, 0xdb, 0x04, 0x94, 0xf0, -0x63, 0xb0, 0x12, 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<malloc.h> -#include <pci.h> -#include <sm501.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* FPGA internal regs */ -#define FPGA_CTRL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x000)) -#define FPGA_STATUS ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x002)) -#define FPGA_CTR ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x004)) -#define FPGA_BL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x006)) - -/* FPGA Control Reg */ -#define FPGA_CTRL_REV0 0x0001 -#define FPGA_CTRL_REV1 0x0002 -#define FPGA_CTRL_VGA0_BL 0x0004 -#define FPGA_CTRL_VGA0_BL_MODE 0x0008 -#define FPGA_CTRL_CF_RESET 0x0040 -#define FPGA_CTRL_PS2_PWR 0x0080 -#define FPGA_CTRL_CF_PWRN 0x0100 /* low active */ -#define FPGA_CTRL_CF_BUS_EN 0x0200 -#define FPGA_CTRL_LCD_CLK 0x7000 /* mask for lcd clock */ -#define FPGA_CTRL_OW_ENABLE 0x8000 - -#define FPGA_STATUS_CF_DETECT 0x8000 - -#ifdef CONFIG_VIDEO_SM501 - -#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\ - (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) ) - -#ifdef CONFIG_VIDEO_SM501_8BPP -#error CONFIG_VIDEO_SM501_8BPP not supported. -#endif /* CONFIG_VIDEO_SM501_8BPP */ - -#ifdef CONFIG_VIDEO_SM501_16BPP -#define BPP 16 - -/* - * 800x600 display B084SN03: PCLK = 40MHz - * => 2*PCLK = 80MHz - * 336/4 = 84MHz - * => PCLK = 84MHz - */ -static const SMI_REGS init_regs_800x600 [] = -{ -#if 1 /* test-only */ - {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */ -#else - {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */ -#endif - {0x00004, SWAP32(0x00000000)}, - /* clocks for pm1... */ - {0x00048, SWAP32(0x00021807)}, - {0x0004C, SWAP32(0x221a0a01)}, - {0x00054, SWAP32(0x00000001)}, - /* clocks for pm0... */ - {0x00040, SWAP32(0x00021807)}, - {0x00044, SWAP32(0x221a0a01)}, - {0x00054, SWAP32(0x00000000)}, - /* GPIO */ - {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ - /* panel control regs... */ - {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */ - {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ - {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */ - {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */ - {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */ - {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */ - {0x80020, SWAP32(0x02580320)}, /* panel plane br location */ - {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */ - {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */ - {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */ - {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */ - {0x80200, SWAP32(0x00010000)}, /* crt display control */ - {0, 0} -}; - -/* - * 1024x768 display G150XG02: PCLK = 65MHz - * => 2*PCLK = 130MHz - * 288/2 = 144MHz - * => PCLK = 72MHz - */ -static const SMI_REGS init_regs_1024x768 [] = -{ - {0x00004, SWAP32(0x00000000)}, - /* clocks for pm1... */ - {0x00048, SWAP32(0x00021807)}, - {0x0004C, SWAP32(0x011a0a01)}, - {0x00054, SWAP32(0x00000001)}, - /* clocks for pm0... */ - {0x00040, SWAP32(0x00021807)}, - {0x00044, SWAP32(0x011a0a01)}, - {0x00054, SWAP32(0x00000000)}, - /* GPIO */ - {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ - /* panel control regs... */ - {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */ - {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ - {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */ - {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */ - {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */ - {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */ - {0x80020, SWAP32(0x03000400)}, /* panel plane br location */ - {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */ - {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */ - {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */ - {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */ - {0x80200, SWAP32(0x00010000)}, /* crt display control */ - {0, 0} -}; - -#endif /* CONFIG_VIDEO_SM501_16BPP */ - -#ifdef CONFIG_VIDEO_SM501_32BPP -#define BPP 32 - -/* - * 800x600 display B084SN03: PCLK = 40MHz - * => 2*PCLK = 80MHz - * 336/4 = 84MHz - * => PCLK = 84MHz - */ -static const SMI_REGS init_regs_800x600 [] = -{ -#if 0 /* test-only */ - {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */ -#else - {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */ -#endif - {0x00004, SWAP32(0x00000000)}, - /* clocks for pm1... */ - {0x00048, SWAP32(0x00021807)}, - {0x0004C, SWAP32(0x221a0a01)}, - {0x00054, SWAP32(0x00000001)}, - /* clocks for pm0... */ - {0x00040, SWAP32(0x00021807)}, - {0x00044, SWAP32(0x221a0a01)}, - {0x00054, SWAP32(0x00000000)}, - /* GPIO */ - {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ - /* panel control regs... */ - {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */ - {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ - {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */ - {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */ - {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */ - {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */ - {0x80020, SWAP32(0x02580320)}, /* panel plane br location */ - {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */ - {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */ - {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */ - {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */ - {0x80200, SWAP32(0x00010000)}, /* crt display control */ - {0, 0} -}; - -/* - * 1024x768 display G150XG02: PCLK = 65MHz - * => 2*PCLK = 130MHz - * 288/2 = 144MHz - * => PCLK = 72MHz - */ -static const SMI_REGS init_regs_1024x768 [] = -{ - {0x00004, SWAP32(0x00000000)}, - /* clocks for pm1... */ - {0x00048, SWAP32(0x00021807)}, - {0x0004C, SWAP32(0x011a0a01)}, - {0x00054, SWAP32(0x00000001)}, - /* clocks for pm0... */ - {0x00040, SWAP32(0x00021807)}, - {0x00044, SWAP32(0x011a0a01)}, - {0x00054, SWAP32(0x00000000)}, - /* GPIO */ - {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ - /* panel control regs... */ - {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */ - {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ - {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */ - {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */ - {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */ - {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */ - {0x80020, SWAP32(0x03000400)}, /* panel plane br location */ - {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */ - {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */ - {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */ - {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */ - {0x80200, SWAP32(0x00010000)}, /* crt display control */ - {0, 0} -}; - -#endif /* CONFIG_VIDEO_SM501_32BPP */ - -#endif /* CONFIG_VIDEO_SM501 */ - -#if 0 -#define FPGA_DEBUG -#endif - -extern void lxt971_no_sleep(void); - -/* fpga configuration data - gzip compressed and generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -/* logo bitmap data - gzip compressed and generated by bin2c */ -unsigned char logo_bmp_320[] = -{ -#include "logo_320_240_4bpp.c" -}; - -unsigned char logo_bmp_320_8bpp[] = -{ -#include "logo_320_240_8bpp.c" -}; - -unsigned char logo_bmp_640[] = -{ -#include "logo_640_480_24bpp.c" -}; - -unsigned char logo_bmp_1024[] = -{ -#include "logo_1024_768_8bpp.c" -}; - - -/* - * include common lcd code (for esd boards) - */ -#include "../common/lcd.c" - -#include "../common/s1d13704_320_240_4bpp.h" -#include "../common/s1d13705_320_240_8bpp.h" -#include "../common/s1d13806_640_480_16bpp.h" -#include "../common/s1d13806_1024_768_8bpp.h" - - -/* - * include common auto-update code (for esd boards) - */ -#include "../common/auto_update.h" - -au_image_t au_image[] = { - {"hh405/preinst.img", 0, -1, AU_SCRIPT}, - {"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE}, - {"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND}, - {"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND}, - {"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND}, - {"hh405/postinst.img", 0, 0, AU_SCRIPT}, -}; - -int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); - - -/* - * Get version of HH405 board from GPIO's - */ -int board_revision(void) -{ - unsigned long osrh_reg; - unsigned long isr1h_reg; - unsigned long tcr_reg; - unsigned long value; - - /* - * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO) - */ - osrh_reg = in_be32((void *)GPIO0_OSRH); - isr1h_reg = in_be32((void *)GPIO0_ISR1H); - tcr_reg = in_be32((void *)GPIO0_TCR); - out_be32((void *)GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */ - out_be32((void *)GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */ - out_be32((void *)GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */ - - udelay(1000); /* wait some time before reading input */ - value = in_be32((void *)GPIO0_IR) & 0x80400000; /* get config bits */ - - /* - * Restore GPIO settings - */ - out_be32((void *)GPIO0_OSRH, osrh_reg); /* output select */ - out_be32((void *)GPIO0_ISR1H, isr1h_reg); /* input select */ - out_be32((void *)GPIO0_TCR, tcr_reg); /* enable output driver for outputs */ - - if (value & 0x80000000) { - /* Revision 1.0 or 1.1 detected */ - return 1; - } else { - if (value & 0x00400000) { - /* unused */ - return 3; - } else { - return 2; - } - } -} - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ - - return 0; -} - -int cf_enable(void) -{ - int i; - - if (gd->board_type >= 2) { - if (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT) { - if (!(in_be16(FPGA_CTRL) & FPGA_CTRL_CF_BUS_EN)) { - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_PWRN); - - for (i=0; i<300; i++) - udelay(1000); - - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) | FPGA_CTRL_CF_BUS_EN); - - for (i=0; i<20; i++) - udelay(1000); - } - } else { - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_BUS_EN); - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) | FPGA_CTRL_CF_PWRN); - } - } - - return 0; -} - -int misc_init_r (void) -{ - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - char *str; - unsigned long contrast0 = 0xffffffff; - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_INIT pin - */ - /* setup FPGA_INIT as output */ - out_be32((void *)GPIO0_TCR, - in_be32((void *)GPIO0_TCR) | FPGA_INIT); - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~FPGA_INIT); /* reset low */ - udelay(1000); /* wait 1ms */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | FPGA_INIT); /* reset high */ - udelay(1000); /* wait 1ms */ - - /* - * Write Board revision into FPGA - */ - out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | (gd->board_type & 0x0003)); - - /* - * Setup and enable EEPROM write protection - */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); - - /* - * Reset touch-screen controller - */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST); - udelay(1000); - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_TOUCH_RST); - - /* - * Enable power on PS/2 interface (with reset) - */ - out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_PS2_PWR); - for (i=0;i<500;i++) - udelay(1000); - out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_PS2_PWR); - - /* - * Get contrast value from environment variable - */ - str = getenv("contrast0"); - if (str) { - contrast0 = simple_strtol(str, NULL, 16); - if (contrast0 > 255) { - printf("ERROR: contrast0 value too high (0x%lx)!\n", - contrast0); - contrast0 = 0xffffffff; - } - } - - /* - * Init lcd interface and display logo - */ - - str = getenv("bd_type"); - if (strcmp(str, "ppc230") == 0) { - /* - * Switch backlight on - */ - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL); - out_be16(FPGA_BL, 0x0000); - - lcd_setup(1, 0); - lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, - regs_13806_1024_768_8bpp, - sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]), - logo_bmp_1024, sizeof(logo_bmp_1024)); - } else if (strcmp(str, "ppc220") == 0) { - /* - * Switch backlight on - */ - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) & ~FPGA_CTRL_VGA0_BL); - out_be16(FPGA_BL, 0x0000); - - lcd_setup(1, 0); - lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, - regs_13806_640_480_16bpp, - sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), - logo_bmp_640, sizeof(logo_bmp_640)); - } else if (strcmp(str, "ppc215") == 0) { - /* - * Set default display contrast voltage - */ - if (contrast0 == 0xffffffff) { - out_be16(FPGA_CTR, 0x0082); - } else { - out_be16(FPGA_CTR, contrast0); - } - out_be16(FPGA_BL, 0xffff); - /* - * Switch backlight on - */ - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) | - FPGA_CTRL_VGA0_BL | - FPGA_CTRL_VGA0_BL_MODE); - /* - * Set lcd clock (small epson) - */ - out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_06250); - udelay(100); /* wait for 100 us */ - - lcd_setup(0, 1); - lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, - regs_13705_320_240_8bpp, - sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]), - logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp)); - } else if (strcmp(str, "ppc210") == 0) { - /* - * Set default display contrast voltage - */ - if (contrast0 == 0xffffffff) { - out_be16(FPGA_CTR, 0x0060); - } else { - out_be16(FPGA_CTR, contrast0); - } - out_be16(FPGA_BL, 0xffff); - /* - * Switch backlight on - */ - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) | - FPGA_CTRL_VGA0_BL | - FPGA_CTRL_VGA0_BL_MODE); - /* - * Set lcd clock (small epson), enable 1-wire interface - */ - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) | - LCD_CLK_08330 | - FPGA_CTRL_OW_ENABLE); - - lcd_setup(0, 1); - lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, - regs_13704_320_240_4bpp, - sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), - logo_bmp_320, sizeof(logo_bmp_320)); -#ifdef CONFIG_VIDEO_SM501 - } else { - pci_dev_t devbusfn; - - /* - * Is SM501 connected (ppc221/ppc231)? - */ - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - puts("VGA: SM501 with 8 MB "); - if (strcmp(str, "ppc221") == 0) { - printf("(800*600, %dbpp)\n", BPP); - out_be16(FPGA_BL, 0x002d); /* max. allowed brightness */ - } else if (strcmp(str, "ppc231") == 0) { - printf("(1024*768, %dbpp)\n", BPP); - out_be16(FPGA_BL, 0x0000); - } else { - printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); - return 0; - } - } else { - printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); - return 0; - } -#endif /* CONFIG_VIDEO_SM501 */ - } - - cf_enable(); - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming HH405"); - } else { - puts(str); - } - - if (getenv_f("bd_type", str, sizeof(str)) != -1) { - printf(" (%s", str); - } else { - puts(" (Missing bd_type!"); - } - - gd->board_type = board_revision(); - printf(", Rev %ld.x)\n", gd->board_type); - - return 0; -} - -#ifdef CONFIG_IDE_RESET -void ide_set_reset(int on) -{ - if (((gd->board_type >= 2) && - (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT)) || - (gd->board_type < 2)) { - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { /* assert RESET */ - cf_enable(); - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) & - ~FPGA_CTRL_CF_RESET); - } else { /* release RESET */ - out_be16(FPGA_CTRL, - in_be16(FPGA_CTRL) | - FPGA_CTRL_CF_RESET); - } - } -} -#endif /* CONFIG_IDE_RESET */ - - -#if defined(CONFIG_SYS_EEPROM_WREN) -/* Input: <dev_addr> I2C address of EEPROM device to enable. - * <state> -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if <state> was -1. - */ -int eeprom_write_enable (unsigned dev_addr, int state) -{ - if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in_be32((void *)GPIO0_OR) & - CONFIG_SYS_EEPROM_WP)); - break; - } - } - return state; -} - -int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); - if (state < 0) { - puts ("Query of write access state failed.\n"); - } else { - printf ("Write access for device 0x%0x is %sabled.\n", - CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); - } - if (state < 0) { - puts ("Setup of write access state failed.\n"); - } - } - - return state; -} - -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - "" -); -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ - - -#ifdef CONFIG_VIDEO_SM501 -#ifdef CONFIG_CONSOLE_EXTRA_INFO -/* - * Return text to be printed besides the logo. - */ -void video_get_info_str (int line_number, char *info) -{ - char str[64]; - char str2[64]; - int i = getenv_f("serial#", str2, sizeof(str)); - - if (line_number == 1) { - sprintf(str, " Board: "); - - if (i == -1) { - strcat(str, "### No HW ID - assuming HH405"); - } else { - strcat(str, str2); - } - - if (getenv_f("bd_type", str2, sizeof(str2)) != -1) { - strcat(str, " ("); - strcat(str, str2); - } else { - strcat(str, " (Missing bd_type!"); - } - - sprintf(str2, ", Rev %ld.x)", gd->board_type); - strcat(str, str2); - strcpy(info, str); - } else { - info [0] = '\0'; - } -} -#endif /* CONFIG_CONSOLE_EXTRA_INFO */ - -/* - * Returns SM501 register base address. First thing called in the driver. - */ -unsigned int board_video_init (void) -{ - pci_dev_t devbusfn; - u32 addr; - - /* - * Is SM501 connected (ppc221/ppc231)? - */ - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr); - return (addr & 0xfffffffe); - } - - return 0; -} - -/* - * Returns SM501 framebuffer address - */ -unsigned int board_video_get_fb (void) -{ - pci_dev_t devbusfn; - u32 addr; - - /* - * Is SM501 connected (ppc221/ppc231)? - */ - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr); - addr &= 0xfffffffe; -#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET - addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET; -#endif - return addr; - } - - return 0; -} - -/* - * Called after initializing the SM501 and before clearing the screen. - */ -void board_validate_screen (unsigned int base) -{ -} - -/* - * Return a pointer to the initialization sequence. - */ -const SMI_REGS *board_get_regs (void) -{ - char *str; - - str = getenv("bd_type"); - if (strcmp(str, "ppc221") == 0) { - return init_regs_800x600; - } else { - return init_regs_1024x768; - } -} - -int board_get_width (void) -{ - char *str; - - str = getenv("bd_type"); - if (strcmp(str, "ppc221") == 0) { - return 800; - } else { - return 1024; - } -} - -int board_get_height (void) -{ - char *str; - - str = getenv("bd_type"); - if (strcmp(str, "ppc221") == 0) { - return 600; - } else { - return 768; - } -} - -#endif /* CONFIG_VIDEO_SM501 */ - - -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} diff --git a/board/esd/hh405/logo_1024_768_8bpp.c b/board/esd/hh405/logo_1024_768_8bpp.c deleted file mode 100644 index 331540f..0000000 --- a/board/esd/hh405/logo_1024_768_8bpp.c +++ /dev/null @@ -1,5087 +0,0 @@ -0x1f, 0x8b, 0x08, 0x08, 0x20, 0xb5, 0x06, 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a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +HH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> DU440 ppc4xx 440epx - - Matthias Fuchs <matthias.fuchs(a)esd.eu> DU405 ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs(a)esd.eu> DP405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs(a)esd.eu> diff --git a/include/configs/HH405.h b/include/configs/HH405.h deleted file mode 100644 index 033dcbf..0000000 --- a/include/configs/HH405.h +++ /dev/null @@ -1,479 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese(a)esd-electronics.com - * - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr(a)denx.de. - * - * (C) Copyright 2006 - * Matthias Fuchs, esd GmbH, matthias.fuchs(a)esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_HH405 1 /* ...on a HH405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT "autoupd" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "pciconfighost=1\0" \ - "" - -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#undef CONFIG_HAS_ETH1 - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - -/* - * Video console - */ -#define CONFIG_VIDEO /* for sm501 video support */ - -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_SM501 -#if 0 -#define CONFIG_VIDEO_SM501_32BPP -#else -#define CONFIG_VIDEO_SM501_16BPP -#endif -#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SPLASH_SCREEN -#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */ -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */ - -#endif /* CONFIG_VIDEO */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DATE -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - -#ifdef CONFIG_VIDEO -#define CONFIG_CMD_BMP -#endif - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ -#undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */ - -#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* print console @ startup */ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * RTC stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_RTC_DS1338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 - -#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ - -#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CONFIG_SYS_NAND_QUIET 1 - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* test-only */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFF80000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */ - -#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) -# define CONFIG_SYS_RAMBOOT 1 -#else -# undef CONFIG_SYS_RAMBOOT -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF4080000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#if 0 /* test-only */ -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#else -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#endif -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -#define CONFIG_SYS_EEPROM_WREN 1 - -#if 1 /* test-only */ -/* CAT24WC08/16... */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#else -/* CAT24WC32/64... */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#endif -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define LCD_BA 0xF1000000 /* Epson LCD Base Address */ -#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ -#define CONFIG_SYS_NVRAM_BASE 0xF4080000 /* NVRAM Base Address */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (Epson LCD) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ -#define CONFIG_SYS_EBC_PB4CR LCD_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */ - -/*----------------------------------------------------------------------- - * LCD Setup - */ - -#define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ -#define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ -#define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ -#define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ - -/*----------------------------------------------------------------------- - * Universal Interrupt Controller (UIC) Setup - */ - -/* - * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high - */ -#define CONFIG_SYS_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6)) - -/*----------------------------------------------------------------------- - * FPGA stuff - */ - -#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ - -#define LCD_CLK_OFF 0x0000 /* Off */ -#define LCD_CLK_02083 0x1000 /* 2.083 MHz */ -#define LCD_CLK_03135 0x2000 /* 3.135 MHz */ -#define LCD_CLK_04165 0x3000 /* 4.165 MHz */ -#define LCD_CLK_06250 0x4000 /* 6.250 MHz */ -#define LCD_CLK_08330 0x5000 /* 8.330 MHz */ -#define LCD_CLK_12500 0x6000 /* 12.50 MHz */ -#define LCD_CLK_25000 0x7000 /* 25.00 MHz */ - -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -#define CONFIG_SYS_GPIO0_OSRL 0x40000550 -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1H 0x15555440 -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0xF7FE0017 - -#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7) -#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ -#define CONFIG_SYS_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */ -#define CONFIG_SYS_LCD0_RST (0x80000000 >> 30) -#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31) - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 1 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ -- 1.7.9.5

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