July 2014 - U-Boot

[U-Boot] [PATCH] kmake: include DTB section into u-boot.bin if CONFIG_OF_EMBED enabled
by Alexey Ignatov 08 Jul '14

08 Jul '14

Fixes a bug when objcopy doesn't put .dtb.init.rodata section to resulting u-boot.bin, so u-boot was unable to find embedded DTB. --- arch/arm/config.mk | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 66ecc2e..5fa1825 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -116,6 +116,10 @@ else OBJCOPYFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn endif +ifdef CONFIG_OF_EMBED +OBJCOPYFLAGS += -j .dtb.init.rodata +endif + ifneq ($(CONFIG_IMX_CONFIG),) ifdef CONFIG_SPL ifndef CONFIG_SPL_BUILD -- 1.8.5.3

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[U-Boot] [PATCH] git-mailrc: Add sunxi custodians.
by Ian Campbell 08 Jul '14

08 Jul '14

Signed-off-by: Ian Campbell <ijc(a)hellion.org.uk> Cc: Hans de Goede <hdegoede(a)redhat.com> --- doc/git-mailrc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/doc/git-mailrc b/doc/git-mailrc index 251586e..d924b26 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -17,10 +17,12 @@ alias ag Anatolij Gustschin <agust(a)denx.de> alias galak Kumar Gala <galak(a)kernel.crashing.org> alias gruss Graeme Russ <graeme.russ(a)gmail.com> alias hs Heiko Schocher <hs(a)denx.de> +alias ijc Ian Campbell <ijc+uboot(a)hellion.org.uk> alias iwamatsu Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> alias jagan Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com> alias jasonjin Jason Jin <jason.jin(a)freescale.com> alias jhersh Joe Hershberger <joe.hershberger(a)gmail.com> +alias jwrdegoede Hans de Goede <hdegoede(a)redhat.com> alias kimphill Kim Phillips <kim.phillips(a)freescale.com> alias macpaul Macpaul Lin <macpaul(a)andestech.com> alias marex Marek Vasut <marex(a)denx.de> @@ -55,6 +57,7 @@ alias rmobile uboot, iwamatsu alias s3c samsung alias s5pc samsung alias samsung uboot, prom +alias sunxi uboot, ijc, jwrdegoede alias tegra uboot, sjg, Tom Warren <twarren(a)nvidia.com>, Stephen Warren <swarren(a)nvidia.com> alias tegra2 tegra alias ti uboot, trini -- 1.9.0

3 2

[U-Boot] [PATCH v4 0/13] Fixes on gdsys boards and some new functionality
by dirk.eibach＠gdsys.cc 08 Jul '14

08 Jul '14

From: Dirk Eibach <dirk.eibach(a)gdsys.cc> Changes in v4: - describe CONFIG_FIT_DISABLE_SHA256 in README Changes in v3: - describe ihs_i2c in README Changes in v2: - make sha256 support optional - move ihs_i2c to drivers/i2c - split unrelated changes - use defines for I2C bus numbers Dirk Eibach (13): board: controlcenterd: Fix pci access board: gdsys: Adapt sdhc_boot.c to mmc_get_env_addr API change board: controlcenterd: Use new API for setting i2c bus board: iocon: Support DisplayPort hardware i2c: IHS I2C master driver board: gdsys: Fix dlvision-10g I2C configuration board: gdsys: Increase iocon and dlv10g version string board: gdsys: Configure bridge on DP501 to support DDC only board: gdsys: Make gdsys osd hardware detection more robust board: gdsys: Enable scrambling on DP501 board: iocon: Modify iocon hardware startup board: gdsys: Remove commands to reduce footprint fit: make sha256 support optional README | 20 ++++ board/gdsys/405ep/iocon.c | 14 ++- board/gdsys/common/Makefile | 2 +- board/gdsys/common/dp501.c | 35 ++++-- board/gdsys/common/osd.c | 189 +++++++++++++++---------------- board/gdsys/p1022/controlcenterd-id.c | 13 ++- board/gdsys/p1022/controlcenterd.c | 6 +- board/gdsys/p1022/sdhc_boot.c | 2 +- drivers/i2c/Makefile | 1 + drivers/i2c/ihs_i2c.c | 203 ++++++++++++++++++++++++++++++++++ include/configs/controlcenterd.h | 7 +- include/configs/dlvision-10g.h | 29 ++++- include/configs/io.h | 8 +- include/configs/iocon.h | 35 ++++-- include/configs/neo.h | 9 +- include/gdsys_fpga.h | 25 ++--- include/image.h | 5 + 17 files changed, 454 insertions(+), 149 deletions(-) create mode 100644 drivers/i2c/ihs_i2c.c -- 1.8.3

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[U-Boot] [PATCH] blackfin, powerpc: remove redundant definitions of ARRAY_SIZE
by Masahiro Yamada 08 Jul '14

08 Jul '14

Since ARRAY_SIZE macro is defined in include/common.h, re-defining it in arch-specific files is redundant. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Sonic Zhang <sonic.zhang(a)analog.com> --- I built all Blackfin and Powerpc boards. I confirmed this patch has no bad impact. arch/blackfin/include/asm/config-pre.h | 3 --- arch/powerpc/cpu/ppc4xx/speed.c | 2 -- 2 files changed, 5 deletions(-) diff --git a/arch/blackfin/include/asm/config-pre.h b/arch/blackfin/include/asm/config-pre.h index d0fd537..2d8b293 100644 --- a/arch/blackfin/include/asm/config-pre.h +++ b/arch/blackfin/include/asm/config-pre.h @@ -9,9 +9,6 @@ #ifndef __ASM_BLACKFIN_CONFIG_PRE_H__ #define __ASM_BLACKFIN_CONFIG_PRE_H__ -/* Misc helper functions */ -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - /* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE. * Depending on your cpu, some of these may not be valid, check your HRM. * The actual values here are meaningless as long as they're unique. diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 7e077d5..4baee77 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -19,8 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; #define DEBUGF(fmt,args...) #endif -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - #if defined(CONFIG_405GP) void get_sys_info (PPC4xx_SYS_INFO * sysInfo) -- 1.9.1

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[U-Boot] [PATCH] README: document CONFIG_ENV_IS_IN_SPI_FLASH
by Josh Wu 08 Jul '14

08 Jul '14

The option can be used to save the environment in spi flash. Implementation code is already exist in command/env_sf.c. But the documentation is missing. This patch add the details for this option to the README file. Signed-off-by: Josh Wu <josh.wu(a)atmel.com> --- README | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/README b/README index fe5cacb..794cfb0 100644 --- a/README +++ b/README @@ -4069,6 +4069,43 @@ to save the current settings. environment area within the total memory of your DataFlash placed at the specified address. +- CONFIG_ENV_IS_IN_SPI_FLASH: + + Define this if you have a SPI Flash memory device which you + want to use for the environment. + + - CONFIG_ENV_OFFSET: + - CONFIG_ENV_SIZE: + + These two #defines specify the offset and size of the + environment area within the SPI Flash. CONFIG_ENV_OFFSET must be + aligned to an erase sector boundary. + + - CONFIG_ENV_SECT_SIZE: + + Define the SPI flash's sector size. + + - CONFIG_ENV_OFFSET_REDUND (optional): + + This setting describes a second storage area of CONFIG_ENV_SIZE + size used to hold a redundant copy of the environment data, so + that there is a valid backup copy in case there is a power failure + during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be + aligned to an erase sector boundary. + + - CONFIG_ENV_SPI_BUS (optional): + - CONFIG_ENV_SPI_CS (optional): + + Define the SPI bus and chip select. If not defined they will be 0. + + - CONFIG_ENV_SPI_MAX_HZ (optional): + + Define the SPI max work clock. If not defined then use 1MHz. + + - CONFIG_ENV_SPI_MODE (optional): + + Define the SPI work mode. If not defined then use SPI_MODE_3. + - CONFIG_ENV_IS_IN_REMOTE: Define this if you have a remote memory space which you -- 1.7.9.5

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[U-Boot] [PATCH] blackfin: Add more dcache functions
by Vasili Galka 08 Jul '14

08 Jul '14

Add invalidate_dcache_range() and flush_dcache_range() for the blackfin architecture. Such functions already exist on this arch with different names, so just forward the call. This fixes the build of bf609-ezkit board as it uses drivers/net/designware.c which requires the above functions. Cc: Sonic Zhang <sonic.adi(a)gmail.com>, Alexey Brodkin <abrodkin(a)synopsys.com> Signed-off-by: Vasili Galka <vvv444(a)gmail.com> --- arch/blackfin/lib/cache.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/blackfin/lib/cache.c b/arch/blackfin/lib/cache.c index 0a321a4..e8a0cb5 100644 --- a/arch/blackfin/lib/cache.c +++ b/arch/blackfin/lib/cache.c @@ -111,3 +111,13 @@ int dcache_status(void) { return bfin_read_DMEM_CONTROL() & ACACHE_BCACHE; } + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + blackfin_dcache_flush_invalidate_range((const void *)start, (const void *)stop); +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ + blackfin_dcache_flush_range((const void *)start, (const void *)stop); +} -- 1.7.9

2 1

[U-Boot] [PATCH] blackfin: Fix warning about undefined function
by Vasili Galka 08 Jul '14

08 Jul '14

get_sclk() was not defined in bfin_wdt.c, include the corresponding header. Cc: Sonic Zhang <sonic.adi(a)gmail.com> Signed-off-by: Vasili Galka <vvv444(a)gmail.com> --- drivers/watchdog/bfin_wdt.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/watchdog/bfin_wdt.c b/drivers/watchdog/bfin_wdt.c index 7a6756b..6a8db59 100644 --- a/drivers/watchdog/bfin_wdt.c +++ b/drivers/watchdog/bfin_wdt.c @@ -9,6 +9,7 @@ #include <common.h> #include <watchdog.h> #include <asm/blackfin.h> +#include <asm/clock.h> #include <asm/mach-common/bits/watchdog.h> void hw_watchdog_reset(void) -- 1.7.9

2 1

[U-Boot] [PATCH] m68k: Fix incorrect memory access on M5235
by Vasili Galka 08 Jul '14

08 Jul '14

The csarX and cscrX registers in the fbcs_t struct are 16-bit for CONFIG_M5235 and 32-bit wide otherwise. The code in cpu_init.c accessed them always as 32-bit, effectively creating a wrong memory access on M5235. Fixed that by choosing out_be16/out_be32 depending on whether CONFIG_M5235 is defined or not. Cc: Jason Jin <Jason.jin(a)freescale.com> Signed-off-by: Vasili Galka <vvv444(a)gmail.com> --- arch/m68k/cpu/mcf523x/cpu_init.c | 39 ++++++++++++++++++++++--------------- 1 files changed, 23 insertions(+), 16 deletions(-) diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c index 5a78954..af1fd56 100644 --- a/arch/m68k/cpu/mcf523x/cpu_init.c +++ b/arch/m68k/cpu/mcf523x/cpu_init.c @@ -20,6 +20,13 @@ #include <asm/fec.h> #endif +/* The registers in fbcs_t struct can be 16-bit for CONFIG_M5235 or 32-bit wide otherwise. */ +#ifdef CONFIG_M5235 +#define out_be_fbcs_reg out_be16 +#else +#define out_be_fbcs_reg out_be32 +#endif + /* * Breath some life into the CPU... * @@ -45,57 +52,57 @@ void cpu_init_f(void) out_8(&gpio->par_cs, 0); #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1); - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2); - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3); - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4); - out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); - out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be_fbcs_reg(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be_fbcs_reg(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5); - out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); - out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be_fbcs_reg(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be_fbcs_reg(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6); - out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE); - out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL); + out_be_fbcs_reg(&fbcs->csar6, CONFIG_SYS_CS6_BASE); + out_be_fbcs_reg(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL); out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK); #endif #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7); - out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE); - out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL); + out_be_fbcs_reg(&fbcs->csar7, CONFIG_SYS_CS7_BASE); + out_be_fbcs_reg(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL); out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK); #endif -- 1.7.9

2 1

[U-Boot] [PATCH] m68k: Fix bug, "address of" operator was forgotten
by Vasili Galka 08 Jul '14

08 Jul '14

in_be16() shall be passed a pointer to register and not its value. This is clearly a typo resulting in a wrong memory access, so fix it. Cc: Alison Wang <b18965(a)freescale.com>, Jason Jin <Jason.jin(a)freescale.com> Signed-off-by: Vasili Galka <vvv444(a)gmail.com> --- arch/m68k/cpu/mcf5445x/speed.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c index 07a9b35..4e363a4 100644 --- a/arch/m68k/cpu/mcf5445x/speed.c +++ b/arch/m68k/cpu/mcf5445x/speed.c @@ -115,7 +115,7 @@ void setup_5441x_clocks(void) gd->cpu_clk = vco / temp; /* cpu clock */ gd->arch.flb_clk = vco / temp; /* FlexBus clock */ gd->arch.flb_clk >>= 1; - if (in_be16(ccm->misccr2) & 2) /* fsys/4 */ + if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */ gd->arch.flb_clk >>= 1; temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1; -- 1.7.9

2 1

[U-Boot] [PATCH 1/2] am43xx: Update EMIF DDR3 Configuration for AM43x GP
by Franklin S Cooper Jr 08 Jul '14

08 Jul '14

From: "Franklin S. Cooper Jr" <fcooper(a)ti.com> * Boot failures have been discovered due to a combination of routing issues and non optimal ddr3 timings in the EMIF * Since ddr3 timings are different after significant board layout changes different timings are required for alpha, beta and production boards. Signed-off-by: Franklin S. Cooper Jr <fcooper(a)ti.com> --- arch/arm/include/asm/arch-am33xx/omap.h | 2 + board/ti/am43xx/board.c | 101 +++++++++++++++++++++++++++++++ board/ti/am43xx/board.h | 11 ++++ 3 files changed, 114 insertions(+) diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 0855d16..e5c0b0d 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -29,6 +29,8 @@ #define SRAM_SCRATCH_SPACE_ADDR 0x40337C00 #define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR #define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC +#define AM4372_BOARD_VERSION_START SRAM_SCRATCH_SPACE_ADDR + 0xD +#define AM4372_BOARD_VERSION_END SRAM_SCRATCH_SPACE_ADDR + 0x14 #define QSPI_BASE 0x47900000 #endif #endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 054a452..5eaa4a5 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -68,6 +68,9 @@ static int read_eeprom(struct am43xx_board_id *header) strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name)); am43xx_board_name[sizeof(header->name)] = 0; + strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version)); + am43xx_board_rev[sizeof(header->version)] = 0; + return 0; } @@ -217,6 +220,44 @@ const struct emif_regs ddr3_emif_regs_400Mhz = { .emif_rd_wr_exec_thresh = 0x00000405 }; +/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ +const struct emif_regs ddr3_emif_regs_400Mhz_beta = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000065, + .emif_ddr_ext_phy_ctrl_3 = 0x00000091, + .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, + .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, + .emif_rd_wr_exec_thresh = 0x00000405 +}; + +/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ +const struct emif_regs ddr3_emif_regs_400Mhz_production = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000066, + .emif_ddr_ext_phy_ctrl_3 = 0x00000091, + .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, + .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, + .emif_rd_wr_exec_thresh = 0x00000405 +}; + static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { .sdram_config = 0x638413b2, .sdram_config2 = 0x00000000, @@ -262,6 +303,52 @@ const u32 ext_phy_ctrl_const_base_ddr3[] = { 0x08102040 }; +const u32 ext_phy_ctrl_const_base_ddr3_beta[] = { + 0x00000000, + 0x00000045, + 0x00000046, + 0x00000048, + 0x00000047, + 0x00000000, + 0x0000004C, + 0x00000070, + 0x00000085, + 0x000000A3, + 0x00000000, + 0x0000000C, + 0x00000030, + 0x00000045, + 0x00000063, + 0x00000000, + 0x0, + 0x0, + 0x40000000, + 0x08102040 +}; + +const u32 ext_phy_ctrl_const_base_ddr3_production[] = { + 0x00000000, + 0x00000044, + 0x00000044, + 0x00000046, + 0x00000046, + 0x00000000, + 0x00000059, + 0x00000077, + 0x00000093, + 0x000000A8, + 0x00000000, + 0x00000019, + 0x00000037, + 0x00000053, + 0x00000068, + 0x00000000, + 0x0, + 0x0, + 0x40000000, + 0x08102040 +}; + static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = { /* first 5 are taken care by emif_regs */ 0x00700070, @@ -309,6 +396,12 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) if (board_is_eposevm()) { *regs = ext_phy_ctrl_const_base_lpddr2; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); + } else if (board_is_evm_14_or_later()) { + *regs = ext_phy_ctrl_const_base_ddr3_production; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production); + } else if (board_is_evm_12_or_later()) { + *regs = ext_phy_ctrl_const_base_ddr3_beta; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta); } else if (board_is_gpevm()) { *regs = ext_phy_ctrl_const_base_ddr3; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); @@ -473,6 +566,14 @@ void sdram_init(void) */ if (board_is_eposevm()) { config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); + } else if (board_is_evm_14_or_later()) { + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400Mhz_production, 0); + } else if (board_is_evm_12_or_later()) { + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400Mhz_beta, 0); } else if (board_is_gpevm()) { enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 017047d..8e12191 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -15,6 +15,7 @@ #include <asm/arch/omap.h> static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START; +static char *const am43xx_board_rev = (char *)AM4372_BOARD_VERSION_START; /* * TI AM437x EVMs define a system EEPROM that defines certain sub-fields. @@ -52,6 +53,16 @@ static inline int board_is_sk(void) return !strncmp(am43xx_board_name, "AM43__SK", HDR_NAME_LEN); } +static inline int board_is_evm_14_or_later(void) +{ + return (board_is_gpevm() && strncmp("1.4", am43xx_board_rev, 3) <= 0); +} + +static inline int board_is_evm_12_or_later(void) +{ + return (board_is_gpevm() && strncmp("1.2", am43xx_board_rev, 3) <= 0); +} + void enable_uart0_pin_mux(void); void enable_board_pin_mux(void); void enable_i2c0_pin_mux(void); -- 1.7.9.5

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