June 2014 - U-Boot

[U-Boot] [PATCH 1/3] blackfin: spi: move spi max chip select to spi.h
by Scott Jiang 09 Jun '14

09 Jun '14

Signed-off-by: Scott Jiang <scott.jiang.linux(a)gmail.com> --- arch/blackfin/include/asm/config-pre.h | 3 --- arch/blackfin/include/asm/mach-common/bits/spi.h | 1 + 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/blackfin/include/asm/config-pre.h b/arch/blackfin/include/asm/config-pre.h index d0fd537..0ffa44c 100644 --- a/arch/blackfin/include/asm/config-pre.h +++ b/arch/blackfin/include/asm/config-pre.h @@ -73,9 +73,6 @@ static inline const char *get_bfin_boot_mode(int bfin_boot) # define BFIN_BOOT_SPI_SSEL 1 #endif -/* Define to get a GPIO CS with the Blackfin SPI controller */ -#define MAX_CTRL_CS 8 - /* There is no Blackfin/NetBSD port */ #undef CONFIG_BOOTM_NETBSD diff --git a/arch/blackfin/include/asm/mach-common/bits/spi.h b/arch/blackfin/include/asm/mach-common/bits/spi.h index 869dcb0..180cfaa 100644 --- a/arch/blackfin/include/asm/mach-common/bits/spi.h +++ b/arch/blackfin/include/asm/mach-common/bits/spi.h @@ -64,4 +64,5 @@ #define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ #define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ +#define MAX_CTRL_CS 7 #endif -- 1.7.9.5

2 3

[U-Boot] [PATCH] arm64: zero cntvoff_el2
by Mark Rutland 09 Jun '14

09 Jun '14

Currently cntvoff_el2 is initialised with an arbitrary bag of bits derived from the initial value of cnthctl_el2 on the current CPU. This is somewhat odd and problematic as some of these bits are UNKNOWN at reset and may differ across CPUs (which may cause an OS at EL1 to observe time going backwards across CPUs). This patch instead initialises cntvoff_el2 with xzr, giving the register a consistent value of zero on all CPUs. Signed-off-by: Mark Rutland <mark.rutland(a)arm.com> Acked-by: Marc Zyngier <marc.zyngier(a)arm.com> Acked-by: Catalin Marinas <catalin.marinas(a)arm.com> Cc: Scott Wood <scottwood(a)freescale.com> Cc: David Feng <fenghua(a)phytium.com.cn> Cc: Tom Rini <trini(a)ti.com> --- arch/arm/cpu/armv8/transition.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S index e0a5946..38dea5c 100644 --- a/arch/arm/cpu/armv8/transition.S +++ b/arch/arm/cpu/armv8/transition.S @@ -43,7 +43,7 @@ ENTRY(armv8_switch_to_el1) mrs x0, cnthctl_el2 orr x0, x0, #0x3 /* Enable EL1 access to timers */ msr cnthctl_el2, x0 - msr cntvoff_el2, x0 + msr cntvoff_el2, xzr mrs x0, cntkctl_el1 orr x0, x0, #0x3 /* Enable EL0 access to timers */ msr cntkctl_el1, x0 -- 1.9.1

3 2

[U-Boot] [PATCH 1/3] arm: vf610: Add QSPI driver support
by Chao Fu 09 Jun '14

09 Jun '14

From: Alison Wang <b18965(a)freescale.com> Add Freescale QSPI driver support for VF610. Signed-off-by: Alison Wang <Huan.Wang(a)freescale.com> Signed-off-by: Chao Fu <b44548(a)freescale.com> --- drivers/spi/Makefile | 1 + drivers/spi/fsl_qspi.c | 482 +++++++++++++++++++++++++++++++++++++++++++++++++ drivers/spi/fsl_qspi.h | 127 +++++++++++++ 3 files changed, 610 insertions(+) create mode 100644 drivers/spi/fsl_qspi.c create mode 100644 drivers/spi/fsl_qspi.h diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 81b6af6..b587308 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -40,3 +40,4 @@ obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o obj-$(CONFIG_TI_QSPI) += ti_qspi.o obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o +obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c new file mode 100644 index 0000000..0dc09ca --- /dev/null +++ b/drivers/spi/fsl_qspi.c @@ -0,0 +1,482 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * Freescale Quad Serial Peripheral Interface (QSPI) driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> +#include <linux/sizes.h> +#include "fsl_qspi.h" + +#define RX_BUFFER_SIZE 0x80 +#define TX_BUFFER_SIZE 0x40 + +#define OFFSET_BITS_MASK 0x00ffffff + +#define FLASH_STATUS_WEL 0x02 + +/* SEQID */ +#define SEQID_WREN 1 +#define SEQID_FAST_READ 2 +#define SEQID_RDSR 3 +#define SEQID_SE 4 +#define SEQID_CHIP_ERASE 5 +#define SEQID_PP 6 +#define SEQID_RDID 7 + +/* Flash opcodes */ +#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ +#define OPCODE_RDSR 0x05 /* Read status register */ +#define OPCODE_WREN 0x06 /* Write enable */ +#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ +#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ +#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ +#define OPCODE_RDID 0x9f /* Read JEDEC ID */ + +/* 4-byte address opcodes - used on Spansion and some Macronix flashes */ +#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ +#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */ +#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */ + +#ifdef CONFIG_SYS_FSL_QSPI_LE +#define qspi_read32 in_le32 +#define qspi_write32 out_le32 +#elif defined(CONFIG_SYS_FSL_QSPI_BE) +#define qspi_read32 in_be32 +#define qspi_write32 out_be32 +#endif + +static unsigned long spi_bases[] = { + QSPI0_BASE_ADDR, +}; + +static unsigned long amba_bases[] = { + QSPI0_AMBA_BASE, +}; + +struct fsl_qspi { + struct spi_slave slave; + unsigned long reg_base; + unsigned long amba_base; + u32 sf_addr; + u8 cur_seqid; +}; + +/* QSPI support swapping the flash read/write data + * in hardware for LS102xA, but not for VF610 */ +static inline u32 qspi_endian_xchg(u32 data) +{ +#ifdef CONFIG_VF610 + return swab32(data); +#else + return data; +#endif +} + +static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave) +{ + return container_of(slave, struct fsl_qspi, slave); +} + +static void qspi_set_lut(struct fsl_qspi *qspi) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 lut_base; + + /* Unlock the LUT */ + qspi_write32(&regs->lutkey, LUT_KEY_VALUE); + qspi_write32(&regs->lckcr, QSPI_LCKCR_UNLOCK); + + /* Write Enable */ + lut_base = SEQID_WREN * 4; + qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_WREN) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); + qspi_write32(&regs->lut[lut_base + 1], 0); + qspi_write32(&regs->lut[lut_base + 2], 0); + qspi_write32(&regs->lut[lut_base + 3], 0); + + /* Fast Read */ + lut_base = SEQID_FAST_READ * 4; + if (FSL_QSPI_FLASH_SIZE <= SZ_16M) + qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_FAST_READ) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + else + qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_FAST_READ_4B) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + qspi_write32(&regs->lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) | + INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) | + INSTR1(LUT_READ)); + qspi_write32(&regs->lut[lut_base + 2], 0); + qspi_write32(&regs->lut[lut_base + 3], 0); + + /* Read Status */ + lut_base = SEQID_RDSR * 4; + qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_RDSR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + qspi_write32(&regs->lut[lut_base + 1], 0); + qspi_write32(&regs->lut[lut_base + 2], 0); + qspi_write32(&regs->lut[lut_base + 3], 0); + + /* Erase a sector */ + lut_base = SEQID_SE * 4; + if (FSL_QSPI_FLASH_SIZE <= SZ_16M) + qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_SE) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + else + qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_SE_4B) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + qspi_write32(&regs->lut[lut_base + 1], 0); + qspi_write32(&regs->lut[lut_base + 2], 0); + qspi_write32(&regs->lut[lut_base + 3], 0); + + /* Erase the whole chip */ + lut_base = SEQID_CHIP_ERASE * 4; + qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_CHIP_ERASE) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); + qspi_write32(&regs->lut[lut_base + 1], 0); + qspi_write32(&regs->lut[lut_base + 2], 0); + qspi_write32(&regs->lut[lut_base + 3], 0); + + /* Page Program */ + lut_base = SEQID_PP * 4; + if (FSL_QSPI_FLASH_SIZE <= SZ_16M) + qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_PP) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + else + qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_PP_4B) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + qspi_write32(&regs->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) | + PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); + qspi_write32(&regs->lut[lut_base + 2], 0); + qspi_write32(&regs->lut[lut_base + 3], 0); + + /* READ ID */ + lut_base = SEQID_RDID * 4; + qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_RDID) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + qspi_write32(&regs->lut[lut_base + 1], 0); + qspi_write32(&regs->lut[lut_base + 2], 0); + qspi_write32(&regs->lut[lut_base + 3], 0); + + /* Lock the LUT */ + qspi_write32(&regs->lutkey, LUT_KEY_VALUE); + qspi_write32(&regs->lckcr, QSPI_LCKCR_LOCK); +} + +void spi_init() +{ + /* do nothing */ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct fsl_qspi *qspi; + struct fsl_qspi_regs *regs; + u32 reg_val, smpr_val; + u32 total_size, seq_id; + + if (bus >= ARRAY_SIZE(spi_bases)) + return NULL; + + qspi = spi_alloc_slave(struct fsl_qspi, bus, cs); + if (!qspi) + return NULL; + + qspi->reg_base = spi_bases[bus]; + qspi->amba_base = amba_bases[bus]; + + qspi->slave.max_write_size = TX_BUFFER_SIZE; + + regs = (struct fsl_qspi_regs *)qspi->reg_base; + qspi_write32(&regs->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); + + smpr_val = qspi_read32(&regs->smpr); + qspi_write32(&regs->smpr, smpr_val & ~(QSPI_SMPR_FSDLY_MASK | + QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK)); + qspi_write32(&regs->mcr, QSPI_MCR_RESERVED_MASK); + + total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; + qspi_write32(&regs->sfa1ad, FSL_QSPI_FLASH_SIZE | qspi->amba_base); + qspi_write32(&regs->sfa2ad, FSL_QSPI_FLASH_SIZE | qspi->amba_base); + qspi_write32(&regs->sfb1ad, total_size | qspi->amba_base); + qspi_write32(&regs->sfb2ad, total_size | qspi->amba_base); + + qspi_set_lut(qspi); + + smpr_val = qspi_read32(&regs->smpr); + smpr_val &= ~QSPI_SMPR_DDRSMP_MASK; + qspi_write32(&regs->smpr, smpr_val); + qspi_write32(&regs->mcr, QSPI_MCR_RESERVED_MASK); + + seq_id = 0; + reg_val = qspi_read32(&regs->bfgencr); + reg_val &= ~QSPI_BFGENCR_SEQID_MASK; + reg_val |= (seq_id << QSPI_BFGENCR_SEQID_SHIFT); + reg_val &= ~QSPI_BFGENCR_PAR_EN_MASK; + qspi_write32(&regs->bfgencr, reg_val); + + return &qspi->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct fsl_qspi *qspi = to_qspi_spi(slave); + + free(qspi); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +static void qspi_op_rdid(struct fsl_qspi *qspi, u32 *rxbuf, u32 len) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 mcr_reg, rbsr_reg, data; + int i, size; + + mcr_reg = qspi_read32(&regs->mcr); + qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS); + + qspi_write32(&regs->sfar, qspi->amba_base); + + qspi_write32(&regs->ipcr, (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + ; + + i = 0; + size = len; + while ((RX_BUFFER_SIZE >= size) && (size > 0)) { + rbsr_reg = qspi_read32(&regs->rbsr); + if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) { + data = qspi_read32(&regs->rbdr[i]); + data = qspi_endian_xchg(data); + memcpy(rxbuf, &data, 4); + rxbuf++; + size -= 4; + i++; + } + } + + qspi_write32(&regs->mcr, mcr_reg); +} + +static void qspi_op_read(struct fsl_qspi *qspi, u32 *rxbuf, u32 len) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 mcr_reg, data; + int i, size; + u32 to_or_from; + + mcr_reg = qspi_read32(&regs->mcr); + qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS); + + to_or_from = qspi->sf_addr + qspi->amba_base; + + while (len > 0) { + qspi_write32(&regs->sfar, to_or_from); + + size = (len > RX_BUFFER_SIZE) ? + RX_BUFFER_SIZE : len; + + qspi_write32(&regs->ipcr, + (SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) | size); + while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + ; + + to_or_from += size; + len -= size; + + i = 0; + while ((RX_BUFFER_SIZE >= size) && (size > 0)) { + data = qspi_read32(&regs->rbdr[i]); + data = qspi_endian_xchg(data); + memcpy(rxbuf, &data, 4); + rxbuf++; + size -= 4; + i++; + } + qspi_write32(&regs->mcr, qspi_read32(&regs->mcr) | + QSPI_MCR_CLR_RXF_MASK); + } + + qspi_write32(&regs->mcr, mcr_reg); +} + +static void qspi_op_pp(struct fsl_qspi *qspi, u32 *txbuf, u32 len) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 mcr_reg, data, reg, status_reg; + int i, size, tx_size; + u32 to_or_from = 0; + + mcr_reg = qspi_read32(&regs->mcr); + qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS); + + status_reg = 0; + while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) { + qspi_write32(&regs->ipcr, + (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + ; + + qspi_write32(&regs->ipcr, + (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1); + while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + ; + + reg = qspi_read32(&regs->rbsr); + if (reg & QSPI_RBSR_RDBFL_MASK) { + status_reg = qspi_read32(&regs->rbdr[0]); + status_reg = qspi_endian_xchg(status_reg); + } + qspi_write32(&regs->mcr, + qspi_read32(&regs->mcr) | QSPI_MCR_CLR_RXF_MASK); + } + + to_or_from = qspi->sf_addr + qspi->amba_base; + qspi_write32(&regs->sfar, to_or_from); + + tx_size = (len > TX_BUFFER_SIZE) ? + TX_BUFFER_SIZE : len; + + size = (tx_size + 3) / 4; + + for (i = 0; i < size; i++) { + data = qspi_endian_xchg(*txbuf); + qspi_write32(&regs->tbdr, data); + txbuf++; + } + + qspi_write32(&regs->ipcr, + (SEQID_PP << QSPI_IPCR_SEQID_SHIFT) | tx_size); + while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + ; + + qspi_write32(&regs->mcr, mcr_reg); +} + +static void qspi_op_rdsr(struct fsl_qspi *qspi, u32 *rxbuf) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 mcr_reg, reg, data; + + mcr_reg = qspi_read32(&regs->mcr); + qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS); + + qspi_write32(&regs->sfar, qspi->amba_base); + + qspi_write32(&regs->ipcr, + (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + ; + + while (1) { + reg = qspi_read32(&regs->rbsr); + if (reg & QSPI_RBSR_RDBFL_MASK) { + data = qspi_read32(&regs->rbdr[0]); + data = qspi_endian_xchg(data); + memcpy(rxbuf, &data, 4); + qspi_write32(&regs->mcr, qspi_read32(&regs->mcr) | + QSPI_MCR_CLR_RXF_MASK); + break; + } + } + + qspi_write32(&regs->mcr, mcr_reg); +} + +static void qspi_op_se(struct fsl_qspi *qspi) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 mcr_reg; + u32 to_or_from = 0; + + mcr_reg = qspi_read32(&regs->mcr); + qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS); + + to_or_from = qspi->sf_addr + qspi->amba_base; + qspi_write32(&regs->sfar, to_or_from); + + qspi_write32(&regs->ipcr, + (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + ; + + qspi_write32(&regs->ipcr, + (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK) + ; + + qspi_write32(&regs->mcr, mcr_reg); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct fsl_qspi *qspi = to_qspi_spi(slave); + u32 bytes = DIV_ROUND_UP(bitlen, 8); + static u32 pp_sfaddr; + u32 txbuf; + + if (dout) { + memcpy(&txbuf, dout, 4); + qspi->cur_seqid = *(u8 *)dout; + + if (flags == SPI_XFER_END) { + qspi->sf_addr = pp_sfaddr; + qspi_op_pp(qspi, (u32 *)dout, bytes); + return 0; + } + + if (qspi->cur_seqid == OPCODE_FAST_READ) { + qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; + } else if (qspi->cur_seqid == OPCODE_SE) { + qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; + qspi_op_se(qspi); + } else if (qspi->cur_seqid == OPCODE_PP) { + pp_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK; + } + } + + if (din) { + if (qspi->cur_seqid == OPCODE_FAST_READ) + qspi_op_read(qspi, din, bytes); + else if (qspi->cur_seqid == OPCODE_RDID) + qspi_op_rdid(qspi, din, bytes); + else if (qspi->cur_seqid == OPCODE_RDSR) + qspi_op_rdsr(qspi, din); + } + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* Nothing to do */ +} diff --git a/drivers/spi/fsl_qspi.h b/drivers/spi/fsl_qspi.h new file mode 100644 index 0000000..db400e6 --- /dev/null +++ b/drivers/spi/fsl_qspi.h @@ -0,0 +1,127 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * Register definitions for Freescale QSPI + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_QSPI_H_ +#define _FSL_QSPI_H_ + +struct fsl_qspi_regs { + u32 mcr; + u32 rsvd0[1]; + u32 ipcr; + u32 flshcr; + u32 buf0cr; + u32 buf1cr; + u32 buf2cr; + u32 buf3cr; + u32 bfgencr; + u32 soccr; + u32 rsvd1[2]; + u32 buf0ind; + u32 buf1ind; + u32 buf2ind; + u32 rsvd2[49]; + u32 sfar; + u32 rsvd3[1]; + u32 smpr; + u32 rbsr; + u32 rbct; + u32 rsvd4[15]; + u32 tbsr; + u32 tbdr; + u32 rsvd5[1]; + u32 sr; + u32 fr; + u32 rser; + u32 spndst; + u32 sptrclr; + u32 rsvd6[4]; + u32 sfa1ad; + u32 sfa2ad; + u32 sfb1ad; + u32 sfb2ad; + u32 rsvd7[28]; + u32 rbdr[32]; + u32 rsvd8[32]; + u32 lutkey; + u32 lckcr; + u32 rsvd9[2]; + u32 lut[64]; +}; + +#define QSPI_IPCR_SEQID_SHIFT 24 +#define QSPI_IPCR_SEQID_MASK (0xf << QSPI_IPCR_SEQID_SHIFT) + +#define QSPI_MCR_END_CFD_SHIFT 2 +#define QSPI_MCR_END_CFD_MASK (3 << QSPI_MCR_END_CFD_SHIFT) +#define QSPI_MCR_END_CFD_LE (1 << QSPI_MCR_END_CFD_SHIFT) +#define QSPI_MCR_DDR_EN_SHIFT 7 +#define QSPI_MCR_DDR_EN_MASK (1 << QSPI_MCR_DDR_EN_SHIFT) +#define QSPI_MCR_CLR_RXF_SHIFT 10 +#define QSPI_MCR_CLR_RXF_MASK (1 << QSPI_MCR_CLR_RXF_SHIFT) +#define QSPI_MCR_CLR_TXF_SHIFT 11 +#define QSPI_MCR_CLR_TXF_MASK (1 << QSPI_MCR_CLR_TXF_SHIFT) +#define QSPI_MCR_MDIS_SHIFT 14 +#define QSPI_MCR_MDIS_MASK (1 << QSPI_MCR_MDIS_SHIFT) +#define QSPI_MCR_RESERVED_SHIFT 16 +#define QSPI_MCR_RESERVED_MASK (0xf << QSPI_MCR_RESERVED_SHIFT) + +#define QSPI_SMPR_HSENA_SHIFT 0 +#define QSPI_SMPR_HSENA_MASK (1 << QSPI_SMPR_HSENA_SHIFT) +#define QSPI_SMPR_FSPHS_SHIFT 5 +#define QSPI_SMPR_FSPHS_MASK (1 << QSPI_SMPR_FSPHS_SHIFT) +#define QSPI_SMPR_FSDLY_SHIFT 6 +#define QSPI_SMPR_FSDLY_MASK (1 << QSPI_SMPR_FSDLY_SHIFT) +#define QSPI_SMPR_DDRSMP_SHIFT 16 +#define QSPI_SMPR_DDRSMP_MASK (7 << QSPI_SMPR_DDRSMP_SHIFT) + +#define QSPI_BFGENCR_SEQID_SHIFT 12 +#define QSPI_BFGENCR_SEQID_MASK (0xf << QSPI_BFGENCR_SEQID_SHIFT) +#define QSPI_BFGENCR_PAR_EN_SHIFT 16 +#define QSPI_BFGENCR_PAR_EN_MASK (1 << QSPI_BFGENCR_PAR_EN_SHIFT) + +#define QSPI_RBSR_RDBFL_SHIFT 8 +#define QSPI_RBSR_RDBFL_MASK (0x3f << QSPI_RBSR_RDBFL_SHIFT) + +#define QSPI_RBCT_RXBRD_SHIFT 8 +#define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT) + +#define QSPI_SR_BUSY_SHIFT 0 +#define QSPI_SR_BUSY_MASK (1 << QSPI_SR_BUSY_SHIFT) + +#define QSPI_LCKCR_LOCK 0x1 +#define QSPI_LCKCR_UNLOCK 0x2 + +#define LUT_KEY_VALUE 0x5af05af0 + +#define OPRND0_SHIFT 0 +#define OPRND0(x) ((x) << OPRND0_SHIFT) +#define PAD0_SHIFT 8 +#define PAD0(x) ((x) << PAD0_SHIFT) +#define INSTR0_SHIFT 10 +#define INSTR0(x) ((x) << INSTR0_SHIFT) +#define OPRND1_SHIFT 16 +#define OPRND1(x) ((x) << OPRND1_SHIFT) +#define PAD1_SHIFT 24 +#define PAD1(x) ((x) << PAD1_SHIFT) +#define INSTR1_SHIFT 26 +#define INSTR1(x) ((x) << INSTR1_SHIFT) + +#define LUT_CMD 1 +#define LUT_ADDR 2 +#define LUT_DUMMY 3 +#define LUT_READ 7 +#define LUT_WRITE 8 + +#define LUT_PAD1 0 +#define LUT_PAD2 1 +#define LUT_PAD4 2 + +#define ADDR24BIT 0x18 +#define ADDR32BIT 0x20 + +#endif /* _FSL_QSPI_H_ */ -- 1.8.4

2 3

[U-Boot] [PULL u-boot-arm]: sunxi fixes + sun4i and sun5i support
by Hans de Goede 09 Jun '14

09 Jun '14

<resend with u-boot list in the CC, sorry about that> Hi Albert, Please pull from my tree for various sunxi fixes + sun4i and sun5i support, all these patches have been reviewed and acked by Ian Campbell. I've not included the i2c and axp pmic patches from my previous posting of these series into this pull-req as these need more work. The following changes since commit 55e8250bd3cfd996d1caa04f520160a89ec04754: Merge branch 'master' of git://git.denx.de/u-boot-arm (2014-06-08 07:58:41 -0400) are available in the git repository at: git://github.com/jwrdegoede/u-boot-sunxi.git sunxi-for-albert for you to fetch changes up to e3dc508420eb8074b003d18a5177b5bd9ec6961c: sunxi: Add Ian Campbell and Hans de Goede as cubietruck board-maintainers (2014-06-09 08:50:20 +0200) ---------------------------------------------------------------- Chen-Yu Tsai (1): sunxi: Add support for using MII phy-s with the GMAC nic Hans de Goede (8): sunxi: mksunxiboot: Fix loading of files with a size which is not a multiple of 4 sunxi: Fix u-boot-spl.lds to refer to .vectors sunxi: Remove mmc DMA support sunxi: Implement reset_cpu sunxi: Add sun4i support sunxi: Add sun5i support sunxi: Add emac glue, enable emac on the cubieboard sunxi: Add Ian Campbell and Hans de Goede as cubietruck board-maintainers Stefan Roese (1): net: Rename and cleanup sunxi (Allwinner) emac driver arch/arm/cpu/armv7/sunxi/Makefile | 4 + arch/arm/cpu/armv7/sunxi/board.c | 27 ++++++ arch/arm/cpu/armv7/sunxi/cpu_info.c | 15 +++ arch/arm/cpu/armv7/sunxi/dram.c | 102 +++++++++++++++++++- arch/arm/cpu/armv7/sunxi/u-boot-spl.lds | 1 + arch/arm/include/asm/arch-sunxi/timer.h | 5 + board/sunxi/Makefile | 3 + board/sunxi/dram_a13_oli_micro.c | 32 +++++++ board/sunxi/dram_cubieboard.c | 31 ++++++ board/sunxi/dram_r7dongle.c | 31 ++++++ board/sunxi/gmac.c | 11 +++ boards.cfg | 7 +- drivers/mmc/sunxi_mmc.c | 140 ++-------------------------- drivers/net/Makefile | 2 +- drivers/net/{sunxi_wemac.c => sunxi_emac.c} | 140 ++++++++++++++-------------- include/configs/sun4i.h | 23 +++++ include/configs/sun5i.h | 23 +++++ include/configs/sunxi-common.h | 8 +- include/netdev.h | 2 +- tools/mksunxiboot.c | 10 +- 20 files changed, 397 insertions(+), 220 deletions(-) create mode 100644 board/sunxi/dram_a13_oli_micro.c create mode 100644 board/sunxi/dram_cubieboard.c create mode 100644 board/sunxi/dram_r7dongle.c rename drivers/net/{sunxi_wemac.c => sunxi_emac.c} (78%) create mode 100644 include/configs/sun4i.h create mode 100644 include/configs/sun5i.h Thanks & Regards, Hans

1 0

[U-Boot] Pull request: u-boot-arm/master
by Albert ARIBAUD 09 Jun '14

09 Jun '14

Hi Tom, The following changes since commit 9637a1bb896efe392a58dd2772e2c3fcb646409d: ARM: at91sam9m10g45ek: add mmc environment configuration support (2014-05-27 00:10:55 +0200) are available in the git repository at: git://git.denx.de/u-boot-arm master for you to fetch changes up to 5ed28948a3ffe6c735386e59c132989869beaa3e: Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' (2014-06-08 09:14:19 +0200) ---------------------------------------------------------------- Aaron Durbin (3): exynos5: Enable tps65090 on exynos5-dt power: Explicitly select pmic device's bus exynos5: support tps65090 pmic Albert ARIBAUD (2): Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' Beomho Seo (3): arm: exynos: pinmux: add sdmmc4 gpio configratuion arm: exynos: clock: Remove exynos4x12_set_mmc_clk function board: trats2: Enable device tree on Trats2 Brian Norris (2): mtd: nand: don't use read_buf for 8-bit ONFI transfers mtd: nand: force NAND_CMD_READID onto 8-bit bus David Mosberger (1): mtd: nand: fix GET/SET_FEATURES address on 16-bit devices Doug Anderson (1): Exynos: Make sure ps_hold gets set in the SPL Hannes Petermaier (6): arch-am33xx: Add defines for timer0-7 board/BuR/common: introduce usage of CONFIG_SYS_GENERIC_BOARD board/BuR/tseries: Add support for using 8-bit on eMMC board/BuR/tseries: only run gpmc_init(...) in NAND-build board/BuR/common: Add CONFIG_CMD_I2C board/BuR/tseries: cosmetic changes Jaehoon Chung (12): ARM: exynos: board: change the mmc/sd init sequence ARM: exynos: clock: modify the set_mmc_clk for exynos4 ARM: dts: exynos: rename from EXYNOS5_DWMMC to EXYNOS_DWMMC mmc: exynos_dw_mmc: restore the property into host mmc: remove the unnecessary define and fix the wrong bit control mmc: support the DDR mode for eMMC mmc: dw_mmc: support the DDR mode ARM: dts: exnyos: enable dw-mmc controller mmc: exynos_dw_mmc: enable the DDR mode ARM: exynos4: enable the dwmmc configuration mmc: s5p_sdhci: add the s5p_sdhci_core_init function ARM: exynos5420: removed undefined gpio structure Jeroen Hofstee (1): tam3517: fix NAND detection Lokesh Vutla (2): ARM: AM43xx: Fix mmcboot command in EXTRA_ENV_SETTINGS ARM: AM43xx: Fix UART clocks enabling Mateusz Zalega (4): arm: goni: Update configuration for Goni target arm: goni: dfu: Add support for DFU to Goni target arm: goni: enable GPT command arm: goni: enable USB Mass Storage Murali Karicheri (1): keystone: init: enable UART1 to be able use it from kernel Piotr Wilczek (1): arm:board:exynos4: add CONFIG_SYS_GENERIC_BOARD Simon Glass (8): exynos: dts: Correct EC interrupt GPIO exynos: Drop old smdk5250.c file power: Rename CONFIG_PMIC_... to CONFIG_POWER_... power: Add PMIC_ prefix to CHARGER_EN/DISABLE exynos: Enable PSHOLD in SPL exynos: dts: Enable LCD for snow exynos: Enable the LCD backlight for snow initcall: Improve debugging support Sourav Poddar (2): am43xx_evm: Add qspiboot target ti: qspi: populate slave device to set flash quad bit. Stephen Warren (1): ARM: tegra: enable USB device mode and UMS on some boards Tom Rini (6): arm:am33xx: Make dram_init call sdram_init() in some contexts arm:am33xx: Rework s_init and add board_early_init_f am43xx: Only read the MPU frequency bits of CTRL_DEV_ATTR arm:am33xx: Add a scale_vcores() hook power: Add support for the TPS65218 PMIC arm:am43xx: Add TPS65218 support to scale voltages up Tom Wai-Hong Tam (1): power: Add support for TPS65090 PMU chip. WingMan Kwok (1): keystone: k2hk: enable support of nand ecclayout command pekon gupta (12): mtd: nand: omap_elm: remove #include omap_gpmc.h mtd: nand: omap_elm: use bch_type instead of nibble count to differentiate between BCH4/BCH8/BCH16 mtd: nand: omap_elm: use macros for register definitions mtd: nand: omap_gpmc: remove unused members of 'struct nand_bch_priv' mtd: nand: omap_gpmc: rename struct nand_bch_priv to struct omap_nand_info mtd: nand: omap_gpmc: minor cleanup of omap_correct_data_bch mtd: nand: omap: fix error-codes returned from omap-elm driver mtd: nand: omap: add CONFIG_SYS_NAND_BUSWIDTH_16BIT to indicate NAND device bus-width omap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT mtd: nand: omap_gpmc: use macro for register definitions mtd: nand: omap: add support for BCH16_ECC - NAND driver updates am335x: update README for BCH16 arch/arm/cpu/armv7/am33xx/board.c | 20 +- arch/arm/cpu/armv7/am33xx/clock.c | 11 + arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 9 + arch/arm/cpu/armv7/am33xx/emif4.c | 4 + arch/arm/cpu/armv7/exynos/clock.c | 45 +-- arch/arm/cpu/armv7/exynos/lowlevel_init.c | 8 +- arch/arm/cpu/armv7/exynos/pinmux.c | 35 +- arch/arm/cpu/armv7/exynos/power.c | 6 + arch/arm/cpu/armv7/keystone/init.c | 9 + arch/arm/cpu/armv7/omap3/mem.c | 12 - arch/arm/dts/exynos4.dtsi | 8 + arch/arm/dts/exynos4412-trats2.dts | 12 + arch/arm/dts/exynos5.dtsi | 8 +- arch/arm/dts/exynos5250-snow.dts | 61 +++- arch/arm/dts/tegra124-jetson-tk1.dts | 9 +- arch/arm/dts/tegra124-venice2.dts | 9 +- arch/arm/dts/tegra30-beaver.dts | 9 +- arch/arm/include/asm/arch-am33xx/clock.h | 1 + arch/arm/include/asm/arch-am33xx/cpu.h | 35 +- arch/arm/include/asm/arch-exynos/clk.h | 5 + arch/arm/include/asm/arch-exynos/power.h | 1 + arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 2 - arch/arm/include/asm/arch-keystone/hardware.h | 3 + arch/arm/include/asm/arch-omap3/mem.h | 8 - board/BuR/tseries/board.c | 2 + board/BuR/tseries/mux.c | 9 +- board/compulab/cm_t35/cm_t35.c | 12 +- board/samsung/common/board.c | 13 +- board/samsung/goni/goni.c | 8 + board/samsung/smdk5250/Makefile | 4 - board/samsung/smdk5250/exynos5-dt.c | 238 +++++++++++++- board/samsung/smdk5250/smdk5250.c | 363 --------------------- board/samsung/smdk5420/smdk5420.c | 3 - board/ti/am43xx/Makefile | 2 +- board/ti/am43xx/board.c | 55 +++- boards.cfg | 1 + doc/README.nand | 60 ++++ doc/device-tree-bindings/exynos/dwmmc.txt | 8 +- doc/device-tree-bindings/power/tps65090.txt | 17 + doc/device-tree-bindings/regulator/tps65090.txt | 122 +++++++ drivers/mmc/dw_mmc.c | 12 +- drivers/mmc/exynos_dw_mmc.c | 205 +++++++----- drivers/mmc/mmc.c | 16 +- drivers/mmc/s5p_sdhci.c | 42 +-- drivers/mtd/nand/am335x_spl_bch.c | 2 +- drivers/mtd/nand/atmel_nand.c | 2 +- drivers/mtd/nand/nand_base.c | 11 +- drivers/mtd/nand/nand_spl_simple.c | 2 +- drivers/mtd/nand/omap_elm.c | 28 +- drivers/mtd/nand/omap_gpmc.c | 193 +++++++---- drivers/power/battery/bat_trats.c | 4 +- drivers/power/battery/bat_trats2.c | 2 +- drivers/power/mfd/pmic_max77693.c | 2 +- drivers/power/pmic/Makefile | 2 + drivers/power/pmic/pmic_max8997.c | 2 +- drivers/power/pmic/pmic_tps65090.c | 310 ++++++++++++++++++ drivers/power/pmic/pmic_tps65218.c | 97 ++++++ drivers/power/power_fsl.c | 6 +- drivers/power/power_i2c.c | 4 + drivers/spi/ti_qspi.c | 1 + include/configs/am3517_crane.h | 1 + include/configs/am43xx_evm.h | 45 ++- include/configs/arndale.h | 4 +- include/configs/beaver.h | 2 + include/configs/bur_am335x_common.h | 4 +- include/configs/cm_t335.h | 1 - include/configs/cm_t35.h | 1 - include/configs/devkit8000.h | 1 + include/configs/dig297.h | 1 + include/configs/exynos4-dt.h | 4 + include/configs/exynos5-dt.h | 1 + include/configs/exynos5250-dt.h | 2 +- include/configs/jetson-tk1.h | 2 + include/configs/k2hk_evm.h | 4 +- include/configs/mx25pdk.h | 2 +- include/configs/mx35pdk.h | 2 +- include/configs/mx53evk.h | 2 +- include/configs/mx53loco.h | 2 +- include/configs/omap3_beagle.h | 1 + include/configs/omap3_evm_common.h | 2 +- include/configs/omap3_igep00x0.h | 1 + include/configs/omap3_logic.h | 1 + include/configs/omap3_overo.h | 1 + include/configs/omap3_zoom1.h | 1 + include/configs/pengwyn.h | 1 - include/configs/s5p_goni.h | 113 +++++-- include/configs/tam3517-common.h | 2 + include/configs/tao3530.h | 2 +- include/configs/tegra-common-ums.h | 26 ++ include/configs/ti_am335x_common.h | 9 + include/configs/ti_armv7_common.h | 3 +- include/configs/tseries.h | 1 - include/configs/venice2.h | 2 + include/configs/woodburn_common.h | 2 +- include/dwmmc.h | 5 + include/fdtdec.h | 4 +- include/initcall.h | 2 +- include/linux/mtd/nand.h | 19 ++ include/linux/mtd/omap_elm.h | 11 +- include/linux/mtd/omap_gpmc.h | 11 +- include/mmc.h | 25 +- include/power/max77693_pmic.h | 2 - include/power/max8997_pmic.h | 1 - include/power/pmic.h | 5 + include/power/tps65090_pmic.h | 73 +++++ include/power/tps65218.h | 63 ++++ lib/fdtdec.c | 4 +- lib/initcall.c | 17 +- 108 files changed, 1918 insertions(+), 763 deletions(-) delete mode 100644 board/samsung/smdk5250/smdk5250.c create mode 100644 doc/device-tree-bindings/power/tps65090.txt create mode 100644 doc/device-tree-bindings/regulator/tps65090.txt create mode 100644 drivers/power/pmic/pmic_tps65090.c create mode 100644 drivers/power/pmic/pmic_tps65218.c create mode 100644 include/configs/tegra-common-ums.h create mode 100644 include/power/tps65090_pmic.h create mode 100644 include/power/tps65218.h Amicalement, -- Albert.

2 1

[U-Boot] [PATCH/RFC] Reintegration of ns9750
by soderstrom.rikard＠gmail.com 08 Jun '14

08 Jun '14

From: Rikard Söderström <soderstrom.rikard(a)gmail.com> This patch is an RFC. ns9750 was removed in commit 4cfc611b4a4ce009cfad46804bec2a1caad8e329, this is an attempt to make it work again. Comparing the files from removal revision and current, there are changes made in board/ns9750dev/ns9750dev.c and in include/configs/ns9750dev.h Currently this fails at linkage stage. Signed-off-by: Rikard Söderström <soderstrom.rikard(a)gmail.com> Cc: Marex <Marex(a)denx.de> --- arch/arm/cpu/arm926ejs/ns9750/Makefile | 8 + arch/arm/cpu/arm926ejs/ns9750/reset.S | 29 ++ arch/arm/cpu/arm926ejs/ns9750/timer.c | 16 ++ board/ns9750dev/Makefile | 9 + board/ns9750dev/flash.c | 474 +++++++++++++++++++++++++++++++++ board/ns9750dev/led.c | 46 ++++ board/ns9750dev/lowlevel_init.S | 298 +++++++++++++++++++++ board/ns9750dev/ns9750dev.c | 127 +++++++++ boards.cfg | 1 + doc/README.ns9750dev | 36 +++ drivers/serial/Makefile | 1 + drivers/serial/ns9750_serial.c | 219 +++++++++++++++ drivers/serial/serial.c | 2 + include/configs/ns9750dev.h | 201 ++++++++++++++ include/ns9750_bbus.h | 125 +++++++++ include/ns9750_mem.h | 172 ++++++++++++ include/ns9750_ser.h | 202 ++++++++++++++ include/ns9750_sys.h | 215 +++++++++++++++ 18 files changed, 2181 insertions(+) create mode 100644 arch/arm/cpu/arm926ejs/ns9750/Makefile create mode 100644 arch/arm/cpu/arm926ejs/ns9750/reset.S create mode 100644 arch/arm/cpu/arm926ejs/ns9750/timer.c create mode 100644 board/ns9750dev/Makefile create mode 100644 board/ns9750dev/flash.c create mode 100644 board/ns9750dev/led.c create mode 100644 board/ns9750dev/lowlevel_init.S create mode 100644 board/ns9750dev/ns9750dev.c create mode 100644 doc/README.ns9750dev create mode 100644 drivers/serial/ns9750_serial.c create mode 100644 include/configs/ns9750dev.h create mode 100644 include/ns9750_bbus.h create mode 100644 include/ns9750_mem.h create mode 100644 include/ns9750_ser.h create mode 100644 include/ns9750_sys.h diff --git a/arch/arm/cpu/arm926ejs/ns9750/Makefile b/arch/arm/cpu/arm926ejs/ns9750/Makefile new file mode 100644 index 0000000..5a1f05c --- /dev/null +++ b/arch/arm/cpu/arm926ejs/ns9750/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset.o timer.o diff --git a/arch/arm/cpu/arm926ejs/ns9750/reset.S b/arch/arm/cpu/arm926ejs/ns9750/reset.S new file mode 100644 index 0000000..1c557b0 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/ns9750/reset.S @@ -0,0 +1,29 @@ +/* + * armboot - Startup Code for ARM926EJS CPU-core + * + * Copyright (c) 2003 Texas Instruments + * + * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ + * + * Copyright (c) 2001 Marius Gröger <mag(a)sysgo.de> + * Copyright (c) 2002 Alex Züpke <azu(a)sysgo.de> + * Copyright (c) 2002 Gary Jennejohn <garyj(a)denx.de> + * Copyright (c) 2003 Richard Woodruff <r-woodruff2(a)ti.com> + * Copyright (c) 2003 Kshitij <kshitij(a)ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + .align 5 +.globl reset_cpu +reset_cpu: + ldr r1, rstctl1 /* get clkm1 reset ctl */ + mov r3, #0x0 + strh r3, [r1] /* clear it */ + mov r3, #0x8 + strh r3, [r1] /* force dsp+arm reset */ +_loop_forever: + b _loop_forever + +rstctl1: + .word 0xfffece10 diff --git a/arch/arm/cpu/arm926ejs/ns9750/timer.c b/arch/arm/cpu/arm926ejs/ns9750/timer.c new file mode 100644 index 0000000..00e6c1e --- /dev/null +++ b/arch/arm/cpu/arm926ejs/ns9750/timer.c @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2014 + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + return CONFIG_SYS_HZ; +} diff --git a/board/ns9750dev/Makefile b/board/ns9750dev/Makefile new file mode 100644 index 0000000..bc8c08c --- /dev/null +++ b/board/ns9750dev/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = ns9750dev.o flash.o led.o +obj-y += lowlevel_init.o diff --git a/board/ns9750dev/flash.c b/board/ns9750dev/flash.c new file mode 100644 index 0000000..185bc2d --- /dev/null +++ b/board/ns9750dev/flash.c @@ -0,0 +1,474 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * (C) Copyright 2003 + * Texas Instruments, <www.ti.com> + * Kshitij Gupta <Kshitij(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/byteorder/swab.h> + +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#undef FLASH_PORT_WIDTH32 +#define FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + + +/* Flash Organization Structure */ +typedef struct OrgDef { + unsigned int sector_number; + unsigned int sector_size; +} OrgDef; + + +/* Flash Organizations */ +OrgDef OrgIntel_28F256L18T[] = { + {4, 32 * 1024}, /* 4 * 32kBytes sectors */ + {255, 128 * 1024}, /* 255 * 128kBytes sectors */ +}; + + +/*----------------------------------------------------------------------- + * Functions + */ +unsigned long flash_init (void); +static ulong flash_get_size (FPW * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); +void inline spin_wheel (void); +void flash_print_info (flash_info_t * info); +void flash_unprotect_sectors (FPWV * addr); +int flash_erase (flash_info_t * info, int s_first, int s_last); +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + OrgDef *pOrgDef; + + pOrgDef = OrgIntel_28F256L18T; + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + if (i > 255) { + info->start[i] = base + (i * 0x8000); + info->protect[i] = 0; + } else { + info->start[i] = base + + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F256L18T: + printf ("FLASH 28F256L18T\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + switch (value) { + + case (FPW) (INTEL_ID_28F256L18T): + info->flash_id += FLASH_28F256L18T; + info->sector_count = 259; + info->size = 0x02000000; + break; /* => 32 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/* unprotects a sector for write and erase + * on some intel parts, this unprotects the entire chip, but it + * wont hurt to call this additional times per sector... + */ +void flash_unprotect_sectors (FPWV * addr) +{ +#define PD_FINTEL_WSMS_READY_MASK 0x0080 + + *addr = (FPW) 0x00500050; /* clear status register */ + + /* this sends the clear lock bit command */ + *addr = (FPW) 0x00600060; + *addr = (FPW) 0x00D000D0; +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + flash_unprotect_sectors (addr); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + *addr = (FPW) 0x00500050;/* clear status register */ + *addr = (FPW) 0x00200020;/* erase setup */ + *addr = (FPW) 0x00D000D0;/* erase confirm */ + + while (((status = + *addr) & (FPW) 0x00800080) != + (FPW) 0x00800080) { + if (get_timer(start) > + CONFIG_SYS_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + /* suspend erase */ + *addr = (FPW) 0x00B000B0; + /* reset to read mode */ + *addr = (FPW) 0x00FF00FF; + rcode = 1; + break; + } + } + + /* clear status register cmd. */ + *addr = (FPW) 0x00500050; + *addr = (FPW) 0x00FF00FF;/* resest to read mode */ + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + ulong start; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); + return (2); + } + flash_unprotect_sectors (addr); + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/ns9750dev/led.c b/board/ns9750dev/led.c new file mode 100644 index 0000000..b85c869 --- /dev/null +++ b/board/ns9750dev/led.c @@ -0,0 +1,46 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: led.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ + * @Author: Markus Pietrek + * @Descr: Defines helper functions for toggeling LEDs + * @Usage: + * @References: [1] + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ***********************************************************************/ + +#ifdef CONFIG_STATUS_LED + +#include <ns9750_bbus.h> + +static inline void __led_init( led_id_t mask, int state ) +{ + XXXX; +} + +static inline void __led_toggle( led_id_t mask ) +{ +} + +static inline void __led_set( led_id_t mask, int state ) +{ +} + +#endif /* CONFIG_STATUS_LED */ diff --git a/board/ns9750dev/lowlevel_init.S b/board/ns9750dev/lowlevel_init.S new file mode 100644 index 0000000..ba5ff81 --- /dev/null +++ b/board/ns9750dev/lowlevel_init.S @@ -0,0 +1,298 @@ +/* + * Board specific setup info + * + * (C) Copyright 2003 + * Texas Instruments, <www.ti.com> + * Kshitij Gupta <Kshitij(a)ti.com> + * + * Modified for the NS9750 DevBoard by + * (C) Copyright 2004 by FS Forth-Systeme GmbH. + * Markus Pietrek <mpietrek(a)fsforth.de> + * @References: [1] NS9750 Hardware Reference/December 2003 + * [2] ns9750_a.cmd from MAJIC configuration + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +#if defined(CONFIG_NS9750DEV) +# ifndef CONFIG_SKIP_LOWLEVEL_INIT +# include <./ns9750_sys.h> +# include <./ns9750_mem.h> +# endif +#endif + +/*********************************************************************** + * @Function: write_register_block + * @Return: nothing + * @Descr: Copies the register block of register_offset:register value to + * the registers at base r0. The block is assumed to start in RAM at r1 + * and end at r2. The linked RAM base address of U-Boot is assumed to be + * in r5 while the ROM base address we are running from is r6 + * Uses r3 and r4 as tempory registers + ***********************************************************************/ + +.macro write_register_block + @@ map the addresses to high memory + sub r1, r1, r5 + add r1, r1, r6 + sub r2, r2, r5 + add r2, r2, r6 + + @@ copy all +1: + @@ Write register/value pair starting at [r1] to register base r0 + ldr r3, [r1], #4 + ldr r4, [r1], #4 + str r4, [r0,r3] + cmp r1, r2 + blt 1b +.endm + +_TEXT_BASE: + .word CONFIG_SYS_TEXT_BASE @ sdram load addr from config.mk +_PHYS_FLASH: + .word PHYS_FLASH_1 @ real flash address (without mirroring) +_CAS_LATENCY: + .word 0x00022000 @ for CAS2 latency + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +.globl lowlevel_init +lowlevel_init: + + /* U-Boot may be linked to RAM at 0x780000. But this code will run in + flash from 0x0. But in order to enable RAM we have to disable the + mirror bit, therefore we have to jump to our real flash address + beginning at PHYS_FLASH_1 (CS4 Base). Therefore, + _run_at_real_flash_address may be 0x500003b0 while be linked to + 0x7803b0. So we must modify our linked addresses */ + + @@ branch to high memory address, away from 0x0 + ldr r5, _TEXT_BASE + ldr r6, _PHYS_FLASH + ldr r0, =_run_at_real_flash_address + sub r0, r0, r5 + add r0, r0, r6 + mov pc, r0 + nop @ for pipelining + +_run_at_real_flash_address: + @@ now we are running > PHYS_FLASH_1, safe to enable memory controller + + @@ Write Memory Configuration Registers + + ldr r0, _NS9750_MEM_MODULE_BASE + ldr r1, =_MEM_CONFIG_START + ldr r2, =_MEM_CONFIG_END + + write_register_block + + @@ Give SDRAM some time to settle + @@ @TODO. According to [2] it should be 2 AHB cycles. Check + + ldr r1, =0x50 +_sdram_settle: + subs r1, r1, #1 + bne _sdram_settle + +_enable_mappings: + @@ Enable SDRAM Mode + + ldr r1, =_MEM_MODE_START + ldr r2, =_MEM_MODE_END + + write_register_block + + ldr r3, _CAS_LATENCY @ perform one read from SDRAM + ldr r3, [r3] + + @@ Enable SDRAM and memory mappings + + ldr r1, =_MEM_ENABLE_START + ldr r2, =_MEM_ENABLE_END + + write_register_block + + @@ Activate AHB monitor + + ldr r0, =NS9750_SYS_MODULE_BASE + ldr r1, =_AHB_MONITOR_START + ldr r2, =_AHB_MONITOR_END + + write_register_block +_relocate_lr: + /* lr and ip (from cpu_init_crit) are still based on 0x0, relocate it to + PHYS_FLASH. */ + mov r1, ip + add r1, r1, r6 + mov ip, r1 + + mov r1, lr + add r1, r1, r6 + mov lr, r1 + + @@ back to arch calling code + mov pc, lr + + .ltorg + +_NS9750_MEM_MODULE_BASE: + .word NS9750_MEM_MODULE_BASE + +_MEM_CONFIG_START: + /* Table of 2 32bit entries. First word is register address offset + relative to NS9750_MEM_MODULE_BASE, second one is value. They are + written in order of appearance */ + + @@ Register values taken from [2] + .word NS9750_MEM_CTRL + .word NS9750_MEM_CTRL_E + + .word NS9750_MEM_DYN_REFRESH + .word (0x6 & NS9750_MEM_DYN_REFRESH_MA) + + .word NS9750_MEM_DYN_READ_CFG + .word (0x1 & NS9750_MEM_DYN_READ_CFG_MA) + + .word NS9750_MEM_DYN_TRP + .word (0x1 & NS9750_MEM_DYN_TRP_MA) + + .word NS9750_MEM_DYN_TRAS + .word (0x4 & NS9750_MEM_DYN_TRAS_MA) + + .word NS9750_MEM_DYN_TAPR + .word (0x1 & NS9750_MEM_DYN_TRAS_MA) + + .word NS9750_MEM_DYN_TDAL + .word (0x5 & NS9750_MEM_DYN_TDAL_MA) + + .word NS9750_MEM_DYN_TWR + .word (0x1 & NS9750_MEM_DYN_TWR_MA) + + .word NS9750_MEM_DYN_TRC + .word (0x6 & NS9750_MEM_DYN_TRC_MA) + + .word NS9750_MEM_DYN_TRFC + .word (0x6 & NS9750_MEM_DYN_TRFC_MA) + + .word NS9750_MEM_DYN_TRRD + .word (0x1 & NS9750_MEM_DYN_TRRD_MA) + + .word NS9750_MEM_DYN_TMRD + .word (0x1 & NS9750_MEM_DYN_TMRD_MA) + + @@ CS 4 + .word NS9750_MEM_DYN_CFG(0) + .word (NS9750_MEM_DYN_CFG_AM | \ + (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) + + .word NS9750_MEM_DYN_RAS_CAS(0) + .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ + (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) + + @@ CS 5 + .word NS9750_MEM_DYN_CFG(1) + .word (NS9750_MEM_DYN_CFG_AM | \ + (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) + + .word NS9750_MEM_DYN_RAS_CAS(1) + .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ + (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) + + @@ CS 6 + .word NS9750_MEM_DYN_CFG(2) + .word (NS9750_MEM_DYN_CFG_AM | \ + (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) + + .word NS9750_MEM_DYN_RAS_CAS(2) + .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ + (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) + + @@ CS 7 + .word NS9750_MEM_DYN_CFG(3) + .word (NS9750_MEM_DYN_CFG_AM | \ + (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) + + .word NS9750_MEM_DYN_RAS_CAS(3) + .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ + (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) + + .word NS9750_MEM_DYN_CTRL + .word (NS9750_MEM_DYN_CTRL_I_PALL | \ + NS9750_MEM_DYN_CTRL_SR | \ + NS9750_MEM_DYN_CTRL_CE ) + + .word NS9750_MEM_DYN_REFRESH + .word (0x1 & NS9750_MEM_DYN_REFRESH_MA) + @@ No further register settings after refresh +_MEM_CONFIG_END: + +_MEM_MODE_START: + .word NS9750_MEM_DYN_REFRESH + .word (0x30 & NS9750_MEM_DYN_REFRESH_MA) + + .word NS9750_MEM_DYN_CTRL + .word (NS9750_MEM_DYN_CTRL_I_MODE | \ + NS9750_MEM_DYN_CTRL_SR | \ + NS9750_MEM_DYN_CTRL_CE ) +_MEM_MODE_END: + +_MEM_ENABLE_START: + .word NS9750_MEM_DYN_CTRL + .word (NS9750_MEM_DYN_CTRL_I_NORMAL | \ + NS9750_MEM_DYN_CTRL_SR | \ + NS9750_MEM_DYN_CTRL_CE ) + + @@ CS 4 + .word NS9750_MEM_DYN_CFG(0) + .word (NS9750_MEM_DYN_CFG_BDMC | \ + NS9750_MEM_DYN_CFG_AM | \ + (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) + + @@ CS 5 + .word NS9750_MEM_DYN_CFG(1) + .word (NS9750_MEM_DYN_CFG_BDMC | \ + NS9750_MEM_DYN_CFG_AM | \ + (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) + + @@ CS 6 + .word NS9750_MEM_DYN_CFG(2) + .word (NS9750_MEM_DYN_CFG_BDMC | \ + NS9750_MEM_DYN_CFG_AM | \ + (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) + + @@ CS 7 + .word NS9750_MEM_DYN_CFG(3) + .word (NS9750_MEM_DYN_CFG_BDMC | \ + NS9750_MEM_DYN_CFG_AM | \ + (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) +_MEM_ENABLE_END: + +_AHB_MONITOR_START: + .word NS9750_SYS_AHB_TIMEOUT + .word 0x01000100 @ @TODO not calculated yet + + .word NS9750_SYS_AHB_MON + .word (NS9750_SYS_AHB_MON_BMTC_GEN_IRQ | \ + NS9750_SYS_AHB_MON_BATC_GEN_IRQ) +_AHB_MONITOR_END: + +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/board/ns9750dev/ns9750dev.c b/board/ns9750dev/ns9750dev.c new file mode 100644 index 0000000..c4ee8ac --- /dev/null +++ b/board/ns9750dev/ns9750dev.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> + * + * (C) Copyright 2003 + * Texas Instruments, <www.ti.com> + * Kshitij Gupta <Kshitij(a)ti.com> + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * Markus Pietrek <mpietrek(a)fsforth.de> + * derived from omap1610innovator.c + * @References: [1] NS9750 Hardware Reference/December 2003 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#if defined(CONFIG_NS9750DEV) +# include <./configs/ns9750dev.h> +# include <./ns9750_bbus.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +void flash__init( void ); +void ether__init( void ); + +static inline void delay( unsigned long loops ) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + + +/*********************************************************************** + * @Function: board_init + * @Return: 0 + * @Descr: Enables BBUS modules and other devices + ***********************************************************************/ + +int board_init( void ) +{ + /* Active BBUS modules */ + *get_bbus_reg_addr( NS9750_BBUS_MASTER_RESET ) = 0; + +#warning Please register your machine at http://www.arm.linux.org.uk/developer/machines/?action=new + /* arch number of OMAP 1510-Board */ + /* to be changed for OMAP 1610 Board */ + gd->bd->bi_arch_number = 234; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x10000100; + + /* Detect ram size @TODO This feels strange considering the dram_init() part */ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + +/* this speeds up your boot a quite a bit. However to make it + * work, you need make sure your kernel startup flush bug is fixed. + * ... rkw ... + */ + icache_enable(); + + flash__init(); + ether__init(); + return 0; +} + + +int misc_init_r (void) +{ + /* currently empty */ + return (0); +} + +/****************************** + Routine: + Description: +******************************/ +void flash__init (void) +{ +} +/************************************************************* + Routine:ether__init + Description: take the Ethernet controller out of reset and wait + for the EEPROM load to complete. +*************************************************************/ +void ether__init (void) +{ +} + +/****************************** + Routine: + Description: +******************************/ +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + +#if CONFIG_NR_DRAM_BANKS > 1 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); +#endif + return 0; +} diff --git a/boards.cfg b/boards.cfg index 69c8936..f51df51 100644 --- a/boards.cfg +++ b/boards.cfg @@ -323,6 +323,7 @@ Active arm armv7 mx6 freescale mx6sabresd Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam(a)freescale.com> Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam(a)freescale.com> Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton(a)gmail.com> +Active arm arm926ejs ns9750 - ns9750dev ns9750dev - - Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman(a)gmail.com> Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas(a)gmail.com> Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat <raph(a)8d.com> diff --git a/doc/README.ns9750dev b/doc/README.ns9750dev new file mode 100644 index 0000000..2991440 --- /dev/null +++ b/doc/README.ns9750dev @@ -0,0 +1,36 @@ +U-Boot Port to the NS9750 DevKit from NetSilicon + +1 Overview +2 Board Configuration +3 Installation + + +1 Overview +---------- + +This port supports these NS9750 features. + +o one UART + +2 Board Configuration +--------------------- + +Switches: +SW10: 4 +SW11: 6,7 +SW16: 6,7,8 +SW17-SW20: 1 +SW4: 3, 6 +SW 1: 1 +SW2: 4 +SW3: 3 +SW8: 3 (rotated by 180 degree!!!!) + +Serial Console is Port B (bottom right port) + +3 Installation +-------------- + +Have fun, +-- +Markus Pietrek <mpietrek(a)fsforth.de> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 571c18f..6d75745 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o obj-$(CONFIG_MCFUART) += mcfuart.o +obj-$(CONFIG_NS9750_UART) += ns9750_serial.o obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o obj-$(CONFIG_SYS_NS16550) += ns16550.o obj-$(CONFIG_S5P) += serial_s5p.o diff --git a/drivers/serial/ns9750_serial.c b/drivers/serial/ns9750_serial.c new file mode 100644 index 0000000..2b7625c --- /dev/null +++ b/drivers/serial/ns9750_serial.c @@ -0,0 +1,219 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: ns9750_serial.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ + * @Author: Markus Pietrek + * @Descr: Serial driver for the NS9750. Only one UART is supported yet. + * @References: [1] NS9750 Hardware Reference/December 2003 + * @TODO: Implement Character GAP Timer when chip is fixed for PLL bypass + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ***********************************************************************/ + +#include <common.h> +#include <serial.h> + +#include "ns9750_bbus.h" /* for GPIOs */ +#include "ns9750_ser.h" /* for serial configuration */ + +DECLARE_GLOBAL_DATA_PTR; + +#if !defined(CONFIG_CONS_INDEX) +#error "No console index specified." +#endif + +#define CONSOLE CONFIG_CONS_INDEX + +static unsigned int calcBitrateRegister( void ); +static unsigned int calcRxCharGapRegister( void ); + +static char cCharsAvailable; /* Numbers of chars in unCharCache */ +static unsigned int unCharCache; /* unCharCache is only valid if + * cCharsAvailable > 0 */ + +/*********************************************************************** + * @Function: serial_init + * @Return: 0 + * @Descr: configures GPIOs and UART. Requires BBUS Master Reset turned off + ***********************************************************************/ + +static int ns9750_serial_init(void) +{ + unsigned int aunGPIOTxD[] = { 0, 8, 40, 44 }; + unsigned int aunGPIORxD[] = { 1, 9, 41, 45 }; + + cCharsAvailable = 0; + + /* configure TxD and RxD pins for their special function */ + set_gpio_cfg_reg_val( aunGPIOTxD[ CONSOLE ], + NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_OUTPUT ); + set_gpio_cfg_reg_val( aunGPIORxD[ CONSOLE ], + NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_INPUT ); + + /* configure serial engine */ + *get_ser_reg_addr_channel( NS9750_SER_CTRL_A, CONSOLE ) = + NS9750_SER_CTRL_A_CE | + NS9750_SER_CTRL_A_STOP | + NS9750_SER_CTRL_A_WLS_8; + + serial_setbrg(); + + *get_ser_reg_addr_channel( NS9750_SER_CTRL_B, CONSOLE ) = + NS9750_SER_CTRL_B_RCGT; + + return 0; +} + +/*********************************************************************** + * @Function: serial_putc + * @Return: n/a + * @Descr: writes one character to the FIFO. Blocks until FIFO is not full + ***********************************************************************/ + +static void ns9750_serial_putc(const char c) +{ + if (c == '\n') + serial_putc( '\r' ); + + while (!(*get_ser_reg_addr_channel( NS9750_SER_STAT_A, CONSOLE) & + NS9750_SER_STAT_A_TRDY ) ) { + /* do nothing, wait for characters in FIFO sent */ + } + + *(volatile char*) get_ser_reg_addr_channel( NS9750_SER_FIFO, + CONSOLE) = c; +} + +/*********************************************************************** + * @Function: serial_getc + * @Return: the character read + * @Descr: performs only 8bit accesses to the FIFO. No error handling + ***********************************************************************/ + +static int ns9750_serial_getc(void) +{ + int i; + + while (!serial_tstc() ) { + /* do nothing, wait for incoming characters */ + } + + /* at least one character in unCharCache */ + i = (int) (unCharCache & 0xff); + + unCharCache >>= 8; + cCharsAvailable--; + + return i; +} + +/*********************************************************************** + * @Function: serial_tstc + * @Return: 0 if no input available, otherwise != 0 + * @Descr: checks for incoming FIFO not empty. Stores the incoming chars in + * unCharCache and the numbers of characters in cCharsAvailable + ***********************************************************************/ + +static int ns9750_serial_tstc(void) +{ + unsigned int unRegCache; + + if ( cCharsAvailable ) + return 1; + + unRegCache = *get_ser_reg_addr_channel( NS9750_SER_STAT_A,CONSOLE ); + if( unRegCache & NS9750_SER_STAT_A_RBC ) { + *get_ser_reg_addr_channel( NS9750_SER_STAT_A, CONSOLE ) = + NS9750_SER_STAT_A_RBC; + unRegCache = *get_ser_reg_addr_channel( NS9750_SER_STAT_A, + CONSOLE ); + } + + if ( unRegCache & NS9750_SER_STAT_A_RRDY ) { + cCharsAvailable = (unRegCache & NS9750_SER_STAT_A_RXFDB_MA)>>20; + if ( !cCharsAvailable ) + cCharsAvailable = 4; + + unCharCache = *get_ser_reg_addr_channel( NS9750_SER_FIFO, + CONSOLE ); + return 1; + } + + /* no chars available */ + return 0; +} + +static void ns9750_serial_setbrg(void) +{ + *get_ser_reg_addr_channel( NS9750_SER_BITRATE, CONSOLE ) = + calcBitrateRegister(); + *get_ser_reg_addr_channel( NS9750_SER_RX_CHAR_TIMER, CONSOLE ) = + calcRxCharGapRegister(); +} + +/*********************************************************************** + * @Function: calcBitrateRegister + * @Return: value for the serial bitrate register + * @Descr: register value depends on clock frequency and baudrate + ***********************************************************************/ + +static unsigned int calcBitrateRegister( void ) +{ + return ( NS9750_SER_BITRATE_EBIT | + NS9750_SER_BITRATE_CLKMUX_BCLK | + NS9750_SER_BITRATE_TMODE | + NS9750_SER_BITRATE_TCDR_16 | + NS9750_SER_BITRATE_RCDR_16 | + ( ( ( ( CONFIG_SYS_CLK_FREQ / 8 ) / /* BBUS clock,[1] Fig. 38 */ + ( gd->baudrate * 16 ) ) - 1 ) & + NS9750_SER_BITRATE_N_MA ) ); +} + +/*********************************************************************** + * @Function: calcRxCharGapRegister + * @Return: value for the character gap timer register + * @Descr: register value depends on clock frequency and baudrate. Currently 0 + * is used as there is a bug with the gap timer in PLL bypass mode. + ***********************************************************************/ + +static unsigned int calcRxCharGapRegister( void ) +{ + return NS9750_SER_RX_CHAR_TIMER_TRUN; +} + +static struct serial_device ns9750_serial_drv = { + .name = "ns9750_serial", + .start = ns9750_serial_init, + .stop = NULL, + .setbrg = ns9750_serial_setbrg, + .putc = ns9750_serial_putc, + .puts = default_serial_puts, + .getc = ns9750_serial_getc, + .tstc = ns9750_serial_tstc, +}; + +void ns9750_serial_initialize(void) +{ + serial_register(&ns9750_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &ns9750_serial_drv; +} diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index df05bde..c9c10c5 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -160,6 +160,7 @@ serial_initfunc(sh_serial_initialize); serial_initfunc(arm_dcc_initialize); serial_initfunc(mxs_auart_initialize); serial_initfunc(arc_serial_initialize); +serial_initfunc(ns9750_serial_initialize); /** * serial_register() - Register serial driver with serial driver core @@ -253,6 +254,7 @@ void serial_initialize(void) arm_dcc_initialize(); mxs_auart_initialize(); arc_serial_initialize(); + ns9750_serial_initialize(); serial_assign(default_serial_console()->name); } diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h new file mode 100644 index 0000000..b364314 --- /dev/null +++ b/include/configs/ns9750dev.h @@ -0,0 +1,201 @@ +/* + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * Markus Pietrek <mpietrek(a)fsforth.de> + * + * Configuation settings for the NetSilicon NS9750 DevBoard + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_NS9750 1 /* in an NetSilicon NS9750 SoC */ +#define CONFIG_NS9750DEV 1 /* on an NetSilicon NS9750 DevBoard */ + +/* input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 324403200 /* Don't use PLL. SW11-4 off */ + +#define CPU_CLK_FREQ (CONFIG_SYS_CLK_FREQ/2) +#define AHB_CLK_FREQ (CONFIG_SYS_CLK_FREQ/4) +#define BBUS_CLK_FREQ (CONFIG_SYS_CLK_FREQ/8) + +/*@TODO #define CONFIG_STATUS_LED*/ +/*@TODO #define CONFIG_USE_IRQ*/ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) + +/* + * Hardware drivers + */ +#define CONFIG_NS9750_UART 1 /* use on-chip UART */ +/*@TODO #define CONFIG_DRIVER_NS9750_ETHERNET 1 */ /* use on-chip ethernet */ + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 1 /* Port B */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ + +#define CONFIG_CMD_BDI +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING + + +#define CONFIG_BOOTDELAY 3 +/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ + +#define CONFIG_ETHADDR 00:04:f3:ff:ff:fb /*@TODO unset */ +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.42.30 +#define CONFIG_SERVERIP 192.168.42.1 + +/*#define CONFIG_BOOTFILE "elinos-lart" */ +/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "NS9750DEV # " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00780000 /* 7,5 MB in DRAM */ /* @TODO */ + +#define CONFIG_SYS_LOAD_ADDR 0x00600000 /* default load address */ /* @TODO */ + +#define CONFIG_SYS_HZ (CPU_CLK_FREQ/64) + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define NS9750_ETH_PHY_ADDRESS (0x0000) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +/* TODO */ +#define CONFIG_NR_DRAM_BANKS 2 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */ +#define PHYS_SDRAM_2 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */ + +#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ + +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* @TODO*/ +#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ +#if 0 +#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ +#endif + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#ifdef CONFIG_AMD_LV800 +#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ +#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */ +#endif +#ifdef CONFIG_AMD_LV400 +#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ +#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */ +#endif + +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ + +/* @TODO */ +/*#define CONFIG_ENV_IS_IN_FLASH 1*/ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +#ifdef CONFIG_STATUS_LED + +extern void __led_init(led_id_t mask, int state); +extern void __led_toggle(led_id_t mask); +extern void __led_set(led_id_t mask, int state); + +#endif /* CONFIG_STATUS_LED */ + +#define CONFIG_SYS_TEXT_BASE 0x00780000 /* .text start address */ + +#endif /* __CONFIG_H */ diff --git a/include/ns9750_bbus.h b/include/ns9750_bbus.h new file mode 100644 index 0000000..9485338 --- /dev/null +++ b/include/ns9750_bbus.h @@ -0,0 +1,125 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: ns9750_bbus.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ + * @Author: Markus Pietrek + * @Descr: Definitions for BBus usage + * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 10 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + ***********************************************************************/ + +#ifndef FS_NS9750_BBUS_H +#define FS_NS9750_BBUS_H + +#define NS9750_BBUS_MODULE_BASE (0x90600000) + +#define get_bbus_reg_addr(c) \ + ((volatile unsigned int *)(NS9750_BBUS_MODULE_BASE+(unsigned int) (c))) + +/* We have support for 50 GPIO pins */ + +#define get_gpio_cfg_reg_addr(pin) \ + get_bbus_reg_addr( NS9750_BBUS_GPIO_CFG_BASE + (((pin) >> 3) * 4) ) + +/* To Read/Modify/Write a pin configuration register, use it like + set_gpio_cfg_reg_val( 12, NS9750_GPIO_CFG_FUNC_GPIO|NS9750_GPIO_CFG_OUTPUT ); + They should be wrapped by cli()/sti() */ +#define set_gpio_cfg_reg_val(pin,cfg) \ + *get_gpio_cfg_reg_addr(pin)=(*get_gpio_cfg_reg_addr((pin)) & \ + ~NS9750_GPIO_CFG_MASK((pin))) |\ + NS9750_GPIO_CFG_VAL((pin),(cfg)); + +#define NS9750_GPIO_CFG_MASK(pin) (NS9750_GPIO_CFG_VAL(pin, \ + NS9750_GPIO_CFG_MA)) +#define NS9750_GPIO_CFG_VAL(pin,cfg) ((cfg) << (((pin) % 8) * 4)) + +#define NS9750_GPIO_CFG_MA (0x0F) +#define NS9750_GPIO_CFG_INPUT (0x00) +#define NS9750_GPIO_CFG_OUTPUT (0x08) +#define NS9750_GPIO_CFG_FUNC_GPIO (0x03) +#define NS9750_GPIO_CFG_FUNC_2 (0x02) +#define NS9750_GPIO_CFG_FUNC_1 (0x01) +#define NS9750_GPIO_CFG_FUNC_0 (0x00) + +/* the register addresses */ + +#define NS9750_BBUS_MASTER_RESET (0x00) +#define NS9750_BBUS_GPIO_CFG_BASE (0x10) +#define NS9750_BBUS_GPIO_CTRL_BASE (0x30) +#define NS9750_BBUS_GPIO_STAT_BASE (0x40) +#define NS9750_BBUS_MONITOR (0x50) +#define NS9750_BBUS_DMA_INT_STAT (0x60) +#define NS9750_BBUS_DMA_INT_ENABLE (0x64) +#define NS9750_BBUS_USB_CFG (0x70) +#define NS9750_BBUS_ENDIAN_CFG (0x80) +#define NS9750_BBUS_ARM_WAKE_UP (0x90) + +/* register bit fields */ + +#define NS9750_BBUS_MASTER_RESET_UTIL (0x00000100) +#define NS9750_BBUS_MASTER_RESET_I2C (0x00000080) +#define NS9750_BBUS_MASTER_RESET_1284 (0x00000040) +#define NS9750_BBUS_MASTER_RESET_SER4 (0x00000020) +#define NS9750_BBUS_MASTER_RESET_SER3 (0x00000010) +#define NS9750_BBUS_MASTER_RESET_SER2 (0x00000008) +#define NS9750_BBUS_MASTER_RESET_SER1 (0x00000004) +#define NS9750_BBUS_MASTER_RESET_USB (0x00000002) +#define NS9750_BBUS_MASTER_RESET_DMA (0x00000001) + +/* BS9750_BBUS_DMA_INT_BINT* are valid for *DMA_INT_STAT and *DMA_INT_ENABLE */ + +#define NS9750_BBUS_DMA_INT_BINT16 (0x00010000) +#define NS9750_BBUS_DMA_INT_BINT15 (0x00008000) +#define NS9750_BBUS_DMA_INT_BINT14 (0x00004000) +#define NS9750_BBUS_DMA_INT_BINT13 (0x00002000) +#define NS9750_BBUS_DMA_INT_BINT12 (0x00001000) +#define NS9750_BBUS_DMA_INT_BINT11 (0x00000800) +#define NS9750_BBUS_DMA_INT_BINT10 (0x00000400) +#define NS9750_BBUS_DMA_INT_BINT9 (0x00000200) +#define NS9750_BBUS_DMA_INT_BINT8 (0x00000100) +#define NS9750_BBUS_DMA_INT_BINT7 (0x00000080) +#define NS9750_BBUS_DMA_INT_BINT6 (0x00000040) +#define NS9750_BBUS_DMA_INT_BINT5 (0x00000020) +#define NS9750_BBUS_DMA_INT_BINT4 (0x00000010) +#define NS9750_BBUS_DMA_INT_BINT3 (0x00000008) +#define NS9750_BBUS_DMA_INT_BINT2 (0x00000004) +#define NS9750_BBUS_DMA_INT_BINT1 (0x00000002) +#define NS9750_BBUS_DMA_INT_BINT0 (0x00000001) + +#define NS9750_BBUS_USB_CFG_OUTEN (0x00000008) +#define NS9750_BBUS_USB_CFG_SPEED (0x00000004) +#define NS9750_BBUS_USB_CFG_CFG_MA (0x00000003) +#define NS9750_BBUS_USB_CFG_CFG_HOST_SOFT (0x00000003) +#define NS9750_BBUS_USB_CFG_CFG_DEVICE (0x00000002) +#define NS9750_BBUS_USB_CFG_CFG_HOST (0x00000001) +#define NS9750_BBUS_USB_CFG_CFG_DIS (0x00000000) + +#define NS9750_BBUS_ENDIAN_CFG_AHBM (0x00001000) +#define NS9750_BBUS_ENDIAN_CFG_I2C (0x00000080) +#define NS9750_BBUS_ENDIAN_CFG_IEEE1284 (0x00000040) +#define NS9750_BBUS_ENDIAN_CFG_SER4 (0x00000020) +#define NS9750_BBUS_ENDIAN_CFG_SER3 (0x00000010) +#define NS9750_BBUS_ENDIAN_CFG_SER2 (0x00000008) +#define NS9750_BBUS_ENDIAN_CFG_SER1 (0x00000004) +#define NS9750_BBUS_ENDIAN_CFG_USB (0x00000002) +#define NS9750_BBUS_ENDIAN_CFG_DMA (0x00000001) + +#endif /* FS_NS9750_BBUS_H */ diff --git a/include/ns9750_mem.h b/include/ns9750_mem.h new file mode 100644 index 0000000..666e412 --- /dev/null +++ b/include/ns9750_mem.h @@ -0,0 +1,172 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: ns9750_mem.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ + * @Author: Markus Pietrek + * @Descr: Definitions for Memory Control Module + * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 5 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ***********************************************************************/ + +#ifndef FS_NS9750_MEM_H +#define FS_NS9750_SYS_H + +#define NS9750_MEM_MODULE_BASE (0xA0700000) + +#define get_mem_reg_addr(c) \ + ((volatile unsigned int *)(NS9750_MEM_MODULE_BASE+(unsigned int) (c))) + +/* the register addresses */ + +#define NS9750_MEM_CTRL (0x0000) +#define NS9750_MEM_STATUS (0x0004) +#define NS9750_MEM_CFG (0x0008) +#define NS9750_MEM_DYN_CTRL (0x0020) +#define NS9750_MEM_DYN_REFRESH (0x0024) +#define NS9750_MEM_DYN_READ_CFG (0x0028) +#define NS9750_MEM_DYN_TRP (0x0030) +#define NS9750_MEM_DYN_TRAS (0x0034) +#define NS9750_MEM_DYN_TSREX (0x0038) +#define NS9750_MEM_DYN_TAPR (0x003C) +#define NS9750_MEM_DYN_TDAL (0x0040) +#define NS9750_MEM_DYN_TWR (0x0044) +#define NS9750_MEM_DYN_TRC (0x0048) +#define NS9750_MEM_DYN_TRFC (0x004C) +#define NS9750_MEM_DYN_TXSR (0x0050) +#define NS9750_MEM_DYN_TRRD (0x0054) +#define NS9750_MEM_DYN_TMRD (0x0058) +#define NS9750_MEM_STAT_EXT_WAIT (0x0080) +#define NS9750_MEM_DYN_CFG_BASE (0x0100) +#define NS9750_MEM_DYN_RAS_CAS_BASE (0x0104) +#define NS9750_MEM_STAT_CFG_BASE (0x0200) +#define NS9750_MEM_STAT_WAIT_WEN_BASE (0x0204) +#define NS9750_MEM_STAT_WAIT_OEN_BASE (0x0208) +#define NS9750_MEM_STAT_WAIT_RD_BASE (0x020C) +#define NS9750_MEM_STAT_WAIT_PAGE_BASE (0x0210) +#define NS9750_MEM_STAT_WAIR_WR_BASE (0x0214) +#define NS9750_MEM_STAT_WAIT_TURN_BASE (0x0218) + +/* the vectored register addresses */ + +#define NS9750_MEM_DYN_CFG(c) (NS9750_MEM_DYN_CFG_BASE + (c)*0x20) +#define NS9750_MEM_DYN_RAS_CAS(c) (NS9750_MEM_DYN_RAS_CAS_BASE + (c)*0x20) +#define NS9750_MEM_STAT_CFG(c) (NS9750_MEM_STAT_CFG_BASE + (c)*0x20) +#define NS9750_MEM_STAT_WAIT_WEN(c) (NS9750_MEM_STAT_WAIT_WEN_BASE+(c)*0x20) +#define NS9750_MEM_STAT_WAIT_OEN(c) (NS9750_MEM_STAT_WAIT_OEN_BASE+(c)*0x20) +#define NS9750_MEM_STAT_RD(c) (NS9750_MEM_STAT_WAIT_RD_BASE+(c)*0x20) +#define NS9750_MEM_STAT_PAGE(c) (NS9750_MEM_STAT_WAIT_PAGE_BASE+(c)*0x20) +#define NS9750_MEM_STAT_WR(c) (NS9750_MEM_STAT_WAIT_WR_BASE+(c)*0x20) +#define NS9750_MEM_STAT_TURN(c) (NS9750_MEM_STAT_WAIT_TURN_BASE+(c)*0x20) + +/* register bit fields */ + +#define NS9750_MEM_CTRL_L (0x00000004) +#define NS9750_MEM_CTRL_M (0x00000002) +#define NS9750_MEM_CTRL_E (0x00000001) + +#define NS9750_MEM_STAT_SA (0x00000004) +#define NS9750_MEM_STAT_S (0x00000002) +#define NS9750_MEM_STAT_B (0x00000001) + +#define NS9750_MEM_CFG_CLK (0x00000010) +#define NS9750_MEM_CFG_N (0x00000001) + +#define NS9750_MEM_DYN_CTRL_NRP (0x00004000) +#define NS9750_MEM_DYN_CTRL_DP (0x00002000) +#define NS9750_MEM_DYN_CTRL_I_MA (0x00000180) +#define NS9750_MEM_DYN_CTRL_I_NORMAL (0x00000000) +#define NS9750_MEM_DYN_CTRL_I_MODE (0x00000080) +#define NS9750_MEM_DYN_CTRL_I_PALL (0x00000100) +#define NS9750_MEM_DYN_CTRL_I_NOP (0x00000180) +#define NS9750_MEM_DYN_CTRL_SR (0x00000002) +#define NS9750_MEM_DYN_CTRL_CE (0x00000001) + + +#define NS9750_MEM_DYN_REFRESH_MA (0x000007FF) + +#define NS9750_MEM_DYN_READ_CFG_MA (0x00000003) +#define NS9750_MEM_DYN_READ_CFG_DELAY0 (0x00000001) +#define NS9750_MEM_DYN_READ_CFG_DELAY1 (0x00000002) +#define NS9750_MEM_DYN_READ_CFG_DELAY2 (0x00000003) + +#define NS9750_MEM_DYN_TRP_MA (0x0000000F) + +#define NS9750_MEM_DYN_TRAS_MA (0x0000000F) + +#define NS9750_MEM_DYN_TSREX_MA (0x0000000F) + +#define NS9750_MEM_DYN_TAPR_MA (0x0000000F) + +#define NS9750_MEM_DYN_TDAL_MA (0x0000000F) + +#define NS9750_MEM_DYN_TWR_MA (0x0000000F) + +#define NS9750_MEM_DYN_TRC_MA (0x0000001F) + +#define NS9750_MEM_DYN_TRFC_MA (0x0000001F) + +#define NS9750_MEM_DYN_TXSR_MA (0x0000001F) + +#define NS9750_MEM_DYN_TRRD_MA (0x0000000F) + +#define NS9750_MEM_DYN_TMRD_MA (0x0000000F) + +#define NS9750_MEM_STAT_EXTW_WAIT_MA (0x0000003F) + +#define NS9750_MEM_DYN_CFG_P (0x00100000) +#define NS9750_MEM_DYN_CFG_BDMC (0x00080000) +#define NS9750_MEM_DYN_CFG_AM (0x00004000) +#define NS9750_MEM_DYN_CFG_AM_MA (0x00001F80) +#define NS9750_MEM_DYN_CFG_MD (0x00000018) + +#define NS9750_MEM_DYN_RAS_CAS_CAS_MA (0x00000300) +#define NS9750_MEM_DYN_RAS_CAS_CAS_1 (0x00000100) +#define NS9750_MEM_DYN_RAS_CAS_CAS_2 (0x00000200) +#define NS9750_MEM_DYN_RAS_CAS_CAS_3 (0x00000300) +#define NS9750_MEM_DYN_RAS_CAS_RAS_MA (0x00000003) +#define NS9750_MEM_DYN_RAS_CAS_RAS_1 (0x00000001) +#define NS9750_MEM_DYN_RAS_CAS_RAS_2 (0x00000002) +#define NS9750_MEM_DYN_RAS_CAS_RAS_3 (0x00000003) + +#define NS9750_MEM_STAT_CFG_PSMC (0x00100000) +#define NS9750_MEM_STAT_CFG_BSMC (0x00080000) +#define NS9750_MEM_STAT_CFG_EW (0x00000100) +#define NS9750_MEM_STAT_CFG_PB (0x00000080) +#define NS9750_MEM_STAT_CFG_PC (0x00000040) +#define NS9750_MEM_STAT_CFG_PM (0x00000008) +#define NS9750_MEM_STAT_CFG_MW_MA (0x00000003) +#define NS9750_MEM_STAT_CFG_MW_8 (0x00000000) +#define NS9750_MEM_STAT_CFG_MW_16 (0x00000001) +#define NS9750_MEM_STAT_CFG_MW_32 (0x00000002) + +#define NS9750_MEM_STAT_WAIT_WEN_MA (0x0000000F) + +#define NS9750_MEM_STAT_WAIT_OEN_MA (0x0000000F) + +#define NS9750_MEM_STAT_WAIT_RD_MA (0x0000001F) + +#define NS9750_MEM_STAT_WAIT_PAGE_MA (0x0000001F) + +#define NS9750_MEM_STAT_WAIT_WR_MA (0x0000001F) + +#define NS9750_MEM_STAT_WAIT_TURN_MA (0x0000000F) + + +#endif /* FS_NS9750_MEM_H */ diff --git a/include/ns9750_ser.h b/include/ns9750_ser.h new file mode 100644 index 0000000..b5c297e --- /dev/null +++ b/include/ns9750_ser.h @@ -0,0 +1,202 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: ns9750_ser.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ + * @Author: Markus Pietrek + * @References: [1] NS9750 Hardware Reference, December 2003 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ***********************************************************************/ + +#ifndef FS_NS9750_SER_H +#define FS_NS9750_SER_H + +#define NS9750_SER_MODULE_BASE (0x90200000) + +#define get_ser_reg_addr(c) \ + ((volatile unsigned int *)(NS9750_SER_MODULE_BASE+(unsigned int) (c))) + +#define get_ser_reg_addr_channel(reg,chan) \ + get_ser_reg_addr((reg)+(((chan)<2)?0:0x00100000)+(((chan)&1)?0x40:0)) + +/* the register addresses */ + +#define NS9750_SER_CTRL_A (0x00) +#define NS9750_SER_CTRL_B (0x04) +#define NS9750_SER_STAT_A (0x08) +#define NS9750_SER_BITRATE (0x0C) +#define NS9750_SER_FIFO (0x10) +#define NS9750_SER_RX_BUF_TIMER (0x14) +#define NS9750_SER_RX_CHAR_TIMER (0x18) +#define NS9750_SER_RX_MATCH (0x1C) +#define NS9750_SER_RX_MATCH_MASK (0x20) +#define NS9750_SER_FLOW_CTRL (0x34) +#define NS9750_SER_FLOW_CTRL_FORCE (0x38) + +/* register bit fields */ + +/* control A register */ + +#define NS9750_SER_CTRL_A_CE (0x80000000) +#define NS9750_SER_CTRL_A_BRK (0x40000000) +#define NS9750_SER_CTRL_A_STICKP (0x20000000) +#define NS9750_SER_CTRL_A_EPS (0x10000000) +#define NS9750_SER_CTRL_A_PE (0x08000000) +#define NS9750_SER_CTRL_A_STOP (0x04000000) +#define NS9750_SER_CTRL_A_WLS_MA (0x03000000) +#define NS9750_SER_CTRL_A_WLS_5 (0x00000000) +#define NS9750_SER_CTRL_A_WLS_6 (0x01000000) +#define NS9750_SER_CTRL_A_WLS_7 (0x02000000) +#define NS9750_SER_CTRL_A_WLS_8 (0x03000000) +#define NS9750_SER_CTRL_A_CTSTX (0x00800000) +#define NS9750_SER_CTRL_A_RTSRX (0x00400000) +#define NS9750_SER_CTRL_A_RL (0x00200000) +#define NS9750_SER_CTRL_A_LL (0x00100000) +#define NS9750_SER_CTRL_A_RES (0x000CF000) +#define NS9750_SER_CTRL_A_DTR (0x00020000) +#define NS9750_SER_CTRL_A_RTS (0x00010000) +#define NS9750_SER_CTRL_A_RIE_MA (0x00000E00) +#define NS9750_SER_CTRL_A_ERXDMA (0x00000100) +#define NS9750_SER_CTRL_A_RIC_MA (0x000000E0) +#define NS9750_SER_CTRL_A_TIC_MA (0x0000001E) +#define NS9750_SER_CTRL_A_ETXDMA (0x00000001) + +/* control B register */ + +#define NS9750_SER_CTRL_B_RDM1 (0x80000000) +#define NS9750_SER_CTRL_B_RDM2 (0x40000000) +#define NS9750_SER_CTRL_B_RDM3 (0x20000000) +#define NS9750_SER_CTRL_B_RDM4 (0x10000000) +#define NS9750_SER_CTRL_B_RBGT (0x08000000) +#define NS9750_SER_CTRL_B_RCGT (0x04000000) +#define NS9750_SER_CTRL_B_MODE_MA (0x00300000) +#define NS9750_SER_CTRL_B_MODE_UART (0x00000000) +#define NS9750_SER_CTRL_B_MODE_HDLC (0x00100000) +#define NS9750_SER_CTRL_B_MODE_SPI_M (0x00200000) +#define NS9750_SER_CTRL_B_MODE_SPI_S (0x00300000) +#define NS9750_SER_CTRL_B_BITORDR (0x00080000) +#define NS9750_SER_CTRL_B_RES (0x0007703F) +#define NS9750_SER_CTRL_B_RTSTX (0x00008000) +#define NS9750_SER_CTRL_B_ENDEC_MA (0x00000FC0) + +/* status A register */ + +#define NS9750_SER_STAT_A_MATCH1 (0x80000000) +#define NS9750_SER_STAT_A_MATCH2 (0x40000000) +#define NS9750_SER_STAT_A_MATCH3 (0x20000000) +#define NS9750_SER_STAT_A_MATCH4 (0x10000000) +#define NS9750_SER_STAT_A_BGAP (0x08000000) +#define NS9750_SER_STAT_A_CGAP (0x04000000) +#define NS9750_SER_STAT_A_RXFDB_MA (0x00300000) +#define NS9750_SER_STAT_A_RXFDB_FULL (0x00000000) +#define NS9750_SER_STAT_A_RXFDB_1 (0x00100000) +#define NS9750_SER_STAT_A_RXFDB_2 (0x00200000) +#define NS9750_SER_STAT_A_RXFDB_3 (0x00300000) +#define NS9750_SER_STAT_A_DCD (0x00080000) +#define NS9750_SER_STAT_A_RI (0x00040000) +#define NS9750_SER_STAT_A_DSR (0x00020000) +#define NS9750_SER_STAT_A_CTS (0x00010000) +#define NS9750_SER_STAT_A_RBRK (0x00008000) +#define NS9750_SER_STAT_A_RFE (0x00004000) +#define NS9750_SER_STAT_A_RPE (0x00002000) +#define NS9750_SER_STAT_A_ROVER (0x00001000) +#define NS9750_SER_STAT_A_RRDY (0x00000800) +#define NS9750_SER_STAT_A_RHALF (0x00000400) +#define NS9750_SER_STAT_A_RBC (0x00000200) +#define NS9750_SER_STAT_A_RFULL (0x00000100) +#define NS9750_SER_STAT_A_DCDI (0x00000080) +#define NS9750_SER_STAT_A_RII (0x00000040) +#define NS9750_SER_STAT_A_DSRI (0x00000020) +#define NS9750_SER_STAT_A_CTSI (0x00000010) +#define NS9750_SER_STAT_A_TRDY (0x00000008) +#define NS9750_SER_STAT_A_THALF (0x00000004) +#define NS9750_SER_STAT_A_TBC (0x00000002) +#define NS9750_SER_STAT_A_TEMPTY (0x00000001) + +#define NS9750_SER_STAT_A_RX_COND_ERR ( NS9750_SER_STAT_A_RFE | \ + NS9750_SER_STAT_A_ROVER | \ + NS9750_SER_STAT_A_RPE ) +#define NS9750_SER_STAT_A_RX_COND_ALL ( NS9750_SER_STAT_A_RX_COND_ERR | \ + NS9750_SER_STAT_A_RBRK | \ + NS9750_SER_STAT_A_RRDY | \ + NS9750_SER_STAT_A_RHALF | \ + NS9750_SER_STAT_A_RBC | \ + NS9750_SER_STAT_A_DCDI | \ + NS9750_SER_STAT_A_RII | \ + NS9750_SER_STAT_A_DSRI | \ + NS9750_SER_STAT_A_CTSI ) +#define NS9750_SER_STAT_A_TX_COND_ALL ( NS9750_SER_STAT_A_TRDY | \ + NS9750_SER_STAT_A_THALF | \ + NS9750_SER_STAT_A_TBC | \ + NS9750_SER_STAT_A_TEMPTY ) +/* bit rate register */ + +#define NS9750_SER_BITRATE_EBIT (0x80000000) +#define NS9750_SER_BITRATE_TMODE (0x40000000) +#define NS9750_SER_BITRATE_RXSRC (0x20000000) +#define NS9750_SER_BITRATE_TXSRC (0x10000000) +#define NS9750_SER_BITRATE_RXEXT (0x08000000) +#define NS9750_SER_BITRATE_TXEXT (0x04000000) +#define NS9750_SER_BITRATE_CLKMUX_MA (0x03000000) +#define NS9750_SER_BITRATE_CLKMUX_XTAL (0x00000000) +#define NS9750_SER_BITRATE_CLKMUX_BCLK (0x01000000) +#define NS9750_SER_BITRATE_CLKMUX_OUT1 (0x02000000) +#define NS9750_SER_BITRATE_CLKMUX_OUT2 (0x03000000) +#define NS9750_SER_BITRATE_TXCINV (0x00800000) +#define NS9750_SER_BITRATE_RXCINV (0x00400000) +#define NS9750_SER_BITRATE_TCDR_MA (0x00180000) +#define NS9750_SER_BITRATE_TCDR_1 (0x00000000) +#define NS9750_SER_BITRATE_TCDR_8 (0x00080000) +#define NS9750_SER_BITRATE_TCDR_16 (0x00100000) +#define NS9750_SER_BITRATE_TCDR_32 (0x00180000) +#define NS9750_SER_BITRATE_RCDR_MA (0x00070000) +#define NS9750_SER_BITRATE_RCDR_1 (0x00000000) +#define NS9750_SER_BITRATE_RCDR_8 (0x00020000) +#define NS9750_SER_BITRATE_RCDR_16 (0x00040000) +#define NS9750_SER_BITRATE_RCDR_32 (0x00060000) +#define NS9750_SER_BITRATE_TICS (0x00010000) +#define NS9750_SER_BITRATE_RICS (0x00008000) +#define NS9750_SER_BITRATE_N_MA (0x00007FFF) + +/* receive buffer gap timer */ + +#define NS9750_SER_RX_BUF_TIMER_TRUN (0x80000000) /* UART and SPI */ +#define NS9750_SER_RX_BUF_TIMER_BT_MA (0x0000FFFF) /* UART and SPI */ +#define NS9750_SER_RX_BUF_TIMER_MAXLEN_MA (0x0000FFFF) /* HDLC only */ + +/* receive character gap timer */ + +#define NS9750_SER_RX_CHAR_TIMER_TRUN (0x80000000) +#define NS9750_SER_RX_CHAR_TIMER_CT_MA (0x000FFFFF) + +/* receive match */ + +#define NS9750_SER_RX_MATCH_RDMB1_MA (0xFF000000) +#define NS9750_SER_RX_MATCH_RDMB2_MA (0x00FF0000) +#define NS9750_SER_RX_MATCH_RDMB3_MA (0x0000FF00) +#define NS9750_SER_RX_MATCH_RDMB4_MA (0x000000FF) + +/* receive match mask */ + +#define NS9750_SER_RX_MATCH_MASK_RDMB1_MA (0xFF000000) +#define NS9750_SER_RX_MATCH_MASK_RDMB2_MA (0x00FF0000) +#define NS9750_SER_RX_MATCH_MASK_RDMB3_MA (0x0000FF00) +#define NS9750_SER_RX_MATCH_MASK_RDMB4_MA (0x000000FF) + +#endif /* FS_NS9750_SER_H */ diff --git a/include/ns9750_sys.h b/include/ns9750_sys.h new file mode 100644 index 0000000..f1dc2b2 --- /dev/null +++ b/include/ns9750_sys.h @@ -0,0 +1,215 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: ns9750_sys.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ + * @Author: Markus Pietrek + * @Descr: Definitions for SYS Control Module + * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 4 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ***********************************************************************/ + +#ifndef FS_NS9750_SYS_H +#define FS_NS9750_SYS_H + +#define NS9750_SYS_MODULE_BASE (0xA0900000) + +#define get_sys_reg_addr(c) \ + ((volatile unsigned int *)(NS9750_SYS_MODULE_BASE+(unsigned int) (c))) + +/* the register addresses */ + +#define NS9750_SYS_AHB_GEN (0x0000) +#define NS9750_SYS_BRC_BASE (0x0004) +#define NS9750_SYS_AHB_TIMEOUT (0x0014) +#define NS9750_SYS_AHB_ERROR1 (0x0018) +#define NS9750_SYS_AHB_ERROR2 (0x001C) +#define NS9750_SYS_AHB_MON (0x0020) +#define NS9750_SYS_TIMER_COUNT_BASE (0x0044) +#define NS9750_SYS_TIMER_READ_BASE (0x0084) +#define NS9750_SYS_INT_VEC_ADR_BASE (0x00C4) +#define NS9750_SYS_INT_CFG_BASE (0x0144) +#define NS9750_SYS_ISRADDR (0x0164) +#define NS9750_SYS_INT_STAT_ACTIVE (0x0168) +#define NS9750_SYS_INT_STAT_RAW (0x016C) +#define NS9750_SYS_TIMER_INT_STAT (0x0170) +#define NS9750_SYS_SW_WDOG_CFG (0x0174) +#define NS9750_SYS_SW_WDOG_TIMER (0x0178) +#define NS9750_SYS_CLOCK (0x017C) +#define NS9750_SYS_RESET (0x0180) +#define NS9750_SYS_MISC (0x0184) +#define NS9750_SYS_PLL (0x0188) +#define NS9750_SYS_ACT_INT_STAT (0x018C) +#define NS9750_SYS_TIMER_CTRL_BASE (0x0190) +#define NS9750_SYS_CS_DYN_BASE_BASE (0x01D0) +#define NS9750_SYS_CS_DYN_MASK_BASE (0x01D4) +#define NS9750_SYS_CS_STATIC_BASE_BASE (0x01F0) +#define NS9750_SYS_CS_STATIC_MASK_BASE (0x01F4) +#define NS9750_SYS_GEN_ID (0x0210) +#define NS9750_SYS_EXT_INT_CTRL_BASE (0x0214) + +/* the vectored register addresses */ + +#define NS9750_SYS_TIMER_COUNT(c) (NS9750_SYS_TIMER_COUNT_BASE + (c)) +#define NS9750_SYS_TIMER_READ(c) (NS9750_SYS_TIMER_READ_BASE + (c)) +#define NS9750_SYS_INT_VEC_ADR(c) (NS9750_SYS_INT_VEC_ADR_BASE + (c)) +#define NS9750_SYS_TIMER_CTRL(c) (NS9750_SYS_TIMER_CTRL_BASE + (c)) +/* CS_DYN start with 4 */ +#define NS9750_SYS_CS_DYN_BASE(c) (NS9750_SYS_CS_DYN_BASE_BASE + ((c)-4)*2) +#define NS9750_SYS_CS_DYN_MASK(c) (NS9750_SYS_CS_DYN_MASK_BASE + ((c)-4)*2) +/* CS_STATIC start with 0 */ +#define NS9750_SYS_CS_STATIC_BASE(c) (NS9750_SYS_CS_STATIC_BASE_BASE + (c)*2) +#define NS9750_SYS_CS_STATIC_MASK(c) (NS9750_SYS_CS_STATIC_MASK_BASE + (c)*2) +#define NS9750_SYS_EXT_INT_CTRL(c) (NS9750_SYS_EXT_INT_CTRL + (c)) + +/* register bit fields */ + +#define NS9750_SYS_AHB_GEN_EXMAM (0x00000001) + +/* need to be n*8bit to BRC channel */ +#define NS9750_SYS_BRC_CEB (0x00000080) +#define NS9750_SYS_BRC_BRF_MA (0x00000030) +#define NS9750_SYS_BRC_BRF_100 (0x00000000) +#define NS9750_SYS_BRC_BRF_75 (0x00000010) +#define NS9750_SYS_BRC_BRF_50 (0x00000020) +#define NS9750_SYS_BRC_BRF_25 (0x00000030) + +#define NS9750_SYS_AHB_TIMEOUT_BAT_MA (0xFFFF0000) +#define NS9750_SYS_AHB_TIMEOUT_BMT_MA (0x0000FFFF) + +#define NS9750_SYS_AHB_ERROR2_ABL (0x00040000) +#define NS9750_SYS_AHB_ERROR2_AER (0x00020000) +#define NS9750_SYS_AHB_ERROR2_ABM (0x00010000) +#define NS9750_SYS_AHB_ERROR2_ABA (0x00008000) +#define NS9750_SYS_AHB_ERROR2_HWRT (0x00004000) +#define NS9750_SYS_AHB_ERROR2_HMID_MA (0x00003C00) +#define NS9750_SYS_AHB_ERROR2_HTPC_MA (0x000003C0) +#define NS9750_SYS_AHB_ERROR2_HSZ_MA (0x00000038) +#define NS9750_SYS_AHB_ERROR2_RR_MA (0x00000007) + +#define NS9750_SYS_AHB_MON_EIC (0x00800000) +#define NS9750_SYS_AHB_MON_MBII (0x00400000) +#define NS9750_SYS_AHB_MON_MBL_MA (0x003FFFC0) +#define NS9750_SYS_AHB_MON_MBLDC (0x00000020) +#define NS9750_SYS_AHB_MON_SERDC (0x00000010) +#define NS9750_SYS_AHB_MON_BMTC_MA (0x0000000C) +#define NS9750_SYS_AHB_MON_BMTC_RECORD (0x00000000) +#define NS9750_SYS_AHB_MON_BMTC_GEN_IRQ (0x00000004) +#define NS9750_SYS_AHB_MON_BMTC_GEN_RES (0x00000008) +#define NS9750_SYS_AHB_MON_BATC_MA (0x00000003) +#define NS9750_SYS_AHB_MON_BATC_RECORD (0x00000000) +#define NS9750_SYS_AHB_MON_BATC_GEN_IRQ (0x00000001) +#define NS9750_SYS_AHB_MON_BATC_GEN_RES (0x00000002) + +/* need to be n*8bit to Int Level */ + +#define NS9750_SYS_INT_CFG_IE (0x00000080) +#define NS9750_SYS_INT_CFG_IT (0x00000020) +#define NS9750_SYS_INT_CFG_IAD_MA (0x0000001F) + +#define NS9750_SYS_TIMER_INT_STAT_MA (0x0000FFFF) + +#define NS9750_SYS_SW_WDOG_CFG_SWWE (0x00000080) +#define NS9750_SYS_SW_WDOG_CFG_SWWI (0x00000020) +#define NS9750_SYS_SW_WDOG_CFG_SWWIC (0x00000010) +#define NS9750_SYS_SW_WDOG_CFG_SWTCS_MA (0x00000007) +#define NS9750_SYS_SW_WDOG_CFG_SWTCS_2 (0x00000000) +#define NS9750_SYS_SW_WDOG_CFG_SWTCS_4 (0x00000001) +#define NS9750_SYS_SW_WDOG_CFG_SWTCS_8 (0x00000002) +#define NS9750_SYS_SW_WDOG_CFG_SWTCS_16 (0x00000003) +#define NS9750_SYS_SW_WDOG_CFG_SWTCS_32 (0x00000004) +#define NS9750_SYS_SW_WDOG_CFG_SWTCS_64 (0x00000005) + +#define NS9750_SYS_CLOCK_LPCS_MA (0x00000380) +#define NS9750_SYS_CLOCK_LPCS_1 (0x00000000) +#define NS9750_SYS_CLOCK_LPCS_2 (0x00000080) +#define NS9750_SYS_CLOCK_LPCS_4 (0x00000100) +#define NS9750_SYS_CLOCK_LPCS_8 (0x00000180) +#define NS9750_SYS_CLOCK_LPCS_EXT (0x00000200) +#define NS9750_SYS_CLOCK_BBC (0x00000040) +#define NS9750_SYS_CLOCK_LCC (0x00000020) +#define NS9750_SYS_CLOCK_MCC (0x00000010) +#define NS9750_SYS_CLOCK_PARBC (0x00000008) +#define NS9750_SYS_CLOCK_PC (0x00000004) +#define NS9750_SYS_CLOCK_MACC (0x00000001) + +#define NS9750_SYS_RESET_SR (0x80000000) +#define NS9750_SYS_RESET_I2CW (0x00100000) +#define NS9750_SYS_RESET_CSE (0x00080000) +#define NS9750_SYS_RESET_SMWE (0x00040000) +#define NS9750_SYS_RESET_EWE (0x00020000) +#define NS9750_SYS_RESET_PI3WE (0x00010000) +#define NS9750_SYS_RESET_BBT (0x00000040) +#define NS9750_SYS_RESET_LCDC (0x00000020) +#define NS9750_SYS_RESET_MEMC (0x00000010) +#define NS9750_SYS_RESET_PCIAR (0x00000008) +#define NS9750_SYS_RESET_PCIM (0x00000004) +#define NS9750_SYS_RESET_MACM (0x00000001) + +#define NS9750_SYS_MISC_REV_MA (0xFF000000) +#define NS9750_SYS_MISC_PCIA (0x00002000) +#define NS9750_SYS_MISC_VDIS (0x00001000) +#define NS9750_SYS_MISC_BMM (0x00000800) +#define NS9750_SYS_MISC_CS1DB (0x00000400) +#define NS9750_SYS_MISC_CS1DW_MA (0x00000300) +#define NS9750_SYS_MISC_MCCM (0x00000080) +#define NS9750_SYS_MISC_PMSS (0x00000040) +#define NS9750_SYS_MISC_CS1P (0x00000020) +#define NS9750_SYS_MISC_ENDM (0x00000008) +#define NS9750_SYS_MISC_MBAR (0x00000004) +#define NS9750_SYS_MISC_IRAM0 (0x00000001) + +#define NS9750_SYS_PLL_PLLBS (0x02000000) +#define NS9750_SYS_PLL_PLLFS_MA (0x01800000) +#define NS9750_SYS_PLL_PLLIS_MA (0x00600000) +#define NS9750_SYS_PLL_PLLND_MA (0x001F0000) +#define NS9750_SYS_PLL_PLLSW (0x00008000) +#define NS9750_SYS_PLL_PLLBSSW (0x00000200) +#define NS9750_SYS_PLL_FSEL_MA (0x00000180) +#define NS9750_SYS_PLL_CPCC_MA (0x00000060) +#define NS9750_SYS_PLL_NDSW_MA (0x0000001F) + +#define NS9750_SYS_ACT_INT_STAT_MA (0x0000FFFF) + +#define NS9750_SYS_TIMER_CTRL_TEN (0x00008000) +#define NS9750_SYS_TIMER_CTRL_INTC (0x00000200) +#define NS9750_SYS_TIMER_CTRL_TLCS_MA (0x000001C0) +#define NS9750_SYS_TIMER_CTRL_TLCS_1 (0x00000000) +#define NS9750_SYS_TIMER_CTRL_TLCS_2 (0x00000040) +#define NS9750_SYS_TIMER_CTRL_TLCS_4 (0x00000080) +#define NS9750_SYS_TIMER_CTRL_TLCS_8 (0x000000C0) +#define NS9750_SYS_TIMER_CTRL_TLCS_16 (0x00000100) +#define NS9750_SYS_TIMER_CTRL_TLCS_32 (0x00000140) +#define NS9750_SYS_TIMER_CTRL_TLCS_64 (0x00000180) +#define NS9750_SYS_TIMER_CTRL_TLCS_EXT (0x000001C0) +#define NS9750_SYS_TIMER_CTRL_TM_MA (0x00000030) +#define NS9750_SYS_TIMER_CTRL_TM_INT (0x00000000) +#define NS9750_SYS_TIMER_CTRL_TM_LOW (0x00000010) +#define NS9750_SYS_TIMER_CTRL_TM_HIGH (0x00000020) +#define NS9750_SYS_TIMER_CTRL_INTS (0x00000008) +#define NS9750_SYS_TIMER_CTRL_UDS (0x00000004) +#define NS9750_SYS_TIMER_CTRL_TSZ (0x00000002) +#define NS9750_SYS_TIMER_CTRL_REN (0x00000001) + +#define NS9750_SYS_EXT_INT_CTRL_STS (0x00000008) +#define NS9750_SYS_EXT_INT_CTRL_CLR (0x00000004) +#define NS9750_SYS_EXT_INT_CTRL_PLTY (0x00000002) +#define NS9750_SYS_EXT_INT_CTRL_LVEDG (0x00000001) + +#endif /* FS_NS9750_SYS_H */ -- 1.8.1.2

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[U-Boot] [PATCH v2 02/04] spi, spi_mxc: do not hang in spi_xchg_single
by Heiko Schocher 08 Jun '14

08 Jun '14

if status register do never set MXC_CSPICTRL_TC, spi_xchg_single endless loops. Add a timeout here to prevent endless hang. Signed-off-by: Heiko Schocher <hs(a)denx.de> Cc: Dirk Behme <dirk.behme(a)gmail.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com> --- - changes for v2: - use timer api to poll till TC bit is set as Jagan Teki suggested and make this timeout configurable through CONFIG_SYS_SPI_MXC_WAIT --- README | 4 ++++ drivers/spi/mxc_spi.c | 18 ++++++++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/README b/README index a280435..ff8928b 100644 --- a/README +++ b/README @@ -2564,6 +2564,10 @@ CBFS (Coreboot Filesystem) support Enables the driver for the SPI controllers on i.MX and MXC SoCs. Currently i.MX31/35/51 are supported. + CONFIG_SYS_SPI_MXC_WAIT + Timeout for waiting until spi transfer completed. + default: (CONFIG_SYS_HZ/100) /* 10 ms */ + - FPGA Support: CONFIG_FPGA Enables FPGA subsystem. diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index f3f029d..4732850 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -30,6 +30,10 @@ static unsigned long spi_bases[] = { #define reg_read readl #define reg_write(a, v) writel(v, a) +#if !defined(CONFIG_SYS_SPI_MXC_WAIT) +#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ +#endif + struct mxc_spi_slave { struct spi_slave slave; unsigned long base; @@ -212,6 +216,8 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, int nbytes = DIV_ROUND_UP(bitlen, 8); u32 data, cnt, i; struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; + u32 ts; + int status; debug("%s: bitlen %d dout 0x%x din 0x%x\n", __func__, bitlen, (u32)dout, (u32)din); @@ -272,9 +278,17 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); + ts = get_timer(0); + status = reg_read(&regs->stat); /* Wait until the TC (Transfer completed) bit is set */ - while ((reg_read(&regs->stat) & MXC_CSPICTRL_TC) == 0) - ; + while ((status & MXC_CSPICTRL_TC) == 0) { + if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) { + printf("spi_xchg_single: Timeout!\n"); + return -1; + } + udelay(10); + status = reg_read(&regs->stat); + } /* Transfer completed, clear any pending request */ reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); -- 1.8.3.1

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[U-Boot] Please pull u-boot-ti/master
by Tom Rini 08 Jun '14

08 Jun '14

Hello, The following changes since commit cc49da249cf2f380d2fed5571fad65ce6494fc95: Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' (2014-06-02 08:43:48 +0200) are available in the git repository at: git://git.denx.de/u-boot-ti.git master for you to fetch changes up to 83bad1026b9e3a4f6b7783cc1cbb434c1bbd3fa2: arm:am43xx: Add TPS65218 support to scale voltages up (2014-06-06 17:46:16 -0400) ---------------------------------------------------------------- Brian Norris (2): mtd: nand: don't use read_buf for 8-bit ONFI transfers mtd: nand: force NAND_CMD_READID onto 8-bit bus David Mosberger (1): mtd: nand: fix GET/SET_FEATURES address on 16-bit devices Hannes Petermaier (6): arch-am33xx: Add defines for timer0-7 board/BuR/common: introduce usage of CONFIG_SYS_GENERIC_BOARD board/BuR/tseries: Add support for using 8-bit on eMMC board/BuR/tseries: only run gpmc_init(...) in NAND-build board/BuR/common: Add CONFIG_CMD_I2C board/BuR/tseries: cosmetic changes Jeroen Hofstee (1): tam3517: fix NAND detection Lokesh Vutla (2): ARM: AM43xx: Fix mmcboot command in EXTRA_ENV_SETTINGS ARM: AM43xx: Fix UART clocks enabling Murali Karicheri (1): keystone: init: enable UART1 to be able use it from kernel Sourav Poddar (2): am43xx_evm: Add qspiboot target ti: qspi: populate slave device to set flash quad bit. Tom Rini (6): arm:am33xx: Make dram_init call sdram_init() in some contexts arm:am33xx: Rework s_init and add board_early_init_f am43xx: Only read the MPU frequency bits of CTRL_DEV_ATTR arm:am33xx: Add a scale_vcores() hook power: Add support for the TPS65218 PMIC arm:am43xx: Add TPS65218 support to scale voltages up WingMan Kwok (1): keystone: k2hk: enable support of nand ecclayout command pekon gupta (12): mtd: nand: omap_elm: remove #include omap_gpmc.h mtd: nand: omap_elm: use bch_type instead of nibble count to differentiate between BCH4/BCH8/BCH16 mtd: nand: omap_elm: use macros for register definitions mtd: nand: omap_gpmc: remove unused members of 'struct nand_bch_priv' mtd: nand: omap_gpmc: rename struct nand_bch_priv to struct omap_nand_info mtd: nand: omap_gpmc: minor cleanup of omap_correct_data_bch mtd: nand: omap: fix error-codes returned from omap-elm driver mtd: nand: omap: add CONFIG_SYS_NAND_BUSWIDTH_16BIT to indicate NAND device bus-width omap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT mtd: nand: omap_gpmc: use macro for register definitions mtd: nand: omap: add support for BCH16_ECC - NAND driver updates am335x: update README for BCH16 arch/arm/cpu/armv7/am33xx/board.c | 20 +- arch/arm/cpu/armv7/am33xx/clock.c | 11 ++ arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 9 + arch/arm/cpu/armv7/am33xx/emif4.c | 4 + arch/arm/cpu/armv7/keystone/init.c | 9 + arch/arm/cpu/armv7/omap3/mem.c | 12 -- arch/arm/include/asm/arch-am33xx/clock.h | 1 + arch/arm/include/asm/arch-am33xx/cpu.h | 35 +++- arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 2 - arch/arm/include/asm/arch-keystone/hardware.h | 3 + arch/arm/include/asm/arch-omap3/mem.h | 8 - board/BuR/tseries/board.c | 2 + board/BuR/tseries/mux.c | 9 +- board/compulab/cm_t35/cm_t35.c | 12 +- board/ti/am43xx/Makefile | 2 +- board/ti/am43xx/board.c | 55 +++++- boards.cfg | 1 + doc/README.nand | 60 ++++++ drivers/mtd/nand/am335x_spl_bch.c | 2 +- drivers/mtd/nand/atmel_nand.c | 2 +- drivers/mtd/nand/nand_base.c | 11 +- drivers/mtd/nand/nand_spl_simple.c | 2 +- drivers/mtd/nand/omap_elm.c | 28 ++- drivers/mtd/nand/omap_gpmc.c | 193 +++++++++++++------- drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps65218.c | 97 ++++++++++ drivers/spi/ti_qspi.c | 1 + include/configs/am3517_crane.h | 1 + include/configs/am43xx_evm.h | 45 ++++- include/configs/bur_am335x_common.h | 4 +- include/configs/cm_t335.h | 1 - include/configs/cm_t35.h | 1 - include/configs/devkit8000.h | 1 + include/configs/dig297.h | 1 + include/configs/k2hk_evm.h | 4 +- include/configs/omap3_beagle.h | 1 + include/configs/omap3_evm_common.h | 2 +- include/configs/omap3_igep00x0.h | 1 + include/configs/omap3_logic.h | 1 + include/configs/omap3_overo.h | 1 + include/configs/omap3_zoom1.h | 1 + include/configs/pengwyn.h | 1 - include/configs/tam3517-common.h | 2 + include/configs/tao3530.h | 2 +- include/configs/ti_am335x_common.h | 9 + include/configs/ti_armv7_common.h | 3 +- include/configs/tseries.h | 1 - include/linux/mtd/nand.h | 19 ++ include/linux/mtd/omap_elm.h | 11 +- include/linux/mtd/omap_gpmc.h | 11 +- include/power/tps65218.h | 63 +++++++ 51 files changed, 624 insertions(+), 155 deletions(-) create mode 100644 drivers/power/pmic/pmic_tps65218.c create mode 100644 include/power/tps65218.h -- Tom

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[U-Boot] pull request for u-boot-tegra/master into ARM/master
by Tom Warren 08 Jun '14

08 Jun '14

Albert, Please pull u-boot-tegra/master into ARM/master. Thanks! ./MAKEALL -s tegra AOK, checkpatch.pl is OK, and ./MAKEALL -a arm only shows failures that were already present in ARM/master. The following changes since commit cc49da249cf2f380d2fed5571fad65ce6494fc95: Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' (2014-06-02 08:43:48 +0200) are available in the git repository at: git://git.denx.de/u-boot-tegra.git master for you to fetch changes up to e6607cffef965011ef0ddc0fbe6f4b7c0d53aeec: ARM: tegra: enable USB device mode and UMS on some boards (2014-06-05 11:25:54 -0700) ---------------------------------------------------------------- Stephen Warren (1): ARM: tegra: enable USB device mode and UMS on some boards arch/arm/dts/tegra124-jetson-tk1.dts | 9 ++++++++- arch/arm/dts/tegra124-venice2.dts | 9 ++++++++- arch/arm/dts/tegra30-beaver.dts | 9 ++++++++- include/configs/beaver.h | 2 ++ include/configs/jetson-tk1.h | 2 ++ include/configs/tegra-common-ums.h | 26 ++++++++++++++++++++++++++ include/configs/venice2.h | 2 ++ 7 files changed, 56 insertions(+), 3 deletions(-) create mode 100644 include/configs/tegra-common-ums.h

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[U-Boot] [RFC PATCH] IMX: Rename IMX image "SPL" to something else for Cygwin
by Masahiro Yamada 07 Jun '14

07 Jun '14

I am not sure how much effort we should make for building U-Boot on Cygwin. Anyway, other than host programs, I notice file name problem. Unlike Unix or Linux, on Windows upper/lower cases for file names are not distinguished. On Cygwin, for example, we cannot do this: $ mkdir abc $ mkdir ABC mkdir: cannot create directory `ABC': File exists It causes some problems in U-Boot too. For example, $ make mrproper CLEAN SPL rm: cannot remove `SPL': Is a directory Makefile:1278: recipe for target 'clobber' failed make: *** [clobber] Error 1 $ make qong_config Configuring for qong board... $ make clean CLEAN arch/arm/imx-common rm: cannot remove `arch/arm/imx-common/../../../SPL': Is a directory scripts/Makefile.clean:79: recipe for target '__clean' failed make[1]: *** [__clean] Error 1 Makefile:1256: recipe for target '_clean_arch/arm/imx-common' failed make: *** [_clean_arch/arm/imx-common] Error 2 I notice at least one file name conflict at the top directory. SPL - image for IMX spl - directory where SPL is built This commit renames the former to a temporary name. I guess there is few developers testing U-Boot on Cygwin. If Cygwin support is mandatory, please consider to rename IMX image. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- .gitignore | 2 +- Makefile | 6 +++--- arch/arm/config.mk | 2 +- arch/arm/imx-common/Makefile | 8 ++++---- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/.gitignore b/.gitignore index 4e4fd00..b68e4f9 100644 --- a/.gitignore +++ b/.gitignore @@ -31,7 +31,7 @@ # Top-level generic files # /MLO* -/SPL +/SPL__PLEASE_RENAME /System.map /u-boot* diff --git a/Makefile b/Makefile index aebee55..a6fe5d8 100644 --- a/Makefile +++ b/Makefile @@ -866,10 +866,10 @@ OBJCOPYFLAGS_u-boot-with-tpl.bin = -I binary -O binary \ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE $(call if_changed,pad_cat) -SPL: spl/u-boot-spl.bin FORCE +SPL__PLEASE_RENAME: spl/u-boot-spl.bin FORCE $(Q)$(MAKE) $(build)=arch/arm/imx-common $@ -u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE +u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL__PLEASE_RENAME u-boot.bin FORCE $(Q)$(MAKE) $(build)=arch/arm/imx-common $@ MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE) @@ -1221,7 +1221,7 @@ CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h \ CLOBBER_DIRS += $(patsubst %,spl/%, $(filter-out Makefile, \ $(shell ls -1 spl 2>/dev/null))) \ tpl -CLOBBER_FILES += u-boot* MLO* SPL System.map +CLOBBER_FILES += u-boot* MLO* SPL__PLEASE_RENAME System.map # Directories & files removed with 'make mrproper' MRPROPER_DIRS += include/config include/generated \ diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 66ecc2e..e5bf171 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -119,7 +119,7 @@ endif ifneq ($(CONFIG_IMX_CONFIG),) ifdef CONFIG_SPL ifndef CONFIG_SPL_BUILD -ALL-y += SPL +ALL-y += SPL__PLEASE_RENAME endif else ifeq ($(CONFIG_OF_SEPARATE),y) diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 016fb98..8bf4d20 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -50,7 +50,7 @@ endif MKIMAGEFLAGS_SPL = -n $(filter-out $< $(PHONY),$^) -T imximage \ -e $(CONFIG_SPL_TEXT_BASE) -SPL: spl/u-boot-spl.bin $(IMX_CONFIG) FORCE +SPL__PLEASE_RENAME: spl/u-boot-spl.bin $(IMX_CONFIG) FORCE $(call if_changed,mkimage) MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \ @@ -61,7 +61,7 @@ u-boot.uim: u-boot.bin FORCE OBJCOPYFLAGS += -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) -u-boot-with-spl.imx: SPL u-boot.uim FORCE +u-boot-with-spl.imx: SPL__PLEASE_RENAME u-boot.uim FORCE $(call if_changed,pad_cat) u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx u-boot.uim FORCE @@ -71,7 +71,7 @@ quiet_cmd_u-boot-nand-spl_imx = GEN $@ cmd_u-boot-nand-spl_imx = (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \ dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@ -spl/u-boot-nand-spl.imx: SPL FORCE +spl/u-boot-nand-spl.imx: SPL__PLEASE_RENAME FORCE $(call if_changed,u-boot-nand-spl_imx) -targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-spl.imx) +targets += $(addprefix ../../../,$(IMX_CONFIG) SPL__PLEASE_RENAME u-boot.uim spl/u-boot-nand-spl.imx) -- 1.9.1

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