April 2014 - U-Boot

[U-Boot] [PATCH 0/3] board:tricorder: late fixups for 2014.04
by Andreas Bießmann 11 Apr '14

11 Apr '14

These fixups are required for tricorder board to run with 2014.04. One big change is a different ecc layout which came in by Pekon Gupta's changes to the omap_gpmc driver. Another point was changed behaviour of omap_gpio driver, we need to switch the clocks now explicitely. Thomas, could you please chack the patches and send your ACK ASAP? Best regards Andreas Bießmann Andreas Bießmann (3): board:tricorder: always work with valid eeprom data board:tricorder: enable omap_gpio clocks board:tricorder: fixup SPL OOB layout board/corscience/tricorder/tricorder.c | 2 ++ include/configs/tricorder.h | 14 +++++++++----- 2 files changed, 11 insertions(+), 5 deletions(-) -- 1.7.10.4

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Re: [U-Boot] [PATCH] AR8035/phy: Enable autonegotiation function for ar8035
by Scott Wood 11 Apr '14

11 Apr '14

On Fri, 2014-04-11 at 15:48 +0800, Xie Xiaobo wrote: > Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before, > but used "if (phydev->supported & SUPPORTED_Autoneg)" now. > So assign "phydev->supported" to "phydev->drv->features" for ar8035 > to enable autonegotiation. Then removed the genphy_config_aneg() function. > > Signed-off-by: Xie Xiaobo <X.Xie(a)freescale.com> > --- > drivers/net/phy/atheros.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) You should be CCing the network custodian, not me. -Scott

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[U-Boot] State of ARMv7 PSCI support?
by Jon Loeliger 11 Apr '14

11 Apr '14

Folks, I am curious about the state of the PSCI support on ARMv7, specifically the Cortex-A9, these days. I see that Marc Zyngier posted a 9 part patch a few months ago: [PATCH 0/9] ARMv7: add PSCI support to u-boot And I see that aspects of that series (Patch 1 Fix alignment requirements for vectors) have otherwise gone into mainline, but I was wondering if a rebased and more recent version of the patch series was available? I checked the ARM repo, and I can't find the series in there either. Is there a plan or interest in seeing this support added still? Thanks, jdl

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[U-Boot] Changes for boards I maintain
by Alexey Brodkin 11 Apr '14

11 Apr '14

Hi Tom, Now I have my own tree ("u-boot-arc") and I may commit there changes for ARC architecture. But I'm wondering if I may commit changes to boards I maintain in the same "u-boot-arc" repo as well? Currently these are all in "board/synopsys" folder. Or I need to send patches for my boards to the mailing list and you'll apply them to the master u-boot git? Regards, Alexey

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[U-Boot] board/freescale/mx6slevk: Add support for SPI NOR on the Freescale MCIMX6SLEVK Board
by Sam Catch 11 Apr '14

11 Apr '14

I hope this email is now in the right format. Hi All, I am trying to add support for the SPI NOR device on the Freescale MCIMX6SLEVK Board. I have created a patch that should enable support but the u-boot probe command still does not find the device. The process fails during the ECSPI transfer. I have tried the following patch to the latest git master of u-boot: http://pastebin.com/hamK7Ybb U-Boot Output: => sf probe SF: Unsupported flash IDs: manuf 00, jedec 0000, ext_jedec 0000 Failed to initialize SPI flash at 0:27392 Does anyone have any insight as to why the Probe may be failing? I modeled the changes on the mx6sabresd board.

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[U-Boot] [PATCH 1/3] board/t208xqds: Add support of 2-stage NAND/SPI/SD boot
by Shengzhou Liu 11 Apr '14

11 Apr '14

Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(96K) to it, SPL further initializes DDR using SPD and environment and copy u-boot from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- board/freescale/t208xqds/Makefile | 5 ++ board/freescale/t208xqds/ddr.c | 7 +- board/freescale/t208xqds/spl.c | 138 ++++++++++++++++++++++++++++++++++++++ board/freescale/t208xqds/tlb.c | 7 ++ boards.cfg | 8 +-- include/configs/T208xQDS.h | 115 +++++++++++++++++++++++++------ 6 files changed, 253 insertions(+), 27 deletions(-) create mode 100644 board/freescale/t208xqds/spl.c diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile index 947b7f7..6cb72c9 100644 --- a/board/freescale/t208xqds/Makefile +++ b/board/freescale/t208xqds/Makefile @@ -4,11 +4,16 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-$(CONFIG_T2080QDS) += t208xqds.o obj-$(CONFIG_T2080QDS) += eth_t208xqds.o obj-$(CONFIG_T2081QDS) += t208xqds.o obj-$(CONFIG_T2081QDS) += eth_t208xqds.o obj-$(CONFIG_PCI) += pci.o +endif + obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c index ed1334d..3348971 100644 --- a/board/freescale/t208xqds/ddr.c +++ b/board/freescale/t208xqds/ddr.c @@ -107,13 +107,16 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif - puts(" DDR: "); return dram_size; } diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c new file mode 100644 index 0000000..ef0191b --- /dev/null +++ b/board/freescale/t208xqds/spl.c @@ -0,0 +1,138 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <spi_flash.h> +#include "../common/qixis.h" +#include "t208xqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#if defined(CONFIG_SPL_MMC_BOOT) + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifndef CONFIG_SPL_NAND_BOOT + env_init(); +#endif + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; +#else + env_relocate(); +#endif + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index 62cd110..8d60298 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -65,6 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCIe 1, 0x80000000 */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -110,6 +111,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -141,6 +143,11 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 18, BOOKE_PAGESZ_1M, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 1d3aab1..4420c46 100644 --- a/boards.cfg +++ b/boards.cfg @@ -974,14 +974,14 @@ Active powerpc mpc85xx - freescale t1040qds Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 -Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,RAMBOOT_SPLPBL,SDCARD +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,RAMBOOT_SPLPBL,SPIFLASH +Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,RAMBOOT_SPLPBL,NAND Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081 Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 +Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,RAMBOOT_SPLPBL,NAND Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080 Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 1f42360..c47c1ee 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -46,15 +46,79 @@ #define CONFIG_ENV_OVERWRITE #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t208xqds/t208x_pbi.cfg #if defined(CONFIG_PPC_T2080) #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2080_rcw.cfg #elif defined(CONFIG_PPC_T2081) #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2081_rcw.cfg #endif + +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD0000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x30000 +#define RESET_VECTOR_OFFSET 0x2FFFC +#define BOOT_PAGE_OFFSET 0x2F000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif +#define CONFIG_SPL_SPI_BOOT +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_MMC_BOOT +#endif + +#endif /* CONFIG_RAMBOOT_PBL */ #define CONFIG_SRIO_PCIE_BOOT_MASTER #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE @@ -85,11 +149,7 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#ifdef CONFIG_SYS_NO_FLASH -#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_ENV_IS_NOWHERE -#endif -#else +#ifndef CONFIG_SYS_NO_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE @@ -110,12 +170,12 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1658) +#define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -140,7 +200,16 @@ unsigned long get_board_ddr_clk(void); /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (256 << 10) +#define CONFIG_SPL_GD_ADDR CONFIG_SYS_INIT_L3_ADDR +#ifdef CONFIG_NAND +#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L3_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L3_ADDR + 10 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L3_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (20 << 10) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -345,7 +414,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_RAMBOOT #endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ #define CONFIG_MISC_INIT_R #define CONFIG_HWCONFIG @@ -364,7 +438,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* @@ -461,15 +535,14 @@ unsigned long get_board_ddr_clk(void); */ #ifdef CONFIG_SPI_FLASH #define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SST #define CONFIG_SPI_FLASH_STMICRO -#if defined(CONFIG_T2080QDS) -#define CONFIG_SPI_FLASH_SPANSION -#elif defined(CONFIG_T2081QDS) +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SPI_FLASH_SST #define CONFIG_SPI_FLASH_EON #endif #define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_BAR #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 #endif @@ -564,14 +637,14 @@ unsigned long get_board_ddr_clk(void); #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 0x820) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing -- 1.8.0

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[U-Boot] [PATCH 10/10][v2] board/t104xrdb: Add support of NAND, SD, SPI boot for T104xRDB
by Prabhakar Kushwaha 11 Apr '14

11 Apr '14

Add support of 2 stage NAND, SD, SPI boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- This patch depends upon A) [PATCH 3] powerpc/t104xrdb: Unification of T104xRDB header files http://patchwork.ozlabs.org/patch/335207/ B) [U-Boot,v5] board/t104xrdb: Add support of CPLD http://patchwork.ozlabs.org/patch/336616/ Changes for v2: - Updated defines of SPL - Updated SPL to load env from SPI, MMC to CPC - Updated NAND FW, QE FMAN address board/freescale/t104xrdb/Makefile | 7 +- board/freescale/t104xrdb/README | 73 ++++++++++++++++++ board/freescale/t104xrdb/ddr.c | 5 +- board/freescale/t104xrdb/spl.c | 122 ++++++++++++++++++++++++++++++ board/freescale/t104xrdb/t1040_rcw.cfg | 7 ++ board/freescale/t104xrdb/t1042_rcw.cfg | 7 ++ board/freescale/t104xrdb/t104x_pbi.cfg | 26 +++++++ board/freescale/t104xrdb/tlb.c | 12 +++ boards.cfg | 6 ++ include/configs/T104xRDB.h | 127 +++++++++++++++++++++++++++----- 10 files changed, 372 insertions(+), 20 deletions(-) create mode 100644 board/freescale/t104xrdb/spl.c create mode 100644 board/freescale/t104xrdb/t1040_rcw.cfg create mode 100644 board/freescale/t104xrdb/t1042_rcw.cfg create mode 100644 board/freescale/t104xrdb/t104x_pbi.cfg diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile index 7e7bfb1..6cd304c 100644 --- a/board/freescale/t104xrdb/Makefile +++ b/board/freescale/t104xrdb/Makefile @@ -4,11 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # - +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-y += t104xrdb.o obj-y += cpld.o -obj-y += ddr.o obj-y += eth.o obj-$(CONFIG_PCI) += pci.o +endif +obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index 1da52bb..cdbe1fa 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -198,3 +198,76 @@ The below commands apply to the board 2.To change from vbank4 to vbank0 => qixis reset (it will boot using vbank0) + +NAND boot with 2 Stage boot loader +---------------------------------- +PBL initialise the internal SRAM and copy SPL(160KB) in SRAM. +SPL further initialise DDR using SPD and environment variables and copy +u-boot(768 KB) from flash to DDR. +Finally SPL transer control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + + Run time view of SPL framework during boot :- + ----------------------------------------------- + Area | Address | +----------------------------------------------- + Secure boot | 0xFFFC0000 (32KB) | + headers | | + ----------------------------------------------- + GD, BD | 0xFFFC8000 (4KB) | + ----------------------------------------------- + ENV | 0xFFFC9000 (8KB) | + ----------------------------------------------- + HEAP | 0xFFFCB000 (30KB) | + ----------------------------------------------- + STACK | 0xFFFD8000 (22KB) | + ----------------------------------------------- + U-boot SPL | 0xFFFD8000 (160KB) | + ----------------------------------------------- + +NAND Flash memory Map on T104xRDB +------------------------------------------ + Start End Definition Size +0x000000 0x0FFFFF u-boot 1MB +0x180000 0x19FFFF u-boot env 128KB +0x280000 0x29FFFF FMAN Ucode 128KB +0x380000 0x39FFFF QE Firmware 128KB + +SD Card memory Map on T104xRDB +------------------------------------------ + Block #blocks Definition Size +0x008 2048 u-boot 1MB +0x800 0024 u-boot env 8KB +0x820 0256 FMAN Ucode 128KB +0x920 0256 QE Firmware 128KB + +SPI Flash memory Map on T104xRDB +------------------------------------------ + Start End Definition Size +0x000000 0x0FFFFF u-boot 1MB +0x100000 0x101FFF u-boot env 8KB +0x110000 0x12FFFF FMAN Ucode 128KB +0x130000 0x14FFFF QE Firmware 128KB + +Please note QE Firmware is only valid for T1040RDB + + +Switch Settings: (ON is 0, OFF is 1) +=============== +NAND boot SW setting: +SW1: 10001000 +SW2: 00111001 +SW3: 11110001 + +SPI boot SW setting: +SW1: 00100010 +SW2: 10111001 +SW3: 11100001 + +SD boot SW setting: +SW1: 00100000 +SW2: 00111001 +SW3: 11100001 diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index 57d0f9c..34c9224 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -113,6 +113,7 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); @@ -120,6 +121,8 @@ phys_size_t initdram(int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); +#else + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c new file mode 100644 index 0000000..c628c95 --- /dev/null +++ b/board/freescale/t104xrdb/spl.c @@ -0,0 +1,122 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <spi_flash.h> + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; +#ifdef CONFIG_SPL_NAND_BOOT + u32 porsr1, pinctl; +#endif + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + +#ifdef CONFIG_SPL_NAND_BOOT + /* + * There is T1040 SoC issue where NOR, FPGA are inaccessible during + * NAND boot because IFC signals > IFC_AD7 are not enabled. + * This workaround changes RCW source to make all signals enabled. + */ + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); +#endif + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + puts("\n\n"); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t104xrdb/t1040_rcw.cfg b/board/freescale/t104xrdb/t1040_rcw.cfg new file mode 100644 index 0000000..3300c18 --- /dev/null +++ b/board/freescale/t104xrdb/t1040_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +66000002 80000002 e8106000 01000000 +00000000 00000000 00000000 00032810 +00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042_rcw.cfg b/board/freescale/t104xrdb/t1042_rcw.cfg new file mode 100644 index 0000000..a3ea8ad --- /dev/null +++ b/board/freescale/t104xrdb/t1042_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +06000002 00400002 e8106000 01000000 +00000000 00000000 00000000 00030810 +00000000 01fe0a06 00000000 00000000 diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg new file mode 100644 index 0000000..7b9e9b0 --- /dev/null +++ b/board/freescale/t104xrdb/t104x_pbi.cfg @@ -0,0 +1,26 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 fffc0007 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +091380c0 000FFFFF diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 84f97a4..95c15aa 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -53,6 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -82,6 +83,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -102,6 +104,16 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1), #endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 12, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 13, BOOKE_PAGESZ_1G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 160b026..94ae200 100644 --- a/boards.cfg +++ b/boards.cfg @@ -933,7 +933,13 @@ Active powerpc mpc85xx - freescale p2041rdb Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Active powerpc mpc85xx - freescale t104xrdb T1040RDB T104xRDB:PPC_T1040,T1040RDB Priyanka Jain <Priyanka.Jain(a)freescale.com> +Active powerpc mpc85xx - freescale t104xrdb T1040RDB_NAND T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND Priyanka Jain <Priyanka.Jain(a)freescale.com> +Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SPIFLASH T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Priyanka Jain <Priyanka.Jain(a)freescale.com> +Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SDCARD T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T104xRDB:PPC_T1042,T1042RDB_PI Priyanka Jain <Priyanka.Jain(a)freescale.com> +Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_NAND T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND Priyanka Jain <Priyanka.Jain(a)freescale.com> +Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SPIFLASH T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Priyanka Jain <Priyanka.Jain(a)freescale.com> +Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SDCARD T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 - Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index c143406..3023491 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -14,8 +14,79 @@ #define CONFIG_PHYS_64BIT #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg +#ifdef CONFIG_T1040RDB +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg +#endif +#ifdef CONFIG_T1042RDB_PI +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg +#endif + +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_SPI_BOOT +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_MMC_BOOT +#endif + #endif /* High Level Configuration Options */ @@ -50,15 +121,12 @@ #define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_NOWHERE -#else +#ifndef CONFIG_SYS_NO_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #endif -#ifndef CONFIG_SYS_NO_FLASH #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_SPI_FLASH @@ -70,11 +138,11 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1658) +#define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_IN_FLASH @@ -82,10 +150,6 @@ #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -#else /* CONFIG_SYS_NO_FLASH */ -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 66666666 @@ -117,6 +181,15 @@ * Config the L3 Cache as L3 SRAM */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE 256 << 10 +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -287,7 +360,11 @@ #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif #if defined(CONFIG_RAMBOOT_PBL) #define CONFIG_SYS_RAMBOOT @@ -335,7 +412,9 @@ #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ +#endif /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER @@ -525,18 +604,32 @@ #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 0x820) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif + +#ifdef CONFIG_T1040RDB +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_QE_FW_ADDR 0x130000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 +#endif +#endif + + #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif /* CONFIG_NOBQFMAN */ -- 1.7.9.5

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[U-Boot] How can I save U-Boot env vars to HUSH shell vars.
by James Chargin 10 Apr '14

10 Apr '14

I'd like to store the values of environment variables in HUSH shell variables and then restore them later. My ultimate goal is to preserve a few environment variables through a "env default -f". I'm working with U-Boot 2010.12. Changing to a newer version is not possible at this time. I realize this is a very old U-Boot. I'm hoping that the relevant parts of U-Boot have not changed between that old version and versions you might provide help for. I tried a few things and haven't found the right combination. I think the following commands demonstrate my problem. Given the U-Boot commands => setenv e "e ethaddr ipaddr rootpath" => => printenv e ethaddr ipaddr rootpath e=e ethaddr ipaddr rootpath ethaddr=00:00:17:88:09:36 ipaddr=10.3.134.80 rootpath=/home/anyuser/a/device/tr/rootfs => => for i in $e; do v_$i=$i; done => What I get: => showvar HUSH_VERSION=0.01 v_e=e v_ethaddr=ethaddr v_ipaddr=ipaddr v_rootpath=rootpath => What I want: => showvar HUSH_VERSION=0.01 v_e=e ethaddr ipaddr rootpath v_ethaddr=00:00:17:88:09:36 v_ipaddr=10.3.134.80 v_rootpath=/home/anyuser/a/device/tr/rootfs => So, how do I re-write the for loop to get the desired results Thanks for any help, Jim -- Jim Chargin AJA Video Systems jimc(a)aja.com (530) 271-3334 http://www.aja.com

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[U-Boot] [PATCH] Fix USB keyboard polling via control endpoint
by Adrian Cox 10 Apr '14

10 Apr '14

USB keyboard polling failed for some keyboards on PowerPC 5020. This was caused by requesting only 4 bytes of data from keyboards that produce an 8 byte HID report. Signed-off-by: Adrian Cox <adrian(a)humboldt.co.uk> --- common/usb_kbd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/usb_kbd.c b/common/usb_kbd.c index 1ad67ca..0f6c579 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -341,8 +341,8 @@ static inline void usb_kbd_poll_for_event(struct usb_device *dev) struct usb_kbd_pdata *data = dev->privptr; iface = &dev->config.if_desc[0]; usb_get_report(dev, iface->desc.bInterfaceNumber, - 1, 0, data->new, sizeof(data->new)); - if (memcmp(data->old, data->new, sizeof(data->new))) + 1, 0, data->new, 8); + if (memcmp(data->old, data->new, 8)) usb_kbd_irq_worker(dev); #endif }

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[U-Boot] [PATCH v2] Add endian support macros to interrupt transfers in the EHCI driver.
by Adrian Cox 10 Apr '14

10 Apr '14

Update the EHCI driver to support interrupt transfers on PowerPC. Signed-off-by: Adrian Cox <adrian(a)humboldt.co.uk> --- Changes in v2: - Whitespace and line length fixes for checkstyle drivers/usb/host/ehci-hcd.c | 56 ++++++++++++++++++++++++------------------- 1 file changed, 31 insertions(+), 25 deletions(-) diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 6017090..eaf5913 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -998,8 +998,8 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) if (!ehcic[index].periodic_list) return -ENOMEM; for (i = 0; i < 1024; i++) { - ehcic[index].periodic_list[i] = (uint32_t)periodic - | QH_LINK_TYPE_QH; + ehcic[index].periodic_list[i] = cpu_to_hc32((uint32_t)periodic + | QH_LINK_TYPE_QH); } flush_dcache_range((uint32_t)ehcic[index].periodic_list, @@ -1089,7 +1089,7 @@ struct int_queue { struct qTD *tds; }; -#define NEXT_QH(qh) (struct QH *)((qh)->qh_link & ~0x1f) +#define NEXT_QH(qh) (struct QH *)(hc32_to_cpu((qh)->qh_link) & ~0x1f) static int enable_periodic(struct ehci_ctrl *ctrl) @@ -1184,41 +1184,47 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, struct qTD *td = result->tds + i; void **buf = &qh->buffer; - qh->qh_link = (uint32_t)(qh+1) | QH_LINK_TYPE_QH; + qh->qh_link = cpu_to_hc32((uint32_t)(qh+1) | QH_LINK_TYPE_QH); if (i == queuesize - 1) - qh->qh_link = QH_LINK_TERMINATE; + qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE); - qh->qh_overlay.qt_next = (uint32_t)td; - qh->qh_overlay.qt_altnext = QT_NEXT_TERMINATE; - qh->qh_endpt1 = (0 << 28) | /* No NAK reload (ehci 4.9) */ + qh->qh_overlay.qt_next = cpu_to_hc32((uint32_t)td); + qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); + qh->qh_endpt1 = + cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */ (usb_maxpacket(dev, pipe) << 16) | /* MPS */ (1 << 14) | QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */ - (usb_pipedevice(pipe) << 0); - qh->qh_endpt2 = (1 << 30) | /* 1 Tx per mframe */ - (1 << 0); /* S-mask: microframe 0 */ + (usb_pipedevice(pipe) << 0)); + qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */ + (1 << 0)); /* S-mask: microframe 0 */ if (dev->speed == USB_SPEED_LOW || dev->speed == USB_SPEED_FULL) { debug("TT: port: %d, hub address: %d\n", dev->portnr, dev->parent->devnum); - qh->qh_endpt2 |= (dev->portnr << 23) | + qh->qh_endpt2 |= cpu_to_hc32((dev->portnr << 23) | (dev->parent->devnum << 16) | - (0x1c << 8); /* C-mask: microframes 2-4 */ + (0x1c << 8)); /* C-mask: microframes 2-4 */ } - td->qt_next = QT_NEXT_TERMINATE; - td->qt_altnext = QT_NEXT_TERMINATE; + td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); + td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); debug("communication direction is '%s'\n", usb_pipein(pipe) ? "in" : "out"); - td->qt_token = (elementsize << 16) | + td->qt_token = cpu_to_hc32((elementsize << 16) | ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */ - 0x80; /* active */ - td->qt_buffer[0] = (uint32_t)buffer + i * elementsize; - td->qt_buffer[1] = (td->qt_buffer[0] + 0x1000) & ~0xfff; - td->qt_buffer[2] = (td->qt_buffer[0] + 0x2000) & ~0xfff; - td->qt_buffer[3] = (td->qt_buffer[0] + 0x3000) & ~0xfff; - td->qt_buffer[4] = (td->qt_buffer[0] + 0x4000) & ~0xfff; + 0x80); /* active */ + td->qt_buffer[0] = + cpu_to_hc32((uint32_t)buffer + i * elementsize); + td->qt_buffer[1] = + cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff); + td->qt_buffer[2] = + cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff); + td->qt_buffer[3] = + cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff); + td->qt_buffer[4] = + cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff); *buf = buffer + i * elementsize; } @@ -1241,7 +1247,7 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, /* hook up to periodic list */ struct QH *list = &ctrl->periodic_queue; result->last->qh_link = list->qh_link; - list->qh_link = (uint32_t)result->first | QH_LINK_TYPE_QH; + list->qh_link = cpu_to_hc32((uint32_t)result->first | QH_LINK_TYPE_QH); flush_dcache_range((uint32_t)result->last, ALIGN_END_ADDR(struct QH, result->last, 1)); @@ -1280,7 +1286,7 @@ void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) /* still active */ invalidate_dcache_range((uint32_t)cur, ALIGN_END_ADDR(struct QH, cur, 1)); - if (cur->qh_overlay.qt_token & 0x80) { + if (cur->qh_overlay.qt_token & cpu_to_hc32(0x80)) { debug("Exit poll_int_queue with no completed intr transfer. " "token is %x\n", cur->qh_overlay.qt_token); return NULL; @@ -1311,7 +1317,7 @@ destroy_int_queue(struct usb_device *dev, struct int_queue *queue) struct QH *cur = &ctrl->periodic_queue; timeout = get_timer(0) + 500; /* abort after 500ms */ - while (!(cur->qh_link & QH_LINK_TERMINATE)) { + while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) { debug("considering %p, with qh_link %x\n", cur, cur->qh_link); if (NEXT_QH(cur) == queue->first) { debug("found candidate. removing from chain\n"); -- 1.7.9.5

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