April 2014 - U-Boot

[U-Boot] [PATCH] powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS
by Aneesh Bansal 24 Apr '14

24 Apr '14

Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/start.S | 9 ++------- arch/powerpc/include/asm/fsl_secure_boot.h | 2 ++ boards.cfg | 6 ++++++ include/configs/BSC9132QDS.h | 2 ++ 4 files changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 4ef0985..c692ba6 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -461,7 +461,8 @@ nexti: mflr r1 /* R1 = our PC */ 2: cmpw r3, r4 blt 1b -#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \ + !defined(CONFIG_SECURE_BOOT) /* * TLB entry for debuggging in AS1 * Create temporary TLB entry in AS0 to handle debug exception @@ -482,12 +483,6 @@ nexti: mflr r1 /* R1 = our PC */ 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 -#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ - 0, BOOKE_PAGESZ_1M, \ - CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ - CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \ - 0, r6 #else /* * TLB entry is created for IVPR + IVOR15 to map on valid OP code address diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 8f5bf10..c705d5a 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -10,6 +10,8 @@ #ifdef CONFIG_SECURE_BOOT #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 +#elif defined(CONFIG_BSC9132QDS) +#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 #else #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 #endif diff --git a/boards.cfg b/boards.cfg index cf2b1df..3e73d7e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -798,6 +798,12 @@ Active powerpc mpc85xx - freescale bsc9132qds Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi(a)freescale.com> Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi(a)freescale.com> Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi(a)freescale.com> +Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal(a)freescale.com> +Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal(a)freescale.com> +Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal(a)freescale.com> +Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal(a)freescale.com> +Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal(a)freescale.com> +Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal(a)freescale.com> Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu(a)freescale.com> Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu(a)freescale.com> Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu(a)freescale.com> diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 052a0f1..772e123 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -696,4 +696,6 @@ combinations. this should be removed later #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND +#include <asm/fsl_secure_boot.h> + #endif /* __CONFIG_H */ -- 1.8.1.4

2 1

[U-Boot] [PATCH][v2] powerpc/mpc8xxx: SECURE BOOT- Disable law 0 for non PBL platforms
by Aneesh Bansal 24 Apr '14

24 Apr '14

ISBC creates a LAW 0 entry for non PBL platforms, which is not disabled before transferring the control to uboot. The LAW 0 entry has to be disabled. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- arch/powerpc/cpu/mpc8xxx/law.c | 10 ++++++++++ 1 file changed, 10 insertions(+) Changes from v1: The LAW was being disabled in start.S in v1. As per discussion, it is moved out of start.S and done when U-boot initializes other LAW's. diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index a401083..55ee125 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -233,6 +233,16 @@ void init_laws(void) #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes #endif +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500) && \ + !defined(CONFIG_E500MC) + /* ISBC (Boot ROM) creates a LAW 0 entry for non PBL platforms, + * which is not disabled before transferring the control to uboot. + * Disable the LAW 0 entry here. + */ + disable_law(0); +#endif + + /* * Any LAWs that were set up before we booted assume they are meant to * be around and mark them used. -- 1.8.1.4

2 1

[U-Boot] [PATCH 2/3] powerpc/p1010rdb: SECURE BOOT- enable workaround for IFC errata A003399
by Aneesh Bansal 24 Apr '14

24 Apr '14

The workaround for IFC errata A003399 was not enabled in case of secure boot. So, secure boot from NOR was not working. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- include/configs/P1010RDB.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index c21cf07..b0e51fb 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -455,8 +455,7 @@ extern unsigned long get_sdram_size(void); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 -#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\ - && !defined(CONFIG_SECURE_BOOT) +#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_A003399_NOR_WORKAROUND #endif #endif -- 1.8.1.4

4 3

[U-Boot] [PATCH][v2] powerpc/p1010rdb: SECURE BOOT enabled for NAND
by Aneesh Bansal 24 Apr '14

24 Apr '14

In case of secure boot from NAND, the DDR is initialized by the BootROM using the config words (CF_WORDS) in the CF_HEADER and u-boot image is copied from NAND to DDR by the BootROM. So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- include/configs/P1010RDB.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) Changes from v1: Changed the subject line from SECURE BOOT- define CONFIG_SYS_RAMBOOT for NAND boot as per discussion diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index eabfc85..0ae45ad 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -541,7 +541,8 @@ extern unsigned long get_sdram_size(void); FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 -#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) +#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ + defined(CONFIG_RAMBOOT_NAND) #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC #else -- 1.8.1.4

2 1

[U-Boot] [PATCH] t1040rdb/qe: add QE support for T1040RDB
by Zhao Qiang 24 Apr '14

24 Apr '14

add CONFIG_QE, CONFIG_U_QE and CONFIG_SYS_QE_FW_ADDR into "include/configs/T1040RDB.h" Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- include/configs/T1040RDB.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index 7420db9..f036192 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -510,6 +510,9 @@ #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME +#define CONFIG_QE +#define CONFIG_U_QE + /* Default address of microcode for the Linux Fman driver */ #if defined(CONFIG_SPIFLASH) /* @@ -532,6 +535,7 @@ #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -- 1.8.5

2 1

[U-Boot] [PATCH v7 1/3] QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and CONFIG_SYS_QE_FW_ADDR
by Zhao Qiang 24 Apr '14

24 Apr '14

CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- Changes for v2: - no Changes for v3: - no Changes for v4: - no Changes for v5: - modify CONFIG_SYS_QE_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR for kmp204x Changes for v6: - rebase Changes for v7: - no README | 9 +++++++-- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- drivers/net/fm/fm.c | 12 ++++++------ drivers/qe/qe.c | 2 +- include/configs/B4860QDS.h | 10 +++++----- include/configs/MPC8569MDS.h | 2 +- include/configs/P1023RDB.h | 2 +- include/configs/P1023RDS.h | 4 ++-- include/configs/P2041RDB.h | 10 +++++----- include/configs/T1040QDS.h | 8 ++++---- include/configs/T1040RDB.h | 8 ++++---- include/configs/T1042RDB_PI.h | 8 ++++---- include/configs/T208xQDS.h | 10 +++++----- include/configs/T208xRDB.h | 10 +++++----- include/configs/T4240EMU.h | 2 +- include/configs/T4240QDS.h | 10 +++++----- include/configs/corenet_ds.h | 10 +++++----- include/configs/km/km8309-common.h | 2 +- include/configs/km/kmp204x-common.h | 2 +- include/configs/p1_p2_rdb_pc.h | 2 +- include/configs/p1_twr.h | 2 +- 21 files changed, 66 insertions(+), 61 deletions(-) diff --git a/README b/README index 216f0c7..c49efee 100644 --- a/README +++ b/README @@ -4485,8 +4485,13 @@ This firmware often needs to be loaded during U-Boot booting, so macros are used to identify the storage device (NOR flash, SPI, etc) and the address within that device. -- CONFIG_SYS_QE_FMAN_FW_ADDR - The address in the storage device where the firmware is located. The +- CONFIG_SYS_FMAN_FW_ADDR + The address in the storage device where the FMAN microcode is located. The + meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro + is also specified. + +- CONFIG_SYS_QE_FW_ADDR + The address in the storage device where the QE microcode is located. The meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro is also specified. diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 81aeadd..e0fb3e5 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -805,7 +805,7 @@ void cpu_secondary_init_r(void) /* load QE firmware from NAND flash to DDR first */ ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, - &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); + &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR); if (ret && ret == -EUCLEAN) { printf ("NAND read for QE firmware at offset %x failed %d\n", diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index bca20b3..400e9dd 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -350,16 +350,16 @@ int fm_init_common(int index, struct ccsr_fman *reg) { int rc; #if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR) - void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; + void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR; #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND) size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); - rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_ADDR, + rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR, &fw_length, (u_char *)addr); if (rc == -EUCLEAN) { printf("NAND read of FMAN firmware at offset 0x%x failed %d\n", - CONFIG_SYS_QE_FMAN_FW_ADDR, rc); + CONFIG_SYS_FMAN_FW_ADDR, rc); } #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH) struct spi_flash *ucode_flash; @@ -371,7 +371,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) if (!ucode_flash) printf("SF: probe for ucode failed\n"); else { - ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FMAN_FW_ADDR, + ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR, CONFIG_SYS_QE_FMAN_FW_LENGTH, addr); if (ret) printf("SF: read for ucode failed\n"); @@ -381,7 +381,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) int dev = CONFIG_SYS_MMC_ENV_DEV; void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; - u32 blk = CONFIG_SYS_QE_FMAN_FW_ADDR / 512; + u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512; struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); if (!mmc) @@ -395,7 +395,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) flush_cache((ulong)addr, cnt * 512); } #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE) - void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; + void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR; #else void *addr = NULL; #endif diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index b5ddc4b..b1da75e 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -165,7 +165,7 @@ void qe_init(uint qe_base) /* * Upload microcode to IRAM for those SOCs which do not have ROM in QE. */ - qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR); + qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR); /* enable the microcode in IRAM */ out_be32(&qe_immr->iram.iready,QE_IRAM_READY); diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index b248302..b9ec957 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -596,7 +596,7 @@ unsigned long get_board_ddr_clk(void); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -604,10 +604,10 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -617,10 +617,10 @@ unsigned long get_board_ddr_clk(void); * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 58b9c26..5165a45 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -493,7 +493,7 @@ extern unsigned long get_clock_freq(void); /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xfff00000 +#define CONFIG_SYS_QE_FW_ADDR 0xfff00000 /* * BOOTP options diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index b41cb4a..d7274f1 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -360,7 +360,7 @@ extern unsigned long get_clock_freq(void); /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index 2ffa354..0ee75dc 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -500,10 +500,10 @@ extern unsigned long get_clock_freq(void); /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x1f00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index b3880f1..f024c29 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -506,7 +506,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -514,10 +514,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -527,10 +527,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 993f9ae..84213b8 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -602,7 +602,7 @@ unsigned long get_board_ddr_clk(void); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -610,13 +610,13 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index 395845b..7420db9 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -517,7 +517,7 @@ * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -525,13 +525,13 @@ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h index 68656e6..a2af6b0 100644 --- a/include/configs/T1042RDB_PI.h +++ b/include/configs/T1042RDB_PI.h @@ -525,7 +525,7 @@ * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -533,13 +533,13 @@ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 399ddbb..04527e3 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -552,7 +552,7 @@ unsigned long get_board_ddr_clk(void); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -560,10 +560,10 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -573,10 +573,10 @@ unsigned long get_board_ddr_clk(void); * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 743eee3..66f8a4c 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -510,7 +510,7 @@ unsigned long get_board_ddr_clk(void); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #define CONFIG_CORTINA_FW_ADDR 0x120000 #elif defined(CONFIG_SDCARD) @@ -520,12 +520,12 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #define CONFIG_CORTINA_FW_ADDR (512 * 1808) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_CORTINA_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* @@ -536,11 +536,11 @@ unsigned long get_board_ddr_clk(void); * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 diff --git a/include/configs/T4240EMU.h b/include/configs/T4240EMU.h index c81c457..ad5a9a6 100644 --- a/include/configs/T4240EMU.h +++ b/include/configs/T4240EMU.h @@ -98,7 +98,7 @@ #define CONFIG_SYS_INTERLAKEN #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 56e1293..1b98cfd 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -375,7 +375,7 @@ unsigned long get_board_ddr_clk(void); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -383,10 +383,10 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -396,10 +396,10 @@ unsigned long get_board_ddr_clk(void); * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 1e4bfc4..ca14558 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -509,7 +509,7 @@ * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -517,10 +517,10 @@ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -530,10 +530,10 @@ * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h index 29c6f60..c8df23b 100644 --- a/include/configs/km/km8309-common.h +++ b/include/configs/km/km8309-common.h @@ -27,7 +27,7 @@ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR /* at end of uboot partition, before env */ -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xF00B0000 +#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000 /* * System IO Config diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 582978a..418e3d1 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -350,7 +350,7 @@ int get_scl(void); * ucode is stored after env, so we got 0x120000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x120000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x120000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 07b6179..d3a792a 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -772,7 +772,7 @@ #ifdef CONFIG_QE /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000 +#define CONFIG_SYS_QE_FW_ADDR 0xefec0000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #endif /* CONFIG_QE */ diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index c296a07..97ec593 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -348,7 +348,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #ifdef CONFIG_QE /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000 +#define CONFIG_SYS_QE_FW_ADDR 0xefec0000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #endif /* CONFIG_QE */ -- 1.8.5

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[U-Boot] [PATCH][v5] board/t104xrdb: Add support of CPLD
by Prabhakar Kushwaha 24 Apr '14

24 Apr '14

T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features. This support of CPLD includes - files and register defintion - Commands to swtich alternate bank and default bank Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Changes for v2: - Updated the cpld command Changes for v3: - fix typo Changes for v4: - fix typo Changes for v5: - fix cpld registers while printing - rebased on top of below patch powerpc/t104xrdb: Unification of T104xRDB header files http://patchwork.ozlabs.org/patch/335207/ board/freescale/t104xrdb/Makefile | 1 + board/freescale/t104xrdb/cpld.c | 112 +++++++++++++++++++++++++++++++++++ board/freescale/t104xrdb/cpld.h | 40 +++++++++++++ board/freescale/t104xrdb/t104xrdb.c | 13 ++++ include/configs/T104xRDB.h | 8 +++ 5 files changed, 174 insertions(+) create mode 100644 board/freescale/t104xrdb/cpld.c create mode 100644 board/freescale/t104xrdb/cpld.h diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile index e51fb7a..7e7bfb1 100644 --- a/board/freescale/t104xrdb/Makefile +++ b/board/freescale/t104xrdb/Makefile @@ -6,6 +6,7 @@ obj-y += t104xrdb.o +obj-y += cpld.o obj-y += ddr.o obj-y += eth.o obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c new file mode 100644 index 0000000..df0e348 --- /dev/null +++ b/board/freescale/t104xrdb/cpld.c @@ -0,0 +1,112 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 reg = CPLD_READ(flash_ctl_status); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; + + CPLD_WRITE(flash_ctl_status, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 reg = CPLD_READ(flash_ctl_status); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; + + CPLD_WRITE(flash_ctl_status, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); + printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); + printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); + printf("int_status = 0x%02x\n", CPLD_READ(int_status)); + printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status)); + printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); + printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); + printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); + printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); + printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); + printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1)); + printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2)); + putc('\n'); +} +#endif + +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - hard reset to default bank\n" + "cpld reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif + ); diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h new file mode 100644 index 0000000..0da9a01 --- /dev/null +++ b/board/freescale/t104xrdb/cpld.h @@ -0,0 +1,40 @@ +/** + * Copyright 2013 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ + u8 hw_ver; /* 0x02 - Hardware Revision Register */ + u8 sw_ver; /* 0x03 - Software Revision register */ + u8 res0[12]; /* 0x04 - 0x0F - not used */ + u8 reset_ctl1; /* 0x10 - Reset control Register1 */ + u8 reset_ctl2; /* 0x11 - Reset control Register2 */ + u8 int_status; /* 0x12 - Interrupt status Register */ + u8 flash_ctl_status; /* 0x13 - Flash control and status register */ + u8 fan_ctl_status; /* 0x14 - Fan control and status register */ + u8 led_ctl_status; /* 0x15 - LED control and status register */ + u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ + u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ + u8 boot_override; /* 0x18 - Boot override register */ + u8 boot_config1; /* 0x19 - Boot config override register*/ + u8 boot_config2; /* 0x1A - Boot config override register*/ +} cpld_data_t; + + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value)\ + cpld_write(offsetof(struct cpld_data, reg), value) diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 6e29d64..b48133a 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -19,14 +19,27 @@ #include <fm_eth.h> #include "t104xrdb.h" +#include "cpld.h" DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; + u8 sw; printf("Board: %sRDB\n", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", + CPLD_READ(hw_ver), CPLD_READ(sw_ver)); + + sw = CPLD_READ(flash_ctl_status); + sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + + if (sw <= 7) + printf("vBank: %d\n", sw); + else + printf("Unsupported Bank=%x\n", sw); + return 0; } diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 8d2fdb0..2bbb78c 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -179,6 +179,14 @@ #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} /* CPLD on IFC */ +#define CPLD_LBMAP_MASK 0x3F +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_OVERRIDE 0x40 +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ +#define CPLD_LBMAP_RESET 0xFF +#define CPLD_LBMAP_SHIFT 0x03 + #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) #define CONFIG_SYS_CSPR2_EXT (0xf) -- 1.7.9.5

2 1

[U-Boot] [PATCH v2] powerpc/cpu/mpc85xx: Add MAC address for layer 2 switch
by Codrin Ciubotariu 24 Apr '14

24 Apr '14

T1040RDB and T1040QDS boards have an integrated l2 switch. The switch needs a MAC address for Layer 2 protocols (MSTP, LLDP, LACP, etc). Setting a MAC address on l2switchaddr will add a MAC in device-tree, under node l2switch. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu(a)freescale.com> Cc: York Sun <yorksun(a)freescale.com> --- Changes v2: - replaced board macros with SoC macro; - added more comments; arch/powerpc/cpu/mpc85xx/fdt.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 33bc900..35bd013 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -582,6 +582,33 @@ static void fdt_fixup_usb(void *fdt) #define fdt_fixup_usb(x) #endif +#if defined(CONFIG_PPC_T1040) +static void fdt_fixup_l2_switch(void *blob) +{ + uchar l2swaddr[6]; + int node; + + /* The l2switch node from device-tree has + * compatible string "vitesse-9953" */ + node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953"); + if (node == -FDT_ERR_NOTFOUND) + /* no l2switch node has been found */ + return; + + /* Get MAC address for the l2switch from "l2switchaddr"*/ + if (!eth_getenv_enetaddr("l2switchaddr", l2swaddr)) { + printf("Warning: MAC address for l2switch not found\n"); + memset(l2swaddr, 0, sizeof(l2swaddr)); + } + + /* Add MAC address to l2switch node */ + fdt_setprop(blob, node, "local-mac-address", l2swaddr, + sizeof(l2swaddr)); +} +#else +#define fdt_fixup_l2_switch(x) +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { int off; @@ -719,6 +746,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", gd->bus_clk/2, 1); fdt_fixup_usb(blob); + + fdt_fixup_l2_switch(blob); } /* -- 1.7.11.7

2 1

[U-Boot] [PATCH] powerpc/T1040: add mtdparts suppport for T104xRDB and T1040QDS
by Prabhakar Kushwaha 24 Apr '14

24 Apr '14

We use dynamical mtdparts partition instead of directly puting mtd partitions nodes in device tree. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- This patch depends upon powerpc/t104xrdb: Unification of T104xRDB header files http://patchwork.ozlabs.org/patch/335207/ include/configs/T1040QDS.h | 17 +++++++++++++++++ include/configs/T104xRDB.h | 17 +++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 993f9ae..e802a82 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -649,6 +649,23 @@ unsigned long get_board_ddr_clk(void); #endif /* + * Dynamic MTD Partition support with mtdparts + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ + "spi0=spife110000.0" +#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ + "128k(dtb),96m(fs),-(user);"\ + "fff800000.flash:2m(uboot),9m(kernel),"\ + "128k(dtb),96m(fs),-(user);spife110000.0:" \ + "2m(uboot),9m(kernel),128k(dtb),-(user)" +#endif + +/* * Environment */ #define CONFIG_LOADS_ECHO /* echo on for serial download */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 8d2fdb0..16d27f3 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -611,6 +611,23 @@ #endif /* + * Dynamic MTD Partition support with mtdparts + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ + "spi0=spife110000.0" +#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ + "128k(dtb),96m(fs),-(user);"\ + "fff800000.flash:2m(uboot),9m(kernel),"\ + "128k(dtb),96m(fs),-(user);spife110000.0:" \ + "2m(uboot),9m(kernel),128k(dtb),-(user)" +#endif + +/* * Environment Configuration */ #define CONFIG_ROOTPATH "/opt/nfsroot" -- 1.7.9.5

2 1

[U-Boot] [U-BOOT] [PATCH v3] powerpc/t104xrdb: Unification of T104xRDB header files
by Vijay Rai 24 Apr '14

24 Apr '14

T1040RDB, T1042RDB header files are very similar so merged into new header file T104xRDB. T104xRDB header file can support both T1040RDB and T1042RDB_PI header. Patch makes following changes -Update Boards.cfg file for T1040RDB and T1042RDB_PI -Add new T104xRDB header file -Delete T1040RDB, T1042RDB_PI header file Signed-off-by: Vijay Rai <vijay.rai(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- v3: - Rebasing to top of the tree boards.cfg | 4 +- include/configs/T1042RDB_PI.h | 695 ---------------------------- include/configs/{T1040RDB.h => T104xRDB.h} | 57 ++- 3 files changed, 35 insertions(+), 721 deletions(-) delete mode 100644 include/configs/T1042RDB_PI.h rename include/configs/{T1040RDB.h => T104xRDB.h} (95%) diff --git a/boards.cfg b/boards.cfg index 69c8936..5afca26 100644 --- a/boards.cfg +++ b/boards.cfg @@ -932,8 +932,8 @@ Active powerpc mpc85xx - freescale p2041rdb Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal(a)freescale.com> -Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal(a)freescale.com> -Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal(a)freescale.com> +Active powerpc mpc85xx - freescale t104xrdb T1040RDB T104xRDB:PPC_T1040,T1040RDB Priyanka Jain <Priyanka.Jain(a)freescale.com> +Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T104xRDB:PPC_T1042,T1042RDB_PI Priyanka Jain <Priyanka.Jain(a)freescale.com> Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 - Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h deleted file mode 100644 index 68656e6..0000000 --- a/include/configs/T1042RDB_PI.h +++ /dev/null @@ -1,695 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * T1042RDB_PI board configuration file - */ -#define CONFIG_T104xRDB -#define CONFIG_T1042RDB_PI -#define CONFIG_PHYS_64BIT - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MP /* support multiple processors */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff40000 -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS -#define CONFIG_FSL_IFC /* Enable IFC Support */ -#define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ -#define CONFIG_PCIE4 /* PCIE controler 4 */ - -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_FSL_LAW /* Use common FSL init code */ - -#define CONFIG_ENV_OVERWRITE - -#ifdef CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_NOWHERE -#else -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#endif - -#ifndef CONFIG_SYS_NO_FLASH -#if defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1658) -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif -#else /* CONFIG_SYS_NO_FLASH */ -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 66666666 - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BACKSIDE_L2_CACHE -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 -#define CONFIG_SYS_ALT_MEMTEST -#define CONFIG_PANIC_HANG /* do not reset board on panic */ - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 - -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define CONFIG_DDR_SPD -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_SYS_FSL_DDR3 - -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x51 - -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) - -#define CONFIG_SYS_NOR_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} - -/* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR2_EXT (0xf) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 -/* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) - -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ - | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ - | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_CMD_NAND - -#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) - -#if defined(CONFIG_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_BOARD_EARLY_INIT_R -#define CONFIG_MISC_INIT_R - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) -#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* new uImage format support */ -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ -#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 - -/* I2C bus multiplexer */ -#define I2C_MUX_PCA_ADDR 0x70 - -/* - * RTC configuration - */ -#define RTC -#define CONFIG_RTC_DS1337 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/*DVI encoder*/ -#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 - -/* - * eSPI - Enhanced SPI - */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_SPEED 10000000 -#define CONFIG_SF_DEFAULT_MODE 0 -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_ENV_SPI_MODE 0 - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -#ifdef CONFIG_PCI -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 4, Base address 203000 */ -#ifdef CONFIG_PCIE4 -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ -#endif - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_DOS_PARTITION -#endif /* CONFIG_PCI */ - -/* SATA */ -#define CONFIG_FSL_SATA_V2 -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#define CONFIG_CMD_SATA -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_EXT2 -#endif - -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_CMD_EXT2 -#endif -#endif - -#define CONFIG_MMC - -#ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_CMD_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 25 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_NUM_PORTALS 25 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME - -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. - */ -#define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) -#else -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_FMAN_ENET -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_REALTEK -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_ETHPRIME "FM1@DTSEC4" -#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ -#endif - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_GREPENV -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SETEXPR - -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NET -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ - -#define CONFIG_BAUDRATE 115200 - -#define __USB_PHY_TYPE utmi - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ - "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=t1040rdb_pi/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=t1040rdb_pi/t1040rdb_pi.dtb\0" \ - "bdev=sda3\0" \ - "c=ffe\0" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#ifdef CONFIG_SECURE_BOOT -#include <asm/fsl_secure_boot.h> -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/T1040RDB.h b/include/configs/T104xRDB.h similarity index 95% rename from include/configs/T1040RDB.h rename to include/configs/T104xRDB.h index 395845b..8d2fdb0 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T104xRDB.h @@ -1,33 +1,16 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ ++ * Copyright 2014 Freescale Semiconductor, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ #ifndef __CONFIG_H #define __CONFIG_H /* - * T1040 RDB board configuration file + * T104x RDB board configuration file */ #define CONFIG_T104xRDB -#define CONFIG_T1040RDB #define CONFIG_PHYS_64BIT #ifdef CONFIG_RAMBOOT_PBL @@ -371,8 +354,21 @@ /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 +#ifdef CONFIG_T1040RDB #define I2C_MUX_CH_DEFAULT 0x8 +#endif + +#ifdef CONFIG_T1042RDB_PI +/* + * RTC configuration + */ +#define RTC +#define CONFIG_RTC_DS1337 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +/*DVI encoder*/ +#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 +#endif /* * eSPI - Enhanced SPI @@ -544,7 +540,9 @@ #endif #ifdef CONFIG_FMAN_ENET +#ifdef CONFIG_T1040RDB #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#endif #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 @@ -564,6 +562,9 @@ */ #include <config_cmd_default.h> +#ifdef CONFIG_T1042RDB_PI +#define CONFIG_CMD_DATE +#endif #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA @@ -625,6 +626,14 @@ #define __USB_PHY_TYPE utmi +#ifdef CONFIG_T1040RDB +#define FDTFILE "t1040rdb/t1040rdb.dtb" +#define RAMDISKFILE "t1040rdb/ramdisk.uboot" +#elif CONFIG_T1042RDB_PI +#define FDTFILE "t1040rdb_pi/t1040rdb_pi.dtb" +#define RAMDISKFILE "t1040rdb_pi/ramdisk.uboot" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ @@ -640,9 +649,9 @@ "cmp.b $loadaddr $ubootaddr $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ - "ramdiskfile=t1040rdb/ramdisk.uboot\0" \ + "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ "fdtaddr=c00000\0" \ - "fdtfile=t1040rdb/t1040rdb.dtb\0" \ + "fdtfile=" __stringify(FDTFILE) "\0" \ "bdev=sda3\0" \ "c=ffe\0" -- 1.6.5.6

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