April 2014 - U-Boot

[U-Boot] [Port] Ecounter a problem while Compiling uboot with android toolchain
by liu tao 24 Apr '14

24 Apr '14

Hi all, When I commpile uboot with android toolchain, I encounter a problem: "u-boot contains unexpected relocations:make V=132 R_ARM_RELATIVE" Below is my steps: # arm-linux-androideabi-gcc -v Using built-in specs. COLLECT_GCC=arm-linux-androideabi-gcc COLLECT_LTO_WRAPPER=/home/lt/app/toolchain/arm-linux-androideabi-4.6/bin/../libexec/gcc/arm-linux-androideabi/4.6/lto-wrapper Target: arm-linux-androideabi Configured with: /s/ndk-toolchain/src/build/../gcc/gcc-4.6/configure --prefix=/tmp/ndk-andrewhsieh/build/toolchain/prefix --target=arm-linux-androideabi --host=x86_64-linux-gnu --build=x86_64-linux-gnu --with-gnu-as --with-gnu-ld --enable-languages=c,c++ --with-gmp=/tmp/ndk-andrewhsieh/build/toolchain/temp-install --with-mpfr=/tmp/ndk-andrewhsieh/build/toolchain/temp-install --with-mpc=/tmp/ndk-andrewhsieh/build/toolchain/temp-install --with-cloog=/tmp/ndk-andrewhsieh/build/toolchain/temp-install --with-ppl=/tmp/ndk-andrewhsieh/build/toolchain/temp-install --disable-ppl-version-check --disable-cloog-version-check --enable-cloog-backend=isl --with-host-libstdcxx='-static-libgcc -Wl,-Bstatic,-lstdc++,-Bdynamic -lm' --disable-libssp --enable-threads --disable-nls --disable-libmudflap --disable-libgomp --disable-libstdc__-v3 --disable-sjlj-exceptions --disable-shared --disable-tls --disable-libitm --with-float=soft --with-fpu=vfp --with-arch=armv5te --enable-target-optspace --enable-initfini-array --disable-nls --prefix=/tmp/ndk-andrewhsieh/build/toolchain/prefix --with-sysroot=/tmp/ndk-andrewhsieh/build/toolchain/prefix/sysroot --with-binutils-version=2.21 --with-mpfr-version=3.1.1 --with-mpc-version=1.0.1 --with-gmp-version=5.0.5 --with-gcc-version=4.6 --with-gdb-version=7.3.x --with-gxx-include-dir=/tmp/ndk-andrewhsieh/build/toolchain/prefix/include/c++/4.6 --with-bugurl=http://source.android.com/source/report-bugs.html --disable-bootstrap --disable-libquadmath --enable-plugins --enable-libgomp --enable-gold --enable-graphite=yes --with-cloog-version=0.17.0 --with-ppl-version=1.0 --with-arch=armv5te --program-transform-name='s&^&arm-linux-androideabi-&' --enable-gold=default Thread model: posix gcc version 4.6 20120106 (prerelease) (GCC) #cd u-boot-2014.04 #export CROSS_COMPOLE=arm-linux-androideabi- #make smdk2410_config #make V=1 Attachment is output of "make V=1". I that should be R_ARM_REL32 not R_ARM_ABS32, and should I modify all OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") in *.lds ? And modufy elf32-littlearm to what? -- Best Wishes, Tao, Liu

1 0

[U-Boot] [RFC PATCH 0/3] Remove CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD}
by Masahiro Yamada 24 Apr '14

24 Apr '14

When I posted the RFC version of Kconfig series, I defined CONFIG_SYS_ARCH, CONFIG_SYS_CPU, CONFIG_SYS_SOC, CONFIG_SYS_VENDOR, CONFIG_SYS_BOARD in Kconfig. For example, configs/harmony_defconfig was like this: CONFIG_SPL=y CONFIG_ARM=y CONFIG_SYS_CPU="armv7" CONFIG_SOC_DIR=y CONFIG_SYS_SOC="tegra20" CONFIG_SYS_BOARD="harmony" CONFIG_VENDOR_DIR=y CONFIG_SYS_VENDOR="nvidia" CONFIG_SYS_CONFIG_NAME="harmony" CONFIG_BOARD_MAINTAINER="Tom Warren <twarren(a)nvidia.com>" But the most reviewers involved did not like that. (See http://patchwork.ozlabs.org/patch/330915/) Instead, Daniel Schwierzeck suggested to select a board by using boolean macro: something like this, CONFIG_BOARD_HARMONY, CONFIG_VENDOR_NVIDIA, ... I agree this is a good idea. But string macros are used everywhere in U-Boot. $(CPU), $(SOC), $(VENDOR), $(BOARD) here and there in makefiles and CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD} in C source files. I took an action little by little to reduce the number of such variables in makefiles For example, these patches: http://patchwork.ozlabs.org/patch/335202/ http://patchwork.ozlabs.org/patch/335201/ I want to do something with CONFIG_SYS_{ARCH,...} in this series. Masahiro Yamada (3): env: drop CONFIG_ENV_VARS_UBOOT_CONFIG support cmd_pxe: remove SoC, ARCH path from pxe_default_path mkconfig: Do not define CONFIG_SYS_{ARCH,CPU,SOC,VENDOR,BOARD} in config.h. README | 14 -------------- arch/arm/include/asm/arch-tegra114/tegra.h | 1 + arch/arm/include/asm/arch-tegra124/tegra.h | 1 + arch/arm/include/asm/arch-tegra20/tegra.h | 1 + arch/arm/include/asm/arch-tegra30/tegra.h | 1 + arch/blackfin/lib/Makefile | 3 --- common/cmd_pxe.c | 4 ---- include/configs/am335x_igep0033.h | 1 - include/configs/apf27.h | 1 - include/configs/exynos4-dt.h | 2 +- include/configs/omap4_panda.h | 1 + include/configs/pcm051.h | 1 - include/configs/rpi_b.h | 1 - include/configs/s5p_goni.h | 1 - include/configs/s5pc210_universal.h | 3 ++- include/configs/siemens-am33x-common.h | 1 - include/configs/tegra-common.h | 1 - include/configs/ti814x_evm.h | 1 - include/configs/ti_armv7_common.h | 1 - include/configs/trats.h | 2 +- include/configs/trats2.h | 3 ++- include/env_default.h | 12 ------------ mkconfig | 8 -------- 23 files changed, 11 insertions(+), 54 deletions(-) -- 1.8.3.2

5 13

[U-Boot] [PATCH 1/2] mpc85xx: Add deep sleep support on T1040QDS
by Tang Yuantian 24 Apr '14

24 Apr '14

From: Tang Yuantian <yuantian.tang(a)freescale.com> Add deep sleep support on T1040QDS platform. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- board/freescale/t1040qds/t1040qds.c | 12 ++++++++++++ include/configs/T1040QDS.h | 4 ++++ 2 files changed, 16 insertions(+) diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index 3dec447..f1d7cde 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -18,6 +18,7 @@ #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> +#include <asm/mpc85xx_gpio.h> #include "../common/qixis.h" #include "t1040qds.h" @@ -245,3 +246,14 @@ int board_need_mem_reset(void) { return 1; } + +#ifdef CONFIG_DEEP_SLEEP +void board_mem_sleep_setup(void) +{ + /* does not provide HW signals for power management */ + QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2)); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 030ea7e..745a2f2 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -43,6 +43,10 @@ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */ +/* support deep sleep */ +#define CONFIG_DEEP_SLEEP +#define CONFIG_SILENT_CONSOLE + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif -- 1.8.5

2 5

[U-Boot] [PATCH 1/2 v2] mpc85xx: Add support for the supplement configuration unit register
by Tang Yuantian 24 Apr '14

24 Apr '14

From: Tang Yuantian <yuantian.tang(a)freescale.com> The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- v2: - fix checkpatch warning arch/powerpc/include/asm/immap_85xx.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 4b6f9d0..0f0f3d4 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -3151,4 +3151,26 @@ struct dcsr_dcfg_regs { #define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */ }; + +#define CONFIG_SYS_MPC85xx_SCFG \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET) +#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000 +/* The supplement configuration unit register */ +struct ccsr_scfg { + u32 dpslpcr; /* 0x000 Deep Sleep Control register */ + u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */ + u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */ + u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */ + u32 res1[4]; + u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */ + u32 res2; + u32 pixclkcr; /* 0x028 Pixel Clock Control register */ + u32 res3[245]; + u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */ + u32 emiiocr; /* 0x404 EMI MDIO Control Register */ + u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */ + u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */ + u32 res4[60]; + u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */ +}; #endif /*__IMMAP_85xx__*/ -- 1.8.5

2 2

[U-Boot] [PATCH] ar8031: modify the config func of ar8031 to ar8021_config
by Zhao Qiang 24 Apr '14

24 Apr '14

ar8031 has the same config steps with ar8021, so change its config func to ar8021_config instead of genphy_config. Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- drivers/net/phy/atheros.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index b80980d..abd4e5b 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -53,7 +53,7 @@ static struct phy_driver AR8031_driver = { .uid = 0x4dd074, .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, - .config = genphy_config, + .config = ar8021_config, .startup = genphy_startup, .shutdown = genphy_shutdown, }; -- 1.8.5

2 1

[U-Boot] [PATCH 1/3 v2] board/t208xqds: Add support of 2-stage NAND/SPI/SD boot
by Shengzhou Liu 24 Apr '14

24 Apr '14

Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(160K) to it, SPL further initializes DDR using SPD and environment and copy u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- v2: updated to adapt to new SPL. board/freescale/t208xqds/Makefile | 5 ++ board/freescale/t208xqds/ddr.c | 7 +- board/freescale/t208xqds/spl.c | 137 ++++++++++++++++++++++++++++++++++++++ board/freescale/t208xqds/tlb.c | 7 ++ boards.cfg | 12 ++-- include/configs/T208xQDS.h | 113 +++++++++++++++++++++++++------ 6 files changed, 253 insertions(+), 28 deletions(-) create mode 100644 board/freescale/t208xqds/spl.c diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile index 947b7f7..6cb72c9 100644 --- a/board/freescale/t208xqds/Makefile +++ b/board/freescale/t208xqds/Makefile @@ -4,11 +4,16 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-$(CONFIG_T2080QDS) += t208xqds.o obj-$(CONFIG_T2080QDS) += eth_t208xqds.o obj-$(CONFIG_T2081QDS) += t208xqds.o obj-$(CONFIG_T2081QDS) += eth_t208xqds.o obj-$(CONFIG_PCI) += pci.o +endif + obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c index ed1334d..3348971 100644 --- a/board/freescale/t208xqds/ddr.c +++ b/board/freescale/t208xqds/ddr.c @@ -107,13 +107,16 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif - puts(" DDR: "); return dram_size; } diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c new file mode 100644 index 0000000..a71c617 --- /dev/null +++ b/board/freescale/t208xqds/spl.c @@ -0,0 +1,137 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <spi_flash.h> +#include "../common/qixis.h" +#include "t208xqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#if defined(CONFIG_SPL_MMC_BOOT) + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index 62cd110..8d60298 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -65,6 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCIe 1, 0x80000000 */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -110,6 +111,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -141,6 +143,11 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 18, BOOKE_PAGESZ_1M, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index ff385b9..2be3d42 100644 --- a/boards.cfg +++ b/boards.cfg @@ -959,14 +959,14 @@ Active powerpc mpc85xx - freescale t104xrdb Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SPIFLASH T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Priyanka Jain <Priyanka.Jain(a)freescale.com> Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 - Active powerpc mpc85xx - freescale t208xqds T2080QDS_SECURE_BOOT T208xQDS:PPC_T2080,SECURE_BOOT Aneesh Bansal <aneesh.bansal(a)freescale.com> -Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - -Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - -Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081 - -Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - -Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - -Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080 - Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index fb3e04f..8bf0843 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -46,15 +46,79 @@ #define CONFIG_ENV_OVERWRITE #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg #if defined(CONFIG_PPC_T2080) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg #elif defined(CONFIG_PPC_T2081) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg #endif + +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif +#define CONFIG_SPL_SPI_BOOT +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_MMC_BOOT +#endif + +#endif /* CONFIG_RAMBOOT_PBL */ #define CONFIG_SRIO_PCIE_BOOT_MASTER #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE @@ -85,11 +149,7 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#ifdef CONFIG_SYS_NO_FLASH -#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_ENV_IS_NOWHERE -#endif -#else +#ifndef CONFIG_SYS_NO_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE @@ -110,12 +170,12 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1658) +#define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -140,7 +200,16 @@ unsigned long get_board_ddr_clk(void); /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (512 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -345,7 +414,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_RAMBOOT #endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ #define CONFIG_MISC_INIT_R #define CONFIG_HWCONFIG @@ -461,15 +535,14 @@ unsigned long get_board_ddr_clk(void); */ #ifdef CONFIG_SPI_FLASH #define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SST #define CONFIG_SPI_FLASH_STMICRO -#if defined(CONFIG_T2080QDS) -#define CONFIG_SPI_FLASH_SPANSION -#elif defined(CONFIG_T2081QDS) +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SPI_FLASH_SST #define CONFIG_SPI_FLASH_EON #endif #define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_BAR #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 #endif @@ -564,14 +637,14 @@ unsigned long get_board_ddr_clk(void); #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing -- 1.8.0

2 5

[U-Boot] [PATCH][v2] powerpc/mpc85xx: Add Differential SYSCLK config support T1040
by Nikhil Badola 24 Apr '14

24 Apr '14

Adds support for clock sourcing from sysclk(100MHz) for usb on T104xRDB and T1040QDS. This requires changing reference divisor and multiplication factor to derive usb clock from sysclk. Signed-off-by: Nikhil Badola <nikhil.badola(a)freescale.com> --- Dependency on patch http://patchwork.ozlabs.org/patch/339164/ Changes for v2: - Changed patch heading arch/powerpc/cpu/mpc85xx/cpu_init.c | 26 ++++++++++++++++++++++++++ include/fsl_usb.h | 5 +++++ 2 files changed, 31 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 81aeadd..0e11a0b 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -36,6 +36,29 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK +/* + * For deriving usb clock from 100MHz sysclk, reference divisor is set + * to a value of 5, which gives an intermediate value 20(100/5). The + * multiplication factor integer is set to 24, which when multiplied to + * above intermediate value provides clock for usb ip. + */ +void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy) +{ + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + if (sysinfo.diff_sysclk == 1) { + clrbits_be32(&usb_phy->pllprg[1], + CONFIG_SYS_FSL_USB_PLLPRG2_MFI); + setbits_be32(&usb_phy->pllprg[1], + CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK | + CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK | + CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN); + } +} +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) { @@ -716,6 +739,9 @@ skip_l2: CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | CONFIG_SYS_FSL_USB_PLLPRG2_MFI | CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + usb_single_source_clk_configure(usb_phy); +#endif setbits_be32(&usb_phy->port1.ctrl, CONFIG_SYS_FSL_USB_CTRL_PHY_EN); setbits_be32(&usb_phy->port1.drvvbuscfg, diff --git a/include/fsl_usb.h b/include/fsl_usb.h index 8b63cdd..1a6c9c1 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -48,6 +48,11 @@ struct ccsr_usb_phy { #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0) #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1) #define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13) +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK +#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4) +#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16) +#define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20) +#endif #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4) #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16) #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21) -- 1.7.11.7

2 1

[U-Boot] [PATCH] powerpc/85xx: Enhance get_sys_info() to check clocking mode
by Vijay Rai 24 Apr '14

24 Apr '14

T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> Signed-off-by: Vijay Rai <vijay.rai(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cpu.c | 5 +++++ arch/powerpc/cpu/mpc85xx/speed.c | 21 +++++++++++++-------- arch/powerpc/include/asm/immap_85xx.h | 6 ++++++ include/e500.h | 3 +++ 4 files changed, 27 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index cb7efc9..0697123 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -129,6 +129,11 @@ int checkcpu (void) get_sys_info(&sysinfo); +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + if (sysinfo.diff_sysclk == 1) + puts("Single Source Clock Configuration\n"); +#endif + puts("Clock Configuration:"); for_each_cpu(i, core, nr_cores, mask) { if (!(i & 3)) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 74e3c1b..d516d4e 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -74,28 +74,33 @@ void get_sys_info(sys_info_t *sys_info) uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; uint mem_pll_rat; -#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK - uint single_src; -#endif sys_info->freq_systembus = sysclk; #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + uint ddr_refclk_sel; + unsigned int porsr1_sys_clk; + porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT + & FSL_DCFG_PORSR1_SYSCLK_MASK; + if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF) + sys_info->diff_sysclk = 1; + else + sys_info->diff_sysclk = 0; + /* * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS * are driven by separate DDR Refclock or single source * differential clock. */ - single_src = (in_be32(&gur->rcwsr[5]) >> + ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >> FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; /* - * For single source clocking, both ddrclock and syclock + * For single source clocking, both ddrclock and sysclock * are driven by differential sysclock. */ - if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) { - printf("Single Source Clock Configuration\n"); + if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; - } else + else #endif #ifdef CONFIG_DDR_CLK_FREQ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index a178187..3ca142d 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1583,6 +1583,12 @@ typedef struct cpc_corenet { typedef struct ccsr_gur { u32 porsr1; /* POR status 1 */ u32 porsr2; /* POR status 2 */ +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK +#define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15 +#define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1 +#define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1 +#define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0 +#endif u8 res_008[0x20-0x8]; u32 gpporcr1; /* General-purpose POR configuration */ u32 gpporcr2; /* General-purpose POR configuration 2 */ diff --git a/include/e500.h b/include/e500.h index 0c24326..5884a22 100644 --- a/include/e500.h +++ b/include/e500.h @@ -24,6 +24,9 @@ typedef struct #ifdef CONFIG_SYS_DPAA_PME unsigned long freq_pme; #endif +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + unsigned char diff_sysclk; +#endif } MPC85xx_SYS_INFO; #endif /* _ASMLANGUAGE */ -- 1.6.5.6

2 1

[U-Boot] [PATCH] powerpc/t1040rdb: added a break in switch case
by shh.xie＠gmail.com 24 Apr '14

24 Apr '14

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> There should be a break for case PHY_INTERFACE_MODE_SGMII, otherwise it will fall into case PHY_INTERFACE_MODE_RGMII. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- board/freescale/t104xrdb/eth.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 0188fd4..63e5f90 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -41,6 +41,7 @@ int board_eth_init(bd_t *bis) /* T1040RDB only supports SGMII on DTSEC3 */ fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_SGMII1_PHY_ADDR); + break; #endif case PHY_INTERFACE_MODE_RGMII: if (FM1_DTSEC4 == i) -- 1.8.0

2 1

[U-Boot] [Patch v2] drivers/ddr: Fix possible out of bounds error
by York Sun 24 Apr '14

24 Apr '14

This is a theoretical possible out of bounds error in DDR driver. Adding check before using array index. Also change some runtime conditions to pre-compiling conditions. Signed-off-by: York Sun <yorksun(a)freescale.com> --- Change log: v2: Revise subject and commit message drivers/ddr/fsl/ctrl_regs.c | 8 ++-- drivers/ddr/fsl/main.c | 6 +++ drivers/ddr/fsl/options.c | 108 +++++++++++++++++++++---------------------- 3 files changed, 64 insertions(+), 58 deletions(-) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index d01eea0..78e82bb 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -507,8 +507,8 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4); wrtord_mclk = max(2, picos_to_mclk(2500)); - if (wrrec_mclk > 24) - printf("Error: WRREC doesn't support more than 24 clocks\n"); + if ((wrrec_mclk < 1) || (wrrec_mclk > 24)) + printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); else wrrec_mclk = wrrec_table[wrrec_mclk - 1]; #else @@ -516,8 +516,8 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps); wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps); - if (wrrec_mclk > 16) - printf("Error: WRREC doesn't support more than 16 clocks\n"); + if ((wrrec_mclk < 1) || (wrrec_mclk > 16)) + printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); else wrrec_mclk = wrrec_table[wrrec_mclk - 1]; #endif diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index f95704f..5e001fc 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -220,6 +220,11 @@ const char * step_to_string(unsigned int step) { if ((1 << s) != step) return step_string_tbl[7]; + if (s >= ARRAY_SIZE(step_string_tbl)) { + printf("Error for the step in %s\n", __func__); + s = 0; + } + return step_string_tbl[s]; } @@ -520,6 +525,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, /* STEP 5: Assign addresses to chip selects */ check_interleaving_options(pinfo); total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust); + debug("Total mem %llu assigned\n", total_mem); case STEP_COMPUTE_REGS: /* STEP 6: compute controller register values */ diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index bf0d1da..5986e1a 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -525,67 +525,66 @@ unsigned int populate_memctl_options(int all_dimms_registered, defined(CONFIG_SYS_FSL_DDR2) || \ defined(CONFIG_SYS_FSL_DDR4) /* Chip select options. */ - if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { - switch (pdimm[0].n_ranks) { - case 1: - pdodt = single_S; - break; +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) + switch (pdimm[0].n_ranks) { + case 1: + pdodt = single_S; + break; + case 2: + pdodt = single_D; + break; + case 4: + pdodt = single_Q; + break; + } +#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + switch (pdimm[0].n_ranks) { +#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + case 4: + pdodt = single_Q; + if (pdimm[1].n_ranks) + printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n"); + break; +#endif + case 2: + switch (pdimm[1].n_ranks) { case 2: - pdodt = single_D; + pdodt = dual_DD; break; - case 4: - pdodt = single_Q; + case 1: + pdodt = dual_DS; break; - } - } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { - switch (pdimm[0].n_ranks) { -#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - case 4: - pdodt = single_Q; - if (pdimm[1].n_ranks) - printf("Error: Quad- and Dual-rank DIMMs " - "cannot be used together\n"); + case 0: + pdodt = dual_D0; break; -#endif + } + break; + case 1: + switch (pdimm[1].n_ranks) { case 2: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_DD; - break; - case 1: - pdodt = dual_DS; - break; - case 0: - pdodt = dual_D0; - break; - } + pdodt = dual_SD; break; case 1: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_SD; - break; - case 1: - pdodt = dual_SS; - break; - case 0: - pdodt = dual_S0; - break; - } + pdodt = dual_SS; break; case 0: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_0D; - break; - case 1: - pdodt = dual_0S; - break; - } + pdodt = dual_S0; break; } + break; + case 0: + switch (pdimm[1].n_ranks) { + case 2: + pdodt = dual_0D; + break; + case 1: + pdodt = dual_0S; + break; + } + break; } -#endif +#endif /* CONFIG_DIMM_SLOTS_PER_CTLR */ +#endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */ /* Pick chip-select local options. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { @@ -847,8 +846,7 @@ unsigned int populate_memctl_options(int all_dimms_registered, popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING; popts->memctl_interleaving = 1; debug("256 Byte interleaving\n"); - goto done; -#endif +#else /* * test null first. if CONFIG_HWCONFIG is not defined * hwconfig_arg_cmp returns non-zero @@ -930,8 +928,9 @@ unsigned int populate_memctl_options(int all_dimms_registered, popts->memctl_interleaving = 0; printf("hwconfig has unrecognized parameter for ctlr_intlv.\n"); } +#endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */ done: -#endif +#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */ if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) && (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { /* test null first. if CONFIG_HWCONFIG is not defined, @@ -1106,10 +1105,11 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo) case FSL_DDR_PAGE_INTERLEAVING: case FSL_DDR_BANK_INTERLEAVING: case FSL_DDR_SUPERBANK_INTERLEAVING: - if (3 == CONFIG_NUM_DDR_CONTROLLERS) +#if (3 == CONFIG_NUM_DDR_CONTROLLERS) k = 2; - else +#else k = CONFIG_NUM_DDR_CONTROLLERS; +#endif break; case FSL_DDR_3WAY_1KB_INTERLEAVING: case FSL_DDR_3WAY_4KB_INTERLEAVING: -- 1.7.9.5

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