March 2014 - U-Boot

[U-Boot] [PATCH 1/9] mmc: mmc header fix
by Mateusz Zalega 16 May '14

16 May '14

Structure definition used type block_dev_desc_t, defined in part.h, which wasn't included in mmc.h. It worked only in circumstances when common.h, or another header using part.h was incuded in implementation files. Change-Id: I3ccf56ce1e5334c32a7bc061e8bd9a5054ccb7f5 Signed-off-by: Mateusz Zalega <m.zalega(a)samsung.com> Cc: Minkyu Kang <mk7.kang(a)samsung.com> Cc: Kyungmin Park <kyungmin.park(a)samsung.com> --- include/mmc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/mmc.h b/include/mmc.h index cb558da..e490a06 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -12,6 +12,7 @@ #include <linux/list.h> #include <linux/compiler.h> +#include <part.h> #define SD_VERSION_SD 0x20000 #define SD_VERSION_3 (SD_VERSION_SD | 0x300) -- 1.8.2.1

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[U-Boot] [PATCH u-boot sunxi 0/4] sun4i support on top of Ian's patches
by Hans de Goede 10 May '14

10 May '14

Hi All, Here is a patch-set adding sun4i support on top of Ian's recent 1st attempt to get sun7i upstream patch-set. Note I've had to drop the raising of the cpu core clock, without matching axp209 changes this causes issues on sun4i. I've been thinking about how to best move forward with this patch-set, and I think it would be best to first complete the job of splitting up what we've in u-boot-sunxi now (at least most of it), keeping this based on v2014.01 so that we can easily diff. And then once we've everything split up, use the split-up patch-set as a base and start working on addressing any review comments there, which will break easy diffs against u-boot-sunxi, but at that point we no longer need them. We can even paralellize things. I can stick with Ian's v1 patchset for now, adding patches on top adding what is missing in piecemeal patches, and Ian can start working on making his initial series ready to go upstream. Ian, does that sound like a plan ? Regards, Hans

4 15

[U-Boot] [PATCH] sh: delete an unused source file
by Masahiro Yamada 08 May '14

08 May '14

Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> --- arch/sh/cpu/sh2/cache.c | 96 ------------------------------------------------- 1 file changed, 96 deletions(-) delete mode 100644 arch/sh/cpu/sh2/cache.c diff --git a/arch/sh/cpu/sh2/cache.c b/arch/sh/cpu/sh2/cache.c deleted file mode 100644 index 8093e98..0000000 --- a/arch/sh/cpu/sh2/cache.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2007 - * Yoshihiro Shimoda <shimoda.yoshihiro(a)renesas.com> - * - * Copyright (C) 2007, 2008 Nobobuhiro Iwamatsu <iwamatsu(a)nigauri.org> - * Copyright (C) 2008 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> - -/* - * Jump to P2 area. - * When handling TLB or caches, we need to do it from P2 area. - */ -#define jump_to_P2() \ -do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "mov.l 1f, %0\n\t" \ - "or %1, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy) \ - : "r" (0x20000000)); \ -} while (0) - -/* - * Back to P1 area. - */ -#define back_to_P1() \ -do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "nop;nop;nop;nop;nop;nop;nop\n\t" \ - "mov.l 1f, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy)); \ -} while (0) - -#define CACHE_VALID 1 -#define CACHE_UPDATED 2 - -static inline void cache_wback_all(void) -{ - unsigned long addr, data, i, j; - - jump_to_P2(); - for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) { - for (j = 0; j < CACHE_OC_NUM_WAYS; j++) { - addr = CACHE_OC_ADDRESS_ARRAY - | (j << CACHE_OC_WAY_SHIFT) - | (i << CACHE_OC_ENTRY_SHIFT); - data = inl(addr); - if (data & CACHE_UPDATED) { - data &= ~CACHE_UPDATED; - outl(data, addr); - } - } - } - back_to_P1(); -} - - -#define CACHE_ENABLE 0 -#define CACHE_DISABLE 1 - -int cache_control(unsigned int cmd) -{ - unsigned long ccr; - - jump_to_P2(); - ccr = inl(CCR); - - if (ccr & CCR_CACHE_ENABLE) - cache_wback_all(); - - if (cmd == CACHE_DISABLE) - outl(CCR_CACHE_STOP, CCR); - else - outl(CCR_CACHE_INIT, CCR); - back_to_P1(); - - return 0; -} -- 1.8.3.2

2 4

[U-Boot] [PATCH 0/3] samsung: misc: add new lcd menu options
by Przemyslaw Marczak 08 May '14

08 May '14

Changes: - small code refactor - add menu option: gpt restore - add menu option: env default Inha Song (1): samsung: misc: add env default option to lcd menu Przemyslaw Marczak (2): samsung: misc: check_keys(), key_pressed() - remove type static. samsung: misc: add gpt restore option to lcd menu board/samsung/common/misc.c | 60 +++++++++++++++++++++---------------------- include/samsung/misc.h | 6 +++++ 2 files changed, 36 insertions(+), 30 deletions(-) -- 1.7.9.5

4 39

[U-Boot] [PATCH] at91: video: atmel_hlcdfb.c: fix bad timing configuration
by Josh Wu 05 May '14

05 May '14

The right correspondance between LCD margins and LCD timings is: * upper margin -> vertical back porch * lower margin -> vertical front porch * left margin -> horizontal back porch * right margin -> horizontal front porch Signed-off-by: Josh Wu <josh.wu(a)atmel.com> --- drivers/video/atmel_hlcdfb.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index fc95897..e5d287d 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -144,12 +144,12 @@ void lcd_ctrl_init(void *lcdbase) value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1); lcdc_writel(&regs->lcdc_lcdcfg1, value); - value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin); - value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1); + value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin); + value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1); lcdc_writel(&regs->lcdc_lcdcfg2, value); - value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1); - value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1); + value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1); + value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1); lcdc_writel(&regs->lcdc_lcdcfg3, value); /* Display size */ -- 1.7.9.5

2 1

[U-Boot] [PATCH v4 0/6] PPC 85xx: Add support for QEMU's ppce500 PV machine
by Alexander Graf 28 Apr '14

28 Apr '14

In QEMU we implement a PV machine type called "ppce500". That board is able to run any e500+ FSL cores (e500v2, e500mc, e5500, e6500). It is heavily inspired by the MPC8544DS SoC and board combination, but implements only the bare minimum to make Linux happy enough to drive a virtual machine. This patch set implements support for this PV machine type in U-Boot, enabling users to run their virtual machines with netboot, u-boot payload binaries or other fun things they come up with. --- v1 -> v2: - Write device tree offset directly into global variable - use r4 rather than r2 for that - access fdt directly from in-memory copy - remove unneeded header includes - clean up pci enumeration - coding style fixes - populate and only use fdt_addr_r - remove unused exported functions - remove unused TLB0 entries - make TLB1 I/O maps non-executable - remove unused defines in board header - make -kernel boot variables more clear - remove TLB0 invalidation - use tlb1.14 for temporary as=1 map - use CONFIG_SYS_MPC85XX_NO_RESETVEC - store fdt pointer in gd through cpu_init_early_f() - replace fixup_tlb1() with dynamic TLB creation hook - find CCSRBAR from device tree - find PCI controllers from device tree - find CPU speed from device tree v2 -> v3: - new patch: fdt_support: split fdt_getprop_u32_default - new patch: fdt_support: Add helper function to read "ranges" property - new patch: PPC: 85xx: Remove IVOR reset - removed patch: PPC 85xx: Detect e500v2 / e500mc during runtime - merge dt patches into machine patch - Document and rename CONFIG_SYS_USE_DYNAMIC_TLBS - remove CONFIG_DDR_SPD - Reduce PCI message to only base address - Map AS=1 fdt behind CCSRBAR - Use CONFIG_SYS_CCSR_DO_NOT_RELOCATE - remove unnecessary ccsr map - s/cell size/cell count/ - add temporary map define - use fdt_get_base_address() to find region - use new APIs - remove myfdt helpers v3 -> v4: - tlb_map_range: return unmapped size - tlb_map_range: take ram/io parameter as enum rather than bool - use new tlb map syntax - check that tlb map mapped everything - always save/restore r3 for cpu_init_early_f - remove CONFIG_DYNAMIC_CCSRBAR - make init_tlbs weak and remove all init_tlbs_dynamic() cruft - always map fdt to fixed virtual address - fold together AS=1 fdt map functions - use tlb_map_range for CCSR map - search for PCI based on device type rather than compatible - remove unnecessary cast - call get_linear_ram_size directly - override get_tbclk with timebase-frequency fetching code Alexander Graf (6): fdt_support: split fdt_getprop_u32_default fdt_support: Add helper function to read "ranges" property PPC: 85xx: Remove IVOR reset PPC: 85xx: Generalize DDR TLB mapping function PPC 85xx: Add ELF entry point PPC 85xx: Add qemu-ppce500 machine arch/powerpc/cpu/mpc85xx/Makefile | 2 + arch/powerpc/cpu/mpc85xx/cpu.c | 4 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 4 - arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 8 +- arch/powerpc/cpu/mpc85xx/fixed_ivor.S | 63 ----- arch/powerpc/cpu/mpc85xx/release.S | 3 - arch/powerpc/cpu/mpc85xx/start.S | 17 +- arch/powerpc/cpu/mpc85xx/tlb.c | 48 ++-- arch/powerpc/cpu/mpc85xx/u-boot.lds | 1 + arch/powerpc/include/asm/config_mpc85xx.h | 4 + arch/powerpc/include/asm/mmu.h | 8 + board/freescale/qemu-ppce500/Makefile | 9 + board/freescale/qemu-ppce500/qemu-ppce500.c | 345 ++++++++++++++++++++++++++ boards.cfg | 1 + common/fdt_support.c | 132 +++++++++- include/configs/qemu-ppce500.h | 203 +++++++++++++++ include/fdt_support.h | 4 + nand_spl/board/freescale/mpc8536ds/Makefile | 4 - nand_spl/board/freescale/mpc8569mds/Makefile | 4 - nand_spl/board/freescale/mpc8572ds/Makefile | 4 - nand_spl/board/freescale/p1023rds/Makefile | 4 - nand_spl/board/freescale/p1_p2_rdb/Makefile | 4 - 22 files changed, 757 insertions(+), 119 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc85xx/fixed_ivor.S create mode 100644 board/freescale/qemu-ppce500/Makefile create mode 100644 board/freescale/qemu-ppce500/qemu-ppce500.c create mode 100644 include/configs/qemu-ppce500.h -- 1.7.10.4

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[U-Boot] [PATCH] Start the deprecation process for generic board
by Simon Glass 26 Apr '14

26 Apr '14

We should move forward to remove the old board init code. Add a prominent message to encourage maintainers to get started on this work. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- common/main.c | 6 ++ doc/README.generic-board | 189 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 195 insertions(+) create mode 100644 doc/README.generic-board diff --git a/common/main.c b/common/main.c index 8b6f274..e54f63b 100644 --- a/common/main.c +++ b/common/main.c @@ -427,6 +427,12 @@ void main_loop(void) bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop"); +#ifndef CONFIG_SYS_GENERIC_BOARD + puts("Warning: Your board does not use generic board. Please read\n"); + puts("doc/README.generic-board and take action. Boards not\n"); + puts("upgraded by the late 2014 may break or be removed.\n"); +#endif + #ifdef CONFIG_MODEM_SUPPORT debug("DEBUG: main_loop: do_mdm_init=%d\n", do_mdm_init); if (do_mdm_init) { diff --git a/doc/README.generic-board b/doc/README.generic-board new file mode 100644 index 0000000..50d3a26 --- /dev/null +++ b/doc/README.generic-board @@ -0,0 +1,189 @@ +# +# (C) Copyright 2014 Google, Inc +# Simon Glass <sjg(a)chromium.org> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +DEPRECATION NOTICE FOR arch/<arch>/lib/board.c + +For board maintainers: Please submit patches for boards you maintain before +July 2014, to make them use generic board. + +For architecture maintainers: Please submit patches to remove your +architecture-specific board.c file before October 2014. + + +Background +---------- + +U-Boot has tranditionally had a board.c file for each architecture. This has +introduced quite a lot of duplication, with each architecture tending to do +initialisation slightly differently. To address this, a new 'generic board +init' feature was introduced a year ago in March 2013 (further motivation is +provided in the cover letter below). + + +What has changed? +----------------- + +The main change is that the arch/<arch>/lib/board.c file is being removed in +favour of common/board_f.c (for pre-relocation init) and common/board_r.c +(for post-relocation init). + +Related to this, the global_data and bd_t structures now have a core set of +fields which are common to all architectures. Architecture-specific fields +have been moved to separate structures. + + +Supported Arcthitectures +------------------------ + +If you are unlucky then your architecture may not support generic board. +The following architectures are supported at the time of writing: + + arc + arm + powerpc + sandbox + x86 + +If your architecture is not supported, you need to adjust your +arch/<arch>/config.mk file to include: + + __HAVE_ARCH_GENERIC_BOARD := y + +and test it with a suitable board, as follows. + + +Adding Support for your Board +----------------------------- + +To enable generic board for your board, define CONFIG_SYS_GENERIC_BOARD in +your board config header file. + +Test that U-Boot still functions correctly on your board, and fix any +problems you find. Don't be surprised if there are no problems - generic +board has had a reasonable amount of testing with common boards. + + +DeadLine +-------- + +Please don't take this the wrong way - there is no intent to make your life +miserable, and we have the greatest respect and admiration for U-Boot users. +However, with any migration there has to be a period where the old way is +deprecated and removed. Every patch to the deprecated code introduces a +potential breakage in the new unused code. Therefore: + +Boards or architectures not converted over to general board by the +end of 2014 may be forcibly changed over (potentially causing run-time +breakage) or removed. + + + +Further Background +------------------ + +The full text of the original generic board series is reproduced below. + +--8<------------- + +This series creates a generic board.c implementation which contains +the essential functions of the major arch/xxx/lib/board.c files. + +What is the motivation for this change? + +1. There is a lot of repeated code in the board.c files. Any change to +things like setting up the baud rate requires a change in 10 separate +places. + +2. Since there are 10 separate files, adding a new feature which requires +initialisation is painful since it must be independently added in 10 +places. + +3. As time goes by the architectures naturely diverge since there is limited +pressure to compare features or even CONFIG options against simiilar things +in other board.c files. + +4. New architectures must implement all the features all over again, and +sometimes in subtley different ways. This places an unfair burden on getting +a new architecture fully functional and running with U-Boot. + +5. While it is a bit of a tricky change, I believe it is worthwhile and +achievable. There is no requirement that all code be common, only that +the code that is common should be located in common/board.c rather than +arch/xxx/lib/board.c. + +All the functions of board_init_f() and board_init_r() are broken into +separate function calls so that they can easily be included or excluded +for a particular architecture. It also makes it easier to adopt Graeme's +initcall proposal when it is ready. + +http://lists.denx.de/pipermail/u-boot/2012-January/114499.html + +This series removes the dependency on generic relocation. So relocation +happens as one big chunk and is still completely arch-specific. See the +relocation series for a proposed solution to this for ARM: + +http://lists.denx.de/pipermail/u-boot/2011-December/112928.html + +or Graeme's recent x86 series v2: + +http://lists.denx.de/pipermail/u-boot/2012-January/114467.html + +Instead of moving over a whole architecture, this series takes the approach +of simply enabling generic board support for an architecture. It is then up +to each board to opt in by defining CONFIG_SYS_GENERIC_BOARD in the board +config file. If this is not done, then the code will be generated as +before. This allows both sets of code to co-exist until we are comfortable +with the generic approach, and enough boards run. + +ARM is a relatively large board.c file and one which I can test, therefore +I think it is a good target for this series. On the other hand, x86 is +relatively small and simple, but different enough that it introduces a +few issues to be solved. So I have chosen both ARM and x86 for this series. +After a suggestion from Wolfgang I have added PPC also. This is the +largest and most feature-full board, so hopefully we have all bases +covered in this RFC. + +A generic global_data structure is also required. This might upset a few +people. Here is my basic reasoning: most fields are the same, all +architectures include and need it, most global_data.h files already have +#ifdefs to select fields for a particular SOC, so it is hard to +see why architecures are different in this area. We can perhaps add a +way to put architecture-specific fields into a separate header file, but +for now I have judged that to be counter-productive. + +Similarly we need a generic bd_info structure, since generic code will +be accessing it. I have done this in the same way as global_data and the +same comments apply. + +There was dicussion on the list about passing gd_t around as a parameter +to pre-relocation init functions. I think this makes sense, but it can +be done as a separate change, and this series does not require it. + +While this series needs to stand on its own (as with the link script +cleanup series and the generic relocation series) the goal is the +unification of the board init code. So I hope we can address issues with +this in mind, rather than focusing too narrowly on particular ARM, x86 or +PPC issues. + +I have run-tested ARM on Tegra Seaboard only. To try it out, define +CONFIG_SYS_GENERIC_BOARD in your board file and rebuild. Most likely on +x86 and PPC at least it will hang, but if you are lucky it will print +something first :-) + +I have run this though MAKEALL with CONFIG_SYS_GENERIC_BOARD on for all +ARM, PPC and x86 boards. There are a few failures due to errors in +the board config, which I have sent patches for. The main issue is +just the difference between __bss_end and __bss_end__. + +Note: the first group of commits are required for this series to build, +but could be separated out if required. I have included them here for +convenience. + +------------->8-- + +Simon Glass, sjg(a)chromium.org +March 2014 -- 1.9.1.423.g4596e3a

5 11

[U-Boot] [PATCH 0/3] mpc83xx: add support for the ids8313 board
by Heiko Schocher 25 Apr '14

25 Apr '14

add support for the ids8313 board. CPU: e300c3, MPC8313, Rev: 2.1 at 396 MHz, CSB: 132 MHz I2C: ready SPI: ready DRAM: 128 MiB (DDR2, 32-bit, ECC off, 264 MHz) Flash: 8 MiB NAND: 128 MiB Net: TSEC0, TSEC1 [PRIME] This board uses signed fit images, signed with sha256,rsa4096 algorithm. Following patches are needed for this board support: [U-Boot] common, ubi: add ubi check volumename command http://patchwork.ozlabs.org/patch/314116/ [U-Boot] common, itest: pass u-boot env variables to itest.s http://patchwork.ozlabs.org/patch/314118/ [U-Boot] i2c, bootcount: add support for bootcounter on i2c devices http://patchwork.ozlabs.org/patch/314117/ Patchserie FIT Images Enhancements [U-Boot,1/7] tools/image-host: fix sign-images bug http://patchwork.ozlabs.org/patch/314125/ [U-Boot,2/7] fdt: add "fdt sign" command http://patchwork.ozlabs.org/patch/314120/ [U-Boot,3/7] fit: add sha256 support http://patchwork.ozlabs.org/patch/314126/ [U-Boot,4/7] rsa: add sha256-rsa2048 algorithm http://patchwork.ozlabs.org/patch/314124/ [U-Boot,5/7] rsa: add sha256,rsa4096 algorithm http://patchwork.ozlabs.org/patch/314121/ [U-Boot,6/7] tools, fit: add fit_info host command http://patchwork.ozlabs.org/patch/314122/ [U-Boot,7/7] tools, fit_check_sign: verify a signed fit image http://patchwork.ozlabs.org/patch/314123/ Heiko Schocher (3): powerpc, ids8247: create vendor board dir ids mpc8313, bootcount: mpc8313 has no qe muram mpc83xx: add ids8313 support arch/powerpc/cpu/mpc83xx/cpu.c | 2 +- arch/powerpc/cpu/mpc83xx/fdt.c | 5 +- board/{ => ids}/ids8247/Makefile | 0 board/{ => ids}/ids8247/ids8247.c | 0 board/ids/ids8313/Makefile | 11 + board/ids/ids8313/ids8313.c | 208 ++++++++++++++ boards.cfg | 3 +- include/configs/ids8313.h | 587 ++++++++++++++++++++++++++++++++++++++ 8 files changed, 812 insertions(+), 4 deletions(-) rename board/{ => ids}/ids8247/Makefile (100%) rename board/{ => ids}/ids8247/ids8247.c (100%) create mode 100644 board/ids/ids8313/Makefile create mode 100644 board/ids/ids8313/ids8313.c create mode 100644 include/configs/ids8313.h Cc: Wolfgang Denk <wd(a)denx.de> Cc: Kim Phillips <kim.phillips(a)freescale.com> -- 1.8.3.1

3 6

[U-Boot] [PATCH V2] 4xx: add support for new PMC440 revision with cleanup
by Matthias Fuchs 24 Apr '14

24 Apr '14

This patch adds support for the new PMC440 hardware revision 1.4. The board now uses Micrel KSZ9031 phys. Add missing i2c initialization before reading bootstrap eeprom. Fix a couple of coding style issues. Make local functions static. Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- board/esd/pmc440/pmc440.c | 165 +++++++++++++++++++++++++++------------------ 1 file changed, 101 insertions(+), 64 deletions(-) V2: - combine two previous patches into a single one - put vsc8601 setup into a separate function - general cleanup - make local functions static - fix a couple of coding style issues diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index e86996c..062ae67 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -12,7 +12,6 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> #include <libfdt.h> #include <fdt_support.h> @@ -34,14 +33,14 @@ DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; extern void __ft_board_setup(void *blob, bd_t *bd); ulong flash_get_size(ulong base, int banknum); -int pci_is_66mhz(void); +static int pci_is_66mhz(void); int is_monarch(void); -int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt); +static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, + uchar *buffer, unsigned cnt); struct serial_device *default_serial_console(void) { @@ -58,23 +57,24 @@ struct serial_device *default_serial_console(void) if (((val & 0xf0000000) >> 29) != 7) return &eserial2_device; - ulong scratchreg = in_be32((void*)GPIO0_ISR3L); + ulong scratchreg = in_be32((void *)GPIO0_ISR3L); if (!(scratchreg & 0x80)) { /* mark scratchreg valid */ scratchreg = (scratchreg & 0xffffff00) | 0x80; + i2c_init_all(); + i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR, 0x10, buf, 4); if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) { scratchreg |= buf[2]; /* bringup delay for console */ - for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) { + for (delay = 0; delay < (1000 * (ulong)buf[3]); delay++) udelay(1000); - } } else scratchreg |= 0x01; - out_be32((void*)GPIO0_ISR3L, scratchreg); + out_be32((void *)GPIO0_ISR3L, scratchreg); } if (scratchreg & 0x01) @@ -93,10 +93,7 @@ int board_early_init_f(void) mtdcr(EBC0_CFGADDR, EBC0_CFG); mtdcr(EBC0_CFGDATA, 0xf8400000); - /* - * Setup the GPIO pins - * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file - */ + /* Setup the GPIO pins */ out_be32((void *)GPIO0_OR, 0x40000102); out_be32((void *)GPIO0_TCR, 0x4c90011f); out_be32((void *)GPIO0_OSRL, 0x28051400); @@ -259,7 +256,7 @@ int misc_init_r(void) * USB suff... */ if ((act == NULL || strcmp(act, "host") == 0) && - !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){ + !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) { /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); mfsdr(SDR0_USB2D0CR, usb2d0cr); @@ -326,16 +323,16 @@ int misc_init_r(void) mtsdr(SDR0_SRST1, 0x00000000); mtsdr(SDR0_SRST0, 0x00000000); - if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) { + if (!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) { /* enable power on USB socket */ - out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N); + out_be32((void *)GPIO1_OR, + in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N); } printf("USB: Host\n"); } else if ((strcmp(act, "dev") == 0) || - (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) { + (in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) { mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; @@ -414,30 +411,31 @@ int misc_init_r(void) #endif /* turn off POST LED */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N); + out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) & ~GPIO1_POST_N); /* turn on RUN LED */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N); + out_be32((void *)GPIO0_OR, + in_be32((void *)GPIO0_OR) & ~GPIO0_LED_RUN_N); return 0; } int is_monarch(void) { - if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH) + if (in_be32((void *)GPIO1_IR) & GPIO1_NONMONARCH) return 0; return 1; } -int pci_is_66mhz(void) +static int pci_is_66mhz(void) { - if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN) + if (in_be32((void *)GPIO1_IR) & GPIO1_M66EN) return 1; return 0; } -int board_revision(void) +static int board_revision(void) { - return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4); + return (int)((in_be32((void *)GPIO1_IR) & GPIO1_HWID_MASK) >> 4); } int checkboard(void) @@ -495,7 +493,7 @@ void pci_target_init(struct pci_controller *hose) out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Addr */ out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */ /* and enable region */ @@ -532,7 +530,8 @@ void pci_target_init(struct pci_controller *hose) if (is_monarch()) { /* BAR2: map FPGA registers behind system memory at 1GB */ - pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008); + pci_hose_write_config_dword(hose, 0, + PCI_BASE_ADDRESS_2, 0x40000008); } /* @@ -562,10 +561,10 @@ void pci_target_init(struct pci_controller *hose) CONFIG_SYS_PCI_CLASSCODE_NONMONARCH); /* PCI configuration done: release ERREADY */ - out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY); - out_be32((void*)GPIO1_TCR, - in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY); + out_be32((void *)GPIO1_OR, + in_be32((void *)GPIO1_OR) | GPIO1_PPC_EREADY); + out_be32((void *)GPIO1_TCR, + in_be32((void *)GPIO1_TCR) | GPIO1_PPC_EREADY); } else { /* Program the board's subsystem id/classcode */ pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID, @@ -595,14 +594,14 @@ void pci_master_init(struct pci_controller *hose) static void wait_for_pci_ready(void) { - if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) { + if (!(in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY)) { printf("PCI: Waiting for EREADY (CTRL-C to skip) ... "); while (1) { if (ctrlc()) { puts("abort\n"); break; } - if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) { + if (in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY) { printf("done\n"); break; } @@ -641,34 +640,73 @@ int is_pci_host(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) */ #ifdef CONFIG_RESET_PHY_R -void reset_phy(void) +static int pmc440_setup_vsc8601(char *devname, int phy_addr, + unsigned short behavior, unsigned short method) { - char *s; - unsigned short val_method, val_behavior; + /* adjust LED behavior */ + if (miiphy_write(devname, phy_addr, 0x1f, 0x0001) != 0) { + printf("Phy%d: register write access failed\n", phy_addr); + return -1; + } - /* special LED setup for NGCC/CANDES */ - if ((s = getenv("bd_type")) && - ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) { - val_method = 0x0e0a; - val_behavior = 0x0cf2; - } else { - /* PMC440 standard type */ - val_method = 0x0e10; - val_behavior = 0x0cf0; + miiphy_write(devname, phy_addr, 0x11, 0x0010); + miiphy_write(devname, phy_addr, 0x11, behavior); + miiphy_write(devname, phy_addr, 0x10, method); + miiphy_write(devname, phy_addr, 0x1f, 0x0000); + + return 0; +} + +static int pmc440_setup_ksz9031(char *devname, int phy_addr) +{ + unsigned short id1, id2; + + if (miiphy_read(devname, phy_addr, 2, &id1) || + miiphy_read(devname, phy_addr, 3, &id2)) { + printf("Phy%d: cannot read id\n", phy_addr); + return -1; } - if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) { - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010); - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior); - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method); - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000); + if ((id1 != 0x0022) || ((id2 & 0xfff0) != 0x1620)) { + printf("Phy%d: unexpected id\n", phy_addr); + return -1; } - if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) { - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010); - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior); - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method); - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000); + /* MMD 2.08: adjust tx_clk pad skew */ + miiphy_write(devname, phy_addr, 0x0d, 2); + miiphy_write(devname, phy_addr, 0x0e, 8); + miiphy_write(devname, phy_addr, 0x0d, 0x4002); + miiphy_write(devname, phy_addr, 0x0e, 0xf | (0x17 << 5)); + + return 0; +} + +void reset_phy(void) +{ + char *s; + unsigned short val_method, val_behavior; + + if (gd->board_type < 4) { + /* special LED setup for NGCC/CANDES */ + s = getenv("bd_type"); + if (s && ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) { + val_method = 0x0e0a; + val_behavior = 0x0cf2; + } else { + /* PMC440 standard type */ + val_method = 0x0e10; + val_behavior = 0x0cf0; + } + + /* boards up to rev. 1.3 use Vitesse VSC8601 phys */ + pmc440_setup_vsc8601("ppc_4xx_eth0", CONFIG_PHY_ADDR, + val_method, val_behavior); + pmc440_setup_vsc8601("ppc_4xx_eth1", CONFIG_PHY1_ADDR, + val_method, val_behavior); + } else { + /* rev. 1.4 uses a Micrel KSZ9031 */ + pmc440_setup_ksz9031("ppc_4xx_eth0", CONFIG_PHY_ADDR); + pmc440_setup_ksz9031("ppc_4xx_eth1", CONFIG_PHY1_ADDR); } } #endif @@ -729,7 +767,6 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, * We must write the address again when changing pages * because the address counter only increments within a page. */ - while (offset < end) { unsigned alen, len; unsigned maxlen; @@ -771,8 +808,8 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, return rcode; } -int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt) +static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, + uchar *buffer, unsigned cnt) { unsigned end = offset + cnt; unsigned blk_off; @@ -820,10 +857,10 @@ int board_usb_init(int index, enum usb_init_type init) int i; if ((act == NULL || strcmp(act, "host") == 0) && - !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) + !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) /* enable power on USB socket */ - out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N); + out_be32((void *)GPIO1_OR, + in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N); for (i=0; i<1000; i++) udelay(1000); @@ -834,7 +871,7 @@ int board_usb_init(int index, enum usb_init_type init) int usb_board_stop(void) { /* disable power on USB socket */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N); + out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) | GPIO1_USB_PWR_N); return 0; } @@ -858,8 +895,8 @@ void ft_board_setup(void *blob, bd_t *bd) rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status", "disabled", sizeof("disabled"), 1); if (rc) { - printf("Unable to update property status in PCI node, err=%s\n", - fdt_strerror(rc)); + printf("Unable to update property status in PCI node, "); + printf("err=%s\n", fdt_strerror(rc)); } } } -- 1.7.9.5

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[U-Boot] [PATCH 1/2 v2] mpc85xx: Add support for the supplement configuration unit register
by Tang Yuantian 24 Apr '14

24 Apr '14

From: Tang Yuantian <yuantian.tang(a)freescale.com> The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- v2: - fix checkpatch warning arch/powerpc/include/asm/immap_85xx.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 4b6f9d0..0f0f3d4 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -3151,4 +3151,26 @@ struct dcsr_dcfg_regs { #define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */ }; + +#define CONFIG_SYS_MPC85xx_SCFG \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET) +#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000 +/* The supplement configuration unit register */ +struct ccsr_scfg { + u32 dpslpcr; /* 0x000 Deep Sleep Control register */ + u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */ + u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */ + u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */ + u32 res1[4]; + u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */ + u32 res2; + u32 pixclkcr; /* 0x028 Pixel Clock Control register */ + u32 res3[245]; + u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */ + u32 emiiocr; /* 0x404 EMI MDIO Control Register */ + u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */ + u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */ + u32 res4[60]; + u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */ +}; #endif /*__IMMAP_85xx__*/ -- 1.8.5

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