March 2014 - U-Boot

[U-Boot] [PATCH 1/2] mini2440: remove board support
by Albert ARIBAUD 24 Sep '14

24 Sep '14

Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- board/friendlyarm/mini2440/Makefile | 8 -- board/friendlyarm/mini2440/mini2440.c | 118 ---------------------------- board/friendlyarm/mini2440/mini2440.h | 144 ---------------------------------- boards.cfg | 1 - doc/README.mini2440 | 28 ------- doc/README.scrapyard | 5 +- 6 files changed, 3 insertions(+), 301 deletions(-) delete mode 100644 board/friendlyarm/mini2440/Makefile delete mode 100644 board/friendlyarm/mini2440/mini2440.c delete mode 100644 board/friendlyarm/mini2440/mini2440.h delete mode 100644 doc/README.mini2440 diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile deleted file mode 100644 index f367107..0000000 --- a/board/friendlyarm/mini2440/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2012 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mini2440.o diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c deleted file mode 100644 index 59ed054..0000000 --- a/board/friendlyarm/mini2440/mini2440.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger(a)sysgo.de> - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> - * - * (C) Copyright 2009 - * Michel Pollet <buserror(a)gmail.com> - * - * (C) Copyright 2012 - * Gabriel Huau <contact(a)huau-gabriel.fr> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/s3c2440.h> -#include <asm/arch/iomux.h> -#include <asm/arch/gpio.h> -#include <asm/io.h> -#include <asm/gpio.h> -#include <netdev.h> -#include "mini2440.h" - -DECLARE_GLOBAL_DATA_PTR; - -static inline void pll_delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b" : "=r" (loops) : "0" (loops)); -} - -int board_early_init_f(void) -{ - struct s3c24x0_clock_power * const clk_power = - s3c24x0_get_base_clock_power(); - - /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */ - clk_power->clkdivn = CLKDIVN_VAL; - - /* configure UPLL */ - clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); - /* some delay between MPLL and UPLL */ - pll_delay(100); - - /* configure MPLL */ - clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); - - /* some delay between MPLL and UPLL */ - pll_delay(10000); - - return 0; -} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* IOMUX Port H : UART Configuration */ - gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 | - IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2; - - gpio_direction_output(GPH8, 0); - gpio_direction_output(GPH9, 0); - gpio_direction_output(GPH10, 0); - - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR; - - return 0; -} - -int dram_init(void) -{ - struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl(); - - /* - * Configuring bus width and timing - * Initialize clocks for each bank 0..5 - * Bank 3 and 4 are used for DM9000 - */ - writel(BANK_CONF, &memctl->bwscon); - writel(B0_CONF, &memctl->bankcon[0]); - writel(B1_CONF, &memctl->bankcon[1]); - writel(B2_CONF, &memctl->bankcon[2]); - writel(B3_CONF, &memctl->bankcon[3]); - writel(B4_CONF, &memctl->bankcon[4]); - writel(B5_CONF, &memctl->bankcon[5]); - - /* Bank 6 and 7 are used for DRAM */ - writel(SDRAM_64MB, &memctl->bankcon[6]); - writel(SDRAM_64MB, &memctl->bankcon[7]); - - writel(MEM_TIMING, &memctl->refresh); - writel(BANKSIZE_CONF, &memctl->banksize); - writel(B6_MRSR, &memctl->mrsrb6); - writel(B7_MRSR, &memctl->mrsrb7); - - gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_SIZE); - return 0; -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_DRIVER_DM9000 - return dm9000_initialize(bis); -#else - return 0; -#endif -} diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h deleted file mode 100644 index db386ea..0000000 --- a/board/friendlyarm/mini2440/mini2440.h +++ /dev/null @@ -1,144 +0,0 @@ -#ifndef __MINI2440_BOARD_CONF_H__ -#define __MINI2440_BOARD_CONF_H__ - -/* PLL Parameters */ -#define CLKDIVN_VAL 7 -#define M_MDIV 0x7f -#define M_PDIV 0x2 -#define M_SDIV 0x1 - -#define U_M_MDIV 0x38 -#define U_M_PDIV 0x2 -#define U_M_SDIV 0x2 - -/* BWSCON */ -#define DW8 0x0 -#define DW16 0x1 -#define DW32 0x2 -#define WAIT (0x1<<2) -#define UBLB (0x1<<3) - -#define B1_BWSCON (DW32) -#define B2_BWSCON (DW16) -#define B3_BWSCON (DW16 + WAIT + UBLB) -#define B4_BWSCON (DW16 + WAIT + UBLB) -#define B5_BWSCON (DW16) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -/* - * Bank Configuration - */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x0 /* 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 /* 0clk */ -#define B0_PMC 0x0 /* normal */ - -#define B1_Tacs 0x0 -#define B1_Tcos 0x0 -#define B1_Tacc 0x7 -#define B1_Tcoh 0x0 -#define B1_Tah 0x0 -#define B1_Tacp 0x0 -#define B1_PMC 0x0 - -#define B2_Tacs 0x0 -#define B2_Tcos 0x0 -#define B2_Tacc 0x7 -#define B2_Tcoh 0x0 -#define B2_Tah 0x0 -#define B2_Tacp 0x0 -#define B2_PMC 0x0 - -#define B3_Tacs 0x0 -#define B3_Tcos 0x3 /* 4clk */ -#define B3_Tacc 0x7 -#define B3_Tcoh 0x1 /* 1clk */ -#define B3_Tah 0x3 /* 4clk */ -#define B3_Tacp 0x0 -#define B3_PMC 0x0 - -#define B4_Tacs 0x0 -#define B4_Tcos 0x3 -#define B4_Tacc 0x7 -#define B4_Tcoh 0x1 -#define B4_Tah 0x3 -#define B4_Tacp 0x0 -#define B4_PMC 0x0 - -#define B5_Tacs 0x0 -#define B5_Tcos 0x0 -#define B5_Tacc 0x7 -#define B5_Tcoh 0x0 -#define B5_Tah 0x0 -#define B5_Tacp 0x0 -#define B5_PMC 0x0 - -/* - * SDRAM Configuration - */ -#define SDRAM_MT 0x3 /* SDRAM */ -#define SDRAM_Trcd 0x0 /* 2clk */ -#define SDRAM_SCAN_9 0x1 /* 9bit */ -#define SDRAM_SCAN_10 0x2 /* 10bit */ - -#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9)) - -/* - * Refresh Parameter - */ -#define REFEN 0x1 /* Refresh enable */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x1 /* 3clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x0 /* unused */ -#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */ - -/* - * MRSR Parameter - */ -#define BL 0x0 -#define BT 0x0 -#define CL 0x3 /* 3 clocks */ -#define TM 0x0 -#define WBL 0x0 - -/* - * BankSize Parameter - */ -#define BK76MAP 0x2 /* 128MB/128MB */ -#define SCLK_EN 0x1 /* SCLK active */ -#define SCKE_EN 0x1 /* SDRAM power down mode enable */ -#define BURST_EN 0x1 /* Burst enable */ - -/* - * Register values - */ -#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \ - (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \ - (B7_BWSCON<<28))) - -#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \ - (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC)) -#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \ - (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC)) -#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \ - (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC)) -#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \ - (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC)) -#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \ - (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC)) -#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \ - (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC)) - -#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \ - (Trc<<18) + (Tchr<<16) + REFCNT - -#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7) -#define B6_MRSR (CL<<4) -#define B7_MRSR (CL<<4) - -#endif diff --git a/boards.cfg b/boards.cfg index d177f82..af73934 100644 --- a/boards.cfg +++ b/boards.cfg @@ -69,7 +69,6 @@ Active arm arm920t imx - - Active arm arm920t imx - - scb9328 - Torsten Koschorrek <koschorrek(a)synertronixx.de> Active arm arm920t ks8695 - - cm4008 - Greg Ungerer <greg.ungerer(a)opengear.com> Active arm arm920t ks8695 - - cm41xx - - -Active arm arm920t s3c24x0 friendlyarm mini2440 mini2440 - Gabriel Huau <contact(a)huau-gabriel.fr> Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Müller <d.mueller(a)elsoft.ch> Active arm arm920t s3c24x0 samsung - smdk2410 - David Müller <d.mueller(a)elsoft.ch> Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij <linus.walleij(a)linaro.org> diff --git a/doc/README.mini2440 b/doc/README.mini2440 deleted file mode 100644 index 311ca52..0000000 --- a/doc/README.mini2440 +++ /dev/null @@ -1,28 +0,0 @@ -U-Boot for FriendlyARM Mini2440 (s3c2440) - -This file contains information for the port of U-Boot to FriendlyARM -mini2440 - -All information about the board can be found on : -http://www.friendlyarm.net/products/mini2440 - -To build u-boot : ./MAKEALL mini2440 - -Overview : --------- -FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440 -ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9 -systems. It's a low cost board. - -Boot Methods : ------------- -Mini2440 can boot from NOR or NAND. - -Build : ------ -./MAKEALL mini2440 - -or - -make mini2440_config -make diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 604de0c..be3e97e 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,8 +11,9 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -omap730p2 arm arm926ejs - 2013-11-11 -pn62 powerpc mpc824x - 2013-11-11 Wolfgang Grandegger <wg(a)grandegger.com> +mini2440 arm arm920t - 2014-01-13 Gabriel Huau <contact(a)huau-gabriel.fr> +omap730p2 arm arm926ejs 79c5c08d 2013-11-11 +pn62 powerpc mpc824x 649acfe1 2013-11-11 Wolfgang Grandegger <wg(a)grandegger.com> pdnb3 arm ixp 304db0b 2013-09-24 Stefan Roese <sr(a)denx.de> scpu arm ixp 304db0b 2013-09-24 Stefan Roese <sr(a)denx.de> omap1510inn arm arm925t 0610a16 2013-09-23 Kshitij Gupta <kshitij(a)ti.com> -- 1.8.3.2

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[U-Boot] [PATCH 1/5] edid: add function to convert edid to fb_videomode
by Christian Gmeiner 15 Sep '14

15 Sep '14

There may be some custom boards in the field which have an seperate eeprom chip to store edid informations in it. To make use of those edid information in the board code this patch add a function to convert edid to fb_videomode. Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- common/edid.c | 29 +++++++++++++++++++++++++++++ include/edid.h | 3 +++ 2 files changed, 32 insertions(+) diff --git a/common/edid.c b/common/edid.c index e66108f..8841c25 100644 --- a/common/edid.c +++ b/common/edid.c @@ -12,6 +12,7 @@ #include <common.h> #include <edid.h> +#include <linux/fb.h> #include <linux/ctype.h> #include <linux/string.h> @@ -288,3 +289,31 @@ void edid_print_info(struct edid1_info *edid_info) if (!have_timing) printf("\tNone\n"); } + +void edid_to_fb_videomode(struct edid1_info *edid, struct fb_videomode *mode) +{ + struct edid_monitor_descriptor *monitor = &edid->monitor_details.descriptor[0]; + unsigned char *bytes = (unsigned char *)monitor; + struct edid_detailed_timing *timing = (struct edid_detailed_timing *)monitor; + + uint32_t pixclock = EDID_DETAILED_TIMING_PIXEL_CLOCK(*timing); + uint32_t h_blanking = EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*timing); + uint32_t h_active = EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*timing); + uint32_t h_sync_offset = EDID_DETAILED_TIMING_HSYNC_OFFSET(*timing); + uint32_t h_sync_width = EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(*timing); + uint32_t v_blanking = EDID_DETAILED_TIMING_VERTICAL_BLANKING(*timing); + uint32_t v_active = EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*timing); + uint32_t v_sync_offset = EDID_DETAILED_TIMING_VSYNC_OFFSET(*timing); + uint32_t v_sync_width = EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(*timing); + + mode->name = "EDID"; + mode->pixclock = pixclock; + mode->yres = v_active; + mode->xres = h_active; + mode->left_margin = h_blanking - h_sync_offset - h_sync_width; + mode->right_margin = h_sync_offset; + mode->upper_margin = v_blanking - v_sync_offset - v_sync_width; + mode->lower_margin = v_sync_offset; + mode->hsync_len = h_sync_width; + mode->vsync_len = v_sync_width; +} diff --git a/include/edid.h b/include/edid.h index 480a773..4423062 100644 --- a/include/edid.h +++ b/include/edid.h @@ -233,6 +233,9 @@ struct edid1_info { */ void edid_print_info(struct edid1_info *edid_info); +struct fb_videomode; +void edid_to_fb_videomode(struct edid1_info *edid, struct fb_videomode *mode); + /** * Check the EDID info. * -- 1.7.10.4

6 30

[U-Boot] Uboot - verified boot - CONFIG_OF_SEPARATE
by Thilo Cestonaro 05 Sep '14

05 Sep '14

Hey! When I build my Uboot with the CONFIG_OF_SEPARATE set to gain access to the compiled dtb, Uboot can't find my concatenated dtb during the boot. After injecting the pulbic keys for the verified boot, I cat the u-boot.dtb behind the u-boot.bin. After that I mkimage the u-boot.img as usuall. I found, that if I change the offset where the fdt_blob is searched for by +300, it finds the dtb correctly. Like this: ------------------- #elif defined CONFIG_OF_SEPARATE /* FDT is at end of image */ - gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE); + gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE + 300); #endif ------------------- But I can't explain why this might be. The 300 isn't a random value! I calculated it via some debug output and it works reliably. But like it is with these workarounds, I don't like them! So I'm searching for an answer. Any ideas, why the offset is not _end_ofs + _TEXT_BASE, like it should be? Cheers, Thilo

2 1

[U-Boot] newbie questions regarding some config options.
by Christopher Harvey 22 Aug '14

22 Aug '14

As per the README file: Subscribe to u-boot mailing list; if (clueless) email("Hi, I am new to U-Boot, how do I get started?"); I'm messing around with uboot and QEMU (qemu-system-arm -M realview-pbx-a9 -kernel u-boot.bin), things are going pretty well in the sense that I'm not having too much trouble reading most of the code and creating a new board. I have some questions that I can't figure out by reading the code. What is the CONFIG_SYS_TEXT_BASE variable and how can I figure out what it should be? I randomly set it to 0x0...then tried to debug u-boot under qemu, but when stepping in the start.S file it was instantly clear that it wasn't really working because gdb said the code ran right though the _start: b reset instruction and qemu eventually crashed with the following output: qemu: fatal: Trying to execute code outside RAM or ROM at 0xfeb70cdc R00=00000000 R01=ffff0000 R02=00000000 R03=000108ac R04=ffff0000 R05=ffbedf70 R06=ffff0000 R07=00000010 R08=00001000 R09=ffff0000 R10=000108ac R11=00000000 R12=00001078 R13=ffbedf60 R14=00000960 R15=feb70cdc PSR=600001d3 -ZC- A svc32 Aborted Apart from that everything is pretty clear to me, but I want to make sure I'm getting this points right: Is the environment the set of variables that can be modified with setenv? How can I determine the "size of the environment"? Is it the number of characters including variable names? Also, is there anything special I need to do with gdb to get it to follow relocating code? thanks, -Chris

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[U-Boot] [PATCH v2 1/2] fsl/diu: ch7301 encoder split off from t1040qds/diu.c
by Dongsheng Wang 20 Aug '14

20 Aug '14

From: Wang Dongsheng <dongsheng.wang(a)freescale.com> The ch7301 encoder not only used in t1040qds platform, so we split it for t1042rdb and LSx platform. Signed-off-by: Wang Dongsheng <dongsheng.wang(a)freescale.com> --- V2: No Change diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index f6a0879..cd4b33b 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -34,6 +34,8 @@ ifndef CONFIG_RAMBOOT_PBL obj-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o endif +obj-$(CONFIG_FSL_DIU_CH7301) += diu_ch7301.o + obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o obj-$(CONFIG_MPC8548CDS) += cds_pci_ft.o obj-$(CONFIG_MPC8555CDS) += cds_pci_ft.o diff --git a/board/freescale/common/diu_ch7301.c b/board/freescale/common/diu_ch7301.c new file mode 100644 index 0000000..497fa1b --- /dev/null +++ b/board/freescale/common/diu_ch7301.c @@ -0,0 +1,136 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Authors: Priyanka Jain <Priyanka.Jain(a)freescale.com> + * Wang Dongsheng <dongsheng.wang(a)freescale.com> + * + * This file is copied and modified from the original t1040qds/diu.c. + * Encoder can be used in T104x and LSx Platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <stdio_dev.h> +#include <i2c.h> + +#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F +#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33 +#define I2C_DVI_PLL_DIVIDER_REG 0x34 +#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35 +#define I2C_DVI_PLL_FILTER_REG 0x36 +#define I2C_DVI_TEST_PATTERN_REG 0x48 +#define I2C_DVI_POWER_MGMT_REG 0x49 +#define I2C_DVI_LOCK_STATE_REG 0x4D +#define I2C_DVI_SYNC_POLARITY_REG 0x56 + +/* + * Set VSYNC/HSYNC to active high. This is polarity of sync signals + * from DIU->DVI. The DIU default is active igh, so DVI is set to + * active high. + */ +#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98 + +#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06 +#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26 +#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0 +#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08 +#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16 +#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60 + +/* Clear test pattern */ +#define I2C_DVI_TEST_PATTERN_VAL 0x18 +/* Exit Power-down mode */ +#define I2C_DVI_POWER_MGMT_VAL 0xC0 + +/* Monitor polarity is handled via DVI Sync Polarity Register */ +#define I2C_DVI_SYNC_POLARITY_VAL 0x00 + +/* Programming of HDMI Chrontel CH7301 connector */ +int diu_set_dvi_encoder(unsigned int pixclock) +{ + int ret; + u8 temp; + + temp = I2C_DVI_TEST_PATTERN_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select proper dvi test pattern\n"); + return ret; + } + temp = I2C_DVI_INPUT_DATA_FORMAT_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG, + 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi input data format\n"); + return ret; + } + + /* Set Sync polarity register */ + temp = I2C_DVI_SYNC_POLARITY_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select dvi syc polarity\n"); + return ret; + } + + /* Set PLL registers based on pixel clock rate*/ + if (pixclock > 65000000) { + temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll charge_cntl\n"); + return ret; + } + temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll divider\n"); + return ret; + } + temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll filter\n"); + return ret; + } + } else { + temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll charge_cntl\n"); + return ret; + } + temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll divider\n"); + return ret; + } + temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll filter\n"); + return ret; + } + } + + temp = I2C_DVI_POWER_MGMT_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select dvi power mgmt\n"); + return ret; + } + + udelay(500); + + return 0; +} diff --git a/board/freescale/common/diu_ch7301.h b/board/freescale/common/diu_ch7301.h new file mode 100644 index 0000000..8b6ead0 --- /dev/null +++ b/board/freescale/common/diu_ch7301.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DIU_HDMI_CH7301__ +#define __DIU_HDMI_CH7301__ + +/* Programming of HDMI Chrontel CH7301 connector */ +int diu_set_dvi_encoder(unsigned int pixclock); + +#endif diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c index ffd074b..0214224 100644 --- a/board/freescale/t1040qds/diu.c +++ b/board/freescale/t1040qds/diu.c @@ -13,42 +13,9 @@ #include <video_fb.h> #include <fsl_diu_fb.h> #include "../common/qixis.h" +#include "../common/diu_ch7301.h" #include "t1040qds.h" #include "t1040qds_qixis.h" -#include <i2c.h> - - -#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F -#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33 -#define I2C_DVI_PLL_DIVIDER_REG 0x34 -#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35 -#define I2C_DVI_PLL_FILTER_REG 0x36 -#define I2C_DVI_TEST_PATTERN_REG 0x48 -#define I2C_DVI_POWER_MGMT_REG 0x49 -#define I2C_DVI_LOCK_STATE_REG 0x4D -#define I2C_DVI_SYNC_POLARITY_REG 0x56 - -/* - * Set VSYNC/HSYNC to active high. This is polarity of sync signals - * from DIU->DVI. The DIU default is active igh, so DVI is set to - * active high. - */ -#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98 - -#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06 -#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26 -#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0 -#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08 -#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16 -#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60 - -/* Clear test pattern */ -#define I2C_DVI_TEST_PATTERN_VAL 0x18 -/* Exit Power-down mode */ -#define I2C_DVI_POWER_MGMT_VAL 0xC0 - -/* Monitor polarity is handled via DVI Sync Polarity Register */ -#define I2C_DVI_SYNC_POLARITY_VAL 0x00 /* * DIU Area Descriptor @@ -69,98 +36,6 @@ #define AD_COMP_1_SHIFT 4 #define AD_COMP_0_SHIFT 0 -/* Programming of HDMI Chrontel CH7301 connector */ -int diu_set_dvi_encoder(unsigned int pixclock) -{ - int ret; - u8 temp; - select_i2c_ch_pca9547(I2C_MUX_CH_DIU); - - temp = I2C_DVI_TEST_PATTERN_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1, - &temp, 1); - if (ret) { - puts("I2C: failed to select proper dvi test pattern\n"); - return ret; - } - temp = I2C_DVI_INPUT_DATA_FORMAT_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG, - 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi input data format\n"); - return ret; - } - - /* Set Sync polarity register */ - temp = I2C_DVI_SYNC_POLARITY_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1, - &temp, 1); - if (ret) { - puts("I2C: failed to select dvi syc polarity\n"); - return ret; - } - - /* Set PLL registers based on pixel clock rate*/ - if (pixclock > 65000000) { - temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll charge_cntl\n"); - return ret; - } - temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll divider\n"); - return ret; - } - temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll filter\n"); - return ret; - } - } else { - temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll charge_cntl\n"); - return ret; - } - temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll divider\n"); - return ret; - } - temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll filter\n"); - return ret; - } - } - - temp = I2C_DVI_POWER_MGMT_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1, - &temp, 1); - if (ret) { - puts("I2C: failed to select dvi power mgmt\n"); - return ret; - } - - udelay(500); - - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); - return 0; -} - void diu_set_pixel_clock(unsigned int pixclock) { unsigned long speed_ccb, temp; @@ -172,12 +47,19 @@ void diu_set_pixel_clock(unsigned int pixclock) pixval = speed_ccb / temp; /* Program HDMI encoder */ + /* Switch channel to DIU */ + select_i2c_ch_pca9547(I2C_MUX_CH_DIU); + + /* Set dispaly encoder */ ret = diu_set_dvi_encoder(temp); if (ret) { puts("Failed to set DVI encoder\n"); return; } + /* Switch channel to default */ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + /* Program pixel clock */ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, ((pixval << PXCK_BITS_START) & PXCK_MASK)); diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 993f9ae..f4c8547 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -404,6 +404,7 @@ unsigned long get_board_ddr_clk(void); /* Video */ #define CONFIG_FSL_DIU_FB #ifdef CONFIG_FSL_DIU_FB +#define CONFIG_FSL_DIU_CH7301 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) #define CONFIG_VIDEO #define CONFIG_CMD_BMP -- 1.8.5

2 3

[U-Boot] [PATCH] OpenRD: relocate environment to 640kB
by Sascha Silbe 14 Aug '14

14 Aug '14

U-Boot has become slightly larger than where the environment sector was previously located. Saving the environment would brick the device. Relocate the environment to where it is with the stock (i.e. Marvell USP) U-Boot version. That should give plenty of room for U-Boot to grow, including local customisations. This obviously breaks compatibility with previous mainline versions of U-Boot. Users will need to back up the environment before an update and restore it afterwards, or manually copy it to the new address before the update. Signed-off-by: Sascha Silbe <t-uboot(a)infra-silbe.de> --- include/configs/openrd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 53bafe1..ea7f9aa 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -90,8 +90,8 @@ * it has to be rounded to sector size */ #define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x60000 -#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ +#define CONFIG_ENV_ADDR 0xa0000 +#define CONFIG_ENV_OFFSET 0xa0000 /* env starts here */ /* * Default environment variables -- 1.8.2.1

4 20

[U-Boot] [PATCH] video: ipu_disp: wait for DP SF end irq when disabling sync BG flows
by Liu Ying 11 Aug '14

11 Aug '14

Instead of waiting for DC triple buffer to be cleared, this patch changes to wait for a relevant DP sync flow end interrupt to come when disabling sync BG flows. In this way, we align the implement to the freescale internal IPUv3 driver. After applying this patch, an uboot hang up issue at the arch_preboot_os() stage, where we disable a relevant ipu display channel, is not observed any more on some MX6DL platforms. Signed-off-by: Liu Ying <Ying.Liu(a)freescale.com> --- drivers/video/ipu.h | 8 ++++++++ drivers/video/ipu_disp.c | 27 ++++++++------------------- drivers/video/ipu_regs.h | 3 +++ 3 files changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/video/ipu.h b/drivers/video/ipu.h index 3d2741f..091b58f 100644 --- a/drivers/video/ipu.h +++ b/drivers/video/ipu.h @@ -176,6 +176,14 @@ typedef union { } ipu_channel_params_t; /* + * Enumeration of IPU interrupts. + */ +enum ipu_irq_line { + IPU_IRQ_DP_SF_END = 448 + 3, + IPU_IRQ_DC_FC_1 = 448 + 9, +}; + +/* * Bitfield of Display Interface signal polarities. */ typedef struct { diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c index cefd2dc..bf39a51 100644 --- a/drivers/video/ipu_disp.c +++ b/drivers/video/ipu_disp.c @@ -666,13 +666,16 @@ void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap) uint32_t csc; uint32_t dc_chan = 0; int timeout = 50; + int irq = 0; dc_swap = swap; if (channel == MEM_DC_SYNC) { dc_chan = 1; + irq = IPU_IRQ_DC_FC_1; } else if (channel == MEM_BG_SYNC) { dc_chan = 5; + irq = IPU_IRQ_DP_SF_END; } else if (channel == MEM_FG_SYNC) { /* Disable FG channel */ dc_chan = 5; @@ -723,25 +726,11 @@ void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap) reg ^= DC_WR_CH_CONF_PROG_DI_ID; __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); } else { - timeout = 50; - - /* Wait for DC triple buffer to empty */ - if (g_dc_di_assignment[dc_chan] == 0) - while ((__raw_readl(DC_STAT) & 0x00000002) - != 0x00000002) { - udelay(2000); - timeout -= 2; - if (timeout <= 0) - break; - } - else if (g_dc_di_assignment[dc_chan] == 1) - while ((__raw_readl(DC_STAT) & 0x00000020) - != 0x00000020) { - udelay(2000); - timeout -= 2; - if (timeout <= 0) - break; - } + /* Make sure that we leave at the irq starting edge */ + __raw_writel(IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq)); + do { + reg = __raw_readl(IPUIRQ_2_STATREG(irq)); + } while (!(reg & IPUIRQ_2_MASK(irq))); reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h index 21e9c99..c2c134a 100644 --- a/drivers/video/ipu_regs.h +++ b/drivers/video/ipu_regs.h @@ -313,9 +313,12 @@ struct ipu_dmfc { #define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \ IPU_STAT_REG_BASE)) +#define IPU_INT_STAT(n) (&IPU_STAT->int_stat[(n) - 1]) #define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32]) #define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32]) #define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32]) +#define IPUIRQ_2_STATREG(irq) (IPU_INT_STAT(1) + ((irq) / 32)) +#define IPUIRQ_2_MASK(irq) (1UL << ((irq) & 0x1F)) #define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1]) -- 1.7.9.5

2 1

[U-Boot] [PATCH] video: Add support for TI's AM335x LCD-Controller
by Hannes Petermaier 11 Aug '14

11 Aug '14

- Adds support for a minimal framebuffer driver of TI's AM335x SoC to be compatible with Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c) Signed-off-by: Hannes Petermaier <oe5hpm(a)oevsv.at> --- drivers/video/Makefile | 1 + drivers/video/am335x-fb.c | 169 +++++++++++++++++++++++++++++++++++++++++++++ drivers/video/am335x-fb.h | 67 ++++++++++++++++++ 3 files changed, 237 insertions(+) create mode 100644 drivers/video/am335x-fb.c create mode 100644 drivers/video/am335x-fb.h diff --git a/drivers/video/Makefile b/drivers/video/Makefile index a7f5469..ac3d6c7 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -39,3 +39,4 @@ obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o obj-$(CONFIG_VIDEO_TEGRA) += tegra.o obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o obj-$(CONFIG_FORMIKE) += formike.o +obj-$(CONFIG_AM335X_LCD) += am335x-fb.o diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c new file mode 100644 index 0000000..ab98941 --- /dev/null +++ b/drivers/video/am335x-fb.c @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2013 Hannes Petermaier <oe5hpm(a)oevsv.at> + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * minimal framebuffer driver for TI's AM335x SoC to be compatible with + * Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c) + * + * - supporting only 24bit RGB/TFT raster Mode (not using palette) + * - sets up LCD controller as in 'am335x_lcdpanel' struct given + * - starts output DMA from gd->fb_base buffer + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/arch/hardware.h> +#include <lcd.h> +#include "am335x-fb.h" + +#if !defined(LCD_CNTL_BASE) +#error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!" +#endif + + +/* LCD Control Register */ +#define LCD_CLK_DIVISOR(x) ((x) << 8) +#define LCD_RASTER_MODE 0x01 +/* LCD Clock Enable Register */ +#define LCD_CORECLKEN (0x01 << 0) +#define LCD_LIDDCLKEN (0x01 << 1) +#define LCD_DMACLKEN (0x01 << 2) +/* LCD DMA Control Register */ +#define LCD_DMA_BURST_SIZE(x) ((x) << 4) +#define LCD_DMA_BURST_1 0x0 +#define LCD_DMA_BURST_2 0x1 +#define LCD_DMA_BURST_4 0x2 +#define LCD_DMA_BURST_8 0x3 +#define LCD_DMA_BURST_16 0x4 +/* LCD Timing_0 Register */ +#define LCD_HBPLSB(x) ((((x)-1) & 0xFF) << 24) +#define LCD_HFPLSB(x) ((((x)-1) & 0xFF) << 16) +#define LCD_HSWLSB(x) ((((x)-1) & 0x3F) << 10) +#define LCD_HORLSB(x) (((((x) >> 4)-1) & 0x3F) << 4) +#define LCD_HORMSB(x) (((((x) >> 4)-1) & 0x40) >> 4) +/* LCD Timing_1 Register */ +#define LCD_VBP(x) ((x) << 24) +#define LCD_VFP(x) ((x) << 16) +#define LCD_VSW(x) (((x)-1) << 10) +#define LCD_VERLSB(x) (((x)-1) & 0x3FF) +/* LCD Timing_2 Register */ +#define LCD_HSWMSB(x) ((((x)-1) & 0x3C0) << 21) +#define LCD_VERMSB(x) ((((x)-1) & 0x400) << 16) +#define LCD_HBPMSB(x) ((((x)-1) & 0x300) >> 4) +#define LCD_HFPMSB(x) ((((x)-1) & 0x300) >> 8) +#define LCD_INVMASK(x) ((x) & 0x3F00000) +/* LCD Raster Ctrl Register */ +#define LCD_TFT_24BPP_MODE (1 << 25) +#define LCD_TFT_24BPP_UNPACK (1 << 26) +#define LCD_PALMODE_RAWDATA (0x10 << 20) +#define LCD_TFT_MODE (0x01 << 7) +#define LCD_RASTER_ENABLE (0x01 << 0) + + +/* Macro definitions */ +#define FBSIZE(x) ((x->hactive * x->vactive * x->bpp) >> 3) + +struct am335x_lcdhw { + unsigned int pid; /* 0x00 */ + unsigned int ctrl; /* 0x04 */ + unsigned int gap0; /* 0x08 */ + unsigned int lidd_ctrl; /* 0x0C */ + unsigned int lidd_cs0_conf; /* 0x10 */ + unsigned int lidd_cs0_addr; /* 0x14 */ + unsigned int lidd_cs0_data; /* 0x18 */ + unsigned int lidd_cs1_conf; /* 0x1C */ + unsigned int lidd_cs1_addr; /* 0x20 */ + unsigned int lidd_cs1_data; /* 0x24 */ + unsigned int raster_ctrl; /* 0x28 */ + unsigned int raster_timing0; /* 0x2C */ + unsigned int raster_timing1; /* 0x30 */ + unsigned int raster_timing2; /* 0x34 */ + unsigned int raster_subpanel; /* 0x38 */ + unsigned int raster_subpanel2; /* 0x3C */ + unsigned int lcddma_ctrl; /* 0x40 */ + unsigned int lcddma_fb0_base; /* 0x44 */ + unsigned int lcddma_fb0_ceiling; /* 0x48 */ + unsigned int lcddma_fb1_base; /* 0x4C */ + unsigned int lcddma_fb1_ceiling; /* 0x50 */ + unsigned int sysconfig; /* 0x54 */ + unsigned int irqstatus_raw; /* 0x58 */ + unsigned int irqstatus; /* 0x5C */ + unsigned int irqenable_set; /* 0x60 */ + unsigned int irqenable_clear; /* 0x64 */ + unsigned int gap1; /* 0x68 */ + unsigned int clkc_enable; /* 0x6C */ + unsigned int clkc_reset; /* 0x70 */ +}; + +static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE; +DECLARE_GLOBAL_DATA_PTR; + +int lcd_get_size(int *line_length) +{ + *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; + return *line_length * panel_info.vl_row + 0x20; +} + +int am335xfb_init(struct am335x_lcdpanel *panel) +{ + if (0 == gd->fb_base) { + printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n"); + return -1; + } + if (0 == panel) { + printf("ERROR: missing ptr to am335x_lcdpanel!\n"); + return -1; + } + + debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ", + panel->hactive, panel->vactive, panel->bpp, + panel->hfp, panel->hbp, panel->hsw); + debug("vfp=%d,vbp=%d,vsw=%d / clk-div=%d)\n", + panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk_div); + debug("using frambuffer at 0x%08x with size %d.\n", + (unsigned int)gd->fb_base, FBSIZE(panel)); + + /* palette default entry */ + memset((void *)gd->fb_base, 0, 0x20); + *(unsigned int *)gd->fb_base = 0x4000; + + lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN; + lcdhw->raster_ctrl = 0; + lcdhw->ctrl = LCD_CLK_DIVISOR(panel->pxl_clk_div) | LCD_RASTER_MODE; + lcdhw->lcddma_fb0_base = gd->fb_base; + lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel) + 0x20; + lcdhw->lcddma_fb1_base = gd->fb_base; + lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel) + 0x20; + lcdhw->lcddma_ctrl = LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); + + lcdhw->raster_timing0 = LCD_HORLSB(panel->hactive) | + LCD_HORMSB(panel->hactive) | + LCD_HFPLSB(panel->hfp) | + LCD_HBPLSB(panel->hbp) | + LCD_HSWLSB(panel->hsw); + lcdhw->raster_timing1 = LCD_VBP(panel->vbp) | + LCD_VFP(panel->vfp) | + LCD_VSW(panel->vsw) | + LCD_VERLSB(panel->vactive); + lcdhw->raster_timing2 = LCD_HSWMSB(panel->hsw) | + LCD_VERMSB(panel->vactive) | + LCD_INVMASK(panel->pol) | + LCD_HBPMSB(panel->hbp) | + LCD_HFPMSB(panel->hfp) | + 0x0000FF00; /* clk cycles for ac-bias */ + lcdhw->raster_ctrl = LCD_TFT_24BPP_MODE | + LCD_TFT_24BPP_UNPACK | + LCD_PALMODE_RAWDATA | + LCD_TFT_MODE | + LCD_RASTER_ENABLE; + + gd->fb_base += 0x20; /* point fb behind palette */ + + /* turn ON display through powercontrol function if accessible */ + if (0 != panel->panel_power_ctrl) { + mdelay(panel->pon_delay); + panel->panel_power_ctrl(1); + } + + return 0; +} diff --git a/drivers/video/am335x-fb.h b/drivers/video/am335x-fb.h new file mode 100644 index 0000000..8a0b131 --- /dev/null +++ b/drivers/video/am335x-fb.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2013 Hannes Petermaier <oe5hpm(a)oevsv.at> - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef AM335X_FB_H +#define AM335X_FB_H + +#define HSVS_CONTROL (0x01 << 25) /* + * 0 = lcd_lp and lcd_fp are driven on + * opposite edges of pixel clock than + * the lcd_pixel_o + * 1 = lcd_lp and lcd_fp are driven + * according to bit 24 Note that this + * bit MUST be set to '0' for Passive + * Matrix displays the edge timing is + * fixed + */ +#define HSVS_RISEFALL (0x01 << 24) /* + * 0 = lcd_lp and lcd_fp are driven on + * the rising edge of pixel clock (bit + * 25 must be set to 1) + * 1 = lcd_lp and lcd_fp are driven on + * the falling edge of pixel clock (bit + * 25 must be set to 1) + */ +#define DE_INVERT (0x01 << 23) /* + * 0 = DE is low-active + * 1 = DE is high-active + */ +#define PXCLK_INVERT (0x01 << 22) /* + * 0 = pix-clk is high-active + * 1 = pic-clk is low-active + */ +#define HSYNC_INVERT (0x01 << 21) /* + * 0 = HSYNC is active high + * 1 = HSYNC is avtive low + */ +#define VSYNC_INVERT (0x01 << 20) /* + * 0 = VSYNC is active high + * 1 = VSYNC is active low + */ + +struct am335x_lcdpanel { + unsigned int hactive; /* Horizontal active area */ + unsigned int vactive; /* Vertical active area */ + unsigned int bpp; /* bits per pixel */ + unsigned int hfp; /* Horizontal front porch */ + unsigned int hbp; /* Horizontal back porch */ + unsigned int hsw; /* Horizontal Sync Pulse Width */ + unsigned int vfp; /* Vertical front porch */ + unsigned int vbp; /* Vertical back porch */ + unsigned int vsw; /* Vertical Sync Pulse Width */ + unsigned int pxl_clk_div; /* Pixel clock divider*/ + unsigned int pol; /* polarity of sync, clock signals */ + unsigned int pon_delay; /* + * time in ms for turning on lcd after + * initializing lcd-controller + */ + void (*panel_power_ctrl)(int); /* fp for power on/off display */ +}; + +int am335xfb_init(struct am335x_lcdpanel *panel); + +#endif /* AM335X_FB_H */ -- 1.7.9.5

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[U-Boot] [PATCH] lcd: cleanup unused functions
by Hannes Petermaier 11 Aug '14

11 Aug '14

This patch removes following two functions: - lcd_getbgcolor(...) not used somewhere outside lcd.c, internally we use now the global variable lcd_color_bg (was return value of function before) - lcd_getfgcolor(...) not used in any place of u-boot Signed-off-by: Hannes Petermaier <oe5hpm(a)oevsv.at> --- common/lcd.c | 17 +---------------- include/lcd.h | 2 -- 2 files changed, 1 insertion(+), 18 deletions(-) diff --git a/common/lcd.c b/common/lcd.c index aa81522..3f73541 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -110,7 +110,6 @@ static int lcd_init(void *lcdbase); static void *lcd_logo(void); -static int lcd_getbgcolor(void); static void lcd_setfgcolor(int color); static void lcd_setbgcolor(int color); @@ -454,7 +453,7 @@ void lcd_clear(void) #else /* set framebuffer to background color */ memset((char *)lcd_base, - COLOR_MASK(lcd_getbgcolor()), + COLOR_MASK(lcd_color_bg), lcd_line_length * panel_info.vl_row); #endif /* Paint the logo and retrieve LCD base address */ @@ -563,20 +562,6 @@ static void lcd_setbgcolor(int color) lcd_color_bg = color; } -/*----------------------------------------------------------------------*/ - -int lcd_getfgcolor(void) -{ - return lcd_color_fg; -} - -/*----------------------------------------------------------------------*/ - -static int lcd_getbgcolor(void) -{ - return lcd_color_bg; -} - /************************************************************************/ /* ** Chipset depending Bitmap / Logo stuff... */ /************************************************************************/ diff --git a/include/lcd.h b/include/lcd.h index d06d6f1..d1cb6b1 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -26,8 +26,6 @@ void lcd_enable(void); void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue); void lcd_initcolregs(void); -int lcd_getfgcolor(void); - /* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */ struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp, void **alloc_addr); -- 1.7.10.4

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[U-Boot] [PATCH] Add support for 32-bit organized framebuffers
by Hannes Petermaier 11 Aug '14

11 Aug '14

- Adds support for 32-bit organized framebuffers to the LCD-framework. - cleaned up unused functions Signed-off-by: Hannes Petermaier <oe5hpm(a)oevsv.at> --- common/lcd.c | 52 +++++++++++++++++++++++++++++++++------------------- include/lcd.h | 19 ++++++++++++++++--- 2 files changed, 49 insertions(+), 22 deletions(-) diff --git a/common/lcd.c b/common/lcd.c index aa81522..e552340 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -94,7 +94,8 @@ #if LCD_BPP == LCD_MONOCHROME # define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \ (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7) -#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) +#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) || \ + (LCD_BPP == LCD_COLOR32) # define COLOR_MASK(c) (c) #else # error Unsupported LCD BPP. @@ -110,7 +111,6 @@ static int lcd_init(void *lcdbase); static void *lcd_logo(void); -static int lcd_getbgcolor(void); static void lcd_setfgcolor(int color); static void lcd_setbgcolor(int color); @@ -164,10 +164,20 @@ static void console_scrollup(void) CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows); /* Clear the last rows */ +#if (LCD_BPP != LCD_COLOR32) memset(lcd_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows, COLOR_MASK(lcd_color_bg), CONSOLE_ROW_SIZE * rows); - +#else + u32 *ppix = lcd_console_address + + CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows; + u32 i; + for (i = 0; + i < (CONSOLE_ROW_SIZE * rows) / NBYTES(panel_info.vl_bpix); + i++) { + *ppix++ = COLOR_MASK(lcd_color_bg); + } +#endif lcd_sync(); console_row -= rows; } @@ -285,13 +295,15 @@ static void lcd_drawchars(ushort x, ushort y, uchar *str, int count) ushort off = x * (1 << LCD_BPP) % 8; #endif - dest = (uchar *)(lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8); + dest = (uchar *)(lcd_base + y * lcd_line_length + x * NBITS(LCD_BPP)/8); for (row = 0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) { uchar *s = str; int i; #if LCD_BPP == LCD_COLOR16 ushort *d = (ushort *)dest; +#elif LCD_BPP == LCD_COLOR32 + u32 *d = (u32 *)dest; #else uchar *d = dest; #endif @@ -324,6 +336,12 @@ static void lcd_drawchars(ushort x, ushort y, uchar *str, int count) lcd_color_fg : lcd_color_bg; bits <<= 1; } +#elif LCD_BPP == LCD_COLOR32 + for (c = 0; c < 8; ++c) { + *d++ = (bits & 0x80) ? + lcd_color_fg : lcd_color_bg; + bits <<= 1; + } #endif } #if LCD_BPP == LCD_MONOCHROME @@ -453,9 +471,19 @@ void lcd_clear(void) test_pattern(); #else /* set framebuffer to background color */ +#if (LCD_BPP != LCD_COLOR32) memset((char *)lcd_base, - COLOR_MASK(lcd_getbgcolor()), + COLOR_MASK(lcd_color_bg), lcd_line_length * panel_info.vl_row); +#else + u32 *ppix = lcd_base; + u32 i; + for (i = 0; + i < (lcd_line_length * panel_info.vl_row)/NBYTES(panel_info.vl_bpix); + i++) { + *ppix++ = COLOR_MASK(lcd_color_bg); + } +#endif #endif /* Paint the logo and retrieve LCD base address */ debug("[LCD] Drawing the logo...\n"); @@ -563,20 +591,6 @@ static void lcd_setbgcolor(int color) lcd_color_bg = color; } -/*----------------------------------------------------------------------*/ - -int lcd_getfgcolor(void) -{ - return lcd_color_fg; -} - -/*----------------------------------------------------------------------*/ - -static int lcd_getbgcolor(void) -{ - return lcd_color_bg; -} - /************************************************************************/ /* ** Chipset depending Bitmap / Logo stuff... */ /************************************************************************/ diff --git a/include/lcd.h b/include/lcd.h index d06d6f1..df707f6 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -26,8 +26,6 @@ void lcd_enable(void); void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue); void lcd_initcolregs(void); -int lcd_getfgcolor(void); - /* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */ struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp, void **alloc_addr); @@ -334,7 +332,7 @@ int lcd_dt_simplefb_enable_existing_node(void *blob); #define LCD_COLOR4 2 #define LCD_COLOR8 3 #define LCD_COLOR16 4 - +#define LCD_COLOR32 5 /*----------------------------------------------------------------------*/ #if defined(CONFIG_LCD_INFO_BELOW_LOGO) # define LCD_INFO_X 0 @@ -385,6 +383,21 @@ int lcd_dt_simplefb_enable_existing_node(void *blob); # define CONSOLE_COLOR_GREY 14 # define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ +#elif LCD_BPP == LCD_COLOR32 +/* + * 32bpp color definitions + */ +# define CONSOLE_COLOR_RED 0x00ff0000 +# define CONSOLE_COLOR_GREEN 0x0000ff00 +# define CONSOLE_COLOR_YELLOW 0x00ffff00 +# define CONSOLE_COLOR_BLUE 0x000000ff +# define CONSOLE_COLOR_MAGENTA 0x00ff00ff +# define CONSOLE_COLOR_CYAN 0x0000ffff +# define CONSOLE_COLOR_GREY 0x00aaaaaa +# define CONSOLE_COLOR_BLACK 0x00000000 +# define CONSOLE_COLOR_WHITE 0x00ffffff /* Must remain last / highest*/ +# define NBYTES(bit_code) (NBITS(bit_code) >> 3) + #else /* -- 1.7.9.5

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