March 2014 - U-Boot

[U-Boot] [PATCH 2/7][v2] powerpc/mpc85xx: Avoid hardcoding in SPL linker script
by Prabhakar Kushwaha 06 Mar '14

06 Mar '14

SPL linker has fix location of bootpg and reset vector with respect to text base. It is not necessary to have fixed locations. Avoid such hardcoding. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Changes for v2: Sending as it is arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index acaa093..4fad68b 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -66,11 +66,16 @@ SECTIONS } :text = 0xffff #else #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ - .bootpg ADDR(.text) + 0x1000 : +#ifndef BOOT_PAGE_OFFSET +#define BOOT_PAGE_OFFSET 0x1000 +#endif + .bootpg ADDR(.text) + BOOT_PAGE_OFFSET : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) } +#ifndef RESET_VECTOR_OFFSET #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ +#endif #elif defined(CONFIG_FSL_ELBC) #define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ #else -- 1.7.9.5

1 0

[U-Boot] [PATCH 0/7][v2] powerpc: Add support 2 stage boot loader for corenet platform
by Prabhakar Kushwaha 06 Mar '14

06 Mar '14

Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Add support of 2 stage NAND boot loader in cornet platforms using SPL framework. In current secenrio size of u-boot can become >=512KB. So This patch set will be helpful for those SoC which has less internal SRAM(512KB). here, PBL initialise the internal SRAM and copy SPL(192K) in SRAM. SPL further initialise DDR using SPD and environment variables and copy u-boot(768 KB) from flash to DDR. Finally SPL transer control to u-boot for futher booting. SPL has following features: - Executes within 256K - No relocation required Run time view of SPL framework :- ----------------------------------------------- Area | Address | ----------------------------------------------- GD, BD | 0xFFFC0000 | ----------------------------------------------- ENV | 0xFFFC1000 | ----------------------------------------------- HEAP | 0xFFFC2800 | ----------------------------------------------- STACK | 0xFFFD0000 | ----------------------------------------------- U-boot SPL | 0xfffD0000 - 0xfffffffc (192K) | ----------------------------------------------- NAND Flash memory Map on B4860 and B4420QDS ------------------------------------------ Start End Definition Size 0x000000 0x0FFFFF u-boot 1MB 0x140000 0x15FFFF u-boot env 128KB 0x160000 0x17FFFF FMAN Ucode 128KB --- This patch set contains:- [PATCH 1/7] powerpc/mpc85xx: Move LAW_EN define outside of config [PATCH 2/7] powerpc/mpc85xx: Avoid hardcoding in SPL linker script [PATCH 3/7] powerpc:Add support of SPL non-relocation [PATCH 4/7] powerpc/mpc8xxx:Allow Parsing of LAW table in both SPL & non SPL [PATCH 5/7] driver/ifc: define nand_spl_load_image() for SPL [PATCH 6/7] Makefile: Add support of RAMBOOT_SPLPBL [PATCH 7/7] B4860QDS: Add support of 2 stage NAND boot loader -- 1.7.9.5

1 0

[U-Boot] [PATCH 3/3] arm: exynos: clock: Remove exynos4x12_set_mmc_clk function
by Beomho Seo 06 Mar '14

06 Mar '14

Remove exynos4x12_set_mmc_clk. Signed-off-by: Beomho Seo <beomho.seo(a)samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Minkyu Kang <mk7.kang(a)samsung.com> --- arch/arm/cpu/armv7/exynos/clock.c | 29 +---------------------------- 1 file changed, 1 insertion(+), 28 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 1fea4d6..2c2029a 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -893,30 +893,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) (div & 0xff) << ((dev_index << 4) + 8)); } -/* exynos4x12: set the mmc clock */ -static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div) -{ - struct exynos4x12_clock *clk = - (struct exynos4x12_clock *)samsung_get_base_clock(); - unsigned int addr; - - /* - * CLK_DIV_FSYS1 - * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24] - * CLK_DIV_FSYS2 - * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] - */ - if (dev_index < 2) { - addr = (unsigned int)&clk->div_fsys1; - } else { - addr = (unsigned int)&clk->div_fsys2; - dev_index -= 2; - } - - clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), - (div & 0xff) << ((dev_index << 4) + 8)); -} - /* exynos5: set the mmc clock */ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) { @@ -1612,10 +1588,7 @@ void set_mmc_clk(int dev_index, unsigned int div) else exynos5_set_mmc_clk(dev_index, div); } else { - if (proid_is_exynos4412()) - exynos4x12_set_mmc_clk(dev_index, div); - else - exynos4_set_mmc_clk(dev_index, div); + exynos4_set_mmc_clk(dev_index, div); } } -- 1.7.9.5 -- Best Regards,

2 2

[U-Boot] [PATCH 0/3] samsung: Add mmc controller to use dw mmc
by Beomho Seo 06 Mar '14

06 Mar '14

This patch set for use dw mmc controller. First, add dw mmc controller initialization. And then, change exynos4 mmc gpio configuration. Additionally, I have removed exynos4x12_set_mmc_clk function. Because samsung_get_base_clock() (exynos4x12/ exynos4) return same value. This patch set is tested on Trats2 board. Beomho Seo (3): board: samsung: trats2: Add DW MMC controller initialization arm: exynos: pinmux: Add sdmmc4 gpio confifuration arm: exynos: clock: Remove exynos4x12_set_mmc_clk function arch/arm/cpu/armv7/exynos/clock.c | 29 +---------------------------- arch/arm/cpu/armv7/exynos/pinmux.c | 20 +++++++++++++++----- board/samsung/trats2/trats2.c | 31 +++++++++++++++++++++---------- 3 files changed, 37 insertions(+), 43 deletions(-) -- Best Regards,

3 3

[U-Boot] [PATCH 1/3] board: samsung: trats2: Add DW MMC controller initialization
by Beomho Seo 06 Mar '14

06 Mar '14

Add DW MMC controller initialization. Selectively use DW MMC controller instead of SDHCI controller. Signed-off-by: Beomho Seo <beomho.seo(a)samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Minkyu Kang <mk7.kang(a)samsung.com> --- board/samsung/trats2/trats2.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index c17c24d..11bebb9 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -11,6 +11,7 @@ #include <asm/io.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> +#include <asm/arch/dwmmc.h> #include <asm/arch/power.h> #include <asm/arch/clk.h> #include <asm/arch/clock.h> @@ -280,18 +281,19 @@ int board_mmc_init(bd_t *bis) gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2(); - /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ + /* eMMC_EN: SD_0_CDn or SD_4_CDn: GPK0[2] Output High */ s5p_gpio_direction_output(&gpio2->k0, 2, 1); s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE); /* * eMMC GPIO: * SDR 8-bit@48MHz at MMC0 - * GPK0[0] SD_0_CLK(2) - * GPK0[1] SD_0_CMD(2) - * GPK0[2] SD_0_CDn -> Not used - * GPK0[3:6] SD_0_DATA[0:3](2) - * GPK1[3:6] SD_0_DATA[0:3](3) + * SDHCI DW-MMC + * GPK0[0] SD_0_CLK(2) SD_4_CLK(3) + * GPK0[1] SD_0_CMD(2) SD_4_CMD(3) + * GPK0[2] SD_0_CDn SD_4_CDn -> Not used + * GPK0[3:6] SD_0_DATA[0:3](2) SD_4_DATA[0:3](3) + * GPK1[3:6] SD_0_DATA[4:7](3) SD_4_DATA[4:7](4) * * DDR 4-bit@26MHz at MMC4 * GPK0[0] SD_4_CLK(3) @@ -301,17 +303,26 @@ int board_mmc_init(bd_t *bis) * GPK1[3:6] SD_4_DATA[4:7](4) */ - err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); - /* * MMC device init - * mmc0 : eMMC (8-bit buswidth) - * mmc2 : SD card (4-bit buswidth) + * mmc0 : eMMC, sdhci controller (8-bit buswidth) + * mmc2 : SD card, sdhci controller (4-bit buswidth) + * mmc4 : eMMC, dw-mmc controller (8-bit buswidth) */ + +#ifndef CONFIG_DWMMC + err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); if (err0) debug("SDMMC0 not configured\n"); else err0 = s5p_mmc_init(0, 8); +#else + err0 = exynos_pinmux_config(PERIPH_ID_SDMMC4, PINMUX_FLAG_8BIT_MODE); + if (err0) + debug("SDMMC4 not configured\n"); + else + err0 = exynos_dwmci_add_port(4, 0x12550000, 8, 0x00010000); +#endif /* T-flash detect */ s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); -- 1.7.9.5 -- Best Regards,

2 2

[U-Boot] [PATCH 2/3] arm: exynos: pinmux: Add sdmmc4 gpio configuration
by Beomho Seo 06 Mar '14

06 Mar '14

For use dwmmc controller, add SDMMC4 gpio configuration. Signed-off-by: Beomho Seo <beomho.seo(a)samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Minkyu Kang <mk7.kang(a)samsung.com> --- arch/arm/cpu/armv7/exynos/pinmux.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 645c497..a67664f 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -623,16 +623,25 @@ static int exynos4_mmc_config(int peripheral, int flags) struct exynos4_gpio_part2 *gpio2 = (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); struct s5p_gpio_bank *bank, *bank_ext; + unsigned int func, func_ext = 0; int i; switch (peripheral) { case PERIPH_ID_SDMMC0: bank = &gpio2->k0; bank_ext = &gpio2->k1; + func = GPIO_FUNC(0x2); + func_ext = GPIO_FUNC(0x3); break; case PERIPH_ID_SDMMC2: bank = &gpio2->k2; - bank_ext = &gpio2->k3; + func = GPIO_FUNC(0x2); + break; + case PERIPH_ID_SDMMC4: + bank = &gpio2->k0; + bank_ext = &gpio2->k1; + func = GPIO_FUNC(0x3); + func_ext = GPIO_FUNC(0x4); break; default: return -1; @@ -640,13 +649,14 @@ static int exynos4_mmc_config(int peripheral, int flags) for (i = 0; i < 7; i++) { if (i == 2) continue; - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(bank, i, func); s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); } - if (flags & PINMUX_FLAG_8BIT_MODE) { + if ((flags & PINMUX_FLAG_8BIT_MODE) && + ~(peripheral & PERIPH_ID_SDMMC2)) { for (i = 3; i < 7; i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(bank_ext, i, func_ext); s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE); s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); } @@ -710,10 +720,10 @@ static int exynos4_pinmux_config(int peripheral, int flags) break; case PERIPH_ID_SDMMC0: case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC4: return exynos4_mmc_config(peripheral, flags); case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC3: - case PERIPH_ID_SDMMC4: debug("SDMMC device %d not implemented\n", peripheral); return -1; default: -- 1.7.9.5 -- Best Regards,

3 2

[U-Boot] Secure booting using u-boot 2013
by JYOTI DUBEY 06 Mar '14

06 Mar '14

Hello, I am trying to perform secure booting on nitrogen 6X SOM using u-boot 2013. I tried to pad and sign the u-boot.imx image for authentication.But the size of both u-boot.imx as well as u-boot-signed-padded.imx remains same. Technically signed and padded image should have more size than normal .imx image. Can anyone inform where and what changes should I make in the source code of u-boot so that I can solve the problem? Thanks in Advance!

1 0

[U-Boot] OMAP3 ECC: Writing u-boot to NAND within u-boot
by Ash Charles 06 Mar '14

06 Mar '14

Hi, I'm working with an OMAP3503 processor with a NAND chip attached via the GPMC interface. The NAND chip required at least 4-bit ECC outside of the first block. Currently, I write the MLO and u-boot.img files from u-boot using 1-bit hardware ECC (i.e. nandecc hw) to NAND and boot the board. It seems like this ECC is not really appropriate for writing u-boot though---is this correct? If I understand correctly, I have three options: 1. Write u-boot to NAND from linux using BCH-8 which SPL can now understand 2. Write u-boot to NAND using the on-die ECC for my NAND chip 3. Write u-boot to NAND from u-boot using BCH8 (nandecc hw bch8)....this is my preference but when I try, I just see errors when trying to load u-boot from nand. Forgive my stupidity if this has been asked and answered a hundred times---I've been getting thoroughly confused with the changes to the ECC on OMAP3 in u-boot. --Ash

1 0

[U-Boot] U-Boot Support for Kontrons COMMe bIP6 Processors
by Nilssen, Sam 05 Mar '14

05 Mar '14

To all, Does anyone know if U-Boot supports Kontron's COMM-e bIP6 Processors ? I believe the core for these processors is Intel's I-series processors. Any info would be appreciated. Thanks, Sam Nilssen

1 0

[U-Boot] [PATCH 1/4] aes: Fix kerneldoc for aes.h
by Marek Vasut 05 Mar '14

05 Mar '14

Fix the function annotations in aes.h so they're compatible with kerneldoc. Signed-off-by: Marek Vasut <marex(a)denx.de> --- include/aes.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/include/aes.h b/include/aes.h index ea06308..c70eda6 100644 --- a/include/aes.h +++ b/include/aes.h @@ -25,29 +25,31 @@ enum { }; /** + * aes_expand_key() - Expand the AES key + * * Expand a key into a key schedule, which is then used for the other * operations. * - * \param key Key, of length AES_KEY_LENGTH bytes - * \param expkey Buffer to place expanded key, AES_EXPAND_KEY_LENGTH + * @key Key, of length AES_KEY_LENGTH bytes + * @expkey Buffer to place expanded key, AES_EXPAND_KEY_LENGTH */ void aes_expand_key(u8 *key, u8 *expkey); /** - * Encrypt a single block of data + * aes_encrypt() - Encrypt single block of data with AES 128 * - * in Input data - * expkey Expanded key to use for encryption (from aes_expand_key()) - * out Output data + * @in Input data + * @expkey Expanded key to use for encryption (from aes_expand_key()) + * @out Output data */ void aes_encrypt(u8 *in, u8 *expkey, u8 *out); /** - * Decrypt a single block of data + * aes_decrypt() - Decrypt single block of data with AES 128 * - * in Input data - * expkey Expanded key to use for decryption (from aes_expand_key()) - * out Output data + * @in Input data + * @expkey Expanded key to use for decryption (from aes_expand_key()) + * @out Output data */ void aes_decrypt(u8 *in, u8 *expkey, u8 *out); -- 1.8.5.3

2 6