March 2014 - U-Boot

[U-Boot] [PATCH v4 0/2] IMX6: Add Gateworks Ventana support
by Tim Harvey 07 Mar '14

07 Mar '14

Changes in v4: - fixed FP calculation - fixed invalid return type for read_eeprom() - use enum and defines for GSC HWMON registers/bits - removed unused CONFIG_SPI_FLASH_WINBOND_ERASESIZE - use defines for I2C bus numbers - added PCIE support - moved board-specific gpio iomux to board_init as imx6_pcie_toggle_reset needs it Changes in v3: - update README fixing typo and removing Freescale document link - use debug() instead of printf() - be more explicit with hwmon error output and use macro for min/max percent - use #defines for GSC slave address and registers - remove extern from function prototype - moved gpio config into structure for better readability - use enum for eeprom bit configs and array to map to fdt property alias - add SATA regardless of cpu type - add FIT support regardless of flash type - display PMIC and device id in misc_init_r() instead of pmic driver Changes in v2: - rebase on top of u-boot-imx - use switch..case for model specific init instead of strcmps - move checkboard to late init allowing i2c_setup to be moved to board_init() eeprom reading to be done after relocation, and move eeprom struct from data segment - move SPI/I2C init to board_init() - update README - remove unnecessary console overwrite function - fix multiline comment style and eliminate >80 char lines - eliminate unnecessary loop in board_mmc_init() - add missing copyright to clocks.cfg - avoid duplicating cfg files where no changes exist - added missing SPDX header to ventana_eeprom.h - use puts() instead of printf() for constant strings - remove messages regarding /dev/i2c-<n> - use get_ram_size() for determing ram_size - cleanup gpio configuration using tables for baseboard pinmux combinations - remove phy init errata as it doesn't pertain to use case (it is for 802.3az which IMX6 MAC does not support) - added pfuze100_pmic driver using PMIC API - moved GSC code (gsc command and i2c_read/i2c_write wrappers into own file) - allow user to quiet down some of the data displayed - remove display support for now - will revisit later - remove display of boot mode info - may revisit later - replace bitwise fields in eeprom structure with bit definitions Tim Harvey (2): power: add PFUZE100 PMIC driver ventana: Add Gateworks Ventana family support board/gateworks/gw_ventana/Makefile | 10 + board/gateworks/gw_ventana/README | 55 ++ board/gateworks/gw_ventana/clocks.cfg | 42 + board/gateworks/gw_ventana/gsc.c | 129 +++ board/gateworks/gw_ventana/gsc.h | 64 ++ board/gateworks/gw_ventana/gw_ventana.c | 1262 +++++++++++++++++++++++++++ board/gateworks/gw_ventana/gw_ventana.cfg | 42 + board/gateworks/gw_ventana/ventana_eeprom.h | 106 +++ boards.cfg | 5 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_pfuze100.c | 32 + include/configs/gw_ventana.h | 425 +++++++++ include/power/pfuze100_pmic.h | 96 ++ 13 files changed, 2269 insertions(+) create mode 100644 board/gateworks/gw_ventana/Makefile create mode 100644 board/gateworks/gw_ventana/README create mode 100644 board/gateworks/gw_ventana/clocks.cfg create mode 100644 board/gateworks/gw_ventana/gsc.c create mode 100644 board/gateworks/gw_ventana/gsc.h create mode 100644 board/gateworks/gw_ventana/gw_ventana.c create mode 100644 board/gateworks/gw_ventana/gw_ventana.cfg create mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h create mode 100644 drivers/power/pmic/pmic_pfuze100.c create mode 100644 include/configs/gw_ventana.h create mode 100644 include/power/pfuze100_pmic.h -- 1.8.3.2

4 13

[U-Boot] [PATCH][v3] board/t104xrdb: Add support of CPLD
by Prabhakar Kushwaha 07 Mar '14

07 Mar '14

T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features. This support of CPLD includes - files and register defintion - Commands to swtich alternate bank and default bank Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Changes for v2: - Updated the cpld command Changes for v3: - fix typo board/freescale/t104xrdb/Makefile | 1 + board/freescale/t104xrdb/cpld.c | 113 +++++++++++++++++++++++++++++++++++ board/freescale/t104xrdb/cpld.h | 40 +++++++++++++ board/freescale/t104xrdb/t104xrdb.c | 13 ++++ include/configs/T1040RDB.h | 8 +++ include/configs/T1042RDB_PI.h | 8 +++ 6 files changed, 183 insertions(+) create mode 100644 board/freescale/t104xrdb/cpld.c create mode 100644 board/freescale/t104xrdb/cpld.h diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile index e51fb7a..af38d9f 100644 --- a/board/freescale/t104xrdb/Makefile +++ b/board/freescale/t104xrdb/Makefile @@ -11,3 +11,4 @@ obj-y += eth.o obj-$(CONFIG_PCI) += pci.o obj-y += law.o obj-y += tlb.o +obj-y += cpld.o diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c new file mode 100644 index 0000000..661816c --- /dev/null +++ b/board/freescale/t104xrdb/cpld.c @@ -0,0 +1,113 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 reg = CPLD_READ(flash_ctl_status); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; + + CPLD_WRITE(flash_ctl_status, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 reg = CPLD_READ(flash_ctl_status); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; + + CPLD_WRITE(flash_ctl_status, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); + printf("reset_ctl[0] = 0x%02x\n", CPLD_READ(reset_ctl[0])); + printf("reset_ctl[1] = 0x%02x\n", CPLD_READ(reset_ctl[1])); + printf("int_status = 0x%02x\n", CPLD_READ(int_status)); + printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); + printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); + printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status)); + printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); + printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); + printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); + printf("boot_config[0] = 0x%02x\n", CPLD_READ(boot_config[0])); + printf("boot_config[1] = 0x%02x\n", CPLD_READ(boot_config[1])); + printf("boot_config[2] = 0x%02x\n", CPLD_READ(boot_config[2])); + putc('\n'); +} +#endif + +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - hard reset to default bank\n" + "cpld_cmd reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "cpld_cmd dump - display the CPLD registers\n" +#endif + ); diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h new file mode 100644 index 0000000..0da9a01 --- /dev/null +++ b/board/freescale/t104xrdb/cpld.h @@ -0,0 +1,40 @@ +/** + * Copyright 2013 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ + u8 hw_ver; /* 0x02 - Hardware Revision Register */ + u8 sw_ver; /* 0x03 - Software Revision register */ + u8 res0[12]; /* 0x04 - 0x0F - not used */ + u8 reset_ctl1; /* 0x10 - Reset control Register1 */ + u8 reset_ctl2; /* 0x11 - Reset control Register2 */ + u8 int_status; /* 0x12 - Interrupt status Register */ + u8 flash_ctl_status; /* 0x13 - Flash control and status register */ + u8 fan_ctl_status; /* 0x14 - Fan control and status register */ + u8 led_ctl_status; /* 0x15 - LED control and status register */ + u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ + u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ + u8 boot_override; /* 0x18 - Boot override register */ + u8 boot_config1; /* 0x19 - Boot config override register*/ + u8 boot_config2; /* 0x1A - Boot config override register*/ +} cpld_data_t; + + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value)\ + cpld_write(offsetof(struct cpld_data, reg), value) diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 6e29d64..b48133a 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -19,14 +19,27 @@ #include <fm_eth.h> #include "t104xrdb.h" +#include "cpld.h" DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; + u8 sw; printf("Board: %sRDB\n", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", + CPLD_READ(hw_ver), CPLD_READ(sw_ver)); + + sw = CPLD_READ(flash_ctl_status); + sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + + if (sw <= 7) + printf("vBank: %d\n", sw); + else + printf("Unsupported Bank=%x\n", sw); + return 0; } diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index fd010c0..596129c 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -196,6 +196,14 @@ #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} /* CPLD on IFC */ +#define CPLD_LBMAP_MASK 0x3F +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_OVERRIDE 0x40 +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ +#define CPLD_LBMAP_RESET 0xFF +#define CPLD_LBMAP_SHIFT 0x03 + #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) #define CONFIG_SYS_CSPR2_EXT (0xf) diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h index 6d07805..12a60f8 100644 --- a/include/configs/T1042RDB_PI.h +++ b/include/configs/T1042RDB_PI.h @@ -196,6 +196,14 @@ #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} /* CPLD on IFC */ +#define CPLD_LBMAP_MASK 0x3F +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_OVERRIDE 0x40 +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ +#define CPLD_LBMAP_RESET 0xFF +#define CPLD_LBMAP_SHIFT 0x03 + #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) #define CONFIG_SYS_CSPR2_EXT (0xf) -- 1.7.9.5

2 1

[U-Boot] [PATCH] board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config
by Prabhakar Kushwaha 07 Mar '14

07 Mar '14

With the default value of MDIO_CLK_DIV generatee MDC is too high and It is violating the IEEE specs much higher than 2.5Mhz. Although there is errata(A-006260) for EMI2(MDIO2), but same errata is been hit on EMI1(MDIO1). unfortunately this errata never hit on B4 rev1. So reduced the MDIO_CLK_DIV value. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- board/freescale/b4860qds/b4_pbi.cfg | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg index 57b726e..05377ba 100644 --- a/board/freescale/b4860qds/b4_pbi.cfg +++ b/board/freescale/b4860qds/b4_pbi.cfg @@ -22,6 +22,9 @@ 09110024 00100008 09110028 00100008 0911002c 00100008 +#slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 #Flush PBL data 09138000 00000000 091380c0 00000000 -- 1.7.9.5

2 1

[U-Boot] [PATCH v6] socfpga: Adding Scan Manager driver
by Chin Liang See 07 Mar '14

07 Mar '14

Scan Manager driver will be called to configure the IOCSR scan chain. This configuration will setup the IO buffer settings Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Wolfgang Denk <wd(a)denx.de> CC: Pavel Machek <pavel(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> --- Changes for v6 - Fixed various coding style issue Changes for v5 - Removal of additional blank line - Added comment for magic number Changes for v4 - avoid code duplication by add goto error - include underscore to variables name Changes for v3 - merge the handoff file and driver into single patch Changes for v2 - rebase with latest v2014.01-rc1 --- arch/arm/cpu/armv7/socfpga/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/scan_manager.c | 211 +++++++ arch/arm/cpu/armv7/socfpga/spl.c | 4 + arch/arm/include/asm/arch-socfpga/scan_manager.h | 96 +++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 1 + board/altera/socfpga/iocsr_config.c | 657 ++++++++++++++++++++ board/altera/socfpga/iocsr_config.h | 17 + include/configs/socfpga_cyclone5.h | 1 + 8 files changed, 988 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h create mode 100644 board/altera/socfpga/iocsr_config.c create mode 100644 board/altera/socfpga/iocsr_config.h diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 3e84a0c..4edc5d4 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -9,4 +9,4 @@ obj-y := lowlevel_init.o obj-y += misc.o timer.o reset_manager.o system_manager.o -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o +obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c b/arch/arm/cpu/armv7/socfpga/scan_manager.c new file mode 100644 index 0000000..a79b57b --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/freeze_controller.h> +#include <asm/arch/scan_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_scan_manager *scan_manager_base = + (void *)(SOCFPGA_SCANMGR_ADDRESS); +static const struct socfpga_freeze_controller *freeze_controller_base = + (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS); + +/* + * Function to check IO scan chain engine status and wait if the engine is + * is active. Poll the IO scan chain engine till maximum iteration reached. + */ +static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter) +{ + uint32_t scanmgr_status; + + scanmgr_status = readl(&scan_manager_base->stat); + + /* Poll the engine until the scan engine is inactive */ + while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) || + (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) { + max_iter--; + if (max_iter > 0) + scanmgr_status = readl(&scan_manager_base->stat); + else + return SCAN_MGR_STATUS_ACTIVE; + } + return SCAN_MGR_STATUS_IDLE; +} + +/* Program HPS IO Scan Chain */ +uint32_t scan_mgr_io_scan_chain_prg( + uint32_t io_scan_chain_id, + uint32_t io_scan_chain_len_in_bits, + const uint32_t *iocsr_scan_chain) +{ + uint16_t tdi_tdo_header; + uint32_t io_program_iter; + uint32_t io_scan_chain_data_residual; + uint32_t residual; + uint32_t i; + uint32_t index = 0; + + /* + * De-assert reinit if the IO scan chain is intended for HIO. In + * this, its the chain 3. + */ + if (io_scan_chain_id == 3) + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK); + + /* + * Check if the scan chain engine is inactive and the + * WFIFO is empty before enabling the IO scan chain + */ + if (scan_chain_engine_is_idle(SCAN_MAX_DELAY) != SCAN_MGR_STATUS_IDLE) + return 1; + + /* + * Enable IO Scan chain based on scan chain id + * Note: only one chain can be enabled at a time + */ + setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id); + + /* + * Calculate number of iteration needed for full 128-bit (4 x32-bits) + * bits shifting. Each TDI_TDO packet can shift in maximum 128-bits + */ + io_program_iter = io_scan_chain_len_in_bits >> + IO_SCAN_CHAIN_128BIT_SHIFT; + io_scan_chain_data_residual = io_scan_chain_len_in_bits & + IO_SCAN_CHAIN_128BIT_MASK; + + /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */ + tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | + (TDI_TDO_MAX_PAYLOAD << TDI_TDO_HEADER_SECOND_BYTE_SHIFT); + + /* Program IO scan chain in 128-bit iteration */ + for (i = 0; i < io_program_iter; i++) { + /* write TDI_TDO packet header to scan manager */ + writel(tdi_tdo_header, &scan_manager_base->fifo_double_byte); + + /* calculate array index. Multiply by 4 as write 4 x 32bits */ + index = i * 4; + + /* write 4 successive 32-bit IO scan chain data into WFIFO */ + writel(iocsr_scan_chain[index], + &scan_manager_base->fifo_quad_byte); + writel(iocsr_scan_chain[index + 1], + &scan_manager_base->fifo_quad_byte); + writel(iocsr_scan_chain[index + 2], + &scan_manager_base->fifo_quad_byte); + writel(iocsr_scan_chain[index + 3], + &scan_manager_base->fifo_quad_byte); + + /* + * Check if the scan chain engine has completed the + * IO scan chain data shifting + */ + if (SCAN_MGR_STATUS_IDLE != scan_chain_engine_is_idle( + SCAN_MAX_DELAY)) + goto error; + } + + /* Calculate array index for final TDI_TDO packet */ + index = io_program_iter * 4; + + /* Final TDI_TDO packet if any */ + if (io_scan_chain_data_residual) { + /* + * Calculate number of quad bytes FIFO write + * needed for the final TDI_TDO packet + */ + io_program_iter = io_scan_chain_data_residual >> + IO_SCAN_CHAIN_32BIT_SHIFT; + + /* + * Construct TDI_TDO packet for remaining IO + * scan chain (2 bytes) + */ + tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | + ((io_scan_chain_data_residual - 1) << + TDI_TDO_HEADER_SECOND_BYTE_SHIFT); + + /* + * Program the last part of IO scan chain write TDI_TDO packet + * header (2 bytes) to scan manager + */ + writel(tdi_tdo_header, &scan_manager_base->fifo_double_byte); + + for (i = 0; i < io_program_iter; i++) { + /* + * write remaining scan chain data into scan + * manager WFIFO with 4 bytes write + */ + writel(iocsr_scan_chain[index + i], + &scan_manager_base->fifo_quad_byte); + } + + index += io_program_iter; + residual = io_scan_chain_data_residual & + IO_SCAN_CHAIN_32BIT_MASK; + + if (IO_SCAN_CHAIN_PAYLOAD_24BIT < residual) { + /* + * write the last 4B scan chain data + * into scan manager WFIFO + */ + writel(iocsr_scan_chain[index], + &scan_manager_base->fifo_quad_byte); + } else { + /* + * write the remaining 1 - 3 bytes scan chain + * data into scan manager WFIFO byte by byte + * to prevent JTAG engine shifting unused data + * from the FIFO and mistaken the data as a + * valid command (even though unused bits are + * set to 0, but just to prevent hardware + * glitch) + */ + for (i = 0; i < residual; i += 8) { + writel(((iocsr_scan_chain[index] >> i) + & IO_SCAN_CHAIN_BYTE_MASK), + &scan_manager_base->fifo_single_byte); + } + } + + /* + * Check if the scan chain engine has completed the + * IO scan chain data shifting + */ + if (SCAN_MGR_STATUS_IDLE != scan_chain_engine_is_idle( + SCAN_MAX_DELAY)) + goto error; + } + + /* Disable IO Scan chain when configuration done*/ + clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id); + return 0; + +error: + /* Disable IO Scan chain when error detected */ + clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id); + return 1; +} + +int scan_mgr_configure_iocsr(void) +{ + int status = 0; + + /* configure the IOCSR through scan chain */ + status |= scan_mgr_io_scan_chain_prg(0, + CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH, iocsr_scan_chain0_table); + status |= scan_mgr_io_scan_chain_prg(1, + CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH, iocsr_scan_chain1_table); + status |= scan_mgr_io_scan_chain_prg(2, + CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH, iocsr_scan_chain2_table); + status |= scan_mgr_io_scan_chain_prg(3, + CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH, iocsr_scan_chain3_table); + return status; +} diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 36a00c3..8a49a1a 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -32,6 +32,10 @@ void spl_board_init(void) /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); + /* configure the IOCSR / IO buffer settings */ + if (scan_mgr_configure_iocsr()) + hang(); + /* configure the pin muxing through system manager */ sysmgr_pinmux_init(); #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ diff --git a/arch/arm/include/asm/arch-socfpga/scan_manager.h b/arch/arm/include/asm/arch-socfpga/scan_manager.h new file mode 100644 index 0000000..101355e --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/scan_manager.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SCAN_MANAGER_H_ +#define _SCAN_MANAGER_H_ + +struct socfpga_scan_manager { + u32 stat; + u32 en; + u32 padding[2]; + u32 fifo_single_byte; + u32 fifo_double_byte; + u32 fifo_quad_byte; +}; + +/* + * Shift count to get number of IO scan chain data in granularity + * of 128-bit ( N / 128 ) + */ +#define IO_SCAN_CHAIN_128BIT_SHIFT 7 + +/* + * Mask to get residual IO scan chain data in + * granularity of 128-bit ( N mod 128 ) + */ +#define IO_SCAN_CHAIN_128BIT_MASK 0x7F + +/* + * Shift count to get number of IO scan chain + * data in granularity of 32-bit ( N / 32 ) + */ +#define IO_SCAN_CHAIN_32BIT_SHIFT 5 + +/* + * Mask to get residual IO scan chain data in + * granularity of 32-bit ( N mod 32 ) + */ +#define IO_SCAN_CHAIN_32BIT_MASK 0x1F + +/* Byte mask */ +#define IO_SCAN_CHAIN_BYTE_MASK 0xFF + +/* 24-bits (3 bytes) IO scan chain payload definition */ +#define IO_SCAN_CHAIN_PAYLOAD_24BIT 24 + +/* + * Maximum length of TDI_TDO packet payload is 128 bits, + * represented by (length - 1) in TDI_TDO header + */ +#define TDI_TDO_MAX_PAYLOAD 127 + +/* TDI_TDO packet header for IO scan chain program */ +#define TDI_TDO_HEADER_FIRST_BYTE 0x80 + +/* Position of second command byte for TDI_TDO packet */ +#define TDI_TDO_HEADER_SECOND_BYTE_SHIFT 8 + +/* IO scan chain engine is idle */ +#define SCAN_MGR_STATUS_IDLE 0 + +/* IO scan chain engine is active */ +#define SCAN_MGR_STATUS_ACTIVE 1 + +/* + * Maximum polling loop to wait for IO scan chain engine + * becomes idle to prevent infinite loop + */ +#define SCAN_MAX_DELAY 100 + +#define SCANMGR_STAT_ACTIVE_GET(x) (((x) & 0x80000000) >> 31) +#define SCANMGR_STAT_WFIFOCNT_GET(x) (((x) & 0x70000000) >> 28) + +/* + * Program HPS IO Scan Chain + * io_scan_chain_id - IO scan chain ID + * io_scan_chain_len_in_bits - IO scan chain length in bits + * iocsr_scan_chain - IO scan chain table + */ +uint32_t scan_mgr_io_scan_chain_prg( + uint32_t io_scan_chain_id, + uint32_t io_scan_chain_len_in_bits, + const uint32_t *iocsr_scan_chain); + +extern const uint32_t iocsr_scan_chain0_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain1_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain2_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain3_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)]; + +#endif /* _SCAN_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index 50c4ebd..8d329cf 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -13,5 +13,6 @@ #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 #endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/board/altera/socfpga/iocsr_config.c b/board/altera/socfpga/iocsr_config.c new file mode 100644 index 0000000..b4b5ff8 --- /dev/null +++ b/board/altera/socfpga/iocsr_config.c @@ -0,0 +1,657 @@ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file is generated by Preloader Generator */ + +#include <iocsr_config.h> + +const unsigned long iocsr_scan_chain0_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00020080, + 0x08020000, + 0x08000000, + 0x00018020, + 0x00000000, + 0x00004000, + 0x00010040, + 0x04010000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x00020000, + 0x02008000, + 0x02000000, + 0x00000008, + 0x00002008, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { + 0x000C0300, + 0x10040000, + 0x100000C0, + 0x00000040, + 0x00010040, + 0x00008000, + 0x00080000, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x00010040, + 0x10000000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x06008020, + 0x02008000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x00004010, + 0x01004000, + 0x01000000, + 0x00003004, + 0x00001004, + 0x00000800, + 0x00000000, + 0x00000000, + 0x00800000, + 0x00000002, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00401000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00600802, + 0x00000000, + 0x80200000, + 0x80000600, + 0x00000200, + 0x00000100, + 0x00300401, + 0xC0100400, + 0x40100000, + 0x40000300, + 0x000C0100, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { + 0x80040100, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C010040, + 0x00008000, + 0x18020080, + 0x00000000, + 0x08000000, + 0x00040020, + 0x06018060, + 0x00004000, + 0x0C010040, + 0x04010000, + 0x00000030, + 0x00000000, + 0x03004010, + 0x00002000, + 0x06008020, + 0x02008000, + 0x02000018, + 0x00006008, + 0x01802008, + 0x00001000, + 0x03004010, + 0x01004000, + 0x0100000C, + 0x00003004, + 0x00C01004, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { + 0x2C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000070, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x906808A2, + 0xA2834024, + 0x05141A00, + 0x808A20D0, + 0x34024906, + 0x01A00A28, + 0xA20D0000, + 0x24906808, + 0x00A28340, + 0xD000001A, + 0x06808A20, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000070, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x906808A2, + 0xA2834024, + 0x05141A00, + 0x808A20D0, + 0x34024906, + 0x01A00040, + 0xA20D0002, + 0x24906808, + 0x00A28340, + 0xD005141A, + 0x06808A20, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x000001C1, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x04510680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x8341D348, + 0x821A0124, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x40120800, + 0x00000070, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x001A1A1A, + 0x085506A0, + 0x0000E1D4, + 0x045506A0, + 0x0000E1D4, + 0x085506A0, + 0x8000E1D4, + 0x00000200, + 0x00000004, + 0x04000000, + 0x00000009, + 0x00002410, + 0x00000040, + 0x41000000, + 0x00002082, + 0x00000350, + 0x000000DA, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x022A8350, + 0x000070EA, + 0x86000000, + 0x08000004, + 0x00000000, + 0x00482000, + 0x21800000, + 0x00101061, + 0x021541A8, + 0x00003875, + 0x011541A8, + 0x00003875, + 0x021541A8, + 0x20003875, + 0x00000080, + 0x00000001, + 0x41000000, + 0x00000002, + 0x00FF0904, + 0x00000000, + 0x90400000, + 0x00000820, + 0xC0000001, + 0x38D612AF, + 0x86F8E38E, + 0x0A0A78B4, + 0x000D020A, + 0x00006800, + 0x028A4320, + 0xEC2CB23D, + 0x8F5D1451, + 0xA47A88A2, + 0x0001A0E9, + 0x00410D00, + 0x40000068, + 0x3D000003, + 0x51EC2CB2, + 0xA28F5D14, + 0xE9A47A88, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000540, + 0x000003A8, + 0x08AA0D40, + 0x8001C3A8, + 0x0000007F, + 0x00000000, + 0x00004060, + 0xE1208000, + 0x0000001F, + 0x00004100, +}; diff --git a/board/altera/socfpga/iocsr_config.h b/board/altera/socfpga/iocsr_config.h new file mode 100644 index 0000000..490f109 --- /dev/null +++ b/board/altera/socfpga/iocsr_config.h @@ -0,0 +1,17 @@ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file is generated by Preloader Generator */ + +#ifndef _PRELOADER_IOCSR_CONFIG_H_ +#define _PRELOADER_IOCSR_CONFIG_H_ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) + +#endif /*_PRELOADER_IOCSR_CONFIG_H_*/ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 608578a..3d553f7 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -8,6 +8,7 @@ #include <asm/arch/socfpga_base_addrs.h> #include "../../board/altera/socfpga/pinmux_config.h" +#include "../../board/altera/socfpga/iocsr_config.h" /* * High level configuration -- 1.7.9.5

3 12

[U-Boot] pull request for u-boot-tegra/master into ARM/master
by Tom Warren 07 Mar '14

07 Mar '14

Albert, Please pull u-boot-tegra/master into ARM/master. Thanks! ./MAKEALL -s tegra AOK, checkpatch.pl is clean, and ./MAKEALL -a arm only shows failures that were already present in ARM/master. The following changes since commit cc07294bc704694ae33db75b25ac557e5917a83f: arm: am335x: DXR2: Reset SMSC LAN9303 switch via GPIO upon bootup (2014-03-04 09:42:07 -0500) are available in the git repository at: git://git.denx.de/u-boot-tegra master for you to fetch changes up to f940c72e16f7bdebaaed79b290c1bcb6dc015053: ARM: tegra: implement bootcmd_pxe (2014-03-05 16:59:08 -0700) ---------------------------------------------------------------- Stephen Warren (8): ARM: tegra: move CONFIG_TEGRAnn ARM: tegra: fix pmc_pwrgate_timer_mult register definition ARM: tegra: fix NV_PA_CSITE_BASE for Tegra124 ARM: tegra: simplify halt_avp() ARM: tegra: set CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS ARM: tegra: convert tegra to use distro defaults ARM: tegra: rework boot scripts ARM: tegra: implement bootcmd_pxe arch/arm/cpu/arm720t/tegra-common/cpu.c | 5 ++- arch/arm/cpu/arm720t/tegra124/cpu.c | 4 +-- arch/arm/include/asm/arch-tegra/pmc.h | 11 ++++++ arch/arm/include/asm/arch-tegra/tegra.h | 5 +++ arch/arm/include/asm/arch-tegra114/tegra.h | 2 ++ arch/arm/include/asm/arch-tegra124/tegra.h | 2 ++ arch/arm/include/asm/arch-tegra20/tegra.h | 2 ++ arch/arm/include/asm/arch-tegra30/tegra.h | 2 ++ include/configs/tegra-common-post.h | 57 ++++++++++++++++++++++++------ include/configs/tegra-common.h | 20 +++-------- include/configs/tegra114-common.h | 10 +++--- include/configs/tegra124-common.h | 6 +--- include/configs/tegra20-common.h | 10 +++--- include/configs/tegra30-common.h | 10 +++--- 14 files changed, 95 insertions(+), 51 deletions(-)

2 1

[U-Boot] Please pull u-boot-ti/master
by Tom Rini 07 Mar '14

07 Mar '14

Hey, The following changes since commit cc07294bc704694ae33db75b25ac557e5917a83f: arm: am335x: DXR2: Reset SMSC LAN9303 switch via GPIO upon bootup (2014-03-04 09:42:07 -0500) are available in the git repository at: git://git.denx.de/u-boot-ti.git master for you to fetch changes up to 4b75fd510076f2261c5e21b9b8cf75c9f01ded3c: board/BuR/common: fix phy addresses (2014-03-06 10:43:50 -0500) ---------------------------------------------------------------- Hannes Petermaier (1): board/BuR/common: fix phy addresses board/BuR/common/common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Thanks! -- Tom

3 4

[U-Boot] [PATCH] cosmetic: boards.cfg: mark dead email addresses
by Masahiro Yamada 07 Mar '14

07 Mar '14

When I Cced board maintainers, some of them resulted in bounce mails. I'd say at least 8 addresses (listed as Cc: below) are dead. After discussing with Detlev, I agreed to just mark them as dead address and keep them. Deleting the e-mail means loosing important information. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Yuli Barcohen <yuli(a)arabellasw.com> Cc: Travis Sawyer <travis.sawyer(a)sandburst.com> Cc: Yusdi Santoso <yusdi_santoso(a)adaptec.com> Cc: David Updegraff <dave(a)cray.com> Cc: Sangmoon Kim <dogoil(a)etinsys.com> Cc: Anton Vorontsov <avorontsov(a)ru.mvista.com> Cc: Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> Cc: Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> --- Detlev suggested to keep the email addresses even though they are dead. See this thread: http://u-boot.10912.n7.nabble.com/A-list-of-dead-email-addresses-of-board-m… boards.cfg | 110 ++++++++++++++++++++++++++++++------------------------------- 1 file changed, 55 insertions(+), 55 deletions(-) diff --git a/boards.cfg b/boards.cfg index d28e09b..b0e7f3f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -415,40 +415,40 @@ Active avr32 at32ap at32ap700x in-circuit - Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson <mpfj(a)mimc.co.uk> Active avr32 at32ap at32ap700x miromico - hammerhead - Julien May <julien.may(a)miromico.ch>:Alex Raimondi <alex.raimondi(a)miromico.ch> Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald <devel(a)bct-electronic.com> -Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <(dead address)u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <(dead address)u-boot-devel(a)blackfin.uclinux.org> Active blackfin blackfin - - - bf525-ucr2 - Haitao Zhang <hzhang(a)ucrobotics.com>:Chong Huang <chuang(a)ucrobotics.com> -Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf527-sdp - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf533-stamp - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <(dead address)u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <(dead address)u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <(dead address)u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf527-sdp - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <(dead address)u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <(dead address)u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf533-stamp - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <(dead address)u-boot-devel(a)blackfin.uclinux.org> Active blackfin blackfin - - - bf537-minotaur - Martin Strubel <strubel(a)section5.ch> -Active blackfin blackfin - - - bf537-pnav - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf537-pnav - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <(dead address)u-boot-devel(a)blackfin.uclinux.org> Active blackfin blackfin - - - bf537-srv1 - Martin Strubel <strubel(a)section5.ch> -Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <(dead address)u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <(dead address)u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <(dead address)u-boot-devel(a)blackfin.uclinux.org> Active blackfin blackfin - - - bf561-acvilon - Anton Shurpin <shurpin.aa(a)niistt.ru>:Valentin Yakovenkov <yakovenkov(a)niistt.ru> -Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> -Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <(dead address)u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <(dead address)u-boot-devel(a)blackfin.uclinux.org> Active blackfin blackfin - - - blackstamp - Wojtek Skulski <skulski(a)pas.rochester.edu>:Wojtek Skulski <info(a)skutek.com>:Benjamin Matthews <mben12(a)gmail.com> Active blackfin blackfin - - - blackvme - Wojtek Skulski <skulski(a)pas.rochester.edu>:Wojtek Skulski <info(a)skutek.com>:Benjamin Matthews <mben12(a)gmail.com> Active blackfin blackfin - - - br4 - Dimitar Penev <dpn(a)switchfin.org> -Active blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> -Active blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> -Active blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> -Active blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> -Active blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> -Active blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> +Active blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards <(dead address)bluetechnix(a)blackfin.uclinux.org> +Active blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards <(dead address)bluetechnix(a)blackfin.uclinux.org> +Active blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards <(dead address)bluetechnix(a)blackfin.uclinux.org> +Active blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards <(dead address)bluetechnix(a)blackfin.uclinux.org> +Active blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards <(dead address)bluetechnix(a)blackfin.uclinux.org> +Active blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards <(dead address)bluetechnix(a)blackfin.uclinux.org> Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) <info(a)ssv-embedded.de> Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule <support(a)i-syst.com> Active blackfin blackfin - - - ip04 - Brent Kandetzki <brentk(a)teleco.com> Active blackfin blackfin - - - pr1 - Dimitar Penev <dpn(a)switchfin.org> -Active blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> -Active blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> -Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> +Active blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards <(dead address)bluetechnix(a)blackfin.uclinux.org> +Active blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards <(dead address)bluetechnix(a)blackfin.uclinux.org> +Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi(a)gmail.com>:Blackfin Team <(dead address)u-boot-devel(a)blackfin.uclinux.org> Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> @@ -646,13 +646,13 @@ Active powerpc mpc824x - - cpc45 Active powerpc mpc824x - - cpc45 CPC45_ROMBOOT CPC45:BOOT_ROM Josef Wagner <Wagner(a)Microsys.de> Active powerpc mpc824x - - cu824 CU824 - Wolfgang Denk <wd(a)denx.de> Active powerpc mpc824x - - eXalion eXalion - Torsten Demke <torsten.demke(a)fci.com> -Active powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso(a)adaptec.com> +Active powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <(dead address)yusdi_santoso(a)adaptec.com> Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim(a)musenki.com> Active powerpc mpc824x - - mvblue MVBLUE - - Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd(a)denx.de> Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim(a)musenki.com> -Active powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil(a)etinsys.com> -Active powerpc mpc824x - etin - kvme080 - Sangmoon Kim <dogoil(a)etinsys.com> +Active powerpc mpc824x - etin - debris - Sangmoon Kim <(dead address)dogoil(a)etinsys.com> +Active powerpc mpc824x - etin - kvme080 - Sangmoon Kim <(dead address)dogoil(a)etinsys.com> Active powerpc mpc8260 - - - atc - Wolfgang Denk <wd(a)denx.de> Active powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno(a)delphintech.com> Active powerpc mpc8260 - - - ep82xxm - - @@ -665,11 +665,11 @@ Active powerpc mpc8260 - - cpu86 Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd(a)denx.de> Active powerpc mpc8260 - - cpu87 CPU87 - - Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM - -Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli(a)arabellasw.com> +Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <(dead address)yuli(a)arabellasw.com> Active powerpc mpc8260 - - ids8247 IDS8247 - Heiko Schocher <hs(a)denx.de> Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg(a)denx.de> -Active powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen <yuli(a)arabellasw.com> +Active powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen <(dead address)yuli(a)arabellasw.com> Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs(a)denx.de> Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs(a)denx.de> Active powerpc mpc8260 - - pm826 PM825 PM826:PCI,SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd(a)denx.de> @@ -684,25 +684,25 @@ Active powerpc mpc8260 - - pm828 Active powerpc mpc8260 - - pm828 PM828_PCI PM828:PCI - Active powerpc mpc8260 - - pm828 PM828_ROMBOOT PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - Active powerpc mpc8260 - - pm828 PM828_ROMBOOT_PCI PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - -Active powerpc mpc8260 - - rattler Rattler - Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli(a)arabellasw.com> +Active powerpc mpc8260 - - rattler Rattler - Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <(dead address)yuli(a)arabellasw.com> Active powerpc mpc8260 - freescale mpc8266ads MPC8266ADS - Rune Torgersen <runet(a)innovsys.com> Active powerpc mpc8260 - funkwerk vovpn-gw VoVPN-GW_66MHz VoVPN-GW:CLKIN_66MHz - Active powerpc mpc8260 - keymile km82xx mgcoge km82xx:MGCOGE Holger Brunck <holger.brunck(a)keymile.com> @@ -753,8 +753,8 @@ Active powerpc mpc83xx - freescale mpc8360emds Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_33 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu(a)freescale.com> Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_66 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu(a)freescale.com> Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu <daveliu(a)freescale.com> -Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov <avorontsov(a)ru.mvista.com> -Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov(a)ru.mvista.com> +Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov <(dead address)avorontsov(a)ru.mvista.com> +Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <(dead address)avorontsov(a)ru.mvista.com> Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS - Dave Liu <daveliu(a)freescale.com> Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu(a)freescale.com> Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015(a)freescale.com> @@ -1016,8 +1016,8 @@ Active powerpc mpc8xx - - - Active powerpc mpc8xx - - - spc1920 - - Active powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz(a)sinovee.com> Active powerpc mpc8xx - - - v37 - - -Active powerpc mpc8xx - - adder Adder - Yuli Barcohen <yuli(a)arabellasw.com> -Active powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen <yuli(a)arabellasw.com> +Active powerpc mpc8xx - - adder Adder - Yuli Barcohen <(dead address)yuli(a)arabellasw.com> +Active powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen <(dead address)yuli(a)arabellasw.com> Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen(a)csiro.au> Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark(a)esteem.com> Active powerpc mpc8xx - - fads MPC86xADS - - @@ -1146,7 +1146,7 @@ Active powerpc ppc4xx - avnet fx12mm Active powerpc ppc4xx - avnet fx12mm fx12mm_flash fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt(a)team-ctech.de> Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda(a)uam.es> Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval_flash v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda(a)uam.es> -Active powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff <dave(a)cray.com> +Active powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff <(dead address)dave(a)cray.com> Active powerpc ppc4xx - dave PPChameleonEVB CATcenter CATcenter:PPCHAMELEON_MODULE_MODEL=1 - Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_25 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 - Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_33 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 - @@ -1196,8 +1196,8 @@ Active powerpc ppc4xx - mpl mip405 Active powerpc ppc4xx - mpl pip405 PIP405 - Denis Peter <d.peter(a)mpl.ch> Active powerpc ppc4xx - prodrive - alpr - Stefan Roese <sr(a)denx.de> Active powerpc ppc4xx - prodrive - p3p440 - Stefan Roese <sr(a)denx.de> -Active powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer (travis.sawyer(a)sandburst.com> -Active powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer (travis.sawyer(a)sandburst.com> +Active powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer <(dead address)travis.sawyer(a)sandburst.com> +Active powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer <(dead address)travis.sawyer(a)sandburst.com> Active powerpc ppc4xx - xes - xpedite1000 - Peter Tyser <ptyser(a)xes-inc.com> Active powerpc ppc4xx - xilinx ml507 ml507 ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda(a)uam.es> Active powerpc ppc4xx - xilinx ml507 ml507_flash ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda(a)uam.es> -- 1.8.3.2

3 7

[U-Boot] U-boot changes
by JYOTI DUBEY 07 Mar '14

07 Mar '14

Hi, I am trying to perform secure booting on nitrogen6x SOM.After compiling the u-boot2013.08 source code I have obtained a u-boot.imx image with fsize 51c00.I tried to pad and sign this image for authentication which returns me a u-boot-signed-padded.imx. The problem is that the size of this new image is still the same i.e 51c00 which impiles that actually no change is happening to u-boot.imx. I tried making some chage u-boot.lds file to attach HAB data but it did not work.How can this problem be solved? Thanks in Advance!

1 0

[U-Boot] [PATCH] drivers/rtc: add support for MCP7941x RTCs
by Philip Paeps 06 Mar '14

06 Mar '14

The Microchip MCP7941x series of chips are very similar to Maxim's DS1307 but have some important differences: o I2C address 0x6f rather than 0x68 o The oscillator start bit logic is reversed o VBATEN bit to enable a power-fail time-stamp o SQWE is bit 6 of the control register, not bit 4 Adapt the DS1307 driver to support these chips. Signed-off-by: Philip Paeps <philip(a)paeps.cx> --- README | 1 + drivers/rtc/Makefile | 1 + drivers/rtc/ds1307.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 50 insertions(+), 1 deletion(-) diff --git a/README b/README index 216f0c7..830379d 100644 --- a/README +++ b/README @@ -1111,6 +1111,7 @@ The following options need to be configured: CONFIG_RTC_DS164x - use Dallas DS164x RTC CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC + CONFIG_RTC_MCP7941X - use Microchip MCP7941x RTC CONFIG_SYS_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337 CONFIG_SYS_RV3029_TCR - enable trickle charger on RV3029 RTC. diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 003d322..49451d9 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_RTC_DS1302) += ds1302.o obj-$(CONFIG_RTC_DS1306) += ds1306.o obj-$(CONFIG_RTC_DS1307) += ds1307.o obj-$(CONFIG_RTC_DS1338) += ds1307.o +obj-$(CONFIG_RTC_MCP7941X) += ds1307.o obj-$(CONFIG_RTC_DS1337) += ds1337.o obj-$(CONFIG_RTC_DS1374) += ds1374.o obj-$(CONFIG_RTC_DS1388) += ds1337.o diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index 1a2bad3..cbbdf9c 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -32,13 +32,21 @@ /*---------------------------------------------------------------------*/ #ifndef CONFIG_SYS_I2C_RTC_ADDR -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 +# ifdef CONFIG_RTC_MCP7941X +# define CONFIG_SYS_I2C_RTC_ADDR 0x6f +# else +# define CONFIG_SYS_I2C_RTC_ADDR 0x68 +# endif #endif #if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000) # error The DS1307 is specified only up to 100kHz! #endif +#if defined(CONFIG_RTC_MCP7941X) && (CONFIG_SYS_I2C_SPEED > 400000) +# error The MCP7941x is specified only up to 400kHz! +#endif + /* * RTC register addresses */ @@ -51,11 +59,20 @@ #define RTC_YR_REG_ADDR 0x06 #define RTC_CTL_REG_ADDR 0x07 +#ifdef CONFIG_RTC_MCP7941X +#define RTC_SEC_BIT_ST 0x80 /* Oscillator start (in reg 0) */ +#define RTC_DAY_BIT_VBATEN 0x08 /* VBAT enable (in register 3) */ +#else #define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */ +#endif #define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */ #define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */ +#ifdef CONFIG_RTC_MCP7941X +#define RTC_CTL_BIT_SQWE 0x40 /* Square Wave Enable */ +#else #define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */ +#endif #define RTC_CTL_BIT_OUT 0x80 /* Output Control */ static uchar rtc_read (uchar reg); @@ -81,6 +98,19 @@ int rtc_get (struct rtc_time *tmp) "hr: %02x min: %02x sec: %02x\n", year, mon, mday, wday, hour, min, sec); +#ifdef CONFIG_RTC_MCP7941X + if (!(wday & RTC_DAY_BIT_VBATEN)) { + printf ("### Warning: VBAT not enabled - enabling\n"); + rtc_write (RTC_DAY_REG_ADDR, + rtc_read (RTC_DAY_REG_ADDR) | RTC_DAY_BIT_VBATEN); + } + if (!(sec & RTC_SEC_BIT_ST)) { + printf ("### Warning: RTC oscillator has stopped\n"); + rtc_write (RTC_SEC_REG_ADDR, + rtc_read (RTC_SEC_REG_ADDR) | RTC_SEC_BIT_ST); + rel = -1; + } +#else if (sec & RTC_SEC_BIT_CH) { printf ("### Warning: RTC oscillator has stopped\n"); /* clear the CH flag */ @@ -88,6 +118,7 @@ int rtc_get (struct rtc_time *tmp) rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH); rel = -1; } +#endif tmp->tm_sec = bcd2bin (sec & 0x7F); tmp->tm_min = bcd2bin (min & 0x7F); @@ -121,11 +152,21 @@ int rtc_set (struct rtc_time *tmp) rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon)); +#ifdef CONFIG_RTC_MCP7941X + /* Don't clobber the VBATEN bit. */ + rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1) | RTC_DAY_BIT_VBATEN); +#else rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1)); +#endif rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); +#ifdef CONFIG_RTC_MCP7941X + /* Don't clobber the ST bit. */ + rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec) | RTC_SEC_BIT_ST); +#else rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); +#endif return 0; } @@ -142,7 +183,13 @@ void rtc_reset (void) { struct rtc_time tmp; +#ifdef CONFIG_RTC_MCP7941X + /* Set the oscillator start and VBATEN bits. */ + rtc_write (RTC_SEC_REG_ADDR, RTC_SEC_BIT_ST); + rtc_write (RTC_DAY_REG_ADDR, RTC_DAY_BIT_VBATEN); +#else rtc_write (RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */ +#endif rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS0); tmp.tm_year = 1970; -- 1.7.10.4

1 0

[U-Boot] Licensing Question on ARM Semihosting Code
by Darwin Rambo 06 Mar '14

06 Mar '14

Given the ARM header below, is this code possible to put into u-boot? For reference, I see this discussion below. http://lists.denx.de/pipermail/u-boot/2011-November/110884.html If this is not acceptable, presumably due to the "All rights reserved" and "Redistribution in binary form..." clauses below, we could try to find an alternative implementation that is GPL2.0+ licensed or rewrite the parts we need from scratch. Any suggestions you have would be most welcome. Thanks. Regards, Darwin Rambo > /* > * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. > * > * Redistribution and use in source and binary forms, with or without > * modification, are permitted provided that the following conditions are met: > * > * Redistributions of source code must retain the above copyright notice, this > * list of conditions and the following disclaimer. > * > * Redistributions in binary form must reproduce the above copyright notice, > * this list of conditions and the following disclaimer in the documentation > * and/or other materials provided with the distribution. > * > * Neither the name of ARM nor the names of its contributors may be used > * to endorse or promote products derived from this software without specific > * prior written permission. > * > * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" > * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE > * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE > * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE > * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR > * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF > * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS > * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN > * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) > * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE > * POSSIBILITY OF SUCH DAMAGE. > */

3 4