March 2014 - U-Boot

[U-Boot] [PATCH] kbuild/makefile: allow building host tools separately
by Alexey Brodkin 31 Mar '14

31 Mar '14

Sometimes it is required to build only host U-Boot tools without building U-Boot itself for either board. For example: * In "buildroot" "uboot-tools" could be built for host just to have an ability to create uImage. * Linux distributions ship "mkimage" utility as a separate substance. This patch allows building host U-Boot tools separately from U-Boot itself and what is more important user only needs to have host compiler (gcc). To build host tools just execute: ===== make tools HOST_TOOLS_ONLY=yes ===== Without this patch to generate tools user needs: 1. Configure any existing board with "make XXX_config" 2. Execute tools building but still cross-compiler will be invoked and if there's no proper cross-compiler in PATH compilation will fail. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Tom Rini <trini(a)ti.com> Cc: Simon Glass <sjg(a)chromium.org> --- Kbuild | 5 +++++ Makefile | 7 +++++++ 2 files changed, 12 insertions(+) diff --git a/Kbuild b/Kbuild index 1d89761..b5e348d 100644 --- a/Kbuild +++ b/Kbuild @@ -4,6 +4,9 @@ # 1) Generate generic-asm-offsets.h # 2) Generate asm-offsets.h +# Don't execute target below if building host tools only +ifneq ($(HOST_TOOLS_ONLY),yes) + ##### # 1) Generate generic-asm-offsets.h @@ -85,3 +88,5 @@ $(CPUDIR)/$(SOC)/asm-offsets.s: $(CPUDIR)/$(SOC)/asm-offsets.c FORCE $(obj)/$(offsets-file): $(CPUDIR)/$(SOC)/asm-offsets.s $(call cmd,offsets) + +endif diff --git a/Makefile b/Makefile index b795338..2fb8ea1 100644 --- a/Makefile +++ b/Makefile @@ -481,9 +481,12 @@ ifeq ($(dot-config),1) # load other configuration include $(srctree)/config.mk +# Don't check for config.mk presence if building host tools only +ifneq ($(HOST_TOOLS_ONLY),yes) ifeq ($(wildcard include/config.mk),) $(error "System not configured - see README") endif +endif # If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use # that (or fail if absent). Otherwise, search for a linker script in a @@ -994,10 +997,14 @@ ifeq ($(CONFIG_SYS_GENERIC_BOARD),y) @/bin/false endif endif + +# Don't check for ldscript presence if building host tools only +ifneq ($(HOST_TOOLS_ONLY),yes) ifeq ($(wildcard $(LDSCRIPT)),) @echo >&2 " Could not find linker script." @/bin/false endif +endif archprepare: prepare1 scripts_basic -- 1.8.5.3

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[U-Boot] [PATCH] mmc:eSDHC: Workaround for data timeout issue on Txxx SoC
by Haijun Zhang 31 Mar '14

31 Mar '14

1. The Data timeout counter value in eSDHC_SYSCTL register is not works as it should be, so add quirks to enable this workaround to fix it to the max value 0xE. 2. For eSDHC the Block Count per data trasmission should not exceed 0xFFFF, add this limitation to eSDHC host. 3. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround. Signed-off-by: Haijun Zhang <Haijun.Zhang(a)freescale.com> --- arch/powerpc/include/asm/config_mpc85xx.h | 5 +++++ drivers/mmc/fsl_esdhc.c | 5 ++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 9a20b97..df44451 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -734,6 +734,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 @@ -778,6 +780,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ISBC_VER 2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE + #elif defined(CONFIG_PPC_C29X) #define CONFIG_MAX_CPUS 1 diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 7b146a3..e888079 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -244,6 +244,9 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) timeout++; #endif +#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE + timeout = 0xE; +#endif esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); return 0; @@ -604,7 +607,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) mmc->f_min = 400000; mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000); - mmc->b_max = 0; + mmc->b_max = 0xFFFF; mmc_register(mmc); return 0; -- 1.8.5

3 2

[U-Boot] [PATCH] drivers: i2c: delete an unused source file
by Masahiro Yamada 31 Mar '14

31 Mar '14

Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Heiko Schocher <hs(a)denx.de> --- drivers/i2c/adi_i2c.c | 387 -------------------------------------------------- 1 file changed, 387 deletions(-) delete mode 100644 drivers/i2c/adi_i2c.c diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c deleted file mode 100644 index 675f417..0000000 --- a/drivers/i2c/adi_i2c.c +++ /dev/null @@ -1,387 +0,0 @@ -/* - * i2c.c - driver for ADI TWI/I2C - * - * Copyright (c) 2006-2013 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <i2c.h> - -#include <asm/clock.h> -#include <asm/twi.h> -#include <asm/io.h> - -/* Every register is 32bit aligned, but only 16bits in size */ -#define ureg(name) u16 name; u16 __pad_##name; -struct twi_regs { - ureg(clkdiv); - ureg(control); - ureg(slave_ctl); - ureg(slave_stat); - ureg(slave_addr); - ureg(master_ctl); - ureg(master_stat); - ureg(master_addr); - ureg(int_stat); - ureg(int_mask); - ureg(fifo_ctl); - ureg(fifo_stat); - char __pad[0x50]; - ureg(xmt_data8); - ureg(xmt_data16); - ureg(rcv_data8); - ureg(rcv_data16); -}; -#undef ureg - -/* U-Boot I2C framework allows only one active device at a time. */ -#ifdef TWI_CLKDIV -#define TWI0_CLKDIV TWI_CLKDIV -#endif -static struct twi_regs *twi = (void *)TWI0_CLKDIV; - -#ifdef DEBUG -# define dmemset(s, c, n) memset(s, c, n) -#else -# define dmemset(s, c, n) -#endif -#define debugi(fmt, args...) \ - debug( \ - "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \ - twi->master_stat, twi->fifo_stat, twi->int_stat, \ - __func__, __LINE__, ## args) - -#ifdef CONFIG_TWICLK_KHZ -# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED -#endif - -/* - * The way speed is changed into duty often results in integer truncation - * with 50% duty, so we'll force rounding up to the next duty by adding 1 - * to the max. In practice this will get us a speed of something like - * 385 KHz. The other limit is easy to handle as it is only 8 bits. - */ -#define I2C_SPEED_MAX 400000 -#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed)) -#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1) -#define I2C_DUTY_MIN 0xff /* 8 bit limited */ -#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED) -/* Note: duty is inverse of speed, so the comparisons below are correct */ -#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN -# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz" -#endif - -/* All transfers are described by this data structure */ -struct i2c_msg { - u8 flags; -#define I2C_M_COMBO 0x4 -#define I2C_M_STOP 0x2 -#define I2C_M_READ 0x1 - int len; /* msg length */ - u8 *buf; /* pointer to msg data */ - int alen; /* addr length */ - u8 *abuf; /* addr buffer */ -}; - -/* Allow msec timeout per ~byte transfer */ -#define I2C_TIMEOUT 10 - -/** - * wait_for_completion - manage the actual i2c transfer - * @msg: the i2c msg - */ -static int wait_for_completion(struct i2c_msg *msg) -{ - u16 int_stat, ctl; - ulong timebase = get_timer(0); - - do { - int_stat = readw(&twi->int_stat); - - if (int_stat & XMTSERV) { - debugi("processing XMTSERV"); - writew(XMTSERV, &twi->int_stat); - if (msg->alen) { - writew(*(msg->abuf++), &twi->xmt_data8); - --msg->alen; - } else if (!(msg->flags & I2C_M_COMBO) && msg->len) { - writew(*(msg->buf++), &twi->xmt_data8); - --msg->len; - } else { - ctl = readw(&twi->master_ctl); - if (msg->flags & I2C_M_COMBO) - writew(ctl | RSTART | MDIR, - &twi->master_ctl); - else - writew(ctl | STOP, &twi->master_ctl); - } - } - if (int_stat & RCVSERV) { - debugi("processing RCVSERV"); - writew(RCVSERV, &twi->int_stat); - if (msg->len) { - *(msg->buf++) = readw(&twi->rcv_data8); - --msg->len; - } else if (msg->flags & I2C_M_STOP) { - ctl = readw(&twi->master_ctl); - writew(ctl | STOP, &twi->master_ctl); - } - } - if (int_stat & MERR) { - debugi("processing MERR"); - writew(MERR, &twi->int_stat); - return msg->len; - } - if (int_stat & MCOMP) { - debugi("processing MCOMP"); - writew(MCOMP, &twi->int_stat); - if (msg->flags & I2C_M_COMBO && msg->len) { - ctl = readw(&twi->master_ctl); - ctl = (ctl & ~RSTART) | - (min(msg->len, 0xff) << 6) | MEN | MDIR; - writew(ctl, &twi->master_ctl); - } else - break; - } - - /* If we were able to do something, reset timeout */ - if (int_stat) - timebase = get_timer(0); - - } while (get_timer(timebase) < I2C_TIMEOUT); - - return msg->len; -} - -/** - * i2c_transfer - setup an i2c transfer - * @return: 0 if things worked, non-0 if things failed - * - * Here we just get the i2c stuff all prepped and ready, and then tail off - * into wait_for_completion() for all the bits to go. - */ -static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, - int len, u8 flags) -{ - int ret; - u16 ctl; - uchar addr_buffer[] = { - (addr >> 0), - (addr >> 8), - (addr >> 16), - }; - struct i2c_msg msg = { - .flags = flags | (len >= 0xff ? I2C_M_STOP : 0), - .buf = buffer, - .len = len, - .abuf = addr_buffer, - .alen = alen, - }; - - dmemset(buffer, 0xff, len); - debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i ", - chip, addr, alen, buffer[0], len); - debugi("flags=0x%02x[%s] ", flags, - (flags & I2C_M_READ ? "rd" : "wr")); - - /* wait for things to settle */ - while (readw(&twi->master_stat) & BUSBUSY) - if (ctrlc()) - return 1; - - /* Set Transmit device address */ - writew(chip, &twi->master_addr); - - /* Clear the FIFO before starting things */ - writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl); - writew(0, &twi->fifo_ctl); - - /* prime the pump */ - if (msg.alen) { - len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len; - debugi("first byte=0x%02x", *msg.abuf); - writew(*(msg.abuf++), &twi->xmt_data8); - --msg.alen; - } else if (!(msg.flags & I2C_M_READ) && msg.len) { - debugi("first byte=0x%02x", *msg.buf); - writew(*(msg.buf++), &twi->xmt_data8); - --msg.len; - } - - /* clear int stat */ - writew(-1, &twi->master_stat); - writew(-1, &twi->int_stat); - writew(0, &twi->int_mask); - - /* Master enable */ - ctl = readw(&twi->master_ctl); - ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN | - ((msg.flags & I2C_M_READ) ? MDIR : 0); - writew(ctl, &twi->master_ctl); - - /* process the rest */ - ret = wait_for_completion(&msg); - debugi("ret=%d", ret); - - if (ret) { - ctl = readw(&twi->master_ctl) & ~MEN; - writew(ctl, &twi->master_ctl); - ctl = readw(&twi->control) & ~TWI_ENA; - writew(ctl, &twi->control); - ctl = readw(&twi->control) | TWI_ENA; - writew(ctl, &twi->control); - } - - return ret; -} - -/** - * i2c_set_bus_speed - set i2c bus speed - * @speed: bus speed (in HZ) - */ -int i2c_set_bus_speed(unsigned int speed) -{ - u16 clkdiv = I2C_SPEED_TO_DUTY(speed); - - /* Set TWI interface clock */ - if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN) - return -1; - clkdiv = (clkdiv << 8) | (clkdiv & 0xff); - writew(clkdiv, &twi->clkdiv); - - /* Don't turn it on */ - writew(speed > 100000 ? FAST : 0, &twi->master_ctl); - - return 0; -} - -/** - * i2c_get_bus_speed - get i2c bus speed - * @speed: bus speed (in HZ) - */ -unsigned int i2c_get_bus_speed(void) -{ - u16 clkdiv = readw(&twi->clkdiv) & 0xff; - /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */ - return 5000000 / clkdiv; -} - -/** - * i2c_init - initialize the i2c bus - * @speed: bus speed (in HZ) - * @slaveaddr: address of device in slave mode (0 - not slave) - * - * Slave mode isn't actually implemented. It'll stay that way until - * we get a real request for it. - */ -void i2c_init(int speed, int slaveaddr) -{ - u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F; - - /* Set TWI internal clock as 10MHz */ - writew(prescale, &twi->control); - - /* Set TWI interface clock as specified */ - i2c_set_bus_speed(speed); - - /* Enable it */ - writew(TWI_ENA | prescale, &twi->control); - - debugi("CONTROL:0x%04x CLKDIV:0x%04x", readw(&twi->control), - readw(&twi->clkdiv)); - -#if CONFIG_SYS_I2C_SLAVE -# error I2C slave support not tested/supported -#endif -} - -/** - * i2c_probe - test if a chip exists at a given i2c address - * @chip: i2c chip addr to search for - * @return: 0 if found, non-0 if not found - */ -int i2c_probe(uchar chip) -{ - u8 byte; - return i2c_read(chip, 0, 0, &byte, 1); -} - -/** - * i2c_read - read data from an i2c device - * @chip: i2c chip addr - * @addr: memory (register) address in the chip - * @alen: byte size of address - * @buffer: buffer to store data read from chip - * @len: how many bytes to read - * @return: 0 on success, non-0 on failure - */ -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - return i2c_transfer(chip, addr, alen, buffer, - len, (alen ? I2C_M_COMBO : I2C_M_READ)); -} - -/** - * i2c_write - write data to an i2c device - * @chip: i2c chip addr - * @addr: memory (register) address in the chip - * @alen: byte size of address - * @buffer: buffer holding data to write to chip - * @len: how many bytes to write - * @return: 0 on success, non-0 on failure - */ -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - return i2c_transfer(chip, addr, alen, buffer, len, 0); -} - -/** - * i2c_set_bus_num - change active I2C bus - * @bus: bus index, zero based - * @returns: 0 on success, non-0 on failure - */ -int i2c_set_bus_num(unsigned int bus) -{ - switch (bus) { -#if CONFIG_SYS_MAX_I2C_BUS > 0 - case 0: - twi = (void *)TWI0_CLKDIV; - return 0; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 1 - case 1: - twi = (void *)TWI1_CLKDIV; - return 0; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 2 - case 2: - twi = (void *)TWI2_CLKDIV; - return 0; -#endif - default: return -1; - } -} - -/** - * i2c_get_bus_num - returns index of active I2C bus - */ -unsigned int i2c_get_bus_num(void) -{ - switch ((unsigned long)twi) { -#if CONFIG_SYS_MAX_I2C_BUS > 0 - case TWI0_CLKDIV: - return 0; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 1 - case TWI1_CLKDIV: - return 1; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 2 - case TWI2_CLKDIV: - return 2; -#endif - default: return -1; - } -} -- 1.8.3.2

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[U-Boot] Enabling uart 3 in arndale
by armdev 31 Mar '14

31 Mar '14

Hi, We are trying to enable the UART3 on COM18 pins of arndale board. The UART3 RXD and TXD are on pins 2 and 4 which as per the base board specification is connected as XuRXD3 : UART_3_RXD/GPA1[4] : 2 XuTXD3 : UART_3_TXD/GPA1[5] : 4 As per the public reference manual of exynos 5250, there is a register GPACON (0x1140_0000) Setting GPACON |= 0x0010_0000 should enable the pins, but I am not able to see any output on UART3. Can you please suggest what is the right procedure -Regards armdev team @FTM

3 9

[U-Boot] Please fix warnings in NIOS2 boards
by Masahiro Yamada 31 Mar '14

31 Mar '14

Hi. When I build NIOS2 boards, warnings are displayed. common/cmd_test.c: In function `do_test': common/cmd_test.c:66: warning: 'op' might be used uninitialized in this function common/cmd_test.c:66: warning: 'adv' might be used uninitialized in this function Could anybody fix them? Best Regards Masahiro Yamada

1 0

[U-Boot] [PATCH] sparc: consolidate CONFIG_{LEON, LEON2, LEON3} definition
by Masahiro Yamada 31 Mar '14

31 Mar '14

CONFIG_LEON is already defined in arch/sparc/cpu/{leon2,leon3}/config.mk. Remove the redundant definition in board header files. All leon3 boards define CONFIG_LEON3 in board header files. Move the definition to arch/sparc/cpu/leon3/config.mk. CONFIG_LEON2 can be move to arch/sparc/cpu/leon2/config.mk as well. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Daniel Hellstrom <daniel(a)gaisler.com> --- arch/sparc/cpu/leon2/config.mk | 2 +- arch/sparc/cpu/leon3/config.mk | 2 +- include/configs/gr_cpci_ax2000.h | 2 -- include/configs/gr_ep2s60.h | 2 -- include/configs/gr_xc3s_1500.h | 2 -- include/configs/grsim.h | 2 -- include/configs/grsim_leon2.h | 2 -- 7 files changed, 2 insertions(+), 12 deletions(-) diff --git a/arch/sparc/cpu/leon2/config.mk b/arch/sparc/cpu/leon2/config.mk index f9b0d34..c44b093 100644 --- a/arch/sparc/cpu/leon2/config.mk +++ b/arch/sparc/cpu/leon2/config.mk @@ -7,4 +7,4 @@ PLATFORM_RELFLAGS += -fPIC -PLATFORM_CPPFLAGS += -DCONFIG_LEON +PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON2 diff --git a/arch/sparc/cpu/leon3/config.mk b/arch/sparc/cpu/leon3/config.mk index f9b0d34..ca6c9b1 100644 --- a/arch/sparc/cpu/leon3/config.mk +++ b/arch/sparc/cpu/leon3/config.mk @@ -7,4 +7,4 @@ PLATFORM_RELFLAGS += -fPIC -PLATFORM_CPPFLAGS += -DCONFIG_LEON +PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON3 diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h index 8f4b85b..a4b5eb3 100644 --- a/include/configs/gr_cpci_ax2000.h +++ b/include/configs/gr_cpci_ax2000.h @@ -22,8 +22,6 @@ * (easy to change) */ -#define CONFIG_LEON3 /* This is an LEON3 CPU */ -#define CONFIG_LEON 1 /* This is an LEON CPU */ #define CONFIG_CPCI_AX2000 1 /* ... on GR-CPCI-AX2000 board */ #define CONFIG_LEON_RAM_SRAM 1 diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h index 1e829aa..b7f094f 100644 --- a/include/configs/gr_ep2s60.h +++ b/include/configs/gr_ep2s60.h @@ -23,8 +23,6 @@ * (easy to change) */ -#define CONFIG_LEON3 /* This is an LEON3 CPU */ -#define CONFIG_LEON 1 /* This is an LEON CPU */ /* Altera NIOS Development board, Stratix II board */ #define CONFIG_GR_EP2S60 1 diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h index e9e64f1..789b3ed 100644 --- a/include/configs/gr_xc3s_1500.h +++ b/include/configs/gr_xc3s_1500.h @@ -21,8 +21,6 @@ * (easy to change) */ -#define CONFIG_LEON3 /* This is an LEON3 CPU */ -#define CONFIG_LEON 1 /* This is an LEON CPU */ #define CONFIG_GRXC3S1500 1 /* ... on GR-XC3S-1500 board */ /* CPU / AMBA BUS configuration */ diff --git a/include/configs/grsim.h b/include/configs/grsim.h index f50dd54..82b7a4e 100644 --- a/include/configs/grsim.h +++ b/include/configs/grsim.h @@ -27,8 +27,6 @@ * */ -#define CONFIG_LEON3 /* This is an LEON3 CPU */ -#define CONFIG_LEON 1 /* This is an LEON CPU */ #define CONFIG_GRSIM 0 /* ... not running on GRSIM */ #define CONFIG_TSIM 1 /* ... running on TSIM */ diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h index 9ea6d9b..8cb077c 100644 --- a/include/configs/grsim_leon2.h +++ b/include/configs/grsim_leon2.h @@ -26,8 +26,6 @@ * */ -#define CONFIG_LEON2 /* This is an LEON2 CPU */ -#define CONFIG_LEON 1 /* This is an LEON CPU */ #define CONFIG_GRSIM 0 /* ... not running on GRSIM */ #define CONFIG_TSIM 1 /* ... running on TSIM */ -- 1.8.3.2

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[U-Boot] [PATCH] powerpc/mpc85xx: Add workaround for erratum A007212
by York Sun 28 Mar '14

28 Mar '14

Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun <yorksun(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 19 ++++++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 69 +++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/speed.c | 7 +++ arch/powerpc/include/asm/config_mpc85xx.h | 2 + arch/powerpc/include/asm/immap_85xx.h | 2 + 5 files changed, 99 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 8b79c05..42b6331 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -113,6 +113,21 @@ static void check_erratum_a4580(uint32_t svr) } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 +/* + * This workaround can be implemented in PBI, or by u-boot. + */ +static void check_erratum_a007212(void) +{ + u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); + + if (in_be32(plldgdcr) & 0x1fe) { + /* check if PLL ratio is set by workaround */ + puts("Work-around for Erratum A007212 enabled\n"); + } +} +#endif + static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 @@ -277,6 +292,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (has_erratum_a006261()) puts("Work-around for Erratum A006261 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 + check_erratum_a007212(); +#endif + return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 81aeadd..4f27bcc 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -267,6 +267,71 @@ static void corenet_tb_init(void) } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 +void fsl_erratum_a007212_workaround(void) +{ + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_pll_ratio; + u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); + u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); + u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); + u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) + u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); + u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); +#endif +#endif + /* + * Even this workaround applies to selected version of SoCs, it is + * safe to apply to all versions, with the limitation of odd ratios. + * If RCW has disabled DDR PLL, we have to apply this workaround, + * otherwise DDR will not work. + */ + ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & + FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + /* check if RCW sets ratio to 0, required by this workaround */ + if (ddr_pll_ratio != 0) + return; + ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & + FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + /* check if reserved bits have the desired ratio */ + if (ddr_pll_ratio == 0) { + printf("Error: Unknown DDR PLL ratio!\n"); + return; + } + ddr_pll_ratio >>= 1; + + setbits_be32(plldadcr1, 0x02000001); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + setbits_be32(plldadcr2, 0x02000001); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) + setbits_be32(plldadcr3, 0x02000001); +#endif +#endif + setbits_be32(dpdovrcr4, 0xe0000000); + out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) + out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); +#endif +#endif + udelay(100); + clrbits_be32(plldadcr1, 0x02000001); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + clrbits_be32(plldadcr2, 0x02000001); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) + clrbits_be32(plldadcr3, 0x02000001); +#endif +#endif + clrbits_be32(dpdovrcr4, 0xe0000000); +} +#endif + void cpu_init_f (void) { extern void m8560_cpm_reset (void); @@ -330,6 +395,10 @@ void cpu_init_f (void) in_be32(&gur->dcsrcr); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 + fsl_erratum_a007212_workaround(); +#endif + } /* Implement a dummy function for those platforms w/o SERDES */ diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index adf09ef..c54d3f9 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -107,6 +107,13 @@ void get_sys_info(sys_info_t *sys_info) mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 + if (mem_pll_rat == 0) { + mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & + FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + } +#endif /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 * it uses 6. diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 727e981..be7d084 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -676,6 +676,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_FSL_ERRATUM_A006475 #define CONFIG_SYS_FSL_ERRATUM_A006384 +#define CONFIG_SYS_FSL_ERRATUM_A007212 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #ifdef CONFIG_PPC_B4860 @@ -784,6 +785,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_FSL_ERRATUM_A007212 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ISBC_VER 2 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 4b6f9d0..75c2cd4 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1739,6 +1739,8 @@ typedef struct ccsr_gur { #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 +/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ +#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 -- 1.7.9.5

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[U-Boot] [PATCH] blackfin: mmc: Correct mmc_host_is_spi and bfin_sdh.c
by Tom Rini 28 Mar '14

28 Mar '14

In the recent mmc cleanup, the mmc_host_is_spi macro was broken and bfin_sdh.c had mmc->bus_width turned into mmc_bus_width(mmc), both of which were incorrect. Signed-off-by: Tom Rini <trini(a)ti.com> --- drivers/mmc/bfin_sdh.c | 2 +- include/mmc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index 7b35d8e..bcd6a3e 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -238,7 +238,7 @@ static void bfin_sdh_set_ios(struct mmc *mmc) u16 cfg = 0; u16 clk_ctl = 0; - if (mmc_bus_width(mmc) == 4) { + if (mmc->bus_width == 4) { cfg = bfin_read_SDH_CFG(); #ifndef RSI_BLKSZ cfg &= ~PD_SDDAT3; diff --git a/include/mmc.h b/include/mmc.h index 0172979..8a82974 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -360,7 +360,7 @@ void mmc_set_preinit(struct mmc *mmc, int preinit); #ifdef CONFIG_GENERIC_MMC #ifdef CONFIG_MMC_SPI -#define mmc_host_is_spi(mmc) ((mmc)->cfg.host_caps & MMC_MODE_SPI) +#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI) #else #define mmc_host_is_spi(mmc) 0 #endif -- 1.7.9.5

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[U-Boot] [PATCH] kbuild: fix bugs in cleaning targets
by Masahiro Yamada 28 Mar '14

28 Mar '14

"make clean", "make clobber", "make mrproper" and "make distclean" missed to clean-up some files when they were run with O=<some_dir> option. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Reported-by: Wolfgang Denk <wd(a)denx.de> --- This bug was reported by Wolfgang. Refer to this thread: http://lists.denx.de/pipermail/u-boot/2014-March/175983.html Makefile | 2 +- dts/Makefile | 2 +- scripts/Makefile.clean | 3 ++- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 0522ba8..c744718 100644 --- a/Makefile +++ b/Makefile @@ -1173,7 +1173,7 @@ MRPROPER_FILES += .config .config.old \ clean: rm-dirs := $(CLEAN_DIRS) clean: rm-files := $(CLEAN_FILES) -clean-dirs := $(foreach f,$(u-boot-alldirs),$(if $(wildcard $f/Makefile),$f)) +clean-dirs := $(foreach f,$(u-boot-alldirs),$(if $(wildcard $(srctree)/$f/Makefile),$f)) clean-dirs := $(addprefix _clean_, $(clean-dirs) doc/DocBook) diff --git a/dts/Makefile b/dts/Makefile index 9907463..e59550c 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -44,4 +44,4 @@ dtbs: $(obj)/dt.dtb clean-files := dt.dtb.S # Let clean descend into dts directories -subdir- += ../arch/*/dts +subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts ../arch/x86/dts diff --git a/scripts/Makefile.clean b/scripts/Makefile.clean index 5cd0f51..d6dcd47 100644 --- a/scripts/Makefile.clean +++ b/scripts/Makefile.clean @@ -39,7 +39,8 @@ subdir-ymn := $(addprefix $(obj)/,$(subdir-ymn)) # Temporal work-around for U-Boot -subdir-ymn := $(foreach f, $(subdir-ymn), $(if $(wildcard $f/Makefile),$f)) +subdir-ymn := $(foreach f, $(subdir-ymn), \ + $(if $(wildcard $(srctree)/$f/Makefile),$f)) # build a list of files to remove, usually relative to the current # directory -- 1.8.3.2

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[U-Boot] [PATCH 1/3] cpu: exynos4: ace_sha: add hardware random number generator support.
by Przemyslaw Marczak 28 Mar '14

28 Mar '14

This patch adds implementation of function hw_rand() based on exynos security sub system. Signed-off-by: Przemyslaw Marczak <p.marczak(a)samsung.com> cc: Akshay Saraswat <akshay.s(a)samsung.com> cc: ARUN MANKUZHI <arun.m(a)samsung.com> cc: Minkyu Kang <mk7.kang(a)samsung.com> --- arch/arm/include/asm/arch-exynos/cpu.h | 4 ++-- drivers/crypto/ace_sha.c | 41 ++++++++++++++++++++++++++++++++ drivers/crypto/ace_sha.h | 8 ++++--- 3 files changed, 48 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index bccce63..a5c280d 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -48,7 +48,7 @@ #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4_ACE_SFR_BASE 0x10830000 #define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE @@ -87,7 +87,7 @@ #define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_ACE_SFR_BASE 0x10830000 #define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE diff --git a/drivers/crypto/ace_sha.c b/drivers/crypto/ace_sha.c index acbafde..d12a507 100644 --- a/drivers/crypto/ace_sha.c +++ b/drivers/crypto/ace_sha.c @@ -111,3 +111,44 @@ void hw_sha1(const unsigned char *pbuf, unsigned int buf_len, if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1)) debug("ACE was not setup properly or it is faulty\n"); } + +unsigned int hw_rand(void) +{ + struct exynos_ace_sfr *reg = + (struct exynos_ace_sfr *)samsung_get_base_ace_sfr(); + int status, i; + int seed[5]; + unsigned int ret = 0; + + /* Seed data */ + for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++) + writel(seed[i], &reg->hash_seed[i]); + + status = 0; + /* Wait for seed setup done */ + while (!(status & ACE_HASH_SEEDSETTING_MASK)) { + status = readl(&reg->hash_status); + if (status & ACE_HASH_PRNGERROR_MASK) + return 0; + } + + /* Start PRNG */ + writel(ACE_HASH_ENGSEL_PRNG | ACE_HASH_STARTBIT_ON, &reg->hash_control); + + status = 0; + /* Wait for PRNG done */ + while (!(status & ACE_HASH_PRNGDONE_MASK)) { + status = readl(&reg->hash_status); + if (status & ACE_HASH_PRNGERROR_MASK) + return 0; + } + + /* Clear Done IRQ */ + writel(ACE_HASH_PRNGDONE_MASK, &reg->hash_status); + + /* Read a PRNG result */ + for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++) + ret += readl(&reg->hash_prng[i]); + + return ret; +} diff --git a/drivers/crypto/ace_sha.h b/drivers/crypto/ace_sha.h index a426d52..f1097f7 100644 --- a/drivers/crypto/ace_sha.h +++ b/drivers/crypto/ace_sha.h @@ -72,9 +72,10 @@ struct exynos_ace_sfr { unsigned char res12[0x30]; unsigned int hash_result[8]; unsigned char res13[0x20]; - unsigned int hash_seed[8]; - unsigned int hash_prng[8]; - unsigned char res14[0x180]; + unsigned int hash_seed[5]; + unsigned char res14[12]; + unsigned int hash_prng[5]; + unsigned char res15[0x18c]; unsigned int pka_sfr[5]; /* base + 0x700 */ }; @@ -291,6 +292,7 @@ struct exynos_ace_sfr { #define ACE_HASH_PRNGERROR_MASK (1 << 7) #define ACE_HASH_PRNGERROR_OFF (0 << 7) #define ACE_HASH_PRNGERROR_ON (1 << 7) +#define ACE_HASH_PRNG_REG_NUM 5 #define ACE_SHA_TYPE_SHA1 1 #define ACE_SHA_TYPE_SHA256 2 -- 1.7.9.5

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