March 2014 - U-Boot

[U-Boot] [PATCH 9/10] board/b4qds:Add support of 2 stage NAND boot-loader
by Prabhakar Kushwaha 04 Apr '14

04 Apr '14

Add support of 2 stage NAND boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- board/freescale/b4860qds/Makefile | 9 ++- board/freescale/b4860qds/ddr.c | 5 +- board/freescale/b4860qds/spl.c | 115 +++++++++++++++++++++++++++++++++++++ board/freescale/b4860qds/tlb.c | 10 ++++ boards.cfg | 4 +- doc/README.b4860qds | 35 +++++++++++ include/configs/B4860QDS.h | 64 ++++++++++++++++++--- 7 files changed, 230 insertions(+), 12 deletions(-) create mode 100644 board/freescale/b4860qds/spl.c diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile index e5cc054..0acd2a9 100644 --- a/board/freescale/b4860qds/Makefile +++ b/board/freescale/b4860qds/Makefile @@ -4,9 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-y += b4860qds.o -obj-y += ddr.o obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o -obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_PCI) += pci.o +endif + +obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c index 187c3b3..2c17156 100644 --- a/board/freescale/b4860qds/ddr.c +++ b/board/freescale/b4860qds/ddr.c @@ -179,6 +179,7 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); @@ -186,7 +187,9 @@ phys_size_t initdram(int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); +#else + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c new file mode 100644 index 0000000..d56cd30 --- /dev/null +++ b/board/freescale/b4860qds/spl.c @@ -0,0 +1,115 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/spl.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include "../common/qixis.h" +#include "b4860qds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((sysclk_conf & 0x0C) >> 2) { + case QIXIS_CLK_100: + return 100000000; + case QIXIS_CLK_125: + return 125000000; + case QIXIS_CLK_133: + return 133333333; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch (ddrclk_conf & 0x03) { + case QIXIS_CLK_100: + return 100000000; + case QIXIS_CLK_125: + return 125000000; + case QIXIS_CLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifndef CONFIG_SPL_NAND_BOOT + env_init(); +#endif + + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; +#else + env_relocate(); +#endif + + i2c_init_all(); + + puts("\n\n"); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_boot(); +#endif +} diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c index 00798a1..7b55b86 100644 --- a/board/freescale/b4860qds/tlb.c +++ b/board/freescale/b4860qds/tlb.c @@ -62,6 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -96,6 +97,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -118,6 +120,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * entry 14 and 15 has been used hard coded, they will be disabled * in cpu_init_f, so we use entry 16 for SRIO2. */ +#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_SYS_SRIO1_MEM_PHYS /* *I*G* - SRIO1 */ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, @@ -140,6 +143,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 17, BOOKE_PAGESZ_1M, 1), #endif +#endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 17, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 5afca26..76f3aae 100644 --- a/boards.cfg +++ b/boards.cfg @@ -740,10 +740,10 @@ Active powerpc mpc85xx - - sbc8548 Active powerpc mpc85xx - - socrates socrates - - Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett(a)boeing.com> Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 - -Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,RAMBOOT_SPLPBL,NAND - Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 - -Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,RAMBOOT_SPLPBL,NAND Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal <poonam.aggrwal(a)freescale.com> diff --git a/doc/README.b4860qds b/doc/README.b4860qds index 3da77d9..44b46da 100644 --- a/doc/README.b4860qds +++ b/doc/README.b4860qds @@ -328,3 +328,38 @@ The below commands apply to both B4860QDS and B4420QDS. On Linux the interfaces are renamed as: . eth2 -> fm1-gb2 . eth3 -> fm1-gb3 + +NAND boot with 2 Stage boot loader +---------------------------------- +PBL initialise the internal SRAM and copy SPL(160KB) in SRAM. +SPL further initialise DDR using SPD and environment variables and copy +u-boot(768 KB) from flash to DDR. +Finally SPL transer control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + + Run time view of SPL framework :- + ----------------------------------------------- + Area | Address | +----------------------------------------------- + Reserve | 0xFFFC0000 (32KB) | + ----------------------------------------------- + GD, BD | 0xFFFC8000 (4KB) | + ----------------------------------------------- + ENV | 0xFFFC9000 (6KB) | + ----------------------------------------------- + HEAP | 0xFFFCA800 (30KB) | + ----------------------------------------------- + STACK | 0xFFFD8000 (20KB) | + ----------------------------------------------- + U-boot SPL | 0xFFFD8000 (160KB) | + ----------------------------------------------- + +NAND Flash memory Map on B4860 and B4420QDS +------------------------------------------ + Start End Definition Size +0x000000 0x0FFFFF u-boot 1MB +0x140000 0x15FFFF u-boot env 128KB +0x160000 0x17FFFF FMAN Ucode 128KB diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 8fcd1de..4df28a2 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -14,10 +14,43 @@ #define CONFIG_PHYS_64BIT #ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg +#ifndef CONFIG_NAND #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/b4860qds/b4_pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/b4860qds/b4_rcw.cfg +#else +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif +#endif #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE @@ -113,8 +146,8 @@ #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -164,7 +197,16 @@ unsigned long get_board_ddr_clk(void); /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE 256 << 10 +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_NAND +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 10 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (34 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (20 << 10) #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf0000000 @@ -193,7 +235,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DDR_SPD #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_FSL_DDR3 +#ifndef CONFIG_SPL_BUILD #define CONFIG_FSL_DDR_INTERACTIVE +#endif #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x51 @@ -381,7 +425,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif #if defined(CONFIG_RAMBOOT_PBL) #define CONFIG_SYS_RAMBOOT @@ -435,7 +483,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ +#endif /* Use the HUSH parser */ @@ -607,7 +657,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing -- 1.7.9.5

2 3

[U-Boot] [PATCH v7] socfpga: Adding Scan Manager driver
by Chin Liang See 03 Apr '14

03 Apr '14

Scan Manager driver will be called to configure the IOCSR scan chain. This configuration will setup the IO buffer settings Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Wolfgang Denk <wd(a)denx.de> CC: Pavel Machek <pavel(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> --- Changes for v7 - Enhance the function scan_chain_engine_is_idle Changes for v6 - Fixed various coding style issue Changes for v5 - Removal of additional blank line - Added comment for magic number Changes for v4 - avoid code duplication by add goto error - include underscore to variables name Changes for v3 - merge the handoff file and driver into single patch Changes for v2 - rebase with latest v2014.01-rc1 --- arch/arm/cpu/armv7/socfpga/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/scan_manager.c | 209 +++++++ arch/arm/cpu/armv7/socfpga/spl.c | 4 + arch/arm/include/asm/arch-socfpga/scan_manager.h | 90 +++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 1 + board/altera/socfpga/iocsr_config.c | 657 ++++++++++++++++++++ board/altera/socfpga/iocsr_config.h | 17 + include/configs/socfpga_cyclone5.h | 1 + 8 files changed, 980 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h create mode 100644 board/altera/socfpga/iocsr_config.c create mode 100644 board/altera/socfpga/iocsr_config.h diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index cbe1d40..eb33f2c 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -9,4 +9,4 @@ obj-y := lowlevel_init.o obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o +obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c b/arch/arm/cpu/armv7/socfpga/scan_manager.c new file mode 100644 index 0000000..a820b1b --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/freeze_controller.h> +#include <asm/arch/scan_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_scan_manager *scan_manager_base = + (void *)(SOCFPGA_SCANMGR_ADDRESS); +static const struct socfpga_freeze_controller *freeze_controller_base = + (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS); + +/* + * Function to check IO scan chain engine status and wait if the engine is + * is active. Poll the IO scan chain engine till maximum iteration reached. + */ +static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter) +{ + uint32_t scanmgr_status; + + scanmgr_status = readl(&scan_manager_base->stat); + + /* Poll the engine until the scan engine is inactive */ + while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) || + (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) { + max_iter--; + if (max_iter > 0) + scanmgr_status = readl(&scan_manager_base->stat); + else + return 0; + } + return 1; +} + +/* Program HPS IO Scan Chain */ +uint32_t scan_mgr_io_scan_chain_prg( + uint32_t io_scan_chain_id, + uint32_t io_scan_chain_len_in_bits, + const uint32_t *iocsr_scan_chain) +{ + uint16_t tdi_tdo_header; + uint32_t io_program_iter; + uint32_t io_scan_chain_data_residual; + uint32_t residual; + uint32_t i; + uint32_t index = 0; + + /* + * De-assert reinit if the IO scan chain is intended for HIO. In + * this, its the chain 3. + */ + if (io_scan_chain_id == 3) + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK); + + /* + * Check if the scan chain engine is inactive and the + * WFIFO is empty before enabling the IO scan chain + */ + if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY)) + return 1; + + /* + * Enable IO Scan chain based on scan chain id + * Note: only one chain can be enabled at a time + */ + setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id); + + /* + * Calculate number of iteration needed for full 128-bit (4 x32-bits) + * bits shifting. Each TDI_TDO packet can shift in maximum 128-bits + */ + io_program_iter = io_scan_chain_len_in_bits >> + IO_SCAN_CHAIN_128BIT_SHIFT; + io_scan_chain_data_residual = io_scan_chain_len_in_bits & + IO_SCAN_CHAIN_128BIT_MASK; + + /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */ + tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | + (TDI_TDO_MAX_PAYLOAD << TDI_TDO_HEADER_SECOND_BYTE_SHIFT); + + /* Program IO scan chain in 128-bit iteration */ + for (i = 0; i < io_program_iter; i++) { + /* write TDI_TDO packet header to scan manager */ + writel(tdi_tdo_header, &scan_manager_base->fifo_double_byte); + + /* calculate array index. Multiply by 4 as write 4 x 32bits */ + index = i * 4; + + /* write 4 successive 32-bit IO scan chain data into WFIFO */ + writel(iocsr_scan_chain[index], + &scan_manager_base->fifo_quad_byte); + writel(iocsr_scan_chain[index + 1], + &scan_manager_base->fifo_quad_byte); + writel(iocsr_scan_chain[index + 2], + &scan_manager_base->fifo_quad_byte); + writel(iocsr_scan_chain[index + 3], + &scan_manager_base->fifo_quad_byte); + + /* + * Check if the scan chain engine has completed the + * IO scan chain data shifting + */ + if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY)) + goto error; + } + + /* Calculate array index for final TDI_TDO packet */ + index = io_program_iter * 4; + + /* Final TDI_TDO packet if any */ + if (io_scan_chain_data_residual) { + /* + * Calculate number of quad bytes FIFO write + * needed for the final TDI_TDO packet + */ + io_program_iter = io_scan_chain_data_residual >> + IO_SCAN_CHAIN_32BIT_SHIFT; + + /* + * Construct TDI_TDO packet for remaining IO + * scan chain (2 bytes) + */ + tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | + ((io_scan_chain_data_residual - 1) << + TDI_TDO_HEADER_SECOND_BYTE_SHIFT); + + /* + * Program the last part of IO scan chain write TDI_TDO packet + * header (2 bytes) to scan manager + */ + writel(tdi_tdo_header, &scan_manager_base->fifo_double_byte); + + for (i = 0; i < io_program_iter; i++) { + /* + * write remaining scan chain data into scan + * manager WFIFO with 4 bytes write + */ + writel(iocsr_scan_chain[index + i], + &scan_manager_base->fifo_quad_byte); + } + + index += io_program_iter; + residual = io_scan_chain_data_residual & + IO_SCAN_CHAIN_32BIT_MASK; + + if (IO_SCAN_CHAIN_PAYLOAD_24BIT < residual) { + /* + * write the last 4B scan chain data + * into scan manager WFIFO + */ + writel(iocsr_scan_chain[index], + &scan_manager_base->fifo_quad_byte); + } else { + /* + * write the remaining 1 - 3 bytes scan chain + * data into scan manager WFIFO byte by byte + * to prevent JTAG engine shifting unused data + * from the FIFO and mistaken the data as a + * valid command (even though unused bits are + * set to 0, but just to prevent hardware + * glitch) + */ + for (i = 0; i < residual; i += 8) { + writel(((iocsr_scan_chain[index] >> i) + & IO_SCAN_CHAIN_BYTE_MASK), + &scan_manager_base->fifo_single_byte); + } + } + + /* + * Check if the scan chain engine has completed the + * IO scan chain data shifting + */ + if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY)) + goto error; + } + + /* Disable IO Scan chain when configuration done*/ + clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id); + return 0; + +error: + /* Disable IO Scan chain when error detected */ + clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id); + return 1; +} + +int scan_mgr_configure_iocsr(void) +{ + int status = 0; + + /* configure the IOCSR through scan chain */ + status |= scan_mgr_io_scan_chain_prg(0, + CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH, iocsr_scan_chain0_table); + status |= scan_mgr_io_scan_chain_prg(1, + CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH, iocsr_scan_chain1_table); + status |= scan_mgr_io_scan_chain_prg(2, + CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH, iocsr_scan_chain2_table); + status |= scan_mgr_io_scan_chain_prg(3, + CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH, iocsr_scan_chain3_table); + return status; +} diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 2ae88bb..4bed19d 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -121,6 +121,10 @@ void spl_board_init(void) /* reconfigure the PLLs */ cm_basic_init(&cm_default_cfg); + /* configure the IOCSR / IO buffer settings */ + if (scan_mgr_configure_iocsr()) + hang(); + /* configure the pin muxing through system manager */ sysmgr_pinmux_init(); #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ diff --git a/arch/arm/include/asm/arch-socfpga/scan_manager.h b/arch/arm/include/asm/arch-socfpga/scan_manager.h new file mode 100644 index 0000000..f9be621 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/scan_manager.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SCAN_MANAGER_H_ +#define _SCAN_MANAGER_H_ + +struct socfpga_scan_manager { + u32 stat; + u32 en; + u32 padding[2]; + u32 fifo_single_byte; + u32 fifo_double_byte; + u32 fifo_quad_byte; +}; + +/* + * Shift count to get number of IO scan chain data in granularity + * of 128-bit ( N / 128 ) + */ +#define IO_SCAN_CHAIN_128BIT_SHIFT 7 + +/* + * Mask to get residual IO scan chain data in + * granularity of 128-bit ( N mod 128 ) + */ +#define IO_SCAN_CHAIN_128BIT_MASK 0x7F + +/* + * Shift count to get number of IO scan chain + * data in granularity of 32-bit ( N / 32 ) + */ +#define IO_SCAN_CHAIN_32BIT_SHIFT 5 + +/* + * Mask to get residual IO scan chain data in + * granularity of 32-bit ( N mod 32 ) + */ +#define IO_SCAN_CHAIN_32BIT_MASK 0x1F + +/* Byte mask */ +#define IO_SCAN_CHAIN_BYTE_MASK 0xFF + +/* 24-bits (3 bytes) IO scan chain payload definition */ +#define IO_SCAN_CHAIN_PAYLOAD_24BIT 24 + +/* + * Maximum length of TDI_TDO packet payload is 128 bits, + * represented by (length - 1) in TDI_TDO header + */ +#define TDI_TDO_MAX_PAYLOAD 127 + +/* TDI_TDO packet header for IO scan chain program */ +#define TDI_TDO_HEADER_FIRST_BYTE 0x80 + +/* Position of second command byte for TDI_TDO packet */ +#define TDI_TDO_HEADER_SECOND_BYTE_SHIFT 8 + +/* + * Maximum polling loop to wait for IO scan chain engine + * becomes idle to prevent infinite loop + */ +#define SCAN_MAX_DELAY 100 + +#define SCANMGR_STAT_ACTIVE_GET(x) (((x) & 0x80000000) >> 31) +#define SCANMGR_STAT_WFIFOCNT_GET(x) (((x) & 0x70000000) >> 28) + +/* + * Program HPS IO Scan Chain + * io_scan_chain_id - IO scan chain ID + * io_scan_chain_len_in_bits - IO scan chain length in bits + * iocsr_scan_chain - IO scan chain table + */ +uint32_t scan_mgr_io_scan_chain_prg( + uint32_t io_scan_chain_id, + uint32_t io_scan_chain_len_in_bits, + const uint32_t *iocsr_scan_chain); + +extern const uint32_t iocsr_scan_chain0_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain1_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain2_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain3_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)]; + +#endif /* _SCAN_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index f564046..20f12e0 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -14,5 +14,6 @@ #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 #endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/board/altera/socfpga/iocsr_config.c b/board/altera/socfpga/iocsr_config.c new file mode 100644 index 0000000..b4b5ff8 --- /dev/null +++ b/board/altera/socfpga/iocsr_config.c @@ -0,0 +1,657 @@ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file is generated by Preloader Generator */ + +#include <iocsr_config.h> + +const unsigned long iocsr_scan_chain0_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00020080, + 0x08020000, + 0x08000000, + 0x00018020, + 0x00000000, + 0x00004000, + 0x00010040, + 0x04010000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x00020000, + 0x02008000, + 0x02000000, + 0x00000008, + 0x00002008, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { + 0x000C0300, + 0x10040000, + 0x100000C0, + 0x00000040, + 0x00010040, + 0x00008000, + 0x00080000, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x00010040, + 0x10000000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x06008020, + 0x02008000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x00004010, + 0x01004000, + 0x01000000, + 0x00003004, + 0x00001004, + 0x00000800, + 0x00000000, + 0x00000000, + 0x00800000, + 0x00000002, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00401000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00600802, + 0x00000000, + 0x80200000, + 0x80000600, + 0x00000200, + 0x00000100, + 0x00300401, + 0xC0100400, + 0x40100000, + 0x40000300, + 0x000C0100, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { + 0x80040100, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C010040, + 0x00008000, + 0x18020080, + 0x00000000, + 0x08000000, + 0x00040020, + 0x06018060, + 0x00004000, + 0x0C010040, + 0x04010000, + 0x00000030, + 0x00000000, + 0x03004010, + 0x00002000, + 0x06008020, + 0x02008000, + 0x02000018, + 0x00006008, + 0x01802008, + 0x00001000, + 0x03004010, + 0x01004000, + 0x0100000C, + 0x00003004, + 0x00C01004, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { + 0x2C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000070, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x906808A2, + 0xA2834024, + 0x05141A00, + 0x808A20D0, + 0x34024906, + 0x01A00A28, + 0xA20D0000, + 0x24906808, + 0x00A28340, + 0xD000001A, + 0x06808A20, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000070, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x906808A2, + 0xA2834024, + 0x05141A00, + 0x808A20D0, + 0x34024906, + 0x01A00040, + 0xA20D0002, + 0x24906808, + 0x00A28340, + 0xD005141A, + 0x06808A20, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x000001C1, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x04510680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x8341D348, + 0x821A0124, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x40120800, + 0x00000070, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x001A1A1A, + 0x085506A0, + 0x0000E1D4, + 0x045506A0, + 0x0000E1D4, + 0x085506A0, + 0x8000E1D4, + 0x00000200, + 0x00000004, + 0x04000000, + 0x00000009, + 0x00002410, + 0x00000040, + 0x41000000, + 0x00002082, + 0x00000350, + 0x000000DA, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x022A8350, + 0x000070EA, + 0x86000000, + 0x08000004, + 0x00000000, + 0x00482000, + 0x21800000, + 0x00101061, + 0x021541A8, + 0x00003875, + 0x011541A8, + 0x00003875, + 0x021541A8, + 0x20003875, + 0x00000080, + 0x00000001, + 0x41000000, + 0x00000002, + 0x00FF0904, + 0x00000000, + 0x90400000, + 0x00000820, + 0xC0000001, + 0x38D612AF, + 0x86F8E38E, + 0x0A0A78B4, + 0x000D020A, + 0x00006800, + 0x028A4320, + 0xEC2CB23D, + 0x8F5D1451, + 0xA47A88A2, + 0x0001A0E9, + 0x00410D00, + 0x40000068, + 0x3D000003, + 0x51EC2CB2, + 0xA28F5D14, + 0xE9A47A88, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000540, + 0x000003A8, + 0x08AA0D40, + 0x8001C3A8, + 0x0000007F, + 0x00000000, + 0x00004060, + 0xE1208000, + 0x0000001F, + 0x00004100, +}; diff --git a/board/altera/socfpga/iocsr_config.h b/board/altera/socfpga/iocsr_config.h new file mode 100644 index 0000000..490f109 --- /dev/null +++ b/board/altera/socfpga/iocsr_config.h @@ -0,0 +1,17 @@ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file is generated by Preloader Generator */ + +#ifndef _PRELOADER_IOCSR_CONFIG_H_ +#define _PRELOADER_IOCSR_CONFIG_H_ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) + +#endif /*_PRELOADER_IOCSR_CONFIG_H_*/ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 0254249..fc921ee 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -8,6 +8,7 @@ #include <asm/arch/socfpga_base_addrs.h> #include "../../board/altera/socfpga/pinmux_config.h" +#include "../../board/altera/socfpga/iocsr_config.h" #include "../../board/altera/socfpga/pll_config.h" /* -- 1.7.9.5

4 11

[U-Boot] Xilinx Zed Board resets with Master
by Tim Sander 03 Apr '14

03 Apr '14

Hi As i have seen that the Xilinx support has entered master i just tried to boot it on a Xilinx Zynx Zedboard Rev. D. The build works with the xilinx git tree so i am pretty confident that its not some issues with bootgen or the embedded fpga image. The board loads the fpga which can be seen by the blue "done" led of the ZedBoard. But then the LED turns off and about after a second or so it just lights up shortly again to turn off again. So it seems as if the board is somehow caught in a reboot loop. Any ideas what might be wrong? I am building with: export PATH=~/xilinx/SDK/2013.3/gnu/arm/lin/bin:$PATH export CROSS_COMPILE=arm-xilinx-linux-gnueabi- make clean make distclean make zynq_zed_config make The BOOT.BIN is build xilinx/SDK/2013.3/bin/lin64/bootgen -image u-boot.bif -w on -o BOOT.BIN And u-boot.bif looks like that: the_ROM_image: { [bootloader]zynq_fsbl_0.elf system.bit u-boot.elf } Best regards Tim

4 13

[U-Boot] [PATCH 1/2] lib: uuid: add function to generate UUID version 4
by Przemyslaw Marczak 03 Apr '14

03 Apr '14

lib/uuid.c: Add get_uuid_str() - this function returns 36 character hexadecimal ASCII string representation of a 128-bit (16 octets) UUID (Universally Unique Identifier) version 4 based on RFC4122, which is randomly generated. Source: https://www.ietf.org/rfc/rfc4122.txt Changes: Move functions: - disk/part_efi.c uuid_string() to lib/uuid.c -> uuid_bin_to_str() - disk/part_efi.c string_uuid() to lib/uuid.c -> uuid_str_to_bin() Update files: - include/common.h - disk/part_efi.c - lib/Makefile Signed-off-by: Przemyslaw Marczak <p.marczak(a)samsung.com> cc: Jason Hobbs <jason.hobbs(a)calxeda.com> cc: Stephen Warren <swarren(a)nvidia.com> cc: Lukasz Majewski <l.majewski(a)samsung.com> cc: trini(a)ti.com --- disk/part_efi.c | 90 ++++++------------------------------------ include/common.h | 7 +++- lib/Makefile | 4 ++ lib/uuid.c | 114 ++++++++++++++++++++++++++++++++++++++++++++++++++++-- 4 files changed, 131 insertions(+), 84 deletions(-) diff --git a/disk/part_efi.c b/disk/part_efi.c index 733d5bd..a280ab5 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -63,26 +63,6 @@ static char *print_efiname(gpt_entry *pte) return name; } -static void uuid_string(unsigned char *uuid, char *str) -{ - static const u8 le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, - 12, 13, 14, 15}; - int i; - - for (i = 0; i < 16; i++) { - sprintf(str, "%02x", uuid[le[i]]); - str += 2; - switch (i) { - case 3: - case 5: - case 7: - case 9: - *str++ = '-'; - break; - } - } -} - static efi_guid_t system_guid = PARTITION_SYSTEM_GUID; static inline int is_bootable(gpt_entry *p) @@ -103,6 +83,7 @@ void print_part_efi(block_dev_desc_t * dev_desc) gpt_entry *gpt_pte = NULL; int i = 0; char uuid[37]; + unsigned char *uuid_bin; if (!dev_desc) { printf("%s: Invalid Argument(s)\n", __func__); @@ -132,9 +113,11 @@ void print_part_efi(block_dev_desc_t * dev_desc) le64_to_cpu(gpt_pte[i].ending_lba), print_efiname(&gpt_pte[i])); printf("\tattrs:\t0x%016llx\n", gpt_pte[i].attributes.raw); - uuid_string(gpt_pte[i].partition_type_guid.b, uuid); + uuid_bin = (unsigned char *)gpt_pte[i].partition_type_guid.b; + uuid_bin_to_str(uuid_bin, uuid); printf("\ttype:\t%s\n", uuid); - uuid_string(gpt_pte[i].unique_partition_guid.b, uuid); + uuid_bin = (unsigned char *)gpt_pte[i].unique_partition_guid.b; + uuid_bin_to_str(uuid_bin, uuid); printf("\tuuid:\t%s\n", uuid); } @@ -182,7 +165,7 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part, sprintf((char *)info->type, "U-Boot"); info->bootable = is_bootable(&gpt_pte[part - 1]); #ifdef CONFIG_PARTITION_UUIDS - uuid_string(gpt_pte[part - 1].unique_partition_guid.b, info->uuid); + uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, info->uuid); #endif debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s", __func__, @@ -237,60 +220,6 @@ static int set_protective_mbr(block_dev_desc_t *dev_desc) return 0; } -/** - * string_uuid(); Convert UUID stored as string to bytes - * - * @param uuid - UUID represented as string - * @param dst - GUID buffer - * - * @return return 0 on successful conversion - */ -static int string_uuid(char *uuid, u8 *dst) -{ - efi_guid_t guid; - u16 b, c, d; - u64 e; - u32 a; - u8 *p; - u8 i; - - const u8 uuid_str_len = 36; - - /* The UUID is written in text: */ - /* 1 9 14 19 24 */ - /* xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx */ - - debug("%s: uuid: %s\n", __func__, uuid); - - if (strlen(uuid) != uuid_str_len) - return -1; - - for (i = 0; i < uuid_str_len; i++) { - if ((i == 8) || (i == 13) || (i == 18) || (i == 23)) { - if (uuid[i] != '-') - return -1; - } else { - if (!isxdigit(uuid[i])) - return -1; - } - } - - a = (u32)simple_strtoul(uuid, NULL, 16); - b = (u16)simple_strtoul(uuid + 9, NULL, 16); - c = (u16)simple_strtoul(uuid + 14, NULL, 16); - d = (u16)simple_strtoul(uuid + 19, NULL, 16); - e = (u64)simple_strtoull(uuid + 24, NULL, 16); - - p = (u8 *) &e; - guid = EFI_GUID(a, b, c, d >> 8, d & 0xFF, - *(p + 5), *(p + 4), *(p + 3), - *(p + 2), *(p + 1) , *p); - - memcpy(dst, guid.b, sizeof(efi_guid_t)); - - return 0; -} - int write_gpt_table(block_dev_desc_t *dev_desc, gpt_header *gpt_h, gpt_entry *gpt_e) { @@ -358,6 +287,7 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e, size_t efiname_len, dosname_len; #ifdef CONFIG_PARTITION_UUIDS char *str_uuid; + unsigned char *bin_uuid; #endif for (i = 0; i < parts; i++) { @@ -391,7 +321,9 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e, #ifdef CONFIG_PARTITION_UUIDS str_uuid = partitions[i].uuid; - if (string_uuid(str_uuid, gpt_e[i].unique_partition_guid.b)) { + bin_uuid = gpt_e[i].unique_partition_guid.b; + + if (uuid_str_to_bin(str_uuid, bin_uuid)) { printf("Partition no. %d: invalid guid: %s\n", i, str_uuid); return -1; @@ -438,7 +370,7 @@ int gpt_fill_header(block_dev_desc_t *dev_desc, gpt_header *gpt_h, gpt_h->header_crc32 = 0; gpt_h->partition_entry_array_crc32 = 0; - if (string_uuid(str_guid, gpt_h->disk_guid.b)) + if (uuid_str_to_bin(str_guid, gpt_h->disk_guid.b)) return -1; return 0; diff --git a/include/common.h b/include/common.h index 96a45a6..18f0224 100644 --- a/include/common.h +++ b/include/common.h @@ -815,7 +815,9 @@ void udelay (unsigned long); void mdelay(unsigned long); /* lib/uuid.c */ -void uuid_str_to_bin(const char *uuid, unsigned char *out); +char *get_uuid_str(void); +int uuid_bin_to_str(unsigned char *uuid, char *str); +int uuid_str_to_bin(char *uuid, unsigned char *out); int uuid_str_valid(const char *uuid); /* lib/vsprintf.c */ @@ -830,7 +832,8 @@ char * strmhz(char *buf, unsigned long hz); /* lib/rand.c */ #if defined(CONFIG_RANDOM_MACADDR) || \ defined(CONFIG_BOOTP_RANDOM_DELAY) || \ - defined(CONFIG_CMD_LINK_LOCAL) + defined(CONFIG_CMD_LINK_LOCAL) || \ + defined(CONFIG_PARTITION_UUIDS) #define RAND_MAX -1U void srand(unsigned int seed); unsigned int rand(void); diff --git a/lib/Makefile b/lib/Makefile index dedb97b..ca7f878 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -65,3 +65,7 @@ obj-y += vsprintf.o obj-$(CONFIG_RANDOM_MACADDR) += rand.o obj-$(CONFIG_BOOTP_RANDOM_DELAY) += rand.o obj-$(CONFIG_CMD_LINK_LOCAL) += rand.o +ifdef CONFIG_PARTITION_UUIDS +obj-y += rand.o +obj-y += uuid.o +endif diff --git a/lib/uuid.c b/lib/uuid.c index c48bf38..d75ae16 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -5,7 +5,29 @@ */ #include <linux/ctype.h> -#include "common.h" +#include <errno.h> +#include <common.h> +#include <part_efi.h> +#include <malloc.h> + +#define UUID_STR_BYTE_LEN 37 + +#define UUID_VERSION_CLEAR_BITS 0x0fff +#define UUID_VERSION_SHIFT 12 +#define UUID_VERSION 0x4 + +#define UUID_VARIANT_CLEAR_BITS 0x3f +#define UUID_VARIANT_SHIFT 7 +#define UUID_VARIANT 0x1 + +struct uuid { + unsigned int time_low; + unsigned short time_mid; + unsigned short time_hi_and_version; + unsigned char clock_seq_hi_and_reserved; + unsigned char clock_seq_low; + unsigned char node[6]; +}; /* * This is what a UUID string looks like. @@ -43,14 +65,17 @@ int uuid_str_valid(const char *uuid) return 1; } -void uuid_str_to_bin(const char *uuid, unsigned char *out) +int uuid_str_to_bin(char *uuid, unsigned char *out) { uint16_t tmp16; uint32_t tmp32; uint64_t tmp64; if (!uuid || !out) - return; + return -EINVAL; + + if (!uuid_str_valid(uuid)) + return -EINVAL; tmp32 = cpu_to_le32(simple_strtoul(uuid, NULL, 16)); memcpy(out, &tmp32, 4); @@ -66,4 +91,87 @@ void uuid_str_to_bin(const char *uuid, unsigned char *out) tmp64 = cpu_to_be64(simple_strtoull(uuid + 24, NULL, 16)); memcpy(out + 10, (char *)&tmp64 + 2, 6); + + return 0; +} + +int uuid_bin_to_str(unsigned char *uuid, char *str) +{ + static const u8 le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, + 12, 13, 14, 15}; + char *str_ptr = str; + int i; + + for (i = 0; i < 16; i++) { + sprintf(str, "%02x", uuid[le[i]]); + str += 2; + switch (i) { + case 3: + case 5: + case 7: + case 9: + *str++ = '-'; + break; + } + } + + if (!uuid_str_valid(str_ptr)) + return -EINVAL; + + return 0; +} + +/* + * get_uuid_str() - this function returns pointer to 36 character hexadecimal + * ASCII string representation of a 128-bit (16 octets) UUID (Universally + * Unique Identifier) version 4 based on RFC4122. + * source: https://www.ietf.org/rfc/rfc4122.txt + * + * Layout of UUID Version 4: + * timestamp - 60-bit: time_low, time_mid, time_hi_and_version + * version - 4 bit (bit 4 through 7 of the time_hi_and_version) + * clock seq - 14 bit: clock_seq_hi_and_reserved, clock_seq_low + * variant: - bit 6 and 7 of clock_seq_hi_and_reserved + * node - 48 bit + * In this version all fields beside 4 bit version are randomly generated. + * + * @ret: pointer to 36 bytes len characters array + */ +char *get_uuid_str(void) +{ + struct uuid uuid; + char *uuid_str = NULL; + int *ptr = (int *)&uuid; + int i; + + uuid_str = malloc(UUID_STR_BYTE_LEN); + if (!uuid_str) { + error("uuid_str pointer is null"); + return NULL; + } + + memset(&uuid, 0x0, sizeof(uuid)); + + /* Set all fields randomly */ + for (i = 0; i < sizeof(uuid) / 4; i++) + *(ptr + i) = rand(); + + /* Set V4 format */ + uuid.time_hi_and_version &= UUID_VERSION_CLEAR_BITS; + uuid.time_hi_and_version |= UUID_VERSION << UUID_VERSION_SHIFT; + + uuid.clock_seq_hi_and_reserved &= UUID_VARIANT_CLEAR_BITS; + uuid.clock_seq_hi_and_reserved |= UUID_VARIANT << UUID_VARIANT_SHIFT; + + uuid_bin_to_str((unsigned char *)&uuid, uuid_str); + + if (!uuid_str_valid(uuid_str)) { + error("Invalid UUID string"); + return NULL; + } + + /* Put end of string */ + uuid_str[UUID_STR_BYTE_LEN - 1] = '\0'; + + return uuid_str; } -- 1.7.9.5

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[U-Boot] [PATCH 7/10] driver/mtd/spi:Read 8KB data chunk during u-boot load in SPL
by Prabhakar Kushwaha 03 Apr '14

03 Apr '14

SPI driver perform its operation(read/write) on 64KB buffer chunk for data greater than 64KB. This buffer chunk is allocated from system heap. During SPL boot, 768KB of data is read from SPI flash. Here, heap size may not be sufficient enough to full-fill 64KB buffer requirement of SPI driver. So break down u-boot read operation at 8KB of chunk. Also, fix a warning i.e. "unused variable buf" during CONFIG_FSL_CORENET Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- drivers/mtd/spi/fsl_espi_spl.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c index e5ac79b..a55d741 100644 --- a/drivers/mtd/spi/fsl_espi_spl.c +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -20,8 +20,10 @@ void spi_boot(void) { void (*uboot)(void) __noreturn; - u32 offset, code_len; + u32 offset, code_len, copy_len = 0; +#ifndef CONFIG_FSL_CORENET unsigned char *buf = NULL; +#endif struct spi_flash *flash; flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, @@ -56,8 +58,15 @@ void spi_boot(void) code_len = code_len - CONFIG_SPL_MAX_SIZE; #endif /* copy code to DDR */ - spi_flash_read(flash, offset, code_len, - (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST); + printf("Loading second stage boot loader "); + while (copy_len <= code_len) { + spi_flash_read(flash, offset + copy_len, 0x2000, + (void *)(CONFIG_SYS_SPI_FLASH_U_BOOT_DST + + copy_len)); + copy_len = copy_len + 0x2000; + putc('.'); + } + /* * Jump to U-Boot image */ -- 1.7.9.5

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[U-Boot] Booting image from ARM for different architecture
by Michal Simek 02 Apr '14

02 Apr '14

Hi all, I want to check with you if someone tried this scenario. Load u-boot on main CPU (for me ARM cortex-a9) and boot different cpu(for me Microblaze) with FIT image or old u-boot image format. IRC I have seen any code regarding this but I am not able to find it out where. :-( My current usage is that I do that steps by hand by tftp 100000 kernel.bin (microblaze kernel in bin format with rootfs and dtb in it) mwr 0xXXXXXX 0x1 (turn on microblaze via custom logic which jumps to 0x100000) tftp 10000000 image.ub (download arm kernel) bootm 0x10000000 (boot arm kernel) I think that will be much better to have both kernels in one FIT image and and use two configurations. One for microblaze kernel and second for arm kernel and boot it with one bootm command. Simon: Is this configuration even supported by FIT image? Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform

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[U-Boot] [PATCH 6/10] driver/ifc: define nand_spl_load_image() for SPL
by Prabhakar Kushwaha 02 Apr '14

02 Apr '14

nand_spl_load_image() can also be used for non TPL framework. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- drivers/mtd/nand/fsl_ifc_spl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index 2f82f7c..8a7a3a3 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -88,7 +88,7 @@ static inline int bad_block(uchar *marker, int port_size) return __raw_readw((u16 *)marker) != 0xffff; } -#ifdef CONFIG_TPL_BUILD +#if defined(CONFIG_TPL_BUILD) || defined(CONFIG_SPL_BUILD) int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) #else static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst) @@ -221,7 +221,7 @@ static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst) * Defines a static function nand_load_image() here, because non-static makes * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes) */ -#ifndef CONFIG_TPL_BUILD +#if !defined(CONFIG_TPL_BUILD) && !defined(CONFIG_SPL_BUILD) #define nand_spl_load_image(offs, uboot_size, vdst) \ nand_load(offs, uboot_size, vdst) #endif -- 1.7.9.5

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[U-Boot] CONFIG_REMAKE_ELF for aarch64
by York Sun 02 Apr '14

02 Apr '14

Scott, I am having a problem recreating u-boot.elf for aarch64 targets. The file is OK when Ttext is aligned with 64KB boundary, for example 0x30000000. But if I use 0x30001000 as the text base, the result u-boot.elf has additional offset of 0x10000. For example, the first instruction should be (from objdump) 30001000: 1400000a b 30001028 But it is 30011000: 1400000a b 30011028 My gcc version is gcc version 4.8.3 20131202 (prerelease) (crosstool-NG linaro-1.13.1-4.8-2013.12 - Linaro GCC 2013.11) GNU ld (crosstool-NG linaro-1.13.1-4.8-2013.12 - Linaro GCC 2013.11) 2.24.0.20131220 Supported emulations: aarch64linux aarch64elf aarch64elf32 aarch64elf32b aarch64elfb armelf armelfb aarch64linuxb aarch64linux32 aarch64linux32b armelfb_linux_eabi armelf_linux_eabi I am hoping you or someone familiar with ABI or something related and shed some light. York

2 2

[U-Boot] [PATCH] config:trats2: Change u-boot's TEXT_BASE from 0x78100000 to 0x43e00000
by Lukasz Majewski 02 Apr '14

02 Apr '14

The u-boot's image TEXT_BASE needs to be changed to 0x43e00000 from 0x78100000. This change provides compatibility with other trats2 (RD_PQ) devices (http://download.tizen.org/releases/system/). Signed-off-by: Lukasz Majewski <l.majewski(a)samsung.com> Cc: Minkyu Kang <mk7.kang(a)samsung.com> --- include/configs/trats2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 823a8ae..85cf4aa 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -36,7 +36,7 @@ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) -#define CONFIG_SYS_TEXT_BASE 0x78100000 +#define CONFIG_SYS_TEXT_BASE 0x43e00000 #include <linux/sizes.h> /* Size of malloc() pool */ -- 1.7.10.4

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[U-Boot] [PATCH] mmc: fsl_esdhc: add controller reset in case of data related errors too
by Andrew Gabbasov 02 Apr '14

02 Apr '14

The controller reset is performed now if command error occurs. This commit adds the reset for the case of data related errors too. Signed-off-by: Andrew Gabbasov <andrew_gabbasov(a)mentor.com> --- drivers/mmc/fsl_esdhc.c | 63 +++++++++++++++++++++++++++-------------------- 1 file changed, 36 insertions(+), 27 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index f4d3132..dfb1cc3 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -265,6 +265,7 @@ static void check_and_invalidate_dcache_range static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { + int err = 0; uint xfertyp; uint irqstat; struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; @@ -296,8 +297,6 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) /* Set up for a data transfer if we have one */ if (data) { - int err; - err = esdhc_setup_data(mmc, data); if(err) return err; @@ -325,27 +324,15 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) irqstat = esdhc_read32(&regs->irqstat); - /* Reset CMD and DATA portions on error */ - if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) { - esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) | - SYSCTL_RSTC); - while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC) - ; - - if (data) { - esdhc_write32(&regs->sysctl, - esdhc_read32(&regs->sysctl) | - SYSCTL_RSTD); - while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD)) - ; - } + if (irqstat & CMD_ERR) { + err = COMM_ERR; + goto out; } - if (irqstat & CMD_ERR) - return COMM_ERR; - - if (irqstat & IRQSTAT_CTOE) - return TIMEOUT; + if (irqstat & IRQSTAT_CTOE) { + err = TIMEOUT; + goto out; + } /* Workaround for ESDHC errata ENGcm03648 */ if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { @@ -360,7 +347,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (timeout <= 0) { printf("Timeout waiting for DAT0 to go high!\n"); - return TIMEOUT; + err = TIMEOUT; + goto out; } } @@ -387,20 +375,41 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) do { irqstat = esdhc_read32(&regs->irqstat); - if (irqstat & IRQSTAT_DTOE) - return TIMEOUT; + if (irqstat & IRQSTAT_DTOE) { + err = TIMEOUT; + goto out; + } - if (irqstat & DATA_ERR) - return COMM_ERR; + if (irqstat & DATA_ERR) { + err = COMM_ERR; + goto out; + } } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); #endif if (data->flags & MMC_DATA_READ) check_and_invalidate_dcache_range(cmd, data); } +out: + /* Reset CMD and DATA portions on error */ + if (err) { + esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) | + SYSCTL_RSTC); + while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC) + ; + + if (data) { + esdhc_write32(&regs->sysctl, + esdhc_read32(&regs->sysctl) | + SYSCTL_RSTD); + while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD)) + ; + } + } + esdhc_write32(&regs->irqstat, -1); - return 0; + return err; } static void set_sysctl(struct mmc *mmc, uint clock) -- 1.7.10.4

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