February 2014 - U-Boot

[U-Boot] Please pull u-boot-mpc85xx master
by York Sun 04 Feb '14

04 Feb '14

Tom, The following changes since commit 07e2822d158940a0e8ba45b6ab0344ffa1011a07: board: nios2: Check if flash is configured before calling early_flash_cmd_reset() (2014-01-29 16:44:18 -0500) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master for you to fetch changes up to 1b4175d6fa12b8012c119889ad5cc1e65c3cf6ba: driver/ifc:Change accessor function to take care of endianness (2014-02-03 08:38:51 -0800) ---------------------------------------------------------------- Nikhil Badola (1): powerpc/usb: Enable dual phy for T1040 Prabhakar Kushwaha (6): driver/fsl_pci:Update print to display PCIe generation powerpc/mpc85xx:Fix README to show correct flash memory map powerpc/mpc85xx: Update serdes protocols for T1040 boards/t1040qds: Adds ethernet support for T1040 powerpc/t104xrdb: Update T1042RDB.h in config folder driver/ifc:Change accessor function to take care of endianness Priyanka Jain (2): powerpc/t104xrdb: Update T1040RDB.h in config folder powerpc/t104xrdb: Add basic ethernet support Rainer Boschung (2): kmp204x: support for QRIO1 bootcounter kmp204x: I2C deblocking support Valentin Longchamp (7): kmp204x: introduce QRIO GPIO functions kmp204x: implement workaround for A-006559 kmp204x: add support for the kmcoge4 board kmp204x: update I2C field of RCW KM: add the KM_UBI_PART_BOOT_OPTS #define kmp204x: enable support for SPANSION SPI NOR kmp204x: initial support for PCIe FPGA configuration poonam aggrwal (1): powerpc/mpc85xx: Update LIODNs for T1040 README | 6 + arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 2 + arch/powerpc/cpu/mpc85xx/t1040_ids.c | 36 -- arch/powerpc/cpu/mpc85xx/t1040_serdes.c | 63 ++- arch/powerpc/include/asm/config_mpc85xx.h | 6 +- arch/powerpc/include/asm/fsl_serdes.h | 8 +- arch/powerpc/include/asm/immap_85xx.h | 11 + board/freescale/t1040qds/Makefile | 1 + board/freescale/t1040qds/README | 6 +- board/freescale/t1040qds/eth.c | 492 ++++++++++++++++++++++++ board/freescale/t1040qds/t1040qds.c | 1 + board/freescale/t104xrdb/Makefile | 1 + board/freescale/t104xrdb/README | 6 +- board/freescale/t104xrdb/eth.c | 72 ++++ board/keymile/kmp204x/Makefile | 2 +- board/keymile/kmp204x/kmp204x.c | 128 +++--- board/keymile/kmp204x/kmp204x.h | 10 + board/keymile/kmp204x/pbi.cfg | 10 + board/keymile/kmp204x/pci.c | 85 ++++ board/keymile/kmp204x/qrio.c | 146 +++++++ board/keymile/kmp204x/rcw_kmp204x.cfg | 2 +- boards.cfg | 1 + doc/README.b4860qds | 4 +- drivers/mtd/nand/fsl_ifc_nand.c | 243 ++++++------ drivers/mtd/nand/fsl_ifc_spl.c | 60 +-- drivers/net/fm/t1040.c | 56 +++ drivers/pci/fsl_pci_init.c | 4 +- include/configs/T1040QDS.h | 5 +- include/configs/T1040RDB.h | 24 +- include/configs/T1042RDB_PI.h | 20 +- include/configs/km/keymile-common.h | 10 +- include/configs/km/kmp204x-common.h | 21 +- include/configs/kmp204x.h | 7 +- include/fsl_ifc.h | 42 +- 34 files changed, 1230 insertions(+), 361 deletions(-) create mode 100644 board/freescale/t1040qds/eth.c create mode 100644 board/freescale/t104xrdb/eth.c create mode 100644 board/keymile/kmp204x/qrio.c Thanks, York

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[U-Boot] [GIT PULL] Uartlite patch
by Michal Simek 04 Feb '14

04 Feb '14

Hi Tom, I have one pending uartlite patch which I would like to add to the mainline. Can you please add it to your tree? Thanks, Michal The following changes since commit b44bd2c73c4cfb6e3b9e7f8cf987e8e39aa74a0b: Prepare v2014.01 (2014-01-20 17:52:59 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git serial for you to fetch changes up to 8c3bd6b596300d0ade265329f44832e89ef54a22: serial: uartlite: Reset RX/TX in init (2014-02-04 16:48:57 +0100) ---------------------------------------------------------------- Michal Simek (1): serial: uartlite: Reset RX/TX in init drivers/serial/serial_xuartlite.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform

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[U-Boot] [GIT PULL] Microblaze/Zynq network fixes
by Michal Simek 04 Feb '14

04 Feb '14

Hi Joe, I have two pending patches for xilinx ethernet drivers. Can you please add them to your net tree? Thanks, Michal The following changes since commit b44bd2c73c4cfb6e3b9e7f8cf987e8e39aa74a0b: Prepare v2014.01 (2014-01-20 17:52:59 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git net for you to fetch changes up to 6f9b93723a39dc6d6231c842bb0166bd6258ee53: net: axi_emac: Check if phy was correctly detected (2014-02-04 16:42:45 +0100) ---------------------------------------------------------------- Michal Simek (2): net: gem: Check if phy was correctly detected net: axi_emac: Check if phy was correctly detected drivers/net/xilinx_axi_emac.c | 4 ++++ drivers/net/zynq_gem.c | 5 +++++ 2 files changed, 9 insertions(+) -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform

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[U-Boot] [GIT PULL] microblaze changes
by Michal Simek 04 Feb '14

04 Feb '14

Hi Tom, please pull these Microblaze changes to your tree. Thanks, Michal The following changes since commit 07e2822d158940a0e8ba45b6ab0344ffa1011a07: board: nios2: Check if flash is configured before calling early_flash_cmd_reset() (2014-01-29 16:44:18 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git master for you to fetch changes up to 9d24274509cdd463992dc1fb1a2820d6a4b6d21d: microblaze: Add SPL support (2014-02-04 16:39:50 +0100) ---------------------------------------------------------------- Michal Simek (4): microblaze: Show u-boot banner microblaze: Report priviledged or stack protection exception microblaze: Enable buffer write for NOR flashes microblaze: Add SPL support arch/microblaze/cpu/Makefile | 1 + arch/microblaze/cpu/exception.c | 3 +++ arch/microblaze/cpu/spl.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/microblaze/cpu/start.S | 12 ++++++++++++ arch/microblaze/cpu/timer.c | 8 +++++++- arch/microblaze/cpu/u-boot-spl.lds | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/microblaze/include/asm/spl.h | 16 ++++++++++++++++ arch/microblaze/include/asm/u-boot.h | 1 + arch/microblaze/lib/board.c | 18 +++++++++++++++++- include/configs/microblaze-generic.h | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 10 files changed, 231 insertions(+), 3 deletions(-) create mode 100644 arch/microblaze/cpu/spl.c create mode 100644 arch/microblaze/cpu/u-boot-spl.lds create mode 100644 arch/microblaze/include/asm/spl.h -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform

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[U-Boot] [GIT PULL] clk command
by Michal Simek 04 Feb '14

04 Feb '14

Hi Tom, please pull this one patch to your tree. It is adding new clk command which I want to use for zynq. When it is applied I will prepare zynq specific patches which will go through arm tree. i.MXes are other users for this as was pointed by Stefano. He also gave me his ACK for this. Thanks, Michal The following changes since commit 07e2822d158940a0e8ba45b6ab0344ffa1011a07: board: nios2: Check if flash is configured before calling early_flash_cmd_reset() (2014-01-29 16:44:18 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git clk for you to fetch changes up to 08d0d6f32ecf75a6c5dede5fc9ee84b84d8b90e7: common: Add new clk command (2014-02-04 16:32:20 +0100) ---------------------------------------------------------------- Michal Simek (1): common: Add new clk command README | 1 + common/Makefile | 1 + common/cmd_clk.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/clk.h | 6 ++++++ include/config_cmd_all.h | 1 + 5 files changed, 60 insertions(+) create mode 100644 common/cmd_clk.c create mode 100644 include/clk.h -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform

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[U-Boot] [PATCH v4 2/5] sf: Optimize flash features code
by Jagannadha Sutradharudu Teki 04 Feb '14

04 Feb '14

- Shrink spi_slave {} - Shrink spi_flash_params {} - Documentation for sf features Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- doc/SPI/README.sf-features | 121 +++++++++++++++++++++++++++++ drivers/mtd/spi/sf.c | 4 +- drivers/mtd/spi/sf_internal.h | 1 - drivers/mtd/spi/sf_ops.c | 8 +- drivers/mtd/spi/sf_params.c | 172 +++++++++++++++++++++--------------------- drivers/mtd/spi/sf_probe.c | 71 ++++++++--------- include/spi.h | 42 ++++------- include/spi_flash.h | 34 ++++----- 8 files changed, 272 insertions(+), 181 deletions(-) create mode 100644 doc/SPI/README.sf-features diff --git a/doc/SPI/README.sf-features b/doc/SPI/README.sf-features new file mode 100644 index 0000000..e203bc0 --- /dev/null +++ b/doc/SPI/README.sf-features @@ -0,0 +1,121 @@ +SPI FLASH feature enhancements: +============================== + +This document describes how to extend the current data structures in spi subsystem +for making use of new flash features/operations w.r.t to controller driver support. + +1. spi_slave: + +struct spi_slave { + .......... + u32 mode; + ........ +}; + +@mode can be used to expose the SPI RX/TX operation modes, bus options and +few flags which are used to extended the flash specific features/operations +- include/spi.h + +mode: +- SPI_TX_QPP: 4-wire tx transfer +- SPI_RX_SLOW: 1-wire rx transfer +- SPI_RX_DUAL: 2-wire rx transfer +- SPI_RX_DUAL_IO: 2-wire io rx transfer +- SPI_RX_QUAD: 4-wire rx transfer +- SPI_RX_QUAD_IO: 4-wire io rx transfer +- SPI_SHARED: bus shared with two slaves +- SPI_SEPARATED: bus parallel with two slaves +- SPI_U_PAGE: access second slave in bus shared + +2. spi_flash_params: + +struct spi_flash_params { + ................ + u16 flags; + .............. +}; + +@flags can be use to verify the flash supported features/operations with respect +to controller driven through @mode and also some internal flash specific +operations - include/spi_flash.h + +flags: +- SST_WP: SST flash write protection +- SECT_4K: 4K erase sector +- SECT_32K: 32 erase sector +- E_FSR: Flag status register for erase/write for micron < 256MB flash +- WR_QPP: Quad page program +- RD_SLOW: Array slow read +- RD_DUAL: Dual fast read +- RD_DUAL_IO: Dual IO read +- RD_QUAD: Quad fast read +- RD_QUAD_IO: Quad IO read +- RD_2WIRE: All 2-wire read commands +- RD_FULL: All read commands +- ALL_CMDS: All read and write commands [1] + +3. spi_flash: + +struct spi_flash { + ............... + u8 dual_flash; + u8 shift; + u8 poll_cmd; + u8 erase_cmd; + u8 read_cmd; + u8 write_cmd; + u8 dummy_byte; + ................ +}; + +Few varibles from spi_flash {} can be used to perform the internal operations +based on the selected flash features/operations from spi_slave {} and +spi_flash_params {} - include/spi_flash.h + +@dual_flash: flash can be operated in dual flash [2] +@shift: variable shift operator useful for dual parallel +@poll_cmd: find the read_status or flag_status for polling erase/write operations +@erase_cmd: discovered erase command +@read_cmd: discovered read command +@write_cmd: discovered write command +@dummy_byte: read dummy_byte based on read dummy_cycles. + +dummy byte is determined based on the dummy cycles of a particular command. +Fast commands - dummy_byte = dummy_cycles/8 +I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8 +For I/O commands except cmd[0] everything goes on no.of lines based on +particular command but in case of fast commands except data all go on +single line irrespective of command. + +4. Usage: + +In drivers/spi/*.c assign spi_slave {} with supported features through mode. +Ex: drivers/spi/ti_qspi.c + +struct ti_qspi_slave { + ................ + struct spi_slave slave; + .............. +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + ......... + + qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs); + if (!qslave) { + printf("SPI_error: Fail to allocate ti_qspi_slave\n"); + return NULL; + } + + qslave->slave.mode = SPI_TX_QPP | SPI_RX_QUAD; + ........ +} + +[1] http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf +[2] doc/SPI/README.dual-flash + +-- +Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> +Sat Jan 18 14:44:28 IST 2014 diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c index 664e860..b4d7e6c 100644 --- a/drivers/mtd/spi/sf.c +++ b/drivers/mtd/spi/sf.c @@ -19,8 +19,8 @@ static int spi_flash_read_write(struct spi_slave *spi, int ret; #ifdef CONFIG_SF_DUAL_FLASH - if (spi->flags & SPI_XFER_U_PAGE) - flags |= SPI_XFER_U_PAGE; + if (spi->mode & SPI_U_PAGE) + flags |= SPI_U_PAGE; #endif if (data_len == 0) flags |= SPI_XFER_END; diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 6bcd522..47d5ac2 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -67,7 +67,6 @@ /* SST specific */ #ifdef CONFIG_SPI_FLASH_SST -# define SST_WP 0x01 /* Supports AAI word program */ # define CMD_SST_BP 0x02 /* Byte Program */ # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index ef91b92..20adeb9 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -139,9 +139,9 @@ static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr) case SF_DUAL_STACKED_FLASH: if (*addr >= (flash->size >> 1)) { *addr -= flash->size >> 1; - flash->spi->flags |= SPI_XFER_U_PAGE; + flash->spi->mode |= SPI_U_PAGE; } else { - flash->spi->flags &= ~SPI_XFER_U_PAGE; + flash->spi->mode &= ~SPI_U_PAGE; } break; case SF_DUAL_PARALLEL_FLASH: @@ -171,8 +171,8 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) } #ifdef CONFIG_SF_DUAL_FLASH - if (spi->flags & SPI_XFER_U_PAGE) - flags |= SPI_XFER_U_PAGE; + if (spi->mode & SPI_U_PAGE) + flags |= SPI_U_PAGE; #endif ret = spi_xfer(spi, 8, &cmd, NULL, flags); if (ret) { diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index eb372b7..9b394f2 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -14,106 +14,106 @@ /* SPI/QSPI flash device params structure */ const struct spi_flash_params spi_flash_params_table[] = { #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ - {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, 0, SECT_4K}, - {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, 0, SECT_4K}, - {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, 0, SECT_4K}, - {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, 0, SECT_4K}, - {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, 0, SECT_4K}, - {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, 0, SECT_4K}, - {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, 0, SECT_4K}, - {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, 0, SECT_4K}, + {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, SECT_4K}, + {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, SECT_4K}, + {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, SECT_4K}, + {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, SECT_4K}, + {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, SECT_4K}, + {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, SECT_4K}, + {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, SECT_4K}, + {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, SECT_4K}, #endif #ifdef CONFIG_SPI_FLASH_EON /* EON */ - {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0, 0}, - {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, 0, SECT_4K}, - {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0, 0}, - {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0, 0}, + {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0}, + {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, SECT_4K}, + {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0}, + {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0}, #endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ - {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, 0, SECT_4K}, - {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, 0, SECT_4K}, + {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, SECT_4K}, + {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, SECT_4K}, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ - {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0, 0}, - {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0, 0}, - {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0, 0}, - {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0}, - {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0}, - {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0}, - {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, - {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP}, - {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP}, - {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0}, + {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0}, + {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0}, + {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0}, + {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0}, + {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0}, + {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, ALL_CMDS}, + {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, ALL_CMDS}, + {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, ALL_CMDS}, + {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, ALL_CMDS}, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ - {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0}, - {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0}, - {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0}, - {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0}, - {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP}, - {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP}, - {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP}, - {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP}, - {"S25FL128S_256K", 0x012018, 0x4d00, 256 * 1024, 64, RD_FULL, WR_QPP}, - {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP}, - {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP}, - {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP}, - {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP}, - {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP}, + {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0}, + {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0}, + {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0}, + {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0}, + {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, ALL_CMDS}, + {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, ALL_CMDS}, + {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, ALL_CMDS}, + {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, ALL_CMDS}, + {"S25FL128S_256K", 0x012018, 0x4d00, 256 * 1024, 64, ALL_CMDS}, + {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, ALL_CMDS}, + {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, ALL_CMDS}, + {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, ALL_CMDS}, + {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, ALL_CMDS}, + {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, ALL_CMDS}, #endif #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ - {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0}, - {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0, 0}, - {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0}, - {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0}, - {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0}, - {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0}, - {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0}, - {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0}, - {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, - {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, - {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, - {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, - {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, - {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, + {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0}, + {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0}, + {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0}, + {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0}, + {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0}, + {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0}, + {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0}, + {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0}, + {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, ALL_CMDS | SECT_4K}, + {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, ALL_CMDS | SECT_4K}, + {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, ALL_CMDS | SECT_4K}, + {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, ALL_CMDS | SECT_4K}, + {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, ALL_CMDS}, + {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, ALL_CMDS}, + {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, ALL_CMDS | SECT_4K}, + {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, ALL_CMDS | SECT_4K}, + {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, ALL_CMDS | E_FSR | SECT_4K}, + {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, ALL_CMDS | E_FSR | SECT_4K}, + {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, ALL_CMDS | E_FSR | SECT_4K}, + {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, ALL_CMDS | E_FSR | SECT_4K}, #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */ - {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP}, - {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP}, - {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, 0, SECT_4K | SST_WP}, - {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, 0, SECT_4K | SST_WP}, - {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, 0, SECT_4K}, - {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, 0, SECT_4K | SST_WP}, - {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, 0, SECT_4K | SST_WP}, - {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, 0, SECT_4K | SST_WP}, - {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP}, - {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP}, + {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WP}, + {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WP}, + {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WP}, + {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WP}, + {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, SECT_4K}, + {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WP}, + {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WP}, + {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WP}, + {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WP}, + {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WP}, #endif #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ - {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0, 0}, - {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0, 0}, - {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0, 0}, - {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, 0, SECT_4K}, - {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K}, - {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K}, - {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K}, - {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, + {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0}, + {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0}, + {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0}, + {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, SECT_4K}, + {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, SECT_4K}, + {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, SECT_4K}, + {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, SECT_4K}, + {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, ALL_CMDS | SECT_4K}, + {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, ALL_CMDS | SECT_4K}, + {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, ALL_CMDS | SECT_4K}, + {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, ALL_CMDS | SECT_4K}, + {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, ALL_CMDS | SECT_4K}, + {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, ALL_CMDS | SECT_4K}, + {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, ALL_CMDS | SECT_4K}, + {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, ALL_CMDS | SECT_4K}, + {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, ALL_CMDS | SECT_4K}, + {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, ALL_CMDS | SECT_4K}, + {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, ALL_CMDS | SECT_4K}, #endif /* * Note: diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index e84ab13..036f48d 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -19,15 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* Read commands array */ -static u8 spi_read_cmds_array[] = { - CMD_READ_ARRAY_SLOW, - CMD_READ_DUAL_OUTPUT_FAST, - CMD_READ_DUAL_IO_FAST, - CMD_READ_QUAD_OUTPUT_FAST, - CMD_READ_QUAD_IO_FAST, -}; - #ifdef CONFIG_SPI_FLASH_MACRONIX static int spi_flash_set_qeb_mxic(struct spi_flash *flash) { @@ -100,7 +91,6 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, { const struct spi_flash_params *params; struct spi_flash *flash; - u8 cmd; u16 jedec = idcode[1] << 8 | idcode[2]; u16 ext_jedec = idcode[3] << 8 | idcode[4]; @@ -136,13 +126,13 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash->dual_flash = flash->spi->option; /* Assign spi_flash ops */ + flash->read = spi_flash_cmd_read_ops; + flash->erase = spi_flash_cmd_erase_ops; flash->write = spi_flash_cmd_write_ops; #ifdef CONFIG_SPI_FLASH_SST if (params->flags & SST_WP) flash->write = sst_write_wp; #endif - flash->erase = spi_flash_cmd_erase_ops; - flash->read = spi_flash_cmd_read_ops; /* Compute the flash size */ flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; @@ -166,18 +156,38 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash->erase_size = flash->sector_size; } - /* Look for the fastest read cmd */ - cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx); - if (cmd) { - cmd = spi_read_cmds_array[cmd - 1]; - flash->read_cmd = cmd; - } else { - /* Go for default supported read cmd */ - flash->read_cmd = CMD_READ_ARRAY_FAST; + /* Compute read command and dummy_byte */ + flash->read_cmd = CMD_READ_ARRAY_FAST; + flash->dummy_byte = 1; + switch (SPI_RX_MODES & flash->spi->mode) { + case SPI_RX_SLOW: + if (params->flags & RD_SLOW) { + flash->read_cmd = CMD_READ_ARRAY_FAST; + flash->dummy_byte = 0; + } + break; + case SPI_RX_DUAL: + if (params->flags & RD_DUAL) + flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST; + break; + case SPI_RX_DUAL_IO: + if (params->flags & RD_DUAL_IO) + flash->read_cmd = CMD_READ_DUAL_IO_FAST; + break; + case SPI_RX_QUAD: + if (params->flags & RD_QUAD) + flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST; + break; + case SPI_RX_QUAD_IO: + if (params->flags & RD_QUAD_IO) { + flash->read_cmd = CMD_READ_QUAD_IO_FAST; + flash->dummy_byte = 2; + } + break; } /* Not require to look for fastest only two write cmds yet */ - if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP) + if (flash->spi->mode & SPI_TX_QPP && params->flags & WR_QPP) flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; else /* Go for default supported write cmd */ @@ -193,25 +203,6 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, } } - /* Read dummy_byte: dummy byte is determined based on the - * dummy cycles of a particular command. - * Fast commands - dummy_byte = dummy_cycles/8 - * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8 - * For I/O commands except cmd[0] everything goes on no.of lines - * based on particular command but incase of fast commands except - * data all go on single line irrespective of command. - */ - switch (flash->read_cmd) { - case CMD_READ_QUAD_IO_FAST: - flash->dummy_byte = 2; - break; - case CMD_READ_ARRAY_SLOW: - flash->dummy_byte = 0; - break; - default: - flash->dummy_byte = 1; - } - /* Poll cmd selection */ flash->poll_cmd = CMD_READ_STATUS; #ifdef CONFIG_SPI_FLASH_STMICRO diff --git a/include/spi.h b/include/spi.h index ffd6647..2ca9631 100644 --- a/include/spi.h +++ b/include/spi.h @@ -30,29 +30,10 @@ #define SPI_XFER_MMAP 0x08 /* Memory Mapped start */ #define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */ #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) -#define SPI_XFER_U_PAGE (1 << 5) - -/* SPI TX operation modes */ -#define SPI_OPM_TX_QPP 1 << 0 - -/* SPI RX operation modes */ -#define SPI_OPM_RX_AS 1 << 0 -#define SPI_OPM_RX_DOUT 1 << 1 -#define SPI_OPM_RX_DIO 1 << 2 -#define SPI_OPM_RX_QOF 1 << 3 -#define SPI_OPM_RX_QIOF 1 << 4 -#define SPI_OPM_RX_EXTN SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \ - SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \ - SPI_OPM_RX_QIOF - -/* SPI bus connection options */ -#define SPI_CONN_DUAL_SHARED 1 << 0 -#define SPI_CONN_DUAL_SEPARATED 1 << 1 /* Header byte that marks the start of the message */ #define SPI_PREAMBLE_END_BYTE 0xec - -#define SPI_DEFAULT_WORDLEN 8 +#define SPI_DEFAULT_WORDLEN 8 /** * struct spi_slave - Representation of a SPI slave @@ -61,25 +42,30 @@ * * @bus: ID of the bus that the slave is attached to. * @cs: ID of the chip select connected to the slave. - * @op_mode_rx: SPI RX operation mode. - * @op_mode_tx: SPI TX operation mode. * @wordlen: Size of SPI word in number of bits * @max_write_size: If non-zero, the maximum number of bytes which can * be written at once, excluding command bytes. + * @mode: SPI RX/TX operation modes, bus options and few flags. * @memory_map: Address of read-only SPI flash access. - * @option: Varies SPI bus options - separate, shared bus. - * @flags: Indication of SPI flags. */ struct spi_slave { unsigned int bus; unsigned int cs; - u8 op_mode_rx; - u8 op_mode_tx; unsigned int wordlen; unsigned int max_write_size; + u16 mode; +#define SPI_TX_QPP (1 << 0) /* 4-wire tx transfer */ +#define SPI_RX_SLOW (1 << 1) /* 1-wire rx transfer */ +#define SPI_RX_DUAL (1 << 2) /* 2-wire rx transfer */ +#define SPI_RX_DUAL_IO (1 << 3) /* 2-wire io rx transfer */ +#define SPI_RX_QUAD (1 << 4) /* 4-wire rx transfer */ +#define SPI_RX_QUAD_IO (1 << 5) /* 4-wire io rx transfer */ +#define SPI_RX_MODES (SPI_RX_SLOW | SPI_RX_DUAL | SPI_RX_DUAL_IO | \ + SPI_RX_QUAD | SPI_RX_QUAD_IO) +#define SPI_SHARED (1 << 6) /* bus shared with two slaves */ +#define SPI_SEPARATED (1 << 7) /* bus parallel with two slaves */ +#define SPI_U_PAGE (1 << 8) /* access second slave in bus shared */ void *memory_map; - u8 option; - u8 flags; }; /** diff --git a/include/spi_flash.h b/include/spi_flash.h index f79f0ea..3a25da0 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -19,23 +19,6 @@ #include <linux/types.h> #include <linux/compiler.h> -/* sf param flags */ -#define SECT_4K 1 << 1 -#define SECT_32K 1 << 2 -#define E_FSR 1 << 3 -#define WR_QPP 1 << 4 - -/* Enum list - Full read commands */ -enum spi_read_cmds { - ARRAY_SLOW = 1 << 0, - DUAL_OUTPUT_FAST = 1 << 1, - DUAL_IO_FAST = 1 << 2, - QUAD_OUTPUT_FAST = 1 << 3, - QUAD_IO_FAST = 1 << 4, -}; -#define RD_EXTN ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST -#define RD_FULL RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST - /* Dual SPI flash memories */ enum spi_dual_flash { SF_SINGLE_FLASH = 0, @@ -51,8 +34,7 @@ enum spi_dual_flash { * @ext_jedec: Device ext_jedec ID * @sector_size: Sector size of this device * @nr_sectors: No.of sectors on this device - * @e_rd_cmd: Enum list for read commands - * @flags: Importent param, for flash specific behaviour + * @flags: Importent params, for flash specific behaviour */ struct spi_flash_params { const char *name; @@ -60,8 +42,20 @@ struct spi_flash_params { u16 ext_jedec; u32 sector_size; u32 nr_sectors; - u8 e_rd_cmd; u16 flags; +#define SST_WP (1 << 0) /* SST write protection */ +#define SECT_4K (1 << 1) /* 4K erase sector */ +#define SECT_32K (1 << 2) /* 32K erase sector */ +#define E_FSR (1 << 3) /* Enable Flag status register */ +#define WR_QPP (1 << 4) /* Quad page program */ +#define RD_SLOW (1 << 5) /* Array slow read */ +#define RD_DUAL (1 << 6) /* Dual fast read */ +#define RD_DUAL_IO (1 << 7) /* Dual IO fast read */ +#define RD_QUAD (1 << 8) /* Quad fast read */ +#define RD_QUAD_IO (1 << 9) /* Quad IO fast read */ +#define RD_2WIRE (RD_SLOW | RD_DUAL | RD_DUAL_IO) +#define RD_FULL (RD_2WIRE | RD_QUAD | RD_QUAD_IO) +#define ALL_CMDS (WR_QPP | RD_FULL) }; extern const struct spi_flash_params spi_flash_params_table[]; -- 1.8.3

2 1

[U-Boot] [PATCH v4 1/5] sf: ops: Squash the malloc+memset combo
by Jagannadha Sutradharudu Teki 04 Feb '14

04 Feb '14

Squash the malloc()+memset() combo in favor of calloc(). Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- drivers/mtd/spi/sf_ops.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 1f1bb36..ef91b92 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <errno.h> #include <malloc.h> #include <spi.h> #include <spi_flash.h> @@ -381,8 +382,11 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, } cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; - cmd = malloc(cmdsz); - memset(cmd, 0, cmdsz); + cmd = calloc(1, cmdsz); + if (!cmd) { + debug("SF: Failed to allocate cmd\n"); + return -ENOMEM; + } cmd[0] = flash->read_cmd; while (len) { -- 1.8.3

2 1

[U-Boot] [PATCH v3] designware_i2c: Enhance DesignWare I2C driver address support
by Chin Liang See 04 Feb '14

04 Feb '14

Enhance the DesignWare I2C driver to support address length more than 1 byte. This enhancement is required as some I2C slave device such as EEPROM chip might have 16 bit address byte. Signed-off-by: Chin Liang See <clsee(a)altera.com> Acked-by: Alexey Brodkin <Alexey.Brodkin(a)synopsys.com> Cc: Tom Rini <trini(a)ti.com> cc: Armando Visconti <armando.visconti(a)st.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Cc: Heiko Schocher <hs(a)denx.de> --- Changes for v3 - Re-based the patch to latest head Changes for v2 - Removed the function check_params() --- drivers/i2c/designware_i2c.c | 41 +++++++++-------------------------------- 1 file changed, 9 insertions(+), 32 deletions(-) diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 9ed9295..deea4f8 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -197,35 +197,18 @@ static int i2c_wait_for_bb(void) return 0; } -/* check parameters for i2c_read and i2c_write */ -static int check_params(uint addr, int alen, uchar *buffer, int len) -{ - if (buffer == NULL) { - printf("Buffer is invalid\n"); - return 1; - } - - if (alen > 1) { - printf("addr len %d not supported\n", alen); - return 1; - } - - if (addr + len > 256) { - printf("address out of range\n"); - return 1; - } - - return 0; -} - -static int i2c_xfer_init(uchar chip, uint addr) +static int i2c_xfer_init(uchar chip, uint addr, int alen) { if (i2c_wait_for_bb()) return 1; i2c_setaddress(chip); - writel(addr, &i2c_regs_p->ic_cmd_data); - + while (alen) { + alen--; + /* high byte address going out first */ + writel((addr >> (alen * 8)) & 0xff, + &i2c_regs_p->ic_cmd_data); + } return 0; } @@ -285,10 +268,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) addr); #endif - if (check_params(addr, alen, buffer, len)) - return 1; - - if (i2c_xfer_init(chip, addr)) + if (i2c_xfer_init(chip, addr, alen)) return 1; start_time_rx = get_timer(0); @@ -345,10 +325,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) addr); #endif - if (check_params(addr, alen, buffer, len)) - return 1; - - if (i2c_xfer_init(chip, addr)) + if (i2c_xfer_init(chip, addr, alen)) return 1; start_time_tx = get_timer(0); -- 1.7.9.5

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[U-Boot] [PATCH v2] designware_i2c: Enhance DesignWare I2C driver address support
by Chin Liang See 04 Feb '14

04 Feb '14

Enhance the DesignWare I2C driver to support address length more than 1 byte. This enhancement is required as some I2C slave device such as EEPROM chip might have 16 bit address byte. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Alexey Brodkin <Alexey.Brodkin(a)synopsys.com> Cc: Tom Rini <trini(a)ti.com> cc: Armando Visconti <armando.visconti(a)st.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Cc: Heiko Schocher <hs(a)denx.de> Cc: Vipin KUMAR <vipin.kumar(a)st.com> Cc: Mischa Jonker <mjonker(a)synopsys.com> --- Changes for v2 - Removed the function check_params() --- drivers/i2c/designware_i2c.c | 41 +++++++++-------------------------------- 1 file changed, 9 insertions(+), 32 deletions(-) diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index cb2ac04..5b8482a 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -197,35 +197,18 @@ static int i2c_wait_for_bb(void) return 0; } -/* check parameters for i2c_read and i2c_write */ -static int check_params(uint addr, int alen, uchar *buffer, int len) -{ - if (buffer == NULL) { - printf("Buffer is invalid\n"); - return 1; - } - - if (alen > 1) { - printf("addr len %d not supported\n", alen); - return 1; - } - - if (addr + len > 256) { - printf("address out of range\n"); - return 1; - } - - return 0; -} - -static int i2c_xfer_init(uchar chip, uint addr) +static int i2c_xfer_init(uchar chip, uint addr, int alen) { if (i2c_wait_for_bb()) return 1; i2c_setaddress(chip); - writel(addr, &i2c_regs_p->ic_cmd_data); - + while (alen) { + alen--; + /* high byte address going out first */ + writel((addr >> (alen * 8)) & 0xff, + &i2c_regs_p->ic_cmd_data); + } return 0; } @@ -266,10 +249,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { unsigned long start_time_rx; - if (check_params(addr, alen, buffer, len)) - return 1; - - if (i2c_xfer_init(chip, addr)) + if (i2c_xfer_init(chip, addr, alen)) return 1; start_time_rx = get_timer(0); @@ -307,10 +287,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) int nb = len; unsigned long start_time_tx; - if (check_params(addr, alen, buffer, len)) - return 1; - - if (i2c_xfer_init(chip, addr)) + if (i2c_xfer_init(chip, addr, alen)) return 1; start_time_tx = get_timer(0); -- 1.7.9.5

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[U-Boot] [PATCH] xilinx_spi: Move timeout calculation out of the loop
by Michal Simek 04 Feb '14

04 Feb '14

Timeout calculation should be out of the data loop. This patch increase spi bandwidth for 30%. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/spi/xilinx_spi.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 5ac0184..56d99d1 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -149,6 +149,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, const unsigned char *txp = dout; unsigned char *rxp = din; unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */ + unsigned global_timeout; debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__, slave->bus, slave->cs, bitlen, bytes, flags); @@ -176,11 +177,12 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, if (flags & SPI_XFER_BEGIN) spi_cs_activate(slave); - while (bytes--) { - unsigned timeout = /* at least 1usec or greater, leftover 1 */ - xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 : + /* at least 1usec or greater, leftover 1 */ + global_timeout = xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 : (XILSPI_MAX_XFER_BITS * 1000000 / xilspi->freq) + 1; + while (bytes--) { + unsigned timeout = global_timeout; /* get Tx element from data out buffer and count up */ unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL; debug("%s: tx:%x ", __func__, d); -- 1.8.2.3

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