February 2014 - U-Boot

[U-Boot] [PATCH] OpenRD: relocate environment to 640kB
by Sascha Silbe 14 Aug '14

14 Aug '14

U-Boot has become slightly larger than where the environment sector was previously located. Saving the environment would brick the device. Relocate the environment to where it is with the stock (i.e. Marvell USP) U-Boot version. That should give plenty of room for U-Boot to grow, including local customisations. This obviously breaks compatibility with previous mainline versions of U-Boot. Users will need to back up the environment before an update and restore it afterwards, or manually copy it to the new address before the update. Signed-off-by: Sascha Silbe <t-uboot(a)infra-silbe.de> --- include/configs/openrd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 53bafe1..ea7f9aa 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -90,8 +90,8 @@ * it has to be rounded to sector size */ #define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x60000 -#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ +#define CONFIG_ENV_ADDR 0xa0000 +#define CONFIG_ENV_OFFSET 0xa0000 /* env starts here */ /* * Default environment variables -- 1.8.2.1

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[U-Boot] [PATCH] video: ipu_disp: wait for DP SF end irq when disabling sync BG flows
by Liu Ying 11 Aug '14

11 Aug '14

Instead of waiting for DC triple buffer to be cleared, this patch changes to wait for a relevant DP sync flow end interrupt to come when disabling sync BG flows. In this way, we align the implement to the freescale internal IPUv3 driver. After applying this patch, an uboot hang up issue at the arch_preboot_os() stage, where we disable a relevant ipu display channel, is not observed any more on some MX6DL platforms. Signed-off-by: Liu Ying <Ying.Liu(a)freescale.com> --- drivers/video/ipu.h | 8 ++++++++ drivers/video/ipu_disp.c | 27 ++++++++------------------- drivers/video/ipu_regs.h | 3 +++ 3 files changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/video/ipu.h b/drivers/video/ipu.h index 3d2741f..091b58f 100644 --- a/drivers/video/ipu.h +++ b/drivers/video/ipu.h @@ -176,6 +176,14 @@ typedef union { } ipu_channel_params_t; /* + * Enumeration of IPU interrupts. + */ +enum ipu_irq_line { + IPU_IRQ_DP_SF_END = 448 + 3, + IPU_IRQ_DC_FC_1 = 448 + 9, +}; + +/* * Bitfield of Display Interface signal polarities. */ typedef struct { diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c index cefd2dc..bf39a51 100644 --- a/drivers/video/ipu_disp.c +++ b/drivers/video/ipu_disp.c @@ -666,13 +666,16 @@ void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap) uint32_t csc; uint32_t dc_chan = 0; int timeout = 50; + int irq = 0; dc_swap = swap; if (channel == MEM_DC_SYNC) { dc_chan = 1; + irq = IPU_IRQ_DC_FC_1; } else if (channel == MEM_BG_SYNC) { dc_chan = 5; + irq = IPU_IRQ_DP_SF_END; } else if (channel == MEM_FG_SYNC) { /* Disable FG channel */ dc_chan = 5; @@ -723,25 +726,11 @@ void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap) reg ^= DC_WR_CH_CONF_PROG_DI_ID; __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); } else { - timeout = 50; - - /* Wait for DC triple buffer to empty */ - if (g_dc_di_assignment[dc_chan] == 0) - while ((__raw_readl(DC_STAT) & 0x00000002) - != 0x00000002) { - udelay(2000); - timeout -= 2; - if (timeout <= 0) - break; - } - else if (g_dc_di_assignment[dc_chan] == 1) - while ((__raw_readl(DC_STAT) & 0x00000020) - != 0x00000020) { - udelay(2000); - timeout -= 2; - if (timeout <= 0) - break; - } + /* Make sure that we leave at the irq starting edge */ + __raw_writel(IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq)); + do { + reg = __raw_readl(IPUIRQ_2_STATREG(irq)); + } while (!(reg & IPUIRQ_2_MASK(irq))); reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h index 21e9c99..c2c134a 100644 --- a/drivers/video/ipu_regs.h +++ b/drivers/video/ipu_regs.h @@ -313,9 +313,12 @@ struct ipu_dmfc { #define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \ IPU_STAT_REG_BASE)) +#define IPU_INT_STAT(n) (&IPU_STAT->int_stat[(n) - 1]) #define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32]) #define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32]) #define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32]) +#define IPUIRQ_2_STATREG(irq) (IPU_INT_STAT(1) + ((irq) / 32)) +#define IPUIRQ_2_MASK(irq) (1UL << ((irq) & 0x1F)) #define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1]) -- 1.7.9.5

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[U-Boot] [PATCH v2] gpio: spear_gpio: Fix gpio_set_value() implementation
by Axel Lin 04 Jul '14

04 Jul '14

In current gpio_set_value() implementation, it always sets the gpio control bit no matter the value argument is 0 or 1. Thus the GPIOs never set to low. This patch fixes this bug. The address bus is used as a mask on read/write operations, so that independent software drivers can set their GPIO bits without affecting any other pins in a single write operation. Thus we don't need a read-modify-write to update the register. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> Acked-by: Stefan Roese <sr(a)denx.de> Reviewed-by: Vipin Kumar <vipin.kumar(a)st.com> Reviewed-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- v2: Update commit log to explain why a read-modify-write is not necessary for clearing specific GPIO bit. Also added Michael Trimarchi's reviewed-by tag since he does review the patch and said the patch is fine. drivers/gpio/spear_gpio.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c index 367b670..6fb4117 100644 --- a/drivers/gpio/spear_gpio.c +++ b/drivers/gpio/spear_gpio.c @@ -36,7 +36,10 @@ int gpio_set_value(unsigned gpio, int value) { struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE; - writel(1 << gpio, &regs->gpiodata[DATA_REG_ADDR(gpio)]); + if (value) + writel(1 << gpio, &regs->gpiodata[DATA_REG_ADDR(gpio)]); + else + writel(0, &regs->gpiodata[DATA_REG_ADDR(gpio)]); return 0; } -- 1.8.1.2

2 1

[U-Boot] [PATCH v2] libfdt: Fix segfault when calling fit_check_format() on corrupt FIT images
by Tom Rini 19 Jun '14

19 Jun '14

From: Jon Nalley <lists(a)bluebot.org> It has been observed that fit_check_format() will fail when passed a corrupt FIT image. This was tracked down to _fdt_string_eq(): return (strlen(p) == len) && (memcmp(p, s, len) == 0); In the case of a corrupt FIT image one can't depend on 'p' being NULL terminated. I changed it to use strnlen() to fix the issue. Signed-off-by: Tom Rini <trini(a)ti.com> --- Changes in v2: - Pass len + 1, not len to strnlen as that's the best practice for strnlen. --- lib/libfdt/fdt_ro.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c index f2154e8..36af043 100644 --- a/lib/libfdt/fdt_ro.c +++ b/lib/libfdt/fdt_ro.c @@ -44,7 +44,7 @@ static int _fdt_string_eq(const void *fdt, int stroffset, { const char *p = fdt_string(fdt, stroffset); - return (strlen(p) == len) && (memcmp(p, s, len) == 0); + return (strnlen(p, len + 1) == len) && (memcmp(p, s, len) == 0); } int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size) -- 1.7.9.5

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[U-Boot] [PATCH] m68k:correct io macros about endian
by Chao Fu 19 Jun '14

19 Jun '14

From: Chao Fu <B44548(a)freescale.com> M68k is big endian cpu ,so use be_out and be_in in big endian. Signed-off-by: Chao Fu <b44548(a)freescale.com> --- arch/m68k/include/asm/io.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h index 5a87a9b..2d2a519 100644 --- a/arch/m68k/include/asm/io.h +++ b/arch/m68k/include/asm/io.h @@ -32,10 +32,10 @@ #define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) #define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) #else -#define readw(addr) in_le16((volatile u16 *)(addr)) -#define readl(addr) in_le32((volatile u32 *)(addr)) -#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) -#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) +#define readw(addr) in_be16((volatile u16 *)(addr)) +#define readl(addr) in_be32((volatile u32 *)(addr)) +#define writew(b,addr) out_be16((volatile u16 *)(addr),(b)) +#define writel(b,addr) out_be32((volatile u32 *)(addr),(b)) #endif /* -- 1.8.4

2 1

[U-Boot] [PATCH 0/3] All M68K boards are broken
by Masahiro Yamada 19 Jun '14

19 Jun '14

Hello. Even after applying the patch "config.mk: fix -fstack-usage support test" (http://patchwork.ozlabs.org/patch/283619/), I still cannot compile m68k correctly. The result of `CROSS_COMPILE=m68k-linux- ./MAKEALL -a m68k` is --------------------- SUMMARY ---------------------------- Boards compiled: 50 Boards with errors: 6 ( M5253DEMO M54455EVB M54455EVB_a66 M54455EVB_i66 M54455EVB_intel M54455EVB_stm33 ) Boards with warnings but no errors: 44 ( M52277EVB M52277EVB_stmicro M5235EVB M5235EVB_Flash32 idmr cobra5272 eb_cpu5282 eb_cpu5282_internal TASREG M5208EVBE M5249EVB M5253EVBE M5271EVB M5272C3 M5275EVB M5282EVB astro_mcf5373l M53017EVB M5329AFEE M5329BFEE M5373EVB M54418TWR M54418TWR_nand_mii M54418TWR_nand_rmii M54418TWR_nand_rmii_lowfreq M54418TWR_serial_mii M54418TWR_serial_rmii M54451EVB M54451EVB_stmicro M5475AFE M5475BFE M5475CFE M5475DFE M5475EFE M5475FFE M5475GFE M5485AFE M5485BFE M5485CFE M5485DFE M5485EFE M5485FFE M5485GFE M5485HFE ) ---------------------------------------------------------- I just took a look and I found lots of files are left broken for a long term. I pick up some them here. (1) drivers/i2c/i2c_core.c i2c_core.c: In function 'i2c_reloc_fixup': i2c_core.c:63:20: warning: assignment from incompatible pointer type [enabled by default] i2c_core.c:67:21: warning: assignment from incompatible pointer type [enabled by default] i2c_core.c:71:20: warning: assignment from incompatible pointer type [enabled by default] i2c_core.c:76:21: warning: assignment from incompatible pointer type [enabled by default] i2c_core.c:81:29: warning: assignment from incompatible pointer type [enabled by default] (2) arch/m68k/lib/bootm.c bootm.c:53:8: warning: unused variable 'rd_len' [-Wunused-variable] bootm.c:99:12: warning: 'initrd_start' may be used uninitialized in this function [-Wuninitialized] bootm.c:99:12: warning: 'initrd_end' may be used uninitialized in this function [-Wuninitialized] bootm.c:99:12: warning: 'cmd_start' may be used uninitialized in this function [-Wuninitialized] bootm.c:99:12: warning: 'cmd_end' may be used uninitialized in this function [-Wuninitialized] (3) arch/m68k/cpu/mcf5445x/cpu_init.c cpu_init.c:367:21: warning: unused variable 'info' [-Wunused-variable] (4) cpu_init.c:48:2: warning: passing argument 1 of 'out_be32' from incompatible pointer type [enabled by default] arch/m68k/include/asm/io.h:207:20: note: expected 'volatile unsigned int *' but argument is of type 'u16 *' cpu_init.c:49:2: warning: passing argument 1 of 'out_be32' from incompatible pointer type [enabled by default] arch/m68k/include/asm/io.h:207:20: note: expected 'volatile unsigned int *' but argument is of type 'u16 *' (5) include/configs/M5253DEMO.h:1:1: error: unknown type name 'TABILITY' include/configs/M5253DEMO.h:1:13: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'FITNESS' include/configs/M5253DEMO.h:1:13: error: unknown type name 'FITNESS' include/configs/M5253DEMO.h:2:2: error: stray '@' in program (6) cpu_init.c: In function 'cpu_init_f': cpu_init.c:211:10: warning: unused variable 'wdog' [-Wunused-variable] (7) mcf5373l.c: In function 'initdram': mcf5373l.c:83:5: warning: pointer targets in passing argument 1 of 'get_ram_size' differ in signedness [-Wpointer-sign] include/common.h:456:6: note: expected 'long int *' but argument is of type 'long unsigned int *' (8) fpga.c:168:2: warning: initialization from incompatible pointer type [enabled by default] fpga.c:168:2: warning: (near initialization for 'altera_fns.write') [enabled by default] fpga.c: In function 'astro5373l_altera_load': fpga.c:196:20: warning: assignment from incompatible pointer type [enabled by default] (9) speed.c: In function 'setup_5441x_clocks': speed.c:118:2: warning: passing argument 1 of 'in_be16' makes pointer from integer without a cast [enabled by default] arch/m68k/include/asm/io.h:177:19: note: expected 'volatile u16 *' but argument is of type 'u16' (10) fsl_i2c.c:50:39: error: 'CONFIG_SYS_FSL_I2C_OFFSET' undeclared here (not in a function) I began to fix some of them and I gave up on the way. Who is the custodian of M68K? I doubt M68K is maintained. Masahiro Yamada (3): i2c: eliminate warnings in i2c_reloc_fixup function m68k: eliminate warnings in do_bootm_linux function m68k: eliminate a warning in cpu_init arch/m68k/cpu/mcf5445x/cpu_init.c | 2 +- arch/m68k/lib/bootm.c | 7 ++++++- drivers/i2c/i2c_core.c | 12 +++++------- 3 files changed, 12 insertions(+), 9 deletions(-) -- 1.8.1.2

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[U-Boot] [PATCH] ARM: fdt support: Add usbethaddr as an acceptable MAC
by Dan Murphy 19 Jun '14

19 Jun '14

A board that has a USB ethernet device only may set the usbetheraddr and not the ethaddr. ethaddr will be the default MAC address that is chosen and if that is not populated then the usbethaddr is looked at. If neither are set then then device tree blob is not modified. Signed-off-by: Dan Murphy <dmurphy(a)ti.com> --- common/fdt_support.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index b034c98..fef7e60 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -450,8 +450,18 @@ void fdt_fixup_ethernet(void *fdt) if (node < 0) return; + if (!getenv("ethaddr")) { + if (getenv("usbethaddr")) { + strcpy(mac, "usbethaddr"); + } else { + debug("No ethernet MAC Address defined\n"); + return; + } + } else { + strcpy(mac, "ethaddr"); + } + i = 0; - strcpy(mac, "ethaddr"); while ((tmp = getenv(mac)) != NULL) { sprintf(enet, "ethernet%d", i); path = fdt_getprop(fdt, node, enet, NULL); -- 1.7.9.5

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[U-Boot] [PATCH 1/3] net: sh-eth: Add support R7S72100 of rmobile
by Nobuhiro Iwamatsu 12 Jun '14

12 Jun '14

The R7S72100 of ARM SoC that Renesas manufactured has one Ether port. This has the same IP SH-Ether. This patch adds support of the R7S72100 in SH-Ether. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> --- drivers/net/sh_eth.c | 10 ++++--- drivers/net/sh_eth.h | 81 +++++++++++++++++++++++++++++++++++++++++++++------- 2 files changed, 77 insertions(+), 14 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 5e132f2..0cb963f 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -148,7 +148,7 @@ int sh_eth_recv(struct eth_device *dev) static int sh_eth_reset(struct sh_eth_dev *eth) { -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) int ret = 0, i; /* Start e-dmac transmitter and receiver */ @@ -218,7 +218,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) /* Point the controller to the tx descriptor list. Must use physical addresses */ sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR); sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */ @@ -288,7 +288,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) /* Point the controller to the rx descriptor list */ sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR); sh_eth_write(eth, RDFFR_RDLF, RDFFR); @@ -384,7 +384,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) sh_eth_write(eth, 0, TFTR); sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); sh_eth_write(eth, RMCR_RST, RMCR); -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) sh_eth_write(eth, 0, RPADIR); #endif sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); @@ -403,6 +403,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) sh_eth_write(eth, RFLR_RFL_MIN, RFLR); #if defined(SH_ETH_TYPE_GETHER) sh_eth_write(eth, 0, PIPR); +#endif +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) sh_eth_write(eth, APR_AP, APR); sh_eth_write(eth, MPR_MP, MPR); sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER); diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 331c07c..0925759 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -230,6 +230,61 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { [RMII_MII] = 0x0790, }; +#if defined(SH_ETH_TYPE_RZ) +static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = { + [EDSR] = 0x0000, + [EDMR] = 0x0400, + [EDTRR] = 0x0408, + [EDRRR] = 0x0410, + [EESR] = 0x0428, + [EESIPR] = 0x0430, + [TDLAR] = 0x0010, + [TDFAR] = 0x0014, + [TDFXR] = 0x0018, + [TDFFR] = 0x001c, + [RDLAR] = 0x0030, + [RDFAR] = 0x0034, + [RDFXR] = 0x0038, + [RDFFR] = 0x003c, + [TRSCER] = 0x0438, + [RMFCR] = 0x0440, + [TFTR] = 0x0448, + [FDR] = 0x0450, + [RMCR] = 0x0458, + [RPADIR] = 0x0460, + [FCFTR] = 0x0468, + [CSMR] = 0x04E4, + + [ECMR] = 0x0500, + [ECSR] = 0x0510, + [ECSIPR] = 0x0518, + [PSR] = 0x0528, + [PIPR] = 0x052c, + [RFLR] = 0x0508, + [APR] = 0x0554, + [MPR] = 0x0558, + [PFTCR] = 0x055c, + [PFRCR] = 0x0560, + [TPAUSER] = 0x0564, + [GECMR] = 0x05b0, + [BCULR] = 0x05b4, + [MAHR] = 0x05c0, + [MALR] = 0x05c8, + [TROCR] = 0x0700, + [CDCR] = 0x0708, + [LCCR] = 0x0710, + [CEFCR] = 0x0740, + [FRECR] = 0x0748, + [TSFRCR] = 0x0750, + [TLFRCR] = 0x0758, + [RFCR] = 0x0760, + [CERCR] = 0x0768, + [CEECR] = 0x0770, + [MAFCR] = 0x0778, + [RMII_MII] = 0x0790, +}; +#endif + static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { [ECMR] = 0x0100, [RFLR] = 0x0108, @@ -306,13 +361,16 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) #define SH_ETH_TYPE_ETHER #define BASE_IO_ADDR 0xEE700200 +#elif defined(CONFIG_R7S72100) +#define SH_ETH_TYPE_RZ +#define BASE_IO_ADDR 0xE8203000 #endif /* * Register's bits * Copy from Linux driver source code */ -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) /* EDSR */ enum EDSR_BIT { EDSR_ENT = 0x01, EDSR_ENR = 0x02, @@ -323,7 +381,7 @@ enum EDSR_BIT { /* EDMR */ enum DMAC_M_BIT { EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) EDMR_SRST = 0x03, /* Receive/Send reset */ EMDR_DESC_R = 0x30, /* Descriptor reserve size */ EDMR_EL = 0x40, /* Litte endian */ @@ -349,7 +407,7 @@ enum DMAC_M_BIT { /* EDTRR */ enum DMAC_T_BIT { -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) EDTRR_TRNS = 0x03, #else EDTRR_TRNS = 0x01, @@ -424,7 +482,7 @@ enum EESR_BIT { }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define TX_CHECK (EESR_TC1 | EESR_FTC) # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) @@ -484,7 +542,8 @@ enum FCFTR_BIT { /* Transfer descriptor bit */ enum TD_STS_BIT { -#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \ + defined(SH_ETH_TYPE_RZ) TD_TACT = 0x80000000, #else TD_TACT = 0x7fffffff, @@ -500,7 +559,7 @@ enum TD_STS_BIT { enum RECV_RST_BIT { RMCR_RST = 0x01, }; /* ECMR */ enum FELIC_MODE_BIT { -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, ECMR_RZPF = 0x00100000, #endif @@ -517,7 +576,7 @@ enum FELIC_MODE_BIT { }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ ECMR_TXF | ECMR_MCT) #elif defined(SH_ETH_TYPE_ETHER) @@ -535,7 +594,7 @@ enum ECSR_STATUS_BIT { ECSR_MPD = 0x02, ECSR_ICD = 0x01, }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) #else # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ @@ -556,7 +615,7 @@ enum ECSIPR_STATUS_MASK_BIT { ECSIPR_ICDIP = 0x01, }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) #else # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ @@ -587,7 +646,7 @@ enum RPADIR_BIT { RPADIR_PADR = 0x0003f, }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define RPADIR_INIT (0x00) #else # define RPADIR_INIT (RPADIR_PADS1) @@ -605,6 +664,8 @@ static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth, const u16 *reg_offset = sh_eth_offset_gigabit; #elif defined(SH_ETH_TYPE_ETHER) const u16 *reg_offset = sh_eth_offset_fast_sh4; +#elif defined(SH_ETH_TYPE_RZ) + const u16 *reg_offset = sh_eth_offset_rz; #else #error #endif -- 1.8.5

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[U-Boot] [PATCH] Separate EBV Socrates board from Altera Cyclone 5 board
by Pavel Machek 05 Jun '14

05 Jun '14

Altera Cyclone 5 board is very different board (big, rectangular, expensive) than EBV Socrates (small, circular, cheap) board. Different parts are used there, too, but same configuration of u-boot works on both. Nevertheless, printing wrong name confuses users. Therefore this splits the configuration so that u-boot knows they are different. So far it is only used for correcting the puts, but there may be other uses in future. Signed-off-by: Pavel Machek <pavel(a)denx.de> diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 576066b..4540b1b 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -26,7 +26,7 @@ int print_cpuinfo(void) */ int checkboard(void) { - puts("BOARD : Altera SOCFPGA Cyclone5 Board\n"); + puts("BOARD : " ALTERA_BOARD_NAME "\n"); return 0; } diff --git a/boards.cfg b/boards.cfg index 375f2d4..20534c3 100644 --- a/boards.cfg +++ b/boards.cfg @@ -340,6 +340,7 @@ Active arm armv7 rmobile kmc kzm9g Active arm armv7 s5pc1xx samsung goni s5p_goni - Minkyu Kang <mk7.kang(a)samsung.com> Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang(a)samsung.com> Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - +Active arm armv7 socfpga altera socfpga socfpga_socrates - - Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier(a)linaro.org> Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965(a)freescale.com> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h new file mode 100644 index 0000000..6d4dfcf --- /dev/null +++ b/include/configs/socfpga_common.h @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_COMMON_H +#define __CONFIG_COMMON_H + +#include <asm/arch/socfpga_base_addrs.h> +#include "../../board/altera/socfpga/pinmux_config.h" + +/* + * High level configuration + */ +/* Virtual target or real hardware */ +#define CONFIG_SOCFPGA_VIRTUAL_TARGET + +#define CONFIG_ARMV7 +#define CONFIG_L2_OFF +#define CONFIG_SYS_DCACHE_OFF +#undef CONFIG_USE_IRQ + +#define CONFIG_MISC_INIT_R +#define CONFIG_SINGLE_BOOTLOADER +#define CONFIG_SOCFPGA + +/* base address for .text section */ +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_SYS_TEXT_BASE 0x08000040 +#else +#define CONFIG_SYS_TEXT_BASE 0x01000040 +#endif +#define CONFIG_SYS_LOAD_ADDR 0x7fc0 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Display CPU and Board Info + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* + * Enable early stage initialization at C environment + */ +#define CONFIG_BOARD_EARLY_INIT_F + +/* flat device tree */ +#define CONFIG_OF_LIBFDT +/* skip updating the FDT blob */ +#define CONFIG_FDT_BLOB_SKIP_UPDATE +/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ +#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) + +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) +#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) + +/* + * Memory allocation (MALLOC) + */ +/* Room required on the stack for the environment data */ +#define CONFIG_ENV_SIZE 1024 +/* Size of DRAM reserved for malloc() use */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) + +/* SP location before relocation, must use scratch RAM */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +/* Reserving 0x100 space at back of scratch RAM for debug info */ +#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) +/* Stack pointer prior relocation, must situated at on-chip RAM */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + + +/* + * Command line configuration. + */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +/* FAT file system support */ +#define CONFIG_CMD_FAT + + +/* + * Misc + */ +#define CONFIG_DOS_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_PARTITIONS +#endif + +/* + * Environment setup + */ + +/* Delay before automatically booting the default image */ +#define CONFIG_BOOTDELAY 3 +/* Enable auto completion of commands using TAB */ +#define CONFIG_AUTO_COMPLETE +/* use "hush" command parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMD_RUN + +#define CONFIG_BOOTCOMMAND "run ramboot" + +/* + * arguments passed to the bootm command. The value of + * CONFIG_BOOTARGS goes into the environment value "bootargs". + * Do note the value will overide also the chosen node in FDT blob. + */ +#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=uImage\0" \ + "fdt_addr=100\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* using environment setting for stdin, stdout, stderr */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +/* Enable the call to overwrite_console() */ +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +/* Enable overwrite of previous console environment settings */ +#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + + +/* + * Hardware drivers + */ + +/* + * SDRAM Memory Map + */ +/* We have 1 bank of DRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +/* SDRAM Bank #1 */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +/* SDRAM memory size */ +#define PHYS_SDRAM_1_SIZE 0x40000000 + +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE + +/* + * NS16550 Configuration + */ +#define UART0_BASE SOCFPGA_UART0_ADDRESS +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 UART0_BASE +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define V_NS16550_CLK 1000000 +#else +#define V_NS16550_CLK 100000000 +#endif +#define CONFIG_BAUDRATE 115200 + +/* + * FLASH + */ +#define CONFIG_SYS_NO_FLASH + +/* + * L4 OSC1 Timer 0 + */ +/* This timer use eosc1 where the clock frequency is fixed + * throughout any condition */ +#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS +/* reload value when timer count to zero */ +#define TIMER_LOAD_VAL 0xFFFFFFFF +/* Timer info */ +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_SYS_TIMER_RATE 2400000 +#else +#define CONFIG_SYS_TIMER_RATE 25000000 +#endif +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) + +#define CONFIG_ENV_IS_NOWHERE + +/* + * SPL "Second Program Loader" aka Initial Software + */ + +/* Enable building of SPL globally */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK + +/* TEXT_BASE for linking the SPL binary */ +#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 + +/* Stack size for SPL */ +#define CONFIG_SPL_STACK_SIZE (4 * 1024) + +/* MALLOC size for SPL */ +#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) + +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT + +#define CHUNKSZ_CRC32 (1 * 1024) + +#define CONFIG_CRC32_VERIFY + +/* Linker script for SPL */ +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" + +/* Support for common/libcommon.o in SPL binary */ +#define CONFIG_SPL_LIBCOMMON_SUPPORT +/* Support for lib/libgeneric.o in SPL binary */ +#define CONFIG_SPL_LIBGENERIC_SUPPORT + +#endif /* __CONFIG_COMMON_H */ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 980636c..87de4d2 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -6,235 +6,12 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/socfpga_base_addrs.h> -#include "../../board/altera/socfpga/pinmux_config.h" +#include <configs/socfpga_common.h> -/* - * High level configuration - */ -/* Virtual target or real hardware */ -#define CONFIG_SOCFPGA_VIRTUAL_TARGET - -#define CONFIG_ARMV7 -#define CONFIG_L2_OFF -#define CONFIG_SYS_DCACHE_OFF -#undef CONFIG_USE_IRQ - -#define CONFIG_MISC_INIT_R -#define CONFIG_SINGLE_BOOTLOADER -#define CONFIG_SOCFPGA - -/* base address for .text section */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_TEXT_BASE 0x08000040 +#define ALTERA_BOARD_NAME "Altera VTDEV5XS1 Virtual Board" #else -#define CONFIG_SYS_TEXT_BASE 0x01000040 -#endif -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* - * Display CPU and Board Info - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -/* - * Enable early stage initialization at C environment - */ -#define CONFIG_BOARD_EARLY_INIT_F - -/* flat device tree */ -#define CONFIG_OF_LIBFDT -/* skip updating the FDT blob */ -#define CONFIG_FDT_BLOB_SKIP_UPDATE -/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ -#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) - -#define CONFIG_SPL_RAM_DEVICE -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) -#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) - -/* - * Memory allocation (MALLOC) - */ -/* Room required on the stack for the environment data */ -#define CONFIG_ENV_SIZE 1024 -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* SP location before relocation, must use scratch RAM */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -/* Reserving 0x100 space at back of scratch RAM for debug info */ -#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) -/* Stack pointer prior relocation, must situated at on-chip RAM */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - - -/* - * Command line configuration. - */ -#define CONFIG_SYS_NO_FLASH -#include <config_cmd_default.h> -/* FAT file system support */ -#define CONFIG_CMD_FAT - - -/* - * Misc - */ -#define CONFIG_DOS_PARTITION 1 - -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_PARTITIONS +#define ALTERA_BOARD_NAME "Altera SOCFPGA Cyclone 5 Board" #endif -/* - * Environment setup - */ - -/* Delay before automatically booting the default image */ -#define CONFIG_BOOTDELAY 3 -/* Enable auto completion of commands using TAB */ -#define CONFIG_AUTO_COMPLETE -/* use "hush" command parser */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_CMD_RUN - -#define CONFIG_BOOTCOMMAND "run ramboot" - -/* - * arguments passed to the bootm command. The value of - * CONFIG_BOOTARGS goes into the environment value "bootargs". - * Do note the value will overide also the chosen node in FDT blob. - */ -#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=uImage\0" \ - "fdt_addr=100\0" \ - "fsloadcmd=ext2load\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ - "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" - -/* using environment setting for stdin, stdout, stderr */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -/* Enable the call to overwrite_console() */ -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -/* Enable overwrite of previous console environment settings */ -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE - -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 - - -/* - * Hardware drivers - */ - -/* - * SDRAM Memory Map - */ -/* We have 1 bank of DRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -/* SDRAM Bank #1 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* SDRAM memory size */ -#define PHYS_SDRAM_1_SIZE 0x40000000 - -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - -/* - * NS16550 Configuration - */ -#define UART0_BASE SOCFPGA_UART0_ADDRESS -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 UART0_BASE -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define V_NS16550_CLK 1000000 -#else -#define V_NS16550_CLK 100000000 -#endif -#define CONFIG_BAUDRATE 115200 - -/* - * FLASH - */ -#define CONFIG_SYS_NO_FLASH - -/* - * L4 OSC1 Timer 0 - */ -/* This timer use eosc1 where the clock frequency is fixed - * throughout any condition */ -#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -/* reload value when timer count to zero */ -#define TIMER_LOAD_VAL 0xFFFFFFFF -/* Timer info */ -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_TIMER_RATE 2400000 -#else -#define CONFIG_SYS_TIMER_RATE 25000000 -#endif -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) - -#define CONFIG_ENV_IS_NOWHERE - -/* - * SPL "Second Program Loader" aka Initial Software - */ - -/* Enable building of SPL globally */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK - -/* TEXT_BASE for linking the SPL binary */ -#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 - -/* Stack size for SPL */ -#define CONFIG_SPL_STACK_SIZE (4 * 1024) - -/* MALLOC size for SPL */ -#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) - -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_BOARD_INIT - -#define CHUNKSZ_CRC32 (1 * 1024) - -#define CONFIG_CRC32_VERIFY - -/* Linker script for SPL */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" - -/* Support for common/libcommon.o in SPL binary */ -#define CONFIG_SPL_LIBCOMMON_SUPPORT -/* Support for lib/libgeneric.o in SPL binary */ -#define CONFIG_SPL_LIBGENERIC_SUPPORT - #endif /* __CONFIG_H */ diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h new file mode 100644 index 0000000..2f1c3a4 --- /dev/null +++ b/include/configs/socfpga_socrates.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/socfpga_common.h> + +#define ALTERA_BOARD_NAME "EBV SoCrates - Cyclone V SoC FPGA Board" + +#endif /* __CONFIG_H */ -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

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[U-Boot] [PATCH 0/9] ARMv7: add PSCI support to u-boot
by Marc Zyngier 04 Jun '14

04 Jun '14

PSCI is an ARM standard that provides a generic interface that supervisory software can use to manage power in the following situations: - Core idle management - CPU hotplug - big.LITTLE migration models - System shutdown and reset It basically allows the kernel to offload these tasks to the firmware, and rely on common kernel side code. More importantly, it gives a way to ensure that CPUs enter the kernel at the appropriate exception level (ie HYP mode, to allow the use of the virtualization extensions), even across events like CPUs being powered off/on or suspended. The main idea here is to reuse some of the existing u-boot code to create a separate blob that can live in SRAM (or a reserved page of memory), containing a secure monitor that will implement the PSCI operations. This code will still be alive when u-boot is long gone, hence the need for a piece of memory that will not be touched by the OS. This patch series contains 3 parts: - the first four patches are just bug fixes - the next three contain the generic PSCI code and build infrastructure - the last two implement the CPU_ON method of the Allwinner A20 (aka sun7i). I realize the A20 u-boot code is not upstream yet (BTW is anyone actively working on that?), but hopefully that should give a good idea of how things are structured so far. The patches are against a merge of u-boot mainline and the sunxi tree as of ten days ago. As for using this code, it goes like this: sun7i# ext2load mmc 0:1 0x40000000 /boot/sunxi-psci.bin 908 bytes read in 18 ms (48.8 KiB/s) sun7i# cp 0x40000000 0x4000 0x1000 sun7i# ext2load mmc 0:1 40008000 /boot/zImage 3415087 bytes read in 184 ms (17.7 MiB/s) sun7i# setenv bootargs console=ttyS0,115200 earlyprintk root=/dev/nfs nfsroot=10.1.203.35:/export/roots/bobby-brown,tcp,v3 rw ip=dhcp sun7i# bootz 40008000 The kernel now boots in HYP mode, finds its secondary CPU without any additional SMP code, and runs KVM out of the box. Hopefully, the Xen/ARM guys can do the same fairly easily. I'm wildly cross-posting this patch series, including to lists I'm not subscribed to. Please keep me on Cc for any comment you may have. Cheers, M. Marc Zyngier (9): ARM: HYP/non-sec: fix alignment requirements for vectors ARM: HYP/non-sec: move switch to non-sec to the last boot phase ARM: HYP/non-sec: add a barrier after setting SCR.NS==1 ARM: non-sec: reset CNTVOFF to zero ARM: HYP/non-sec: add generic ARMv7 PSCI code ARM: HYP/non-sec: make pen code sections depend on !ARMV7_PSCI ARM: HYP/non-sec: add the option for a second-stage monitor sunxi: HYP/non-sec: add sun7i PSCI backend sunxi: HYP/non-sec: configure CNTFRQ on all CPUs Makefile | 5 ++ arch/arm/cpu/armv7/Makefile | 4 ++ arch/arm/cpu/armv7/nonsec_virt.S | 21 +++++- arch/arm/cpu/armv7/psci.S | 109 ++++++++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/Makefile | 3 + arch/arm/cpu/armv7/sunxi/config.mk | 6 +- arch/arm/cpu/armv7/sunxi/psci.S | 119 +++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/u-boot-psci.lds | 63 ++++++++++++++++ arch/arm/cpu/armv7/virt-v7.c | 2 + arch/arm/lib/bootm.c | 5 +- include/configs/sun7i.h | 7 ++ psci/Makefile | 67 +++++++++++++++++ 12 files changed, 406 insertions(+), 5 deletions(-) create mode 100644 arch/arm/cpu/armv7/psci.S create mode 100644 arch/arm/cpu/armv7/sunxi/psci.S create mode 100644 arch/arm/cpu/armv7/sunxi/u-boot-psci.lds create mode 100644 psci/Makefile -- 1.8.2.3

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