November 2014 - U-Boot

[U-Boot] [PATCH v3 2/2] imx: mx6sxsabresd: Add board support for USDHC2 and USDHC3
by Ye.Li 20 Nov '14

20 Nov '14

Add full support for USDHC2, USDHC3, USDHC4 on mx6sx sabresd board. The default boot socket is USDHC4, so the MMC environment device and mmcdev variable are set to this device. Signed-off-by: Ye.Li <B37916(a)freescale.com> --- Changes since v2: - Modify the default mmcdev environment variable to USDHC4 (dev 2) Changes since v1: - Modify the function return value board/freescale/mx6sxsabresd/mx6sxsabresd.c | 99 +++++++++++++++++++++++++-- include/configs/mx6sxsabresd.h | 8 ++- 2 files changed, 100 insertions(+), 7 deletions(-) diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 68d3718..f799998 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -68,6 +68,34 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD pin */ + MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* RST_B, used for power reset cycle */ + MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -255,23 +283,84 @@ int board_early_init_f(void) return 0; } -static struct fsl_esdhc_cfg usdhc_cfg[1] = { +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, {USDHC4_BASE_ADDR}, }; +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) +#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11) +#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21) + int board_mmc_getcd(struct mmc *mmc) { - return 1; /* Assume boot SD always present */ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = 1; /* Assume uSDHC2 is always present */ + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = !gpio_get_value(USDHC4_CD_GPIO); + break; + } + + return ret; } int board_mmc_init(bd_t *bis) { - imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + int i, ret; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC2 + * mmc1 USDHC3 + * mmc2 USDHC4 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + gpio_direction_output(USDHC3_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + gpio_direction_input(USDHC4_CD_GPIO); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; } + int board_init(void) { /* Address of boot parameters */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index e02ea18..d8ab291 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -59,7 +59,7 @@ "fdt_addr=0x88000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=0\0" \ + "mmcdev=2\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ @@ -214,7 +214,6 @@ #define CONFIG_ENV_OFFSET (6 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ @@ -223,4 +222,9 @@ #define CONFIG_CMD_CACHE #endif +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/ +#endif + #endif /* __CONFIG_H */ -- 1.7.4.1

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[U-Boot] [PATCH v3 1/2] mmc: fsl_esdhc: Update esdhc driver for iMX6SX
by Ye.Li 20 Nov '14

20 Nov '14

The reset value of "uSDHCx_INT_STATUS_EN" register is changed to 0 on iMX6SX. So the fsl_esdhc driver must update to set the register, otherwise no state can be detected. Signed-off-by: Ye.Li <B37916(a)freescale.com> --- Changes since v2: - None Changes since v1: - Remove codes which set INT_STATUS_EN register according PIO or DMA mode. drivers/mmc/fsl_esdhc.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 2640607..59b470d 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -23,6 +23,13 @@ DECLARE_GLOBAL_DATA_PTR; +#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ + IRQSTATEN_CINT | \ + IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ + IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ + IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ + IRQSTATEN_DINT) + struct fsl_esdhc { uint dsaddr; /* SDMA system address register */ uint blkattr; /* Block attributes register */ @@ -558,6 +565,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); + writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten); memset(&cfg->cfg, 0, sizeof(cfg->cfg)); voltage_caps = 0; -- 1.7.4.1

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[U-Boot] [PATCH] mx6sabresd: Access SRC_SBMR1 register via structure
by Fabio Estevam 20 Nov '14

20 Nov '14

In U-boot it is preferred to access the register via structure pointer, so convert it such style. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/freescale/mx6sabresd/mx6sabresd.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index d5cd37d..bd8f55a 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -31,8 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define BOOT_CFG 0x020D8004 - #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) @@ -300,7 +298,8 @@ int board_mmc_init(bd_t *bis) return 0; #else - unsigned reg = readl(BOOT_CFG) >> 11; + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr1) >> 11; /* * Upon reading BOOT_CFG register the following map is done: * Bit 11 and 12 of BOOT_CFG register can determine the current -- 1.9.1

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[U-Boot] [RESEND PATCH 0/4] tqma6: improvements and cleanup
by Markus Niebel 20 Nov '14

20 Nov '14

From: Markus Niebel <Markus.Niebel(a)tq-group.com> This series contains some cosmetic and code cleanups. No functional changes. resend because of typo in Mailaddress. Markus Niebel (4): tqma6: (cosmetic) remove CONFIG_FLASH_SECTOR_SIZE tqma6: add missing include tqma6: add warning on failed setup_i2c tqma6: use imx_ddr_size board/tqc/tqma6/tqma6.c | 13 ++++++++++--- board/tqc/tqma6/tqma6_mba6.c | 10 ++++++++-- include/configs/tqma6.h | 28 ++++++++++++++-------------- 3 files changed, 32 insertions(+), 19 deletions(-) -- 2.1.1

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[U-Boot] [PATCH] mx6sabresd: State that only mx6q is supported in SPL
by Fabio Estevam 20 Nov '14

20 Nov '14

From: Fabio Estevam <fabio.estevam(a)freescale.com> Make clear that current SPL code only supports the mx6q variant. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/freescale/mx6sabresd/mx6sabresd.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 343c3b6..d5cd37d 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -754,10 +754,8 @@ static void gpr_init(void) } /* - * This section require the differentiation - * between iMX6 Sabre Families. - * But for now, it will configure only for - * SabreSD. + * This section requires the differentiation between iMX6 Sabre boards, but + * for now, it will configure only for the mx6q variant. */ static void spl_dram_init(void) { -- 1.9.1

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[U-Boot] [PATCH 1/2] wandboard: Fix error handling in board_mmc_init()
by Fabio Estevam 20 Nov '14

20 Nov '14

From: Fabio Estevam <fabio.estevam(a)freescale.com> When an invalid USDHC port is passed we should return -EINVAL instead of 0. Also, return the error immediately on fsl_esdhc_initialize() failure. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/wandboard/wandboard.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 3c8b7a5..1075c65 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -144,7 +144,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { - s32 status = 0; + int ret; u32 index = 0; /* @@ -173,13 +173,15 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; + return -EINVAL; } - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; } - return status; + return 0; } static int mx6_rgmii_rework(struct phy_device *phydev) -- 1.9.1

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[U-Boot] [PATCH] tools/msximage.c: fix warning about nptr possibly uninitialized
by Albert ARIBAUD 20 Nov '14

20 Nov '14

Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- tools/mxsimage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/mxsimage.c b/tools/mxsimage.c index 81c7f2d..55e61e2 100644 --- a/tools/mxsimage.c +++ b/tools/mxsimage.c @@ -1416,7 +1416,7 @@ static int sb_parse_line(struct sb_image_ctx *ictx, struct sb_cmd_list *cmd) { char *tok; char *line = cmd->cmd; - char *rptr; + char *rptr = NULL; int ret; /* Analyze the identifier on this line first. */ -- 2.1.0

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[U-Boot] [PATCH 1/3] imx: consolidate set_chipselect_size function
by Fabio Estevam 20 Nov '14

20 Nov '14

From: Fabio Estevam <fabio.estevam(a)freescale.com> Move MX5 specific set_chipselect_size function into generic i.MX part, such that MX6 based boards are able to use this function as well. While doing this the iomuxc gpr member needed to be consolidated between MX5 and MX6. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- arch/arm/cpu/armv7/mx5/soc.c | 31 ------------------------------- arch/arm/imx-common/cpu.c | 31 +++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-imx/cpu.h | 5 +++++ arch/arm/include/asm/arch-mx5/imx-regs.h | 12 ++---------- arch/arm/include/asm/arch-mx6/sys_proto.h | 1 + 5 files changed, 39 insertions(+), 41 deletions(-) diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c index 2d53669..3753c14 100644 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -85,37 +85,6 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) } #endif -void set_chipselect_size(int const cs_size) -{ - unsigned int reg; - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - reg = readl(&iomuxc_regs->gpr1); - - switch (cs_size) { - case CS0_128: - reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */ - reg |= 0x5; - break; - case CS0_64M_CS1_64M: - reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */ - reg |= 0x1B; - break; - case CS0_64M_CS1_32M_CS2_32M: - reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */ - reg |= 0x4B; - break; - case CS0_32M_CS1_32M_CS2_32M_CS3_32M: - reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */ - reg |= 0x249; - break; - default: - printf("Unknown chip select size: %d\n", cs_size); - break; - } - - writel(reg, &iomuxc_regs->gpr1); -} - #ifdef CONFIG_MX53 void boot_mode_apply(unsigned cfg_val) { diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 09fc227..24740b8 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -187,3 +187,34 @@ void arch_preboot_os(void) ipuv3_fb_shutdown(); } #endif + +void set_chipselect_size(int const cs_size) +{ + unsigned int reg; + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + reg = readl(&iomuxc_regs->gpr[1]); + + switch (cs_size) { + case CS0_128: + reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */ + reg |= 0x5; + break; + case CS0_64M_CS1_64M: + reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */ + reg |= 0x1B; + break; + case CS0_64M_CS1_32M_CS2_32M: + reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */ + reg |= 0x4B; + break; + case CS0_32M_CS1_32M_CS2_32M_CS3_32M: + reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */ + reg |= 0x249; + break; + default: + printf("Unknown chip select size: %d\n", cs_size); + break; + } + + writel(reg, &iomuxc_regs->gpr[1]); +} diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index a3cc96f..254136e 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -12,3 +12,8 @@ #define MXC_CPU_MX6Q 0x63 #define MXC_CPU_MX6D 0x64 #define MXC_CPU_MX6SOLO 0x65 /* dummy ID */ + +#define CS0_128 0 +#define CS0_64M_CS1_64M 1 +#define CS0_64M_CS1_32M_CS2_32M 2 +#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 054c680..f059d0f 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -202,11 +202,6 @@ */ #define WBED 1 -#define CS0_128 0 -#define CS0_64M_CS1_64M 1 -#define CS0_64M_CS1_32M_CS2_32M 2 -#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 - /* * CSPI register definitions */ @@ -414,8 +409,7 @@ struct weim { #if defined(CONFIG_MX51) struct iomuxc { - u32 gpr0; - u32 gpr1; + u32 gpr[2]; u32 omux0; u32 omux1; u32 omux2; @@ -424,9 +418,7 @@ struct iomuxc { }; #elif defined(CONFIG_MX53) struct iomuxc { - u32 gpr0; - u32 gpr1; - u32 gpr2; + u32 gpr[3]; u32 omux0; u32 omux1; u32 omux2; diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index c35a905..28ba844 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -26,6 +26,7 @@ u32 get_cpu_rev(void); const char *get_imx_type(u32 imxtype); unsigned imx_ddr_size(void); +void set_chipselect_size(int const); /* * Initializes on-chip ethernet controllers. -- 1.9.1

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[U-Boot] [PATCH] imx: mx6slevk: Change default mmcdev to USDHC2 device
by Ye.Li 20 Nov '14

20 Nov '14

Since USDHC1 and USDHC3 added, the dev index for USDHC2 changed to 1. So modify the default mmcdev in environment variables to dev 1. Signed-off-by: Ye.Li <B37916(a)freescale.com> --- include/configs/mx6slevk.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 4fcaf51..271548c 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -87,7 +87,7 @@ "fdt_addr=0x88000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=0\0" \ + "mmcdev=1\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ -- 1.7.4.1

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[U-Boot] [PATCH] imx:mx6sxsabresd fix pfuz probe failed
by Peng Fan 20 Nov '14

20 Nov '14

The PFUZ probe failed with the following msg: " wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0x8 retry=0 wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0x8 retry=1 wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0x8 retry=2 i2c_init_transfer: give up i2c_regs=021a0000 Can't find PMIC:PFUZE100 " board_early_init_f is too early to call i2c related setting, because init_func_i2c is called after board_early_init_f being invoked. Thus move setup_i2c into board_init. Also PFUZ is connected to I2C bus 0, so change "1" -> "0". Using this patch PFUZ can be correctly probed: "PMIC: PFUZE100 ID=0x11" Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> --- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 68d3718..256ea29 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -243,7 +243,6 @@ int board_phy_config(struct phy_device *phydev) int board_early_init_f(void) { setup_iomux_uart(); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, @@ -277,6 +276,10 @@ int board_init(void) /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + return 0; } -- 1.8.4

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