November 2014 - U-Boot

[U-Boot] [PATCH v2 00/12] spi: sf: ICH SPI driver fix and flash params update
by Bin Meng 04 Dec '14

04 Dec '14

This series fix several bugs in current ICH SPI driver as well as adding byte program support for the SST25* flash. Flash params are updated to explicitly list supported read commands and change flash sector size to 4KiB as long as flash supports sector erase (20h) command. Changes for v2: - Rebased to u-boot-spi/mater. - Reviewed and updated the params of all currently supported flash parts per their datasheets. - Corrected AT25DF321 JEDEC ID. - Corrected Atmel bulk erase command to 50h instead of D8h. - Added AT25DF321A, W25X10, W25X20, W25X80 params. Bin Meng (12): spi/ich.c: Fix a bug of reading from a non-64 bytes aligned address spi/ich.c: Set the rx operation mode for ich 7 spi: sf: Support byte program for sst spi flash sf: Update SST flash params sf: Update Atmel flash params sf: Update EON flash params sf: Update GigaDevice flash params sf: Update Macronix flash params sf: Update Spansion flash params sf: Update Micron flash params sf: Update Winbond flash params sf: Give proper spacing between flash table params drivers/mtd/spi/sf_internal.h | 11 ++- drivers/mtd/spi/sf_ops.c | 31 +++++++ drivers/mtd/spi/sf_params.c | 186 ++++++++++++++++++++++-------------------- drivers/mtd/spi/sf_probe.c | 12 ++- drivers/spi/ich.c | 26 +++--- include/spi.h | 1 + 6 files changed, 159 insertions(+), 108 deletions(-) -- 1.8.2.1

3 8

[U-Boot] [PATCH v2 1/4] mx6sabresd: Move the DCD settings to spl code
by Fabio Estevam 04 Dec '14

04 Dec '14

From: Fabio Estevam <fabio.estevam(a)freescale.com> mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR. Move the configuration to the spl code. CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v1: - None. Send it as a series and use a common spl .cfg per Stefano's suggestion board/freescale/mx6sabresd/mx6sabresd.c | 27 +++++++++++++++++++ board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 38 --------------------------- 2 files changed, 27 insertions(+), 38 deletions(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 1142e8a..343c3b6 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -729,6 +729,30 @@ static struct mx6_ddr3_cfg mem_ddr = { .trasmin = 3500, }; +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + /* * This section require the differentiation * between iMX6 Sabre Families. @@ -768,6 +792,9 @@ void board_init_f(ulong dummy) /* setup AIPS and disable watchdog */ arch_cpu_init(); + ccgr_init(); + gpr_init(); + /* iomux and setup of i2c */ board_early_init_f(); diff --git a/board/freescale/mx6sabresd/mx6sabresd_spl.cfg b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg index 2bf4817..1d031ba 100644 --- a/board/freescale/mx6sabresd/mx6sabresd_spl.cfg +++ b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg @@ -18,41 +18,3 @@ IMAGE_VERSION 2 * spi, sd (the board has no nand neither onenand) */ BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* set the default clock gate to save power */ -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4 0x020e0010 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F - -/* - * Setup CCM_CCOSR register as follows: - * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root - * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz - */ -DATA 4 0x020c4060 0x000000fb -- 1.9.1

4 11

[U-Boot] [PATCH v1] tools/kwboot: Allow just -t to function
by Suriyan Ramasami 04 Dec '14

04 Dec '14

When kwboot is invoked with -t <tty> the code implicitly assumes that one of -b (boot message) or -d (debug message) with an image file is specified. This is not necessarily true. This allows kwboot -t <tty> to function. Signed-off-by: Suriyan Ramasami <suriyan.r(a)gmail.com> --- Changes in v1: - First try tools/kwboot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/kwboot.c b/tools/kwboot.c index 1368b4c..449564e 100644 --- a/tools/kwboot.c +++ b/tools/kwboot.c @@ -785,7 +785,7 @@ main(int argc, char **argv) perror("debugmsg"); goto out; } - } else { + } else if (bootmsg) { rc = kwboot_bootmsg(tty, bootmsg); if (rc) { perror("bootmsg"); -- 1.8.3.1

2 2

[U-Boot] Attached DTB no longer supported u-boot.imx?
by Bill Pringlemeir 03 Dec '14

03 Dec '14

I tried to update the new u-boot I get, Bytes transferred = 3413041 (341431 hex) Kernel image @ 0x86000000 [ 0x000000 - 0x33e150 ] Could not find a valid device tree The 'bootcmd' is, tftp ${loadaddr} zImage.dtb; bootz ${loadaddr} has the syntax changed and I am not up to date? I think I saw something about an attached DTB not supported. u-boot-imx$ git describe v2009.08-18413-g5c84206 err, that is no good. I have 2a82ec77d27ef5f860a107c4b764643a655dceeb as 'Prepare v2015.01-rc2' and I had to apply 5c84206 to compile with a 4.9 hard-float ARM compiler. I pulled the main 'u-boot.git' and this does not happen. u-boot$ git describe v2015.01-rc2-87-g0f89149 It is '38cd8c4253013ccdd4052ee021f6066fe9a52551', with the same patch as 'pwclient git-am 415336' Is the imx just using newer patches to be merged to the main tree and I must switch to a detached DT? Or is there something else? Thanks, Bill.

2 4

[U-Boot] [PATCH] image-fdt: boot_get_fdt() return value when no DTB exists
by Noam Camus 03 Dec '14

03 Dec '14

From: Noam Camus <noamc(a)ezchip.com> I believe that when no DTB is around we should return 1. This why I fixed such scenarious to not return zero anymore. Else kernel might get NULL pointer to DTB which doesn't exists. Signed-off-by: Noam Camus <noamc(a)ezchip.com> --- common/image-fdt.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/common/image-fdt.c b/common/image-fdt.c index 9fc7481..c142ae6 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -413,11 +413,11 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, } } else { debug("## No Flattened Device Tree\n"); - return 0; + goto error; } } else { debug("## No Flattened Device Tree\n"); - return 0; + goto error; } *of_flat_tree = fdt_blob; -- 1.7.1

3 5

[U-Boot] [PATCH 0/8] PSCI v0.2 framework for ARMv8
by Arnab Basu 03 Dec '14

03 Dec '14

This series of patches creates a generic PSCI v0.2 framework for ARMv8. The first 3 patches refactor existing code so that ARMv7 PSCI, ARMv8 spin-table and ARMv8 PSCI can coexist. The next 5 patches create a generic framework for PSCI v0.2 in ARMv8. The implementation is modelled on the pre-existing PSCI v0.1 support in ARMv7. PSCI support patches for the ARMv8 Foundation model will follow shortly. Arnab Basu (8): ARM: PSCI: Update psci.h for psci v0.2 ARM: PSCI: Alow arch specific DT patching ARMv8/fsl-lsch3: Refactor spin-table code ARMv8: PSCI: Add linker section to hold PSCI code ARMv8: PCSI: Add generic ARMv8 PSCI code ARMv8: PSCI: Fixup the device tree for PSCI v0.2 ARMv8: PSCI: Setup ARMv8 PSCI ARMv8: PSCI: Enable SMC arch/arm/config.mk | 2 +- arch/arm/cpu/armv7/virt-dt.c | 7 +- arch/arm/cpu/armv8/Makefile | 2 + arch/arm/cpu/armv8/cpu-dt.c | 128 ++++++++++++++++++++++++++ arch/arm/cpu/armv8/cpu.c | 23 +++++ arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 46 +++------ arch/arm/cpu/armv8/psci.S | 177 ++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/u-boot.lds | 30 ++++++ arch/arm/include/asm/macro.h | 4 + arch/arm/include/asm/psci.h | 42 ++++++++- arch/arm/include/asm/system.h | 7 ++ arch/arm/lib/bootm-fdt.c | 11 ++- arch/arm/lib/bootm.c | 3 + 13 files changed, 446 insertions(+), 36 deletions(-) create mode 100644 arch/arm/cpu/armv8/cpu-dt.c create mode 100644 arch/arm/cpu/armv8/psci.S -- 1.7.7.4

7 32

[U-Boot] Building fw_env tools seems broken
by Denys Dmytriyenko 03 Dec '14

03 Dec '14

Hi, I came across this issue recently, that affects 2014.10 as well as master, but used to work fine in 2014.07 and older. Please let me know if I'm missing something or you need additional info. Thanks! $ make CROSS_COMPILE=arm-linux-gnueabihf- am335x_evm_defconfig HOSTCC scripts/basic/fixdep HOSTCC scripts/kconfig/conf.o HOSTCC scripts/kconfig/zconf.tab.o HOSTLD scripts/kconfig/conf # # configuration written to .config # # # configuration written to spl/.config # $ make CROSS_COMPILE=arm-linux-gnueabihf- env scripts/kconfig/conf --silentoldconfig Kconfig scripts/kconfig/conf --silentoldconfig Kconfig CHK include/config.h GEN include/autoconf.mk GEN include/autoconf.mk.dep GEN spl/include/autoconf.mk HOSTCC tools/env/fw_env.o In file included from tools/env/fw_env.c:117:0: include/env_default.h:110:11: error: expected ‘}’ before ‘CONFIG_SYS_ARCH’ scripts/Makefile.host:108: recipe for target 'tools/env/fw_env.o' failed make[1]: *** [tools/env/fw_env.o] Error 1 Makefile:1208: recipe for target 'env' failed make: *** [env] Error 2 -- Denys

2 3

[U-Boot] [PATCH v3 0/8] Add SD/NAND boot support for LS1021AQDS/TWR board
by Alison Wang 03 Dec '14

03 Dec '14

This series contain SD boot support for LS1021AQDS/TWR board and NAND boot support for LS1021AQDS board.SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card or NAND flash to DDR, finally SPL transfer control to u-boot. The patches are based on the previous 5 patches, [U-Boot,v2,5/5] arm: ls102xa: Select ge2_clk125 for eTSEC clock muxing [U-Boot,v2,4/5] arm: ls102xa: Add SystemID EEPROM support for LS1021ATWR board [U-Boot,v2,3/5] ls102xa: ifc: nor: fix the write issue when bytes unaligned [U-Boot,v2,2/5] arm: ls102xa: Remove bit reversing for SCFG registers [U-Boot,v2,1/5] arm: ls102xa: Add snoop disable for slave port 0, 1 and 2 Change log: v3: Change the Copyright year. Gave more explaination in the commit. Update MAINTAINERS files. Update PBI and RCW for SD boot. v2: Remove the definition of CONFIG_SPL_MAX_SIZE. Pad the variable u-boot size to 64 byte boundary in pblimage tool. Use pblimage_check_params() insteady of basing on the file name. Use generic u-boot-spl.lds. ---------------------------------------------------------------- Alison Wang (8): ls102xa: pblimage: Add pblimage tool support for LS102xA spl: Use u-boot.img instead of u-boot.bin arm: spl: Add I2C linker list in generic .lds common: spl: Add interactive DDR debugger support for SPL image ls102xa: qixis: Add CONFIG_QIXIS_I2C_ACCESS macro arm: ls102xa: Add SD boot support for LS1021AQDS board arm: ls102xa: Add SD boot support for LS1021ATWR board arm: ls102xa: Add NAND boot support for LS1021AQDS board Makefile | 11 +++++- arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/spl.c | 33 +++++++++++++++++ arch/arm/cpu/u-boot-spl.lds | 3 ++ arch/arm/include/asm/arch-ls102xa/config.h | 1 + arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 + arch/arm/include/asm/arch-ls102xa/spl.h | 20 ++++++++++ board/freescale/common/qixis.h | 7 ++++ board/freescale/ls1021aqds/MAINTAINERS | 2 + board/freescale/ls1021aqds/ddr.c | 5 ++- board/freescale/ls1021aqds/ls1021aqds.c | 47 +++++++++++++++++++++++ board/freescale/ls1021aqds/ls102xa_pbi.cfg | 12 ++++++ board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg | 7 ++++ board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg | 14 +++++++ board/freescale/ls1021atwr/MAINTAINERS | 1 + board/freescale/ls1021atwr/ls1021atwr.c | 30 +++++++++++++++ board/freescale/ls1021atwr/ls102xa_pbi.cfg | 12 ++++++ board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg | 14 +++++++ common/Makefile | 20 +++++----- configs/ls1021aqds_nand_defconfig | 4 ++ configs/ls1021aqds_sdcard_defconfig | 4 ++ configs/ls1021atwr_sdcard_defconfig | 4 ++ drivers/mtd/nand/fsl_ifc_spl.c | 8 ++++ include/configs/ls1021aqds.h | 134 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/configs/ls1021atwr.h | 51 +++++++++++++++++++++++++ tools/pblimage.c | 108 ++++++++++++++++++++++++++++++++++++----------------- 26 files changed, 508 insertions(+), 47 deletions(-) create mode 100644 arch/arm/cpu/armv7/ls102xa/spl.c create mode 100644 arch/arm/include/asm/arch-ls102xa/spl.h create mode 100644 board/freescale/ls1021aqds/ls102xa_pbi.cfg create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg create mode 100644 board/freescale/ls1021atwr/ls102xa_pbi.cfg create mode 100644 board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg create mode 100644 configs/ls1021aqds_nand_defconfig create mode 100644 configs/ls1021aqds_sdcard_defconfig create mode 100644 configs/ls1021atwr_sdcard_defconfig

4 14

[U-Boot] Bare x86 support is merged to u-boot-x86
by Simon Glass 03 Dec '14

03 Dec '14

Hi Bin (and others interested in U-Boot on x86), I've applied the remaining x86 patches to u-boot-x86. It runs on chromebook_link (Pixel) with support for most hardware relevant to a boot loader: SDRAM, SPI, PCI, USB (and USB Ethernet), SATA (internal 32GB SSD), SD card, LCD, UART, keyboard, EC. Bin this should be a good base for you to send patches for your Atom platform and I have no major work pending now so should not get in your way. Instructions on how to build and run are here: http://www.denx.de/wiki/U-Boot/X86 For this platform 4 binary blobs are needed. This is an unavoidable feature of the platform at present. The blobs cover flash descriptor, SDRAM init, video init and Management Engine. Instructions on how to get these are on the same page. Here is a list of some missing features: - README.x86 in the source (mostly the content from the Wiki page would be a good start) - MTRR support (for performance) - Audio - Chrome OS verified boot (only a rough rebase has been done, I'm not sure how to track mainline anyway) - SMI and ACPI support, to provide platform info and facilities to Linux Regards, Simon

5 9

[U-Boot] [PATCH 1/2] blackfin: spi: move spi max chip select to spi.h
by Scott Jiang 02 Dec '14

02 Dec '14

This macro is only related to spi. So it's better to place it in spi.h. Signed-off-by: Scott Jiang <scott.jiang.linux(a)gmail.com> --- arch/blackfin/include/asm/config-pre.h | 3 --- arch/blackfin/include/asm/mach-common/bits/spi.h | 1 + 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/blackfin/include/asm/config-pre.h b/arch/blackfin/include/asm/config-pre.h index 2d8b293..189cb05 100644 --- a/arch/blackfin/include/asm/config-pre.h +++ b/arch/blackfin/include/asm/config-pre.h @@ -70,9 +70,6 @@ static inline const char *get_bfin_boot_mode(int bfin_boot) # define BFIN_BOOT_SPI_SSEL 1 #endif -/* Define to get a GPIO CS with the Blackfin SPI controller */ -#define MAX_CTRL_CS 8 - /* There is no Blackfin/NetBSD port */ #undef CONFIG_BOOTM_NETBSD diff --git a/arch/blackfin/include/asm/mach-common/bits/spi.h b/arch/blackfin/include/asm/mach-common/bits/spi.h index 869dcb0..180cfaa 100644 --- a/arch/blackfin/include/asm/mach-common/bits/spi.h +++ b/arch/blackfin/include/asm/mach-common/bits/spi.h @@ -64,4 +64,5 @@ #define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ #define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ +#define MAX_CTRL_CS 7 #endif -- 1.7.9.5

2 8