October 2014 - U-Boot

[U-Boot] [PATCH 2/2] ls1: config: Enable USB EHCI Host on LS1021AQDS
by Nikhil Badola 25 Nov '14

25 Nov '14

Enable USB EHCI Host on LS1021AQDS Signed-off-by: Nikhil Badola <nikhil.badola(a)freescale.com> --- include/configs/ls1021aqds.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index bb47813..fd43a3e 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -273,6 +273,23 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_GENERIC_MMC /* + * USB + */ +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#endif +#endif + +/* * eTSEC */ #define CONFIG_TSEC_ENET -- 1.7.11.7

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[U-Boot] [PATCH 1/2] drivers: usb: fsl: Define USB configs for LS102XA
by Nikhil Badola 25 Nov '14

25 Nov '14

Define USB configs for LS1021XA such as CONFIG_SYS_FSL_USB1_ADDR, CONFIG_USB_MAX_CONTROLLER_COUNT Signed-off-by: Nikhil Badola <nikhil.badola(a)freescale.com> --- arch/arm/include/asm/arch-ls102xa/config.h | 4 ++++ include/usb/ehci-fsl.h | 3 +++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index a500b5b..cbf41da 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -25,7 +25,10 @@ #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) #define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) +#define CONFIG_SYS_LS102XA_USB1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET) +#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 #define CONFIG_SYS_TSEC3_OFFSET 0x01d90000 @@ -76,6 +79,7 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #else #error SoC not defined #endif diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index dd77ad6..897018b 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -163,6 +163,9 @@ #elif defined(CONFIG_MPC512X) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 +#elif defined(CONFIG_LS102XA) +#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR +#define CONFIG_SYS_FSL_USB2_ADDR 0 #endif /* -- 1.7.11.7

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[U-Boot] [PATCH] drivers : usb: fsl: Implement usb Erratum A007798 workaround
by Nikhil Badola 25 Nov '14

25 Nov '14

Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large usb writes Signed-off-by: Nikhil Badola <nikhil.badola(a)freescale.com> --- Depends on patch https://patchwork.ozlabs.org/patch/394797/ arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + drivers/usb/host/ehci-fsl.c | 3 +-- include/fsl_usb.h | 11 +++++++++++ 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 349ce52..fe3eb06 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -294,6 +294,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (has_erratum_a007075()) puts("Work-around for Erratum A007075 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007798 + if (has_erratum_a007798()) + puts("Work-around for Erratum A007798 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 712f2ef..486bc53 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -677,6 +677,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A007798 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_PCI_VER_3_X diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index c125e2c..7101202 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -131,8 +131,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, in_le32(&ehci->usbmode); - if (SVR_SOC_VER(get_svr()) == SVR_T4240 && - IS_SVR_REV(get_svr(), 2, 0)) + if (has_erratum_a007798()) set_txfifothresh(ehci, TXFIFOTHRESH); return 0; diff --git a/include/fsl_usb.h b/include/fsl_usb.h index 66f8934..e4902aa 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -139,6 +139,12 @@ static inline bool has_erratum_a007075(void) } return false; } + +static inline bool has_erratum_a007798(void) +{ + return SVR_SOC_VER(get_svr()) == SVR_T4240 && + IS_SVR_REV(get_svr(), 2, 0); +} #else static inline bool has_erratum_a006261(void) { @@ -150,5 +156,10 @@ static inline bool has_erratum_a007075(void) return false; } +static inline bool has_erratum_a007798(void) +{ + return false; +} + #endif #endif /*_ASM_FSL_USB_H_ */ -- 1.7.11.7

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[U-Boot] [PATCH 1/3] drivers: usb: fsl: Move USB Errata checking code
by Nikhil Badola 25 Nov '14

25 Nov '14

Move USB Errata checking code from "arch/powerpc" to architecture independent file "fsl_usb.h" so that errata(s) become independent of the architecture. For each erratum checking function for PPC arch, define a nop function for non PPC arch for successful compilation in either case Signed-off-by: Nikhil Badola <nikhil.badola(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 1 + arch/powerpc/include/asm/fsl_errata.h | 55 ----------------------------- drivers/usb/host/ehci-fsl.c | 2 +- include/fsl_usb.h | 66 +++++++++++++++++++++++++++++++++++ 4 files changed, 68 insertions(+), 56 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 3a04a89..349ce52 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -9,6 +9,7 @@ #include <linux/compiler.h> #include <asm/fsl_errata.h> #include <asm/processor.h> +#include <fsl_usb.h> #include "fsl_corenet_serdes.h" #ifdef CONFIG_SYS_FSL_ERRATUM_A004849 diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index 64da4bb..b9e2fb0 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -26,59 +26,4 @@ static inline bool has_erratum_a006379(void) return false; } #endif - -#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 -static inline bool has_erratum_a006261(void) -{ - u32 svr = get_svr(); - u32 soc = SVR_SOC_VER(svr); - - switch (soc) { - case SVR_P1010: - return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); - case SVR_P2041: - case SVR_P2040: - return IS_SVR_REV(svr, 1, 0) || - IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1); - case SVR_P3041: - return IS_SVR_REV(svr, 1, 0) || - IS_SVR_REV(svr, 1, 1) || - IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1); - case SVR_P5010: - case SVR_P5020: - case SVR_P5021: - return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); - case SVR_T4240: - case SVR_T4160: - case SVR_T4080: - return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); - case SVR_T1040: - return IS_SVR_REV(svr, 1, 0); - case SVR_T2080: - case SVR_T2081: - return IS_SVR_REV(svr, 1, 0); - case SVR_P5040: - return IS_SVR_REV(svr, 1, 0); - } - - return false; -} -#endif - -static inline bool has_erratum_a007075(void) -{ - u32 svr = get_svr(); - u32 soc = SVR_SOC_VER(svr); - - switch (soc) { - case SVR_B4860: - case SVR_B4420: - return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); - case SVR_P1010: - return IS_SVR_REV(svr, 1, 0); - case SVR_P4080: - return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0); - } - return false; -} #endif diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 45062e6..d5361d7 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -14,7 +14,7 @@ #include <asm/io.h> #include <usb/ehci-fsl.h> #include <hwconfig.h> -#include <asm/fsl_errata.h> +#include <fsl_usb.h> #include "ehci.h" diff --git a/include/fsl_usb.h b/include/fsl_usb.h index 1a6c9c1..66f8934 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -85,4 +85,70 @@ struct ccsr_usb_phy { #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07 #endif +/* USB Erratum Checking code */ +#ifdef CONFIG_PPC +static inline bool has_erratum_a006261(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_P1010: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P2041: + case SVR_P2040: + return IS_SVR_REV(svr, 1, 0) || + IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1); + case SVR_P3041: + return IS_SVR_REV(svr, 1, 0) || + IS_SVR_REV(svr, 1, 1) || + IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1); + case SVR_P5010: + case SVR_P5020: + case SVR_P5021: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_T4240: + case SVR_T4160: + case SVR_T4080: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_T1040: + return IS_SVR_REV(svr, 1, 0); + case SVR_T2080: + case SVR_T2081: + return IS_SVR_REV(svr, 1, 0); + case SVR_P5040: + return IS_SVR_REV(svr, 1, 0); + } + + return false; +} + +static inline bool has_erratum_a007075(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_B4860: + case SVR_B4420: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P1010: + return IS_SVR_REV(svr, 1, 0); + case SVR_P4080: + return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0); + } + return false; +} +#else +static inline bool has_erratum_a006261(void) +{ + return false; +} + +static inline bool has_erratum_a007075(void) +{ + return false; +} + +#endif #endif /*_ASM_FSL_USB_H_ */ -- 1.7.11.7

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[U-Boot] [PATCH 0/4] Deep sleep patches for Freescale QorIQ platforms
by Yuantian.Tang＠freescale.com 25 Nov '14

25 Nov '14

From: Tang Yuantian <Yuantian.Tang(a)freescale.com> These patches depend on the following patches: https://patchwork.ozlabs.org/patch/389949/ https://patchwork.ozlabs.org/patch/389950/ https://patchwork.ozlabs.org/patch/389951/ https://patchwork.ozlabs.org/patch/389952/ Tang Yuantian (4): Add deep sleep framework support for Freescale QorIQ platforms ARM: HYP/non-sec: Make armv7_init_nonsec() usable before relocation arm: ls102xa: Fixed a register definition error arm: ls1021qds: Add deep sleep support arch/arm/cpu/armv7/virt-v7.c | 14 +++--- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- board/freescale/ls1021aqds/ddr.c | 7 +++ board/freescale/ls1021aqds/ls1021aqds.c | 60 +++++++++++++++++++++++ common/board_f.c | 10 ++++ drivers/ddr/fsl/arm_ddr_gen3.c | 48 ++++++++++++++++-- include/configs/ls1021aqds.h | 4 ++ include/fsl_ddr_sdram.h | 2 + include/fsl_sleep.h | 32 ++++++++++++ 9 files changed, 167 insertions(+), 12 deletions(-) create mode 100644 include/fsl_sleep.h -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 3/4] qe: add qe support to ls1021aqds
by Zhao Qiang 25 Nov '14

25 Nov '14

add qe support to ls1021aqds Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- board/freescale/ls1021aqds/ls1021aqds.c | 8 ++++++++ include/configs/ls1021aqds.h | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 12e83f7..3bc4a68 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -16,6 +16,9 @@ #include "../common/qixis.h" #include "ls1021aqds_qixis.h" +#ifdef CONFIG_U_QE +#include "../../../drivers/qe/qe.h" +#endif DECLARE_GLOBAL_DATA_PTR; @@ -227,6 +230,11 @@ int board_init(void) fsl_serdes_init(); config_serdes_mux(); #endif + +#ifdef CONFIG_U_QE + u_qe_init(); +#endif + return 0; } diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 657e3b6..e19b81e 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -67,6 +67,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_HAS_SERDES +#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI) +#define CONFIG_U_QE +#endif /* * IFC Definitions */ @@ -329,6 +332,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTDELAY 3 +#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 + #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "fdt_high=0xcfffffff\0" \ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 2/4] qe: add u-qe support to arm board
by Zhao Qiang 25 Nov '14

25 Nov '14

ls1021 is arm-core and support qe which is u-qe. add u-qe init for arm board. Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- arch/arm/include/asm/arch-ls102xa/config.h | 4 ++++ arch/arm/include/asm/global_data.h | 8 ++++++++ drivers/Makefile | 1 + drivers/qe/Makefile | 3 ++- drivers/qe/fdt.c | 2 ++ drivers/qe/qe.c | 13 +++++++++++++ drivers/qe/qe.h | 1 + 7 files changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index ed78c33..526ceb4 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -65,6 +65,10 @@ #define DCU_LAYER_MAX_NUM 16 +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 + #define CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_LS102XA diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 63e4ad5..900f127 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -17,6 +17,14 @@ struct arch_global_data { #if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; #endif + +#if defined(CONFIG_U_QE) + u32 qe_clk; + u32 brg_clk; + uint mp_alloc_base; + uint mp_alloc_top; +#endif /* CONFIG_U_QE */ + #ifdef CONFIG_AT91FAMILY /* "static data" needed by at91's clock.c */ unsigned long cpu_clk_rate_hz; diff --git a/drivers/Makefile b/drivers/Makefile index b23076f..f4ae477 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -14,4 +14,5 @@ obj-y += twserial/ obj-y += video/ obj-y += watchdog/ obj-$(CONFIG_QE) += qe/ +obj-$(CONFIG_U_QE) += qe/ obj-y += memory/ diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile index 7f1bd06..8fa4866 100644 --- a/drivers/qe/Makefile +++ b/drivers/qe/Makefile @@ -4,5 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := qe.o uccf.o uec.o uec_phy.o +obj-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o +obj-$(CONFIG_U_QE) += qe.o obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c index d9a7d82..dfae4bf 100644 --- a/drivers/qe/fdt.c +++ b/drivers/qe/fdt.c @@ -12,6 +12,7 @@ #include <fdt_support.h> #include "qe.h" +#ifdef CONFIG_QE DECLARE_GLOBAL_DATA_PTR; /* @@ -72,3 +73,4 @@ void ft_qe_setup(void *blob) "clock-frequency", gd->arch.qe_clk / 2, 1); fdt_fixup_qe_firmware(blob); } +#endif diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index be09a17..075fd48 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -40,6 +40,7 @@ void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data) return; } +#ifdef CONFIG_QE uint qe_muram_alloc(uint size, uint align) { uint retloc; @@ -70,6 +71,7 @@ uint qe_muram_alloc(uint size, uint align) return retloc; } +#endif void *qe_muram_addr(uint offset) { @@ -180,6 +182,15 @@ void qe_init(uint qe_base) qe_snums_init(); } +void u_qe_init(void) +{ + uint qe_base = CONFIG_SYS_IMMR + 0x01400000; /* QE immr base */ + qe_immr = (qe_map_t *)qe_base; + + qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR); + out_be32(&qe_immr->iram.iready, QE_IRAM_READY); +} + void qe_reset(void) { qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID, @@ -212,6 +223,7 @@ void qe_assign_page(uint snum, uint para_ram_base) #define BRG_CLK (gd->arch.brg_clk) +#ifdef CONFIG_QE int qe_set_brg(uint brg, uint rate) { volatile uint *bp; @@ -239,6 +251,7 @@ int qe_set_brg(uint brg, uint rate) return 0; } +#endif /* Set ethernet MII clock master */ diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index ebb7c5f..30484b8 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -275,6 +275,7 @@ void *qe_muram_addr(uint offset); int qe_get_snum(void); void qe_put_snum(u8 snum); void qe_init(uint qe_base); +void u_qe_init(void); void qe_reset(void); void qe_assign_page(uint snum, uint para_ram_base); int qe_set_brg(uint brg, uint rate); -- 2.1.0.27.g96db324

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[U-Boot] [Patch] mmc: fsl_esdhc: fix f_max retrieval during init
by Markus Niebel 25 Nov '14

25 Nov '14

From: Markus Niebel <Markus.Niebel(a)tq-group.com> for multi instance API we use struct fsl_esdhc_cfg to pass the clock rate. Do not set f_max from global data, since this is wrong for multi instance case. Signed-off-by: Markus Niebel <Markus.Niebel(a)tq-group.com> --- drivers/mmc/fsl_esdhc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 2640607..8a1a461 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -610,7 +610,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) #endif cfg->cfg.f_min = 400000; - cfg->cfg.f_max = min(gd->arch.sdhc_clk, 52000000); + cfg->cfg.f_max = min(cfg->sdhc_clk, 52000000); cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; -- 2.1.1

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[U-Boot] [PATCH 1/4] net/fm: add 2.5G SGMII support
by Shengzhou Liu 25 Nov '14

25 Nov '14

As auto-negotiation is not supported for 2.5G SGMII, we need to add a new type PHY_INTERFACE_MODE_SGMII_2500 to differentiate SGMII-1G and SGMII-2.5G with different setting for auto-negotiation. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- arch/powerpc/include/asm/fsl_serdes.h | 16 ++++++++++++++++ drivers/net/fm/eth.c | 16 ++++++++++++---- include/phy.h | 2 ++ 3 files changed, 30 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index f60cb0a..8e0e190 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -71,6 +71,22 @@ enum srds_prtcl { INTERLAKEN, QSGMII_SW1_A, /* Indicates ports on L2 Switch */ QSGMII_SW1_B, + SGMII_2500_FM1_DTSEC1, + SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC3, + SGMII_2500_FM1_DTSEC4, + SGMII_2500_FM1_DTSEC5, + SGMII_2500_FM1_DTSEC6, + SGMII_2500_FM1_DTSEC9, + SGMII_2500_FM1_DTSEC10, + SGMII_2500_FM2_DTSEC1, + SGMII_2500_FM2_DTSEC2, + SGMII_2500_FM2_DTSEC3, + SGMII_2500_FM2_DTSEC4, + SGMII_2500_FM2_DTSEC5, + SGMII_2500_FM2_DTSEC6, + SGMII_2500_FM2_DTSEC9, + SGMII_2500_FM2_DTSEC10, }; enum srds { diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 218a5ed..137886c 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -39,9 +39,14 @@ static void dtsec_configure_serdes(struct fm_eth *priv) u32 value; struct mii_dev bus; bus.priv = priv->mac->phyregs; + bool sgmii_2500 = (priv->enet_if == + PHY_INTERFACE_MODE_SGMII_2500) ? true : false; + + /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */ + value = PHY_SGMII_IF_MODE_SGMII; + if (!sgmii_2500) + value |= PHY_SGMII_IF_MODE_AN; - /* SGMII IF mode + AN enable */ - value = PHY_SGMII_IF_MODE_AN | PHY_SGMII_IF_MODE_SGMII; memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value); /* Dev ability according to SGMII specification */ @@ -54,7 +59,9 @@ static void dtsec_configure_serdes(struct fm_eth *priv) memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40); /* Restart AN */ - value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN; + value = PHY_SGMII_CR_DEF_VAL; + if (!sgmii_2500) + value |= PHY_SGMII_CR_RESET_AN; memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value); #else struct dtsec *regs = priv->mac->base; @@ -83,7 +90,8 @@ static void dtsec_init_phy(struct eth_device *dev) out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE); #endif - if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) + if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII || + fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) dtsec_configure_serdes(fm_eth); } diff --git a/include/phy.h b/include/phy.h index d3ecd63..3c5f111 100644 --- a/include/phy.h +++ b/include/phy.h @@ -39,6 +39,7 @@ typedef enum { PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_SGMII, + PHY_INTERFACE_MODE_SGMII_2500, PHY_INTERFACE_MODE_QSGMII, PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RMII, @@ -55,6 +56,7 @@ static const char *phy_interface_strings[] = { [PHY_INTERFACE_MODE_MII] = "mii", [PHY_INTERFACE_MODE_GMII] = "gmii", [PHY_INTERFACE_MODE_SGMII] = "sgmii", + [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500", [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", [PHY_INTERFACE_MODE_TBI] = "tbi", [PHY_INTERFACE_MODE_RMII] = "rmii", -- 1.8.0

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[U-Boot] [PATCH 2/2][v2] powerpc/t2080qds: fix for 1000BASE-KX
by shh.xie＠gmail.com 25 Nov '14

25 Nov '14

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> 1000BASE-KX(1G-KX) uses SGMII protocol but the serdes lane runs in 1G-KX mode. By default, the lane runs in SGMII mode, when a MAC uses a lane in 1G-KX mode, corresponding bit in PCCR1 for the lane needs to be set, and needs to fixup dtb accordingly for kernel to do proper initialization. Hwconfig "fsl_1gkx" is used to indicate a MAC runs in 1G-KX mode, FM1 MAC 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a MAC runs in 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1' stands for FM1-MAC1, 'fm1_1g2' stands for FM1-MAC2, etc. If all MAC 1/2/5/6/9/10 run in 1G-KX mode, the hwconfig should has below setting: fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10 Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- changes for V2: - add 1G-KX description in t208xqds README. - refined commit message. board/freescale/t208xqds/README | 12 +++++ board/freescale/t208xqds/eth_t208xqds.c | 86 +++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+) diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README index e3eb5ba..83060c1 100755 --- a/board/freescale/t208xqds/README +++ b/board/freescale/t208xqds/README @@ -104,6 +104,18 @@ XFI: set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two XFI ports will use copper cable, the other two XFI ports will use fiber cable. +1000BASE-KX(1G-KX): + - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane + runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane + in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration + Register 1 (PCCR1), and U-boot fixup the dtb for kernel to do proper + initialization. + Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC + 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a + MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1' + stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc. + For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in + hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode. System Memory map ---------------- diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 8675dbb..b3a4317 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -47,6 +47,15 @@ #define EMI2 8 #endif +#define PCCR1_SGMIIA_KX_MASK 0x00008000 +#define PCCR1_SGMIIB_KX_MASK 0x00004000 +#define PCCR1_SGMIIC_KX_MASK 0x00002000 +#define PCCR1_SGMIID_KX_MASK 0x00001000 +#define PCCR1_SGMIIE_KX_MASK 0x00000800 +#define PCCR1_SGMIIF_KX_MASK 0x00000400 +#define PCCR1_SGMIIG_KX_MASK 0x00000200 +#define PCCR1_SGMIIH_KX_MASK 0x00000100 + static int mdio_mux[NUM_FM_PORTS]; static const char * const mdio_names[] = { @@ -195,6 +204,10 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, int off; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1); + u32 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; @@ -205,9 +218,54 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, switch (port) { #if defined(CONFIG_T2080QDS) case FM1_DTSEC1: + if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx1"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1"); + sprintf(buf, "%s%s%s", buf, "lane-c,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIH_KX_MASK); + break; + } case FM1_DTSEC2: + if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx2"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2"); + sprintf(buf, "%s%s%s", buf, "lane-d,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIG_KX_MASK); + break; + } case FM1_DTSEC9: + if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx9"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9"); + sprintf(buf, "%s%s%s", buf, "lane-a,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIE_KX_MASK); + break; + } case FM1_DTSEC10: + if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx10"); + fdt_status_okay_by_alias(fdt, + "1gkx_pcs_mdio10"); + sprintf(buf, "%s%s%s", buf, "lane-b,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIF_KX_MASK); + break; + } if (mdio_mux[port] == EMI1_SLOT2) { sprintf(alias, "phy_sgmii_s2_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); @@ -219,7 +277,29 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, } break; case FM1_DTSEC5: + if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx5"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5"); + sprintf(buf, "%s%s%s", buf, "lane-g,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIC_KX_MASK); + break; + } case FM1_DTSEC6: + if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx6"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6"); + sprintf(buf, "%s%s%s", buf, "lane-h,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIID_KX_MASK); + break; + } if (mdio_mux[port] == EMI1_SLOT1) { sprintf(alias, "phy_sgmii_s1_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); @@ -263,6 +343,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, default: break; } + if (media_type) { + /* set property for 1000BASE-KX in dtb */ + off = fdt_node_offset_by_compat_reg(fdt, + "fsl,fman-memac-mdio", addr + 0x1000); + fdt_setprop_string(fdt, off, "lane-instance", buf); + } } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { switch (srds_s1) { -- 1.8.0

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