October 2014 - U-Boot

[U-Boot] [PATCH] image-fdt: boot_get_fdt() return value when no DTB exists
by Noam Camus 03 Dec '14

03 Dec '14

From: Noam Camus <noamc(a)ezchip.com> I believe that when no DTB is around we should return 1. This why I fixed such scenarious to not return zero anymore. Else kernel might get NULL pointer to DTB which doesn't exists. Signed-off-by: Noam Camus <noamc(a)ezchip.com> --- common/image-fdt.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/common/image-fdt.c b/common/image-fdt.c index 9fc7481..c142ae6 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -413,11 +413,11 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, } } else { debug("## No Flattened Device Tree\n"); - return 0; + goto error; } } else { debug("## No Flattened Device Tree\n"); - return 0; + goto error; } *of_flat_tree = fdt_blob; -- 1.7.1

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[U-Boot] [PATCH 0/8] PSCI v0.2 framework for ARMv8
by Arnab Basu 03 Dec '14

03 Dec '14

This series of patches creates a generic PSCI v0.2 framework for ARMv8. The first 3 patches refactor existing code so that ARMv7 PSCI, ARMv8 spin-table and ARMv8 PSCI can coexist. The next 5 patches create a generic framework for PSCI v0.2 in ARMv8. The implementation is modelled on the pre-existing PSCI v0.1 support in ARMv7. PSCI support patches for the ARMv8 Foundation model will follow shortly. Arnab Basu (8): ARM: PSCI: Update psci.h for psci v0.2 ARM: PSCI: Alow arch specific DT patching ARMv8/fsl-lsch3: Refactor spin-table code ARMv8: PSCI: Add linker section to hold PSCI code ARMv8: PCSI: Add generic ARMv8 PSCI code ARMv8: PSCI: Fixup the device tree for PSCI v0.2 ARMv8: PSCI: Setup ARMv8 PSCI ARMv8: PSCI: Enable SMC arch/arm/config.mk | 2 +- arch/arm/cpu/armv7/virt-dt.c | 7 +- arch/arm/cpu/armv8/Makefile | 2 + arch/arm/cpu/armv8/cpu-dt.c | 128 ++++++++++++++++++++++++++ arch/arm/cpu/armv8/cpu.c | 23 +++++ arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 46 +++------ arch/arm/cpu/armv8/psci.S | 177 ++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/u-boot.lds | 30 ++++++ arch/arm/include/asm/macro.h | 4 + arch/arm/include/asm/psci.h | 42 ++++++++- arch/arm/include/asm/system.h | 7 ++ arch/arm/lib/bootm-fdt.c | 11 ++- arch/arm/lib/bootm.c | 3 + 13 files changed, 446 insertions(+), 36 deletions(-) create mode 100644 arch/arm/cpu/armv8/cpu-dt.c create mode 100644 arch/arm/cpu/armv8/psci.S -- 1.7.7.4

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[U-Boot] [PATCH v3 0/8] Add SD/NAND boot support for LS1021AQDS/TWR board
by Alison Wang 03 Dec '14

03 Dec '14

This series contain SD boot support for LS1021AQDS/TWR board and NAND boot support for LS1021AQDS board.SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card or NAND flash to DDR, finally SPL transfer control to u-boot. The patches are based on the previous 5 patches, [U-Boot,v2,5/5] arm: ls102xa: Select ge2_clk125 for eTSEC clock muxing [U-Boot,v2,4/5] arm: ls102xa: Add SystemID EEPROM support for LS1021ATWR board [U-Boot,v2,3/5] ls102xa: ifc: nor: fix the write issue when bytes unaligned [U-Boot,v2,2/5] arm: ls102xa: Remove bit reversing for SCFG registers [U-Boot,v2,1/5] arm: ls102xa: Add snoop disable for slave port 0, 1 and 2 Change log: v3: Change the Copyright year. Gave more explaination in the commit. Update MAINTAINERS files. Update PBI and RCW for SD boot. v2: Remove the definition of CONFIG_SPL_MAX_SIZE. Pad the variable u-boot size to 64 byte boundary in pblimage tool. Use pblimage_check_params() insteady of basing on the file name. Use generic u-boot-spl.lds. ---------------------------------------------------------------- Alison Wang (8): ls102xa: pblimage: Add pblimage tool support for LS102xA spl: Use u-boot.img instead of u-boot.bin arm: spl: Add I2C linker list in generic .lds common: spl: Add interactive DDR debugger support for SPL image ls102xa: qixis: Add CONFIG_QIXIS_I2C_ACCESS macro arm: ls102xa: Add SD boot support for LS1021AQDS board arm: ls102xa: Add SD boot support for LS1021ATWR board arm: ls102xa: Add NAND boot support for LS1021AQDS board Makefile | 11 +++++- arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/spl.c | 33 +++++++++++++++++ arch/arm/cpu/u-boot-spl.lds | 3 ++ arch/arm/include/asm/arch-ls102xa/config.h | 1 + arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 + arch/arm/include/asm/arch-ls102xa/spl.h | 20 ++++++++++ board/freescale/common/qixis.h | 7 ++++ board/freescale/ls1021aqds/MAINTAINERS | 2 + board/freescale/ls1021aqds/ddr.c | 5 ++- board/freescale/ls1021aqds/ls1021aqds.c | 47 +++++++++++++++++++++++ board/freescale/ls1021aqds/ls102xa_pbi.cfg | 12 ++++++ board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg | 7 ++++ board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg | 14 +++++++ board/freescale/ls1021atwr/MAINTAINERS | 1 + board/freescale/ls1021atwr/ls1021atwr.c | 30 +++++++++++++++ board/freescale/ls1021atwr/ls102xa_pbi.cfg | 12 ++++++ board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg | 14 +++++++ common/Makefile | 20 +++++----- configs/ls1021aqds_nand_defconfig | 4 ++ configs/ls1021aqds_sdcard_defconfig | 4 ++ configs/ls1021atwr_sdcard_defconfig | 4 ++ drivers/mtd/nand/fsl_ifc_spl.c | 8 ++++ include/configs/ls1021aqds.h | 134 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/configs/ls1021atwr.h | 51 +++++++++++++++++++++++++ tools/pblimage.c | 108 ++++++++++++++++++++++++++++++++++++----------------- 26 files changed, 508 insertions(+), 47 deletions(-) create mode 100644 arch/arm/cpu/armv7/ls102xa/spl.c create mode 100644 arch/arm/include/asm/arch-ls102xa/spl.h create mode 100644 board/freescale/ls1021aqds/ls102xa_pbi.cfg create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg create mode 100644 board/freescale/ls1021atwr/ls102xa_pbi.cfg create mode 100644 board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg create mode 100644 configs/ls1021aqds_nand_defconfig create mode 100644 configs/ls1021aqds_sdcard_defconfig create mode 100644 configs/ls1021atwr_sdcard_defconfig

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[U-Boot] [PATCH 1/2] blackfin: spi: move spi max chip select to spi.h
by Scott Jiang 02 Dec '14

02 Dec '14

This macro is only related to spi. So it's better to place it in spi.h. Signed-off-by: Scott Jiang <scott.jiang.linux(a)gmail.com> --- arch/blackfin/include/asm/config-pre.h | 3 --- arch/blackfin/include/asm/mach-common/bits/spi.h | 1 + 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/blackfin/include/asm/config-pre.h b/arch/blackfin/include/asm/config-pre.h index 2d8b293..189cb05 100644 --- a/arch/blackfin/include/asm/config-pre.h +++ b/arch/blackfin/include/asm/config-pre.h @@ -70,9 +70,6 @@ static inline const char *get_bfin_boot_mode(int bfin_boot) # define BFIN_BOOT_SPI_SSEL 1 #endif -/* Define to get a GPIO CS with the Blackfin SPI controller */ -#define MAX_CTRL_CS 8 - /* There is no Blackfin/NetBSD port */ #undef CONFIG_BOOTM_NETBSD diff --git a/arch/blackfin/include/asm/mach-common/bits/spi.h b/arch/blackfin/include/asm/mach-common/bits/spi.h index 869dcb0..180cfaa 100644 --- a/arch/blackfin/include/asm/mach-common/bits/spi.h +++ b/arch/blackfin/include/asm/mach-common/bits/spi.h @@ -64,4 +64,5 @@ #define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ #define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ +#define MAX_CTRL_CS 7 #endif -- 1.7.9.5

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[U-Boot] [PATCH 1/3] sf: stmicro: Add support for N25Q32
by Michal Simek 02 Dec '14

02 Dec '14

From: Jagannadha Sutradharudu Teki <jagannadha.sutradharudu-teki(a)xilinx.com> Add support for Numonyx N25Q32 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/mtd/spi/stmicro.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c index 32df827..09a3d68 100644 --- a/drivers/mtd/spi/stmicro.c +++ b/drivers/mtd/spi/stmicro.c @@ -93,6 +93,12 @@ static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = { .name = "M25P128", }, { + .id = 0xba16, + .pages_per_sector = 256, + .nr_sectors = 64, + .name = "N25Q32", + }, + { .id = 0xba17, .pages_per_sector = 256, .nr_sectors = 128, -- 1.7.0.4

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[U-Boot] WARNING Could not get liodn of node /pcie@ffe240000: FDT_ERR_NOTFOUND
by Joakim Tjernlund 01 Dec '14

01 Dec '14

Booting my t1042 I get: Loading Ramdisk to 2e639000, end 2ffffcc4 ... OK Loading Device Tree to 03fe4000, end 03fffd45 ... OK WARNING Could not get liodn of node /pcie@ffe240000: FDT_ERR_NOTFOUND WARNING Could not get liodn of node /pcie@ffe250000: FDT_ERR_NOTFOUND WARNING Could not get liodn of node /pcie@ffe240000: FDT_ERR_NOTFOUND WARNING Could not get liodn of node /pcie@ffe250000: FDT_ERR_NOTFOUND .... This apperas to come from base_liodn = fdt_getprop(fdt, off, "fsl,liodn", &rc); if (!base_liodn) { char path[64]; if (fdt_get_path(fdt, off, path, sizeof(path)) < 0) strcpy(path, "(unknown)"); printf("WARNING Could not get liodn of node %s: %s\n", path, fdt_strerror(rc)); continue; } but I cannot find out what what this property should be. Anyone?

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[U-Boot] arm kirkwood pending patches
by Luka Perkov 29 Nov '14

29 Nov '14

Hi, I have noticed that there are 3 pending kirkwood patches that I've sent a while back. It seems that there has been no action since then. Patches have been ACKed... Can we get some progress on these: http://patchwork.ozlabs.org/patch/366225/ http://patchwork.ozlabs.org/patch/366226/ http://patchwork.ozlabs.org/patch/366227/ Thanks. Regards, Luka

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[U-Boot] [PATCH v1 0/9] Add full DDR init for Marvell Armada-XP MV78xx0 (AXP)
by Stefan Roese 27 Nov '14

27 Nov '14

This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the AXP boot image. Not linked with the main U-Boot. With this code addition and the also included SERDES / PHY setup code, the Armada-XP support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Hopefully other MVEBU SoC's will follow here. Tested on AXP using a SPD DIMM setup on the Marvell DB-MV784MP-GP board and on a custom fixed DDR configuration board (maxbcm with MV78460). Thanks, Stefan Stefan Roese (9): arm: mvebu: drivers/ddr: Add DDR3 driver with training code from Marvell bin_hdr arm: mvebu: Add Serdes PHY config code arm: armada-xp: Add SPL support used to include the DDR training code scripts/Makefile.spl: Add MVEBU DDR code to SPL tools: kwbimage: Support u-boot.img padding to CONFIG_SYS_SPI_U_BOOT_OFFS Makefile: Add another kwb build target used on Marvell Armada-XP (AXP) arm: db-mv784mp-gp: Enable SPL to include DDR training code into U-Boot arm: maxbcm: Enable SPL to include DDR training code into U-Boot arm: armada-xp: Change built target to include the SPL binary as bin_hdr Makefile | 6 + arch/arm/Kconfig | 2 + arch/arm/cpu/armv7/armada-xp/Makefile | 2 + arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S | 62 + arch/arm/cpu/armv7/armada-xp/spl.c | 38 + arch/arm/include/asm/arch-armada-xp/config.h | 4 + arch/arm/include/asm/arch-armada-xp/cpu.h | 16 + arch/arm/mvebu-common/Makefile | 2 + arch/arm/mvebu-common/serdes/Makefile | 6 + arch/arm/mvebu-common/serdes/board_env_spec.h | 262 ++++ arch/arm/mvebu-common/serdes/high_speed_env_lib.c | 1572 +++++++++++++++++++ arch/arm/mvebu-common/serdes/high_speed_env_spec.c | 185 +++ arch/arm/mvebu-common/serdes/high_speed_env_spec.h | 87 ++ arch/arm/mvebu-common/u-boot-spl.lds | 57 + board/Marvell/db-mv784mp-gp/kwbimage.cfg | 2 +- board/maxbcm/kwbimage.cfg | 2 +- board/maxbcm/maxbcm.c | 83 +- configs/db-mv784mp-gp_defconfig | 5 +- configs/maxbcm_defconfig | 5 +- drivers/ddr/mvebu/Makefile | 14 + drivers/ddr/mvebu/ddr3_axp.h | 510 +++++++ drivers/ddr/mvebu/ddr3_axp_config.h | 146 ++ drivers/ddr/mvebu/ddr3_axp_mc_static.h | 284 ++++ drivers/ddr/mvebu/ddr3_axp_training_static.h | 770 ++++++++++ drivers/ddr/mvebu/ddr3_axp_vars.h | 226 +++ drivers/ddr/mvebu/ddr3_dfs.c | 1552 +++++++++++++++++++ drivers/ddr/mvebu/ddr3_dqs.c | 1374 +++++++++++++++++ drivers/ddr/mvebu/ddr3_hw_training.c | 1115 ++++++++++++++ drivers/ddr/mvebu/ddr3_hw_training.h | 392 +++++ drivers/ddr/mvebu/ddr3_init.c | 1219 +++++++++++++++ drivers/ddr/mvebu/ddr3_init.h | 143 ++ drivers/ddr/mvebu/ddr3_patterns_64bit.h | 924 ++++++++++++ drivers/ddr/mvebu/ddr3_pbs.c | 1592 ++++++++++++++++++++ drivers/ddr/mvebu/ddr3_read_leveling.c | 1214 +++++++++++++++ drivers/ddr/mvebu/ddr3_sdram.c | 669 ++++++++ drivers/ddr/mvebu/ddr3_spd.c | 1300 ++++++++++++++++ drivers/ddr/mvebu/ddr3_write_leveling.c | 1366 +++++++++++++++++ drivers/ddr/mvebu/xor.c | 436 ++++++ drivers/ddr/mvebu/xor.h | 70 + drivers/ddr/mvebu/xor_regs.h | 103 ++ include/configs/db-mv784mp-gp.h | 49 + include/configs/maxbcm.h | 47 + scripts/Makefile.spl | 3 + tools/kwbimage.c | 11 + 44 files changed, 17919 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S create mode 100644 arch/arm/cpu/armv7/armada-xp/spl.c create mode 100644 arch/arm/mvebu-common/serdes/Makefile create mode 100644 arch/arm/mvebu-common/serdes/board_env_spec.h create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_lib.c create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_spec.c create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_spec.h create mode 100644 arch/arm/mvebu-common/u-boot-spl.lds create mode 100644 drivers/ddr/mvebu/Makefile create mode 100644 drivers/ddr/mvebu/ddr3_axp.h create mode 100644 drivers/ddr/mvebu/ddr3_axp_config.h create mode 100644 drivers/ddr/mvebu/ddr3_axp_mc_static.h create mode 100644 drivers/ddr/mvebu/ddr3_axp_training_static.h create mode 100644 drivers/ddr/mvebu/ddr3_axp_vars.h create mode 100644 drivers/ddr/mvebu/ddr3_dfs.c create mode 100644 drivers/ddr/mvebu/ddr3_dqs.c create mode 100644 drivers/ddr/mvebu/ddr3_hw_training.c create mode 100644 drivers/ddr/mvebu/ddr3_hw_training.h create mode 100644 drivers/ddr/mvebu/ddr3_init.c create mode 100644 drivers/ddr/mvebu/ddr3_init.h create mode 100644 drivers/ddr/mvebu/ddr3_patterns_64bit.h create mode 100644 drivers/ddr/mvebu/ddr3_pbs.c create mode 100644 drivers/ddr/mvebu/ddr3_read_leveling.c create mode 100644 drivers/ddr/mvebu/ddr3_sdram.c create mode 100644 drivers/ddr/mvebu/ddr3_spd.c create mode 100644 drivers/ddr/mvebu/ddr3_write_leveling.c create mode 100644 drivers/ddr/mvebu/xor.c create mode 100644 drivers/ddr/mvebu/xor.h create mode 100644 drivers/ddr/mvebu/xor_regs.h -- 2.1.2

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[U-Boot] [PATCH 0/1] ls1021aqds: add hwconfig setting to do pin mux
by Yuan Yao 25 Nov '14

25 Nov '14

Added in v1: - Add pin mux support for ls1021aqds. Test log: U-Boot 2014.07-01993-g052b512-dirty (Oct 20 2014 - 19:58:20) CPU: Freescale LayerScape LS1020E, Version: 1.0, (0x87081010) Clock Configuration: CPU0(ARMV7):1000 MHz, Bus:300 MHz, DDR:800 MHz (1600 MT/s data rate), Reset Configuration Word (RCW): 00000000: 0608000a 00000000 00000000 00000000 00000010: 60000000 00407900 e0025a00 21046000 00000020: 00000000 00000000 00000000 00038000 00000030: 00000000 001b7200 00000000 00000000 Board: LS1021AQDS vBank: 4 Sys ID:0x2b, Sys Ver: 0x11 FPGA: v13 (QIXIS_LS1021QDS_2014_08_27_1658), build 65386 I2C: ready DRAM: Initializing DDR....using SPD Detected UDIMM 18KSF51272AZ-1G6K1 2 GiB (DDR3, 32-bit, CL=11, ECC off) Using SERDES1 Protocol: 96 (0x60) Flash: 128 MiB NAND: 0 MiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: eTSEC1 is in sgmii mode eTSEC2 is in sgmii mode Phy not found PHY reset timed out Phy not found PHY reset timed out eTSEC1, eTSEC2, eTSEC3 [PRIME] => pri baudrate=115200 boot=dhcp 82000000 r66431/ls1/uImage.ls1021a; tftp 8f000000 r66431/ls1/ls1021a-qds.dtb; tftp 88000000 r66431/ls1/fsl-image-x11-ls1021aqds-20140424073555.rootfs.ext2.gz.u-boot ; bootm 82000000 88000000 8f000000 boot_bank0=i2c mw 0x66 0x50 0x40;i2c mw 0x66 0x10 0x20;i2c mw 0x66 0x10 0x21 boot_bank4=i2c mw 0x66 0x50 0x44;i2c mw 0x66 0x10 0x20;i2c mw 0x66 0x10 0x21 bootargs=root=/dev/ram0 rw console=ttyS0,115200 bootdelay=3 eth1addr=00:04:9f:03:2e:c5 eth2addr=00:04:9f:03:2e:c6 eth3addr=00:04:9f:03:2e:c7 eth4addr=00:04:9f:03:2e:c8 eth5addr=00:04:9f:03:2e:c9 eth6addr=00:04:9f:03:2e:ca ethact=eTSEC3 ethaddr=00:04:9f:03:2e:c4 ethprime=eTSEC3 fdt_high=0xffffffff hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null,ecc=off initrd_high=0xffffffff ipaddr=192.168.1.121 loadaddr=0x82000000 scsidevs=0 serverip=192.168.1.1 stderr=serial stdin=serial stdout=serial zhuoboot=tftp 82000000 b46552/ls1021aqds/uImage.ls1021a; tftp 8f000000 b46552/ls1021aqds/ls1021a-qds.dtb;tftp 88000000 b46552/ls1021aqds/ramdisk.small;bootm 82000000 88000000 8f000000 Environment size: 1117/8188 bytes => i2c md 0x66 0x5e 005e: 00 00 12 81 f7 ff ff ff ff ef e7 00 3f ff ff ff ............?... => set hwconfig "fsl_ddr:ctlr_intlv=null,bank_intlv=null,ecc=off;sai" => save Saving Environment to Flash... Un-Protected 1 sectors Erasing Flash... . done Erased 1 sectors Writing to Flash... 9....8....7....6....5....4....3....2....1....9....8....7....6....5....4....3....2....1....done Protected 1 sectors => run boot_bank4 U-Boot 2014.07-01993-g052b512-dirty (Oct 20 2014 - 19:58:20) CPU: Freescale LayerScape LS1020E, Version: 1.0, (0x87081010) Clock Configuration: CPU0(ARMV7):1000 MHz, Bus:300 MHz, DDR:800 MHz (1600 MT/s data rate), Reset Configuration Word (RCW): 00000000: 0608000a 00000000 00000000 00000000 00000010: 60000000 00407900 e0025a00 21046000 00000020: 00000000 00000000 00000000 00038000 00000030: 00000000 001b7200 00000000 00000000 Board: LS1021AQDS vBank: 4 Sys ID:0x2b, Sys Ver: 0x11 FPGA: v13 (QIXIS_LS1021QDS_2014_08_27_1658), build 65386 I2C: ready DRAM: Initializing DDR....using SPD Detected UDIMM 18KSF51272AZ-1G6K1 2 GiB (DDR3, 32-bit, CL=11, ECC off) Using SERDES1 Protocol: 96 (0x60) Flash: 128 MiB NAND: 0 MiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: eTSEC1 is in sgmii mode eTSEC2 is in sgmii mode Phy not found PHY reset timed out Phy not found PHY reset timed out eTSEC1, eTSEC2, eTSEC3 [PRIME] => i2c md 0x66 0x5e 005e: 0c 00 12 81 f7 ff ff ff ff ef e7 00 3f ff ff ff ............?... => [b46683@rhuath ~]$

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[U-Boot] [PATCH v2 1/5] arm: ls102xa: Add snoop disable for slave port 0, 1 and 2
by Alison Wang 25 Nov '14

25 Nov '14

From: Jason Jin <Jason.Jin(a)freescale.com> Disable the snoop for slave interface 0, 1 and 2 to avoid the interleaving on the CCI400 BUS. Signed-off-by: Jason Jin <Jason.Jin(a)freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian(a)freescale.com> --- Change log: v2: Add tag "arm: ls102xa:" in the subject. arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 + board/freescale/ls1021aqds/ls1021aqds.c | 7 +++++++ board/freescale/ls1021atwr/ls1021atwr.c | 10 ++++++++++ 3 files changed, 18 insertions(+) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 7995fe2..a1f4fdb 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -448,6 +448,7 @@ struct ccsr_ddr { #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 #define CCI400_CTRLORD_EN_BARRIER 0 +#define CCI400_SHAORD_NON_SHAREABLE 0x00000002 /* CCI-400 registers */ struct ccsr_cci400 { diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 12e83f7..e32dbeb 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -220,6 +220,13 @@ int board_init(void) /* Set CCI-400 control override register to * enable barrier transaction */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + /* + * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register + * All transactions are treated as non-shareable + */ + out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index b522ff2..811c911 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -272,6 +272,16 @@ int board_early_init_f(void) int board_init(void) { + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + + /* + * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register + * All transactions are treated as non-shareable + */ + out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); config_serdes_mux(); -- 2.1.0.27.g96db324

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