October 2014 - U-Boot

[U-Boot] [PATCH] arndale: Increase command line buffer size (CONFIG_SYS_CBSIZE)
by Ian Campbell 07 Oct '14

07 Oct '14

From: Ian Campbell <ian.campbell(a)citrix.com> I was running into this limit with a not overly long PXE append line. Since the PXE code wants to print the resulting command line increase CONFIG_SYS_PBSIZE too. Signed-off-by: Ian Campbell <ian.campbell(a)citrix.com> --- include/configs/arndale.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/arndale.h b/include/configs/arndale.h index f702b6e..adc3eaa 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -116,8 +116,8 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_PROMPT "ARNDALE # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" /* Boot Argument Buffer Size */ -- 2.1.0

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[U-Boot] [PATCH] sunxi: Increase command line buffer size (CONFIG_SYS_CBSIZE)
by Ian Campbell 07 Oct '14

07 Oct '14

From: Ian Campbell <ian.campbell(a)citrix.com> I was running into this limit with a not overly long PXE append line. Since the PXE code wants to print the resulting command line increase CONFIG_SYS_PBSIZE too. Signed-off-by: Ian Campbell <ian.campbell(a)citrix.com> --- include/configs/sunxi-common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 1d947d7..d4419a2 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -92,8 +92,8 @@ * Miscellaneous configurable options */ #define CONFIG_CMD_ECHO -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_GENERIC_BOARD -- 2.1.0

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[U-Boot] [PATCH] arndale: Increase command line buffer size (CONFIG_SYS_CBSIZE)
by Ian Campbell 07 Oct '14

07 Oct '14

I was running into this limit with a not overly long PXE append line. Since the PXE code wants to print the resulting command line increase CONFIG_SYS_PBSIZE too. Signed-off-by: Ian Campbell <ian.campbell(a)citrix.com> --- include/configs/arndale.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/arndale.h b/include/configs/arndale.h index f702b6e..adc3eaa 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -116,8 +116,8 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_PROMPT "ARNDALE # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" /* Boot Argument Buffer Size */ -- 2.1.0

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[U-Boot] [PATCH] sunxi: Increase command line buffer size (CONFIG_SYS_CBSIZE)
by Ian Campbell 07 Oct '14

07 Oct '14

I was running into this limit with a not overly long PXE append line. Since the PXE code wants to print the resulting command line increase CONFIG_SYS_PBSIZE too. Signed-off-by: Ian Campbell <ian.campbell(a)citrix.com> --- include/configs/sunxi-common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 1d947d7..d4419a2 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -92,8 +92,8 @@ * Miscellaneous configurable options */ #define CONFIG_CMD_ECHO -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_GENERIC_BOARD -- 2.1.0

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[U-Boot] [PATCH RESEND] vf610twr: Tune DDR initialization settings
by Stefan Agner 07 Oct '14

07 Oct '14

From: Anthony Felice <tony.felice(a)timesys.com> Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: Anthony Felice <tony.felice(a)timesys.com> [rebased on v2014.10-rc2] Signed-off-by: Stefan Agner <stefan(a)agner.ch> --- As discuessed in the initial patch set this fixes a lot of wrong/ undocummented access and it would be nice to have in the next U-Boot release. Verified the patchset after rebase again using memtester on Vybrid Tower. arch/arm/include/asm/arch-vf610/imx-regs.h | 49 +++++++++++--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 44 +++++++------ arch/arm/include/asm/imx-common/iomux-v3.h | 2 + board/freescale/vf610twr/vf610twr.c | 94 +++++++++++++++++---------- 4 files changed, 127 insertions(+), 62 deletions(-) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index bb00217..9d797db 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -103,9 +103,11 @@ /* DDRMC */ #define DDRMC_PHY_DQ_TIMING 0x00002613 #define DDRMC_PHY_DQS_TIMING 0x00002615 -#define DDRMC_PHY_CTRL 0x01210080 +#define DDRMC_PHY_CTRL 0x00210000 #define DDRMC_PHY_MASTER_CTRL 0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00012020 +#define DDRMC_PHY_SLAVE_CTRL 0x00002000 +#define DDRMC_PHY_OFF 0x00000000 +#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 #define DDRMC_PHY50_DDR3_MODE (1 << 12) #define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8) @@ -138,7 +140,7 @@ #define DDRMC_CR21_CCMAP_EN 1 #define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) #define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24) -#define DDRMC_CR23_TDLL(v) ((v) & 0xff) +#define DDRMC_CR23_TDLL(v) ((v) & 0xffff) #define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f) #define DDRMC_CR25_TREF_EN (1 << 16) #define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16) @@ -151,7 +153,7 @@ #define DDRMC_CR33_EN_QK_SREF (1 << 16) #define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16) #define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8) -#define DDRMC_CR38_FREQ_CHG_EN (1 << 8) +#define DDRMC_CR38_FREQ_CHG_EN(v) (((v) & 0x1) << 8) #define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16) #define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8) #define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3) @@ -163,7 +165,7 @@ #define DDRMC_CR67_ZQCS(v) ((v) & 0xfff) #define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8) #define DDRMC_CR70_REF_PER_ZQ(v) (v) -#define DDRMC_CR72_ZQCS_ROTATE (1 << 24) +#define DDRMC_CR72_ZQCS_ROTATE(v) (((v) & 0x1) << 24) #define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24) #define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16) #define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8) @@ -182,9 +184,10 @@ #define DDRMC_CR77_CS_MAP (1 << 24) #define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8) #define DDRMC_CR77_SWAP_EN 1 +#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24) #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) -#define DDRMC_CR79_CTLUPD_AREF (1 << 24) -#define DDRMC_CR82_INT_MASK 0x1fffffff +#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24) +#define DDRMC_CR82_INT_MASK 0x10000000 #define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24) #define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16) #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) @@ -192,9 +195,17 @@ #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) +#define DDRMC_CR97_WRLVL_EN (1 << 24) +#define DDRMC_CR98_WRLVL_DL_0 (0) +#define DDRMC_CR99_WRLVL_DL_1 (0) +#define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) +#define DDRMC_CR102_RDLVL_REG_EN (1 << 8) #define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8) +#define DDRMC_CR106_RDLVL_GTDL_0(v) ((v) & 0xff) #define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff) +#define DDRMC_CR110_RDLVL_GTDL_1(v) (((v) & 0xff) << 16) #define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8) +#define DDRMC_CR115_RDLVL_GTDL_2(v) ((v) & 0xff) #define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8) #define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3) #define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24) @@ -208,20 +219,42 @@ #define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff) #define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8) #define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf) +#define DDRMC_CR123_AXI1_P_ODR_EN (1 << 16) #define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff) #define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8) #define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8) #define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f) +#define DDRMC_CR137_PHYCTL_DL(v) (((v) & 0xf) << 16) +#define DDRMC_CR138_PHY_WRLV_MXDL(v) (((v) & 0xffff) << 16) +#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x8) << 8) #define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24) #define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16) #define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8) #define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff) +#define DDRMC_CR140_PHY_WRLV_WW(v) ((v) & 0x3ff) +#define DDRMC_CR143_RDLV_GAT_MXDL(v) (((v) & 0xffff) << 16) +#define DDRMC_CR143_RDLV_MXDL(v) ((v) & 0xffff) +#define DDRMC_CR144_PHY_RDLVL_RES(v) (((v) & 0xff) << 24) +#define DDRMC_CR144_PHY_RDLV_LOAD(v) (((v) & 0xff) << 16) +#define DDRMC_CR144_PHY_RDLV_DLL(v) (((v) & 0xff) << 8) +#define DDRMC_CR144_PHY_RDLV_EN(v) ((v) & 0xff) +#define DDRMC_CR145_PHY_RDLV_RR(v) ((v) & 0x3ff) +#define DDRMC_CR146_PHY_RDLVL_RESP(v) (v) +#define DDRMC_CR147_RDLV_RESP_MASK(v) ((v) & 0xfffff) +#define DDRMC_CR148_RDLV_GATE_RESP_MASK(v) ((v) & 0xfffff) +#define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(v) (((v) & 0xf) << 8) +#define DDRMC_CR151_RDLVL_DQ_ZERO_CNT(v) ((v) & 0xf) #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27) #define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21) #define DDRMC_CR154_DDR_SEL_PAD_CONTR(v) (((v) & 0x3) << 18) +#define DDRMC_CR154_PAD_ZQ_HW_FOR(v) (((v) & 0x1) << 14) #define DDRMC_CR155_AXI0_AWCACHE (1 << 10) -#define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7) +#define DDRMC_CR155_PAD_ODT_BYTE1(v) (((v) & 0x7) << 3) +#define DDRMC_CR155_PAD_ODT_BYTE0(v) ((v) & 0x7) #define DDRMC_CR158_TWR(v) ((v) & 0x3f) +#define DDRMC_CR161_ODT_EN(v) (((v) & 0x1) << 16) +#define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8) +#define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf) #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 7464da8..9226e69 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -17,6 +17,8 @@ #define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ PAD_CTL_OBE_IBE_ENABLE) #define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm +#define VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_25ohm | \ + PAD_CTL_INPUT_DIFFERENTIAL) #define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE) #define VF610_NFC_IO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ @@ -102,6 +104,7 @@ enum { VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL), @@ -117,6 +120,7 @@ enum { VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, 0x025c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL), @@ -124,26 +128,26 @@ enum { VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index 70ee86c..a8ca49c 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -120,6 +120,8 @@ typedef u64 iomux_v3_cfg_t; #define PAD_MUX_MODE_SHIFT 20 +#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16) + #define PAD_CTL_SPEED_MED (1 << 12) #define PAD_CTL_SPEED_HIGH (3 << 12) diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 54a9f2c..21f49fd 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -45,6 +45,7 @@ void setup_iomux_ddr(void) VF610_PAD_DDR_A3__DDR_A_3, VF610_PAD_DDR_A2__DDR_A_2, VF610_PAD_DDR_A1__DDR_A_1, + VF610_PAD_DDR_A0__DDR_A_0, VF610_PAD_DDR_BA2__DDR_BA_2, VF610_PAD_DDR_BA1__DDR_BA_1, VF610_PAD_DDR_BA0__DDR_BA_0, @@ -76,6 +77,7 @@ void setup_iomux_ddr(void) VF610_PAD_DDR_WE__DDR_WE_B, VF610_PAD_DDR_ODT1__DDR_ODT_0, VF610_PAD_DDR_ODT0__DDR_ODT_1, + VF610_PAD_DDR_RESETB, }; imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); @@ -88,30 +90,30 @@ void ddr_phy_init(void) writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]); writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]); writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]); - writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]); writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]); writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]); - writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]); - writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]); - writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]); - writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]); - writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]); + + /* LPDDR2 only parameter */ + writel(DDRMC_PHY_OFF, &ddrmr->phy[49]); writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]); + + /* Processor Pad ODT settings */ + writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]); } void ddr_ctrl_init(void) @@ -120,12 +122,12 @@ void ddr_ctrl_init(void) writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]); - writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]); + writel(DDRMC_CR10_TRST_PWRON(80000), &ddrmr->cr[10]); - writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]); + writel(DDRMC_CR11_CKE_INACTIVE(200000), &ddrmr->cr[11]); writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]); - writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) | - DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]); + writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4), + &ddrmr->cr[13]); writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) | DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]); writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]); @@ -134,24 +136,23 @@ void ddr_ctrl_init(void) writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]); writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]); - writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT | - DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]); + writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]); - writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]); + writel(DDRMC_CR22_TDAL(12), &ddrmr->cr[22]); writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]); writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]); writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]); - writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]); - writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]); + writel(DDRMC_CR26_TREF(3120) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]); + writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]); writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]); writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]); - writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]); + writel(DDRMC_CR31_TXSNR(48) | DDRMC_CR31_TXSR(468), &ddrmr->cr[31]); writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]); writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]); - writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]); + writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]); writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) | DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]); @@ -164,37 +165,45 @@ void ddr_ctrl_init(void) writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]); writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]); - writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]); + writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]); writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) | DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]); writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN | - DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255), + DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64), &ddrmr->cr[74]); writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN | DDRMC_CR75_PLEN, &ddrmr->cr[75]); writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) | - DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]); + DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]); writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE | DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]); - writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]); - writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]); + writel(DDRMC_CR78_Q_FULLNESS(7) | DDRMC_CR78_BUR_ON_FLY_BIT(12), + &ddrmr->cr[78]); + writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]); writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]); - writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0, - &ddrmr->cr[87]); + writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]); writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]); writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]); writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]); writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]); + writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]); + writel(DDRMC_CR98_WRLVL_DL_0, &ddrmr->cr[98]); + writel(DDRMC_CR99_WRLVL_DL_1, &ddrmr->cr[99]); + + writel(DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, + &ddrmr->cr[102]); - writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]); - writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]); - writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]); + writel(DDRMC_CR105_RDLVL_DL_0(0), &ddrmr->cr[105]); + writel(DDRMC_CR106_RDLVL_GTDL_0(4), &ddrmr->cr[106]); + writel(DDRMC_CR110_RDLVL_GTDL_1(4), &ddrmr->cr[110]); + writel(DDRMC_CR114_RDLVL_GTDL_2(0), &ddrmr->cr[114]); + writel(DDRMC_CR115_RDLVL_GTDL_2(0), &ddrmr->cr[115]); - writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), + writel(DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]); writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]); @@ -205,23 +214,40 @@ void ddr_ctrl_init(void) &ddrmr->cr[121]); writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]); - writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1), - &ddrmr->cr[123]); + writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | + DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]); writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]); - writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]); + writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]); writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]); + writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]); + writel(DDRMC_CR138_PHY_WRLV_MXDL(256) | DDRMC_CR138_PHYDRAM_CK_EN(1), + &ddrmr->cr[138]); writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]); + writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]); + writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) | DDRMC_CR143_RDLV_MXDL(128), + &ddrmr->cr[143]); + writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) | + DDRMC_CR144_PHY_RDLV_DLL(3) | DDRMC_CR144_PHY_RDLV_EN(3), + &ddrmr->cr[144]); + writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]); + writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]); + writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]); + writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]); + writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) | + DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]); writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | - DDRMC_CR154_PAD_ZQ_MODE(1) | - DDRMC_CR154_DDR_SEL_PAD_CONTR(3), &ddrmr->cr[154]); - writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2), + DDRMC_CR154_PAD_ZQ_MODE(1) | DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | + DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]); + writel(DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]); writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]); + writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | + DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]); ddr_phy_init(); -- 2.1.0

3 6

[U-Boot] [PATCH 2/3][v4] mpc85xx: configs - Enable blob command in freescale platforms
by Ruchika Gupta 07 Oct '14

07 Oct '14

Enable blob commands for platforms having SEC 4.0 or greater for secure boot scenarios Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> --- Changes from v3 No changes include/configs/B4860QDS.h | 4 ++++ include/configs/BSC9132QDS.h | 4 ++++ include/configs/P1010RDB.h | 4 ++++ include/configs/P2041RDB.h | 4 ++++ include/configs/T1040QDS.h | 1 + include/configs/T104xRDB.h | 1 + include/configs/T208xQDS.h | 1 + include/configs/T208xRDB.h | 1 + include/configs/T4240QDS.h | 4 ++++ include/configs/T4240RDB.h | 1 + include/configs/corenet_ds.h | 4 ++++ 11 files changed, 29 insertions(+) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 2bf8ca0..c9fd2bb 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -917,4 +917,8 @@ unsigned long get_board_ddr_clk(void); #include <asm/fsl_secure_boot.h> +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 922ac00..32fc099 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -708,4 +708,8 @@ combinations. this should be removed later #include <asm/fsl_secure_boot.h> +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 1fa858e..7039da4 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -960,4 +960,8 @@ extern unsigned long get_sdram_size(void); #include <asm/fsl_secure_boot.h> +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 7ff2dd5..0b12cf5 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -747,4 +747,8 @@ unsigned long get_board_sys_clk(unsigned long dummy); #include <asm/fsl_secure_boot.h> +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 5870a49..bbe54bf 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -822,6 +822,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_SECURE_BOOT #include <asm/fsl_secure_boot.h> +#define CONFIG_CMD_BLOB #endif #endif /* __CONFIG_H */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index b21eb3a..0c90040 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -869,6 +869,7 @@ #ifdef CONFIG_SECURE_BOOT #include <asm/fsl_secure_boot.h> +#define CONFIG_CMD_BLOB #endif #endif /* __CONFIG_H */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 9a8a3b6..f40ad9a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -913,6 +913,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_SECURE_BOOT #include <asm/fsl_secure_boot.h> +#define CONFIG_CMD_BLOB #undef CONFIG_CMD_USB #endif diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 4ff31e6..8d4b02f 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -872,6 +872,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_SECURE_BOOT #include <asm/fsl_secure_boot.h> +#define CONFIG_CMD_BLOB #undef CONFIG_CMD_USB #endif diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index d2faf94..e3bbfeb 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -629,4 +629,8 @@ unsigned long get_board_ddr_clk(void); #include <asm/fsl_secure_boot.h> +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index b3fbbe3..82e5efd 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -755,6 +755,7 @@ unsigned long get_board_ddr_clk(void); * which is anyways not used in Secure Environment. */ #undef CONFIG_CMD_USB +#define CONFIG_CMD_BLOB #endif #endif /* __CONFIG_H */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 4fd290e..b0c8277 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -749,4 +749,8 @@ #include <asm/fsl_secure_boot.h> +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ -- 1.8.1.4

1 1

[U-Boot] [PATCH 1/3][v4] crypto/fsl: Add command for encapsulating/decapsulating blobs
by Ruchika Gupta 07 Oct '14

07 Oct '14

Freescale's SEC block has built-in Blob Protocol which provides a method for protecting user-defined data across system power cycles. SEC block protects data in a data structure called a Blob, which provides both confidentiality and integrity protection. Encapsulating data as a blob Each time that the Blob Protocol is used to protect data, a different randomly generated key is used to encrypt the data. This random key is itself encrypted using a key which is derived from SoC's non volatile secret key and a 16 bit Key identifier. The resulting encrypted key along with encrypted data is called a blob. The non volatile secure key is available for use only during secure boot. During decapsulation, the reverse process is performed to get back the original data. Commands added -------------- blob enc - encapsulating data as a cryptgraphic blob blob dec - decapsulating cryptgraphic blob to get the data Commands Syntax --------------- blob enc src dst len km Encapsulate and create blob of data $len bytes long at address $src and store the result at address $dst. $km is the 16 byte key modifier is also required for generation/use as key for cryptographic operation. Key modifier should be 16 byte long. blob dec src dst len km Decapsulate the blob of data at address $src and store result of $len byte at addr $dst. $km is the 16 byte key modifier is also required for generation/use as key for cryptographic operation. Key modifier should be 16 byte long. Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> --- Changes from v3 No changes common/Makefile | 2 + common/cmd_blob.c | 109 ++++++++++++++++++++++++++++++++++++ drivers/crypto/fsl/Makefile | 1 + drivers/crypto/fsl/fsl_blob.c | 61 ++++++++++++++++++++ drivers/crypto/fsl/jobdesc.c | 80 ++++++++++++++++++++++++++ drivers/crypto/fsl/jobdesc.h | 11 ++++ drivers/crypto/fsl/jr.c | 127 +++++++++++++++++++++++++++++++++++++++++- include/fsl_sec.h | 34 ++++++++++- 8 files changed, 423 insertions(+), 2 deletions(-) create mode 100644 common/cmd_blob.c create mode 100644 drivers/crypto/fsl/fsl_blob.c diff --git a/common/Makefile b/common/Makefile index b19d379..c84b3bc 100644 --- a/common/Makefile +++ b/common/Makefile @@ -265,4 +265,6 @@ obj-y += aboot.o obj-y += fb_mmc.o endif +obj-$(CONFIG_CMD_BLOB) += cmd_blob.o + CFLAGS_env_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null) diff --git a/common/cmd_blob.c b/common/cmd_blob.c new file mode 100644 index 0000000..82ecaf0 --- /dev/null +++ b/common/cmd_blob.c @@ -0,0 +1,109 @@ +/* + * + * Command for encapsulating/decapsulating blob of memory. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <environment.h> +#include <malloc.h> +#include <asm/byteorder.h> +#include <linux/compiler.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * blob_decap() - Decapsulate the data as a blob + * @key_mod: - Pointer to key modifier/key + * @src: - Address of data to be decapsulated + * @dst: - Address of data to be decapsulated + * @len: - Size of data to be decapsulated + * + * Returns zero on success,and negative on error. + */ +__weak int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) +{ + return 0; +} + +/** + * blob_encap() - Encapsulate the data as a blob + * @key_mod: - Pointer to key modifier/key + * @src: - Address of data to be encapsulated + * @dst: - Address of data to be encapsulated + * @len: - Size of data to be encapsulated + * + * Returns zero on success,and negative on error. + */ +__weak int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) +{ + return 0; +} + +/** + * do_blob() - Handle the "blob" command-line command + * @cmdtp: Command data struct pointer + * @flag: Command flag + * @argc: Command-line argument count + * @argv: Array of command-line arguments + * + * Returns zero on success, CMD_RET_USAGE in case of misuse and negative + * on error. + */ +static int do_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + uint32_t key_addr, src_addr, dst_addr, len; + uint8_t *km_ptr, *src_ptr, *dst_ptr; + int enc, ret = 0; + + if (argc != 6) + return CMD_RET_USAGE; + + if (!strncmp(argv[1], "enc", 3)) + enc = 1; + else if (!strncmp(argv[1], "dec", 3)) + enc = 0; + else + return CMD_RET_USAGE; + + src_addr = simple_strtoul(argv[2], NULL, 16); + dst_addr = simple_strtoul(argv[3], NULL, 16); + len = simple_strtoul(argv[4], NULL, 16); + key_addr = simple_strtoul(argv[5], NULL, 16); + + km_ptr = (uint8_t *)key_addr; + src_ptr = (uint8_t *)src_addr; + dst_ptr = (uint8_t *)dst_addr; + + if (enc) + ret = blob_encap(km_ptr, src_ptr, dst_ptr, len); + else + ret = blob_decap(km_ptr, src_ptr, dst_ptr, len); + + return ret; +} + +/***************************************************/ +static char blob_help_text[] = + "enc src dst len km - Encapsulate and create blob of data\n" + " $len bytes long at address $src and\n" + " store the result at address $dst.\n" + " $km is the 16 byte key modifier\n" + " is also required for generation/use as\n" + " key for cryptographic operation. Key\n" + " modifier should be 16 byte long.\n" + "blob dec src dst len km - Decapsulate the blob of data at address\n" + " $src and store result of $len byte at\n" + " addr $dst.\n" + " $km is the 16 byte key modifier\n" + " is also required for generation/use as\n" + " key for cryptographic operation. Key\n" + " modifier should be 16 byte long.\n"; + +U_BOOT_CMD( + blob, 6, 1, do_blob, + "Blob encapsulation/decryption", + blob_help_text +); diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index 59d9651..cb13d2e 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -7,3 +7,4 @@ # obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o +obj-$(CONFIG_CMD_BLOB) += fsl_blob.o diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c new file mode 100644 index 0000000..bc01075 --- /dev/null +++ b/drivers/crypto/fsl/fsl_blob.c @@ -0,0 +1,61 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <malloc.h> +#include "jobdesc.h" +#include "desc.h" +#include "jr.h" + +int blob_decrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len) +{ + int ret, i = 0; + u32 *desc; + + printf("\nDecapsulating data to form blob\n"); + desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE); + if (!desc) { + debug("Not enough memory for descriptor allocation\n"); + return -1; + } + + inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len); + + for (i = 0; i < 14; i++) + printf("%x\n", *(desc + i)); + ret = run_descriptor_jr(desc); + + if (ret) + printf("Error in Decapsulation %d\n", ret); + + free(desc); + return ret; +} + +int blob_encrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len) +{ + int ret, i = 0; + u32 *desc; + + printf("\nEncapsulating data to form blob\n"); + desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE); + if (!desc) { + debug("Not enough memory for descriptor allocation\n"); + return -1; + } + + inline_cnstr_jobdesc_blob_encap(desc, key_mod, src, dst, len); + for (i = 0; i < 14; i++) + printf("%x\n", *(desc + i)); + ret = run_descriptor_jr(desc); + + if (ret) + printf("Error in Encapsulation %d\n", ret); + + free(desc); + return ret; +} diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index cbe5c30..1386bae 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -12,6 +12,9 @@ #include "desc_constr.h" #include "jobdesc.h" +#define KEY_BLOB_SIZE 32 +#define MAC_SIZE 16 + void inline_cnstr_jobdesc_hash(uint32_t *desc, const uint8_t *msg, uint32_t msgsz, uint8_t *digest, u32 alg_type, uint32_t alg_size, int sg_tbl) @@ -43,3 +46,80 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc, append_store(desc, dma_addr_out, storelen, LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_CONTEXT); } + +void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr, + uint8_t *plain_txt, uint8_t *enc_blob, + uint32_t in_sz) +{ + dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; + uint32_t key_sz = KEY_IDNFR_SZ_BYTES; + /* output blob will have 32 bytes key blob in beginning and + * 16 byte HMAC identifier at end of data blob */ + uint32_t out_sz = in_sz + KEY_BLOB_SIZE + MAC_SIZE; + + dma_addr_key_idnfr = virt_to_phys((void *)key_idnfr); + dma_addr_in = virt_to_phys((void *)plain_txt); + dma_addr_out = virt_to_phys((void *)enc_blob); + + init_job_desc(desc, 0); + + append_key(desc, dma_addr_key_idnfr, key_sz, CLASS_2); + + append_seq_in_ptr(desc, dma_addr_in, in_sz, 0); + + append_seq_out_ptr(desc, dma_addr_out, out_sz, 0); + + append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB); +} + +void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, + uint8_t *enc_blob, uint8_t *plain_txt, + uint32_t out_sz) +{ + dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; + uint32_t key_sz = KEY_IDNFR_SZ_BYTES; + uint32_t in_sz = out_sz + KEY_BLOB_SIZE + MAC_SIZE; + + dma_addr_key_idnfr = virt_to_phys((void *)key_idnfr); + dma_addr_in = virt_to_phys((void *)enc_blob); + dma_addr_out = virt_to_phys((void *)plain_txt); + + init_job_desc(desc, 0); + + append_key(desc, dma_addr_key_idnfr, key_sz, CLASS_2); + + append_seq_in_ptr(desc, dma_addr_in, in_sz, 0); + + append_seq_out_ptr(desc, dma_addr_out, out_sz, 0); + + append_operation(desc, OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB); +} + +/* + * Descriptor to instantiate RNG State Handle 0 in normal mode and + * load the JDKEK, TDKEK and TDSK registers + */ +void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc) +{ + u32 *jump_cmd; + + init_job_desc(desc, 0); + + /* INIT RNG in non-test mode */ + append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | + OP_ALG_AS_INIT); + + /* wait for done */ + jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); + set_jump_tgt_here(desc, jump_cmd); + + /* + * load 1 to clear written reg: + * resets the done interrrupt and returns the RNG to idle. + */ + append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); + + /* generate secure keys (non-test) */ + append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | + OP_ALG_RNG4_SK); +} diff --git a/drivers/crypto/fsl/jobdesc.h b/drivers/crypto/fsl/jobdesc.h index ed61579..3cf7226 100644 --- a/drivers/crypto/fsl/jobdesc.h +++ b/drivers/crypto/fsl/jobdesc.h @@ -11,8 +11,19 @@ #include <common.h> #include <asm/io.h> +#define KEY_IDNFR_SZ_BYTES 16 + void inline_cnstr_jobdesc_hash(uint32_t *desc, const uint8_t *msg, uint32_t msgsz, uint8_t *digest, u32 alg_type, uint32_t alg_size, int sg_tbl); +void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr, + uint8_t *plain_txt, uint8_t *enc_blob, + uint32_t in_sz); + +void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, + uint8_t *enc_blob, uint8_t *plain_txt, + uint32_t out_sz); + +void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc); #endif diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index a107e6a..29681e1 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -10,6 +10,7 @@ #include <malloc.h> #include "fsl_sec.h" #include "jr.h" +#include "jobdesc.h" #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1)) #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size)) @@ -319,6 +320,120 @@ int sec_reset(void) return 0; } +static int instantiate_rng(void) +{ + struct result op; + u32 *desc; + u32 rdsta_val; + int ret = 0; + ccsr_sec_t __iomem *sec = + (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + struct rng4tst __iomem *rng = + (struct rng4tst __iomem *)&sec->rng; + + memset(&op, 0, sizeof(struct result)); + + desc = malloc(sizeof(int) * 6); + if (!desc) { + printf("cannot allocate RNG init descriptor memory\n"); + return -1; + } + + inline_cnstr_jobdesc_rng_instantiation(desc); + ret = run_descriptor_jr(desc); + + if (ret) + printf("RNG: Instantiation failed with error %x\n", ret); + + rdsta_val = sec_in32(&rng->rdsta); + if (op.status || !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED)) + return -1; + + return ret; +} + +static u8 get_rng_vid(void) +{ + ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + u32 cha_vid = sec_in32(&sec->chavid_ls); + + return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT; +} + +/* + * By default, the TRNG runs for 200 clocks per sample; + * 1200 clocks per sample generates better entropy. + */ +static void kick_trng(int ent_delay) +{ + ccsr_sec_t __iomem *sec = + (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + struct rng4tst __iomem *rng = + (struct rng4tst __iomem *)&sec->rng; + u32 val; + + /* put RNG4 into program mode */ + sec_setbits32(&rng->rtmctl, RTMCTL_PRGM); + /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the + * length (in system clocks) of each Entropy sample taken + * */ + val = sec_in32(&rng->rtsdctl); + val = (val & ~RTSDCTL_ENT_DLY_MASK) | + (ent_delay << RTSDCTL_ENT_DLY_SHIFT); + sec_out32(&rng->rtsdctl, val); + /* min. freq. count, equal to 1/4 of the entropy sample length */ + sec_out32(&rng->rtfreqmin, ent_delay >> 2); + /* max. freq. count, equal to 8 times the entropy sample length */ + sec_out32(&rng->rtfreqmax, ent_delay << 3); + /* put RNG4 into run mode */ + sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM); +} + +static int rng_init(void) +{ + int ret, ent_delay = RTSDCTL_ENT_DLY_MIN; + ccsr_sec_t __iomem *sec = + (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + struct rng4tst __iomem *rng = + (struct rng4tst __iomem *)&sec->rng; + + u32 rdsta = sec_in32(&rng->rdsta); + + /* Check if RNG state 0 handler is already instantiated */ + if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED) + return 0; + + do { + /* + * If either of the SH's were instantiated by somebody else + * then it is assumed that the entropy + * parameters are properly set and thus the function + * setting these (kick_trng(...)) is skipped. + * Also, if a handle was instantiated, do not change + * the TRNG parameters. + */ + kick_trng(ent_delay); + ent_delay += 400; + /* + * if instantiate_rng(...) fails, the loop will rerun + * and the kick_trng(...) function will modfiy the + * upper and lower limits of the entropy sampling + * interval, leading to a sucessful initialization of + * the RNG. + */ + ret = instantiate_rng(); + } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); + if (ret) { + printf("RNG: Failed to instantiate RNG\n"); + return ret; + } + + /* Enable RDB bit so that RNG works faster */ + sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE); + + return ret; +} + int sec_init(void) { int ret = 0; @@ -330,8 +445,18 @@ int sec_init(void) sec_out32(&sec->mcfgr, mcr | 1 << MCFGR_PS_SHIFT); #endif ret = jr_init(); - if (ret < 0) + if (ret < 0) { + printf("SEC initialization failed\n"); return -1; + } + + if (get_rng_vid() >= 4) { + if (rng_init() < 0) { + printf("RNG instantiation failed\n"); + return -1; + } + printf("SEC: RNG instantiated\n"); + } return ret; } diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 2a26d85..aa850a3 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -29,6 +29,36 @@ /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 +/* RNG4 TRNG test registers */ +struct rng4tst { +#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ + u32 rtmctl; /* misc. control register */ + u32 rtscmisc; /* statistical check misc. register */ + u32 rtpkrrng; /* poker range register */ +#define RTSDCTL_ENT_DLY_MIN 1200 +#define RTSDCTL_ENT_DLY_MAX 12800 + union { + u32 rtpkrmax; /* PRGM=1: poker max. limit register */ + u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ + }; +#define RTSDCTL_ENT_DLY_SHIFT 16 +#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) + u32 rtsdctl; /* seed control register */ + union { + u32 rtsblim; /* PRGM=1: sparse bit limit register */ + u32 rttotsam; /* PRGM=0: total samples register */ + }; + u32 rtfreqmin; /* frequency count min. limit register */ + union { + u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */ + u32 rtfreqcnt; /* PRGM=0: freq. count register */ + }; + u32 rsvd1[40]; +#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001 + u32 rdsta; /*RNG DRNG Status Register*/ + u32 rsvd2[15]; +}; + typedef struct ccsr_sec { u32 res0; u32 mcfgr; /* Master CFG Register */ @@ -53,7 +83,9 @@ typedef struct ccsr_sec { u8 res4[0x40]; u32 dar; /* DECO Avail Register */ u32 drr; /* DECO Reset Register */ - u8 res5[0xe78]; + u8 res5[0x4d8]; + struct rng4tst rng; /* RNG Registers */ + u8 res11[0x8a0]; u32 crnr_ms; /* CHA Revision Number Register, MS */ u32 crnr_ls; /* CHA Revision Number Register, LS */ u32 ctpr_ms; /* Compile Time Parameters Register, MS */ -- 1.8.1.4

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[U-Boot] Pull request: u-boot-uniphier/master
by Masahiro YAMADA 07 Oct '14

07 Oct '14

Hi Albert, The following changes since commit be9f643ae6aa9044c60fe80e3a2c10be8371c692: Merge branch 'for-tom' of git://git.denx.de/u-boot-dm (2014-09-26 20:10:48 -0400) are available in the git repository at: git://git.denx.de/u-boot-uniphier.git master for you to fetch changes up to 6dd0e7c00bfa5ce861a72b8e4a3ef9e787306125: git-mailrc: add me as a maintainer of UniPhier platform (2014-10-05 14:10:09 +0900) ---------------------------------------------------------------- Masahiro Yamada (7): mtd: denali: add Denali controller configs to Kconfig mtd: denali: add Denali NAND driver for SPL serial: add UniPhier serial driver ARM: UniPhier: add UniPhier SoC support code ARM: UniPhier: add Kconfig and defconfig MAINTAINERS: add me as a maintainer of UniPhier platform git-mailrc: add me as a maintainer of UniPhier platform MAINTAINERS | 9 + arch/arm/Kconfig | 5 + arch/arm/cpu/armv7/uniphier/Kconfig | 32 ++ arch/arm/cpu/armv7/uniphier/Makefile | 23 ++ arch/arm/cpu/armv7/uniphier/board_common.c | 32 ++ arch/arm/cpu/armv7/uniphier/board_late_init.c | 91 +++++ arch/arm/cpu/armv7/uniphier/cache_uniphier.c | 154 ++++++++ arch/arm/cpu/armv7/uniphier/cmd_pinmon.c | 33 ++ arch/arm/cpu/armv7/uniphier/cpu_info.c | 59 +++ arch/arm/cpu/armv7/uniphier/dram_init.c | 37 ++ arch/arm/cpu/armv7/uniphier/init_page_table.c | 1068 +++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/uniphier/lowlevel_init.S | 159 ++++++++ arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c | 33 ++ arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c | 16 + arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c | 42 +++ arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c | 29 ++ arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c | 63 ++++ arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c | 189 ++++++++++ arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c | 44 +++ arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c | 28 ++ arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c | 162 ++++++++ arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c | 16 + arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c | 39 ++ arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c | 66 ++++ arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c | 29 ++ arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c | 45 +++ arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c | 168 +++++++++ arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c | 18 + arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c | 75 ++++ arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c | 28 ++ arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c | 136 +++++++ arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c | 16 + arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c | 29 ++ arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c | 57 +++ arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c | 201 ++++++++++ arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c | 51 +++ arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c | 142 +++++++ arch/arm/cpu/armv7/uniphier/reset.c | 29 ++ arch/arm/cpu/armv7/uniphier/smp.S | 54 +++ arch/arm/cpu/armv7/uniphier/spl.c | 17 + arch/arm/cpu/armv7/uniphier/support_card.c | 180 +++++++++ arch/arm/cpu/armv7/uniphier/timer.c | 39 ++ arch/arm/include/asm/arch-uniphier/arm-mpcore.h | 46 +++ arch/arm/include/asm/arch-uniphier/bcu-regs.h | 30 ++ arch/arm/include/asm/arch-uniphier/board.h | 35 ++ arch/arm/include/asm/arch-uniphier/boot-device.h | 20 + arch/arm/include/asm/arch-uniphier/led.h | 101 +++++ arch/arm/include/asm/arch-uniphier/sbc-regs.h | 108 ++++++ arch/arm/include/asm/arch-uniphier/sc-regs.h | 62 ++++ arch/arm/include/asm/arch-uniphier/sg-regs.h | 182 +++++++++ arch/arm/include/asm/arch-uniphier/ssc-regs.h | 67 ++++ arch/arm/include/asm/arch-uniphier/umc-regs.h | 119 ++++++ configs/ph1_ld4_defconfig | 8 + configs/ph1_pro4_defconfig | 8 + configs/ph1_sld8_defconfig | 8 + doc/README.nand | 6 - doc/git-mailrc | 1 + drivers/mtd/Kconfig | 1 + drivers/mtd/nand/Kconfig | 42 +++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/denali_spl.c | 231 ++++++++++++ drivers/serial/Makefile | 1 + drivers/serial/serial.c | 2 + drivers/serial/serial_uniphier.c | 204 ++++++++++ include/configs/ph1_ld4.h | 59 +++ include/configs/ph1_pro4.h | 61 +++ include/configs/ph1_sld8.h | 61 +++ include/configs/uniphier-common.h | 266 +++++++++++++ 78 files changed, 5504 insertions(+), 6 deletions(-) create mode 100644 arch/arm/cpu/armv7/uniphier/Kconfig create mode 100644 arch/arm/cpu/armv7/uniphier/Makefile create mode 100644 arch/arm/cpu/armv7/uniphier/board_common.c create mode 100644 arch/arm/cpu/armv7/uniphier/board_late_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/cache_uniphier.c create mode 100644 arch/arm/cpu/armv7/uniphier/cmd_pinmon.c create mode 100644 arch/arm/cpu/armv7/uniphier/cpu_info.c create mode 100644 arch/arm/cpu/armv7/uniphier/dram_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/init_page_table.c create mode 100644 arch/arm/cpu/armv7/uniphier/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/reset.c create mode 100644 arch/arm/cpu/armv7/uniphier/smp.S create mode 100644 arch/arm/cpu/armv7/uniphier/spl.c create mode 100644 arch/arm/cpu/armv7/uniphier/support_card.c create mode 100644 arch/arm/cpu/armv7/uniphier/timer.c create mode 100644 arch/arm/include/asm/arch-uniphier/arm-mpcore.h create mode 100644 arch/arm/include/asm/arch-uniphier/bcu-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/board.h create mode 100644 arch/arm/include/asm/arch-uniphier/boot-device.h create mode 100644 arch/arm/include/asm/arch-uniphier/led.h create mode 100644 arch/arm/include/asm/arch-uniphier/sbc-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/sc-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/sg-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/ssc-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/umc-regs.h create mode 100644 configs/ph1_ld4_defconfig create mode 100644 configs/ph1_pro4_defconfig create mode 100644 configs/ph1_sld8_defconfig create mode 100644 drivers/mtd/nand/Kconfig create mode 100644 drivers/mtd/nand/denali_spl.c create mode 100644 drivers/serial/serial_uniphier.c create mode 100644 include/configs/ph1_ld4.h create mode 100644 include/configs/ph1_pro4.h create mode 100644 include/configs/ph1_sld8.h create mode 100644 include/configs/uniphier-common.h -- Best Regards Masahiro Yamada

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[U-Boot] [PATCH][v2] ls102x: configs - Add hash command in freescale LS1 platforms
by Ruchika Gupta 07 Oct '14

07 Oct '14

Hardware accelerated support for SHA-1 and SHA-256 has been added. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> --- Changes in v2 Warning fixed for ls1021atwr build arch/arm/include/asm/arch-ls102xa/config.h | 8 ++++++++ arch/arm/include/asm/arch-ls102xa/config.h.rej | 19 +++++++++++++++++++ board/freescale/ls1021aqds/ls1021aqds.c | 10 ++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 10 ++++++++++ include/configs/ls1021aqds.h | 6 ++++++ include/configs/ls1021atwr.h | 6 ++++++ 6 files changed, 59 insertions(+) create mode 100644 arch/arm/include/asm/arch-ls102xa/config.h.rej diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index a500b5b..588f37b 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -20,6 +20,8 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) +#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) @@ -66,6 +68,7 @@ #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE #define CONFIG_SYS_FSL_DCU_BE +#define CONFIG_SYS_FSL_SEC_LE #define DCU_LAYER_MAX_NUM 16 @@ -76,8 +79,13 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 #else #error SoC not defined #endif +#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 +#define CONFIG_FSL_CAAM +#endif + #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h.rej b/arch/arm/include/asm/arch-ls102xa/config.h.rej new file mode 100644 index 0000000..00e587e --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/config.h.rej @@ -0,0 +1,19 @@ +--- arch/arm/include/asm/arch-ls102xa/config.h ++++ arch/arm/include/asm/arch-ls102xa/config.h +@@ -73,8 +75,16 @@ + #define CONFIG_MAX_CPUS 2 + #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 + #define CONFIG_NUM_DDR_CONTROLLERS 1 ++#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 ++#define CONFIG_SYS_FSL_SEC_COMPAT 5 + #else + #error SoC not defined + #endif + ++#define CONFIG_SYS_FSL_SEC_LE ++ ++#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 ++#define CONFIG_FSL_CAAM ++#endif ++ + #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 12e83f7..d6278b9 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -13,6 +13,7 @@ #include <mmc.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> +#include <fsl_sec.h> #include "../common/qixis.h" #include "ls1021aqds_qixis.h" @@ -213,6 +214,15 @@ int config_serdes_mux(void) return 0; } +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ + if (sec_init() < 0) + return -1; + return 0; +} +#endif + int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index b522ff2..469b502 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -16,6 +16,7 @@ #include <netdev.h> #include <fsl_mdio.h> #include <tsec.h> +#include <fsl_sec.h> DECLARE_GLOBAL_DATA_PTR; @@ -280,6 +281,15 @@ int board_init(void) return 0; } +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ + if (sec_init() < 0) + return -1; + return 0; +} +#endif + void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index bb47813..e1ca78a 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -388,4 +388,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_OF_BOARD_SETUP #define CONFIG_CMD_BOOTZ +#define CONFIG_MISC_INIT_R + +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 45b2272..7199c92 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -288,4 +288,10 @@ #define CONFIG_OF_BOARD_SETUP #define CONFIG_CMD_BOOTZ +#define CONFIG_MISC_INIT_R + +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + #endif -- 1.8.1.4

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[U-Boot] [PATCH 1/3] edid: add function to convert edid to fb_videomode
by Christian Gmeiner 07 Oct '14

07 Oct '14

There may be some custom boards in the field which have an seperate eeprom chip to store edid informations in it. To make use of those edid information in the board code this patch add a function to convert edid to fb_videomode. Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- common/edid.c | 30 ++++++++++++++++++++++++++++++ include/edid.h | 9 +++++++++ 2 files changed, 39 insertions(+) diff --git a/common/edid.c b/common/edid.c index e66108f..ea9419c 100644 --- a/common/edid.c +++ b/common/edid.c @@ -12,6 +12,7 @@ #include <common.h> #include <edid.h> +#include <linux/fb.h> #include <linux/ctype.h> #include <linux/string.h> @@ -288,3 +289,32 @@ void edid_print_info(struct edid1_info *edid_info) if (!have_timing) printf("\tNone\n"); } + +void edid_to_fb_videomode(struct edid1_info *edid, struct fb_videomode *mode) +{ + struct edid_monitor_descriptor *monitor = + &edid->monitor_details.descriptor[0]; + struct edid_detailed_timing *timing = + (struct edid_detailed_timing *)monitor; + + uint32_t pixclock = EDID_DETAILED_TIMING_PIXEL_CLOCK(*timing); + uint32_t h_blanking = EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*timing); + uint32_t h_active = EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*timing); + uint32_t h_sync_offset = EDID_DETAILED_TIMING_HSYNC_OFFSET(*timing); + uint32_t h_sync_width = EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(*timing); + uint32_t v_blanking = EDID_DETAILED_TIMING_VERTICAL_BLANKING(*timing); + uint32_t v_active = EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*timing); + uint32_t v_sync_offset = EDID_DETAILED_TIMING_VSYNC_OFFSET(*timing); + uint32_t v_sync_width = EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(*timing); + + mode->name = "EDID"; + mode->pixclock = KHZ2PICOS(pixclock/1000); + mode->yres = v_active; + mode->xres = h_active; + mode->left_margin = h_blanking - h_sync_offset - h_sync_width; + mode->right_margin = h_sync_offset; + mode->upper_margin = v_blanking - v_sync_offset - v_sync_width; + mode->lower_margin = v_sync_offset; + mode->hsync_len = h_sync_width; + mode->vsync_len = v_sync_width; +} diff --git a/include/edid.h b/include/edid.h index 480a773..357d6d6 100644 --- a/include/edid.h +++ b/include/edid.h @@ -234,6 +234,15 @@ struct edid1_info { void edid_print_info(struct edid1_info *edid_info); /** + * Convert EDID info to struct fb_videomode + * + * @param edid The EDID info to be converted + * @param mode The destination fb_videomode to be filled + */ +struct fb_videomode; +void edid_to_fb_videomode(struct edid1_info *edid, struct fb_videomode *mode); + +/** * Check the EDID info. * * @param info The EDID info to be checked -- 1.9.3

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