October 2014 - U-Boot

[U-Boot] Upstream uboot and Arndale 5250 support
by Paolo Pisati 08 Oct '14

08 Oct '14

Hi, i've been trying to update the u-boot on my board (sd booting), from the Linaro one (2012.10) to a v2014.X, but so far had no luck: make arndale_config export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf- make ... dd if=arndale-bl1.bin of=/dev/sdc bs=512 skip=1 dd if=arndale-spl.bin of=/dev/sdc bs=512 skip=17 dd if=./u-boot-dtb.bin of=/dev/sdc bs=512 skip=49 ... u-boot 3.10rc3 (same happens with v2014.07 or 2014.04): U-Boot 2014.10-rc3 (Oct 07 2014 - 13:26:48) for ARNDALE CPU: Exynos5250@1000MHz Board: Arndale I2C: i2c_init: failed to init bus 0 for speed = 100000 ready DRAM: 2 GiB trace: copying 00086db4 bytes of early data from 50000000 to beff0000 trace: enabled WARNING: Caches not enabled MMC: EXYNOS DWMMC: 0, EXYNOS DWMMC: 1 dwmci_send_cmd: DATA ERROR! i2c_init: failed to init bus 0 for speed = 100000 In: serial Out: serial Err: serial Net: Net Initialization Skipped No ethernet found. Hit any key to stop autoboot: 0 ARNDALE # printenv baudrate=115200 bootargs=console=ttySAC2,115200n8 root=/dev/mmcblk1p1 rw rootwait debug earlyprintk bootcmd=run bootcmd_ubuntu bootcmd_ubuntu=run loadk; run loadf; run loadr; bootm ${kernel_addr_r} ${ramdisk_addr_r}:${filesize} ${fdt_addr_r} bootdelay=3 fdt_addr_r=0x41000000 filesize=5b9902 kernel_addr_r=0x40007000 loadf=ext2load mmc 1:1 ${fdt_addr_r} /boot/exynos5250-arndale.dtb loadk=ext2load mmc 1:1 ${kernel_addr_r} /boot/uImage loadr=ext2load mmc 1:1 ${ramdisk_addr_r} /boot/uInitrd ramdisk_addr_r=0x42000000 stderr=serial stdin=serial stdout=serial Environment size: 589/16380 bytes ARNDALE # run loadk 6002946 bytes read in 1117 ms (5.1 MiB/s) ARNDALE # bootm ${kernel_addr_r} ## Booting kernel from Legacy Image at 40007000 ... Image Name: kernel 3.16.0-20-generic Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 6002882 Bytes = 5.7 MiB Load Address: 40008000 Entry Point: 40008000 Verifying Checksum ... OK Loading Kernel Image ... OK Starting kernel ...(fake run for tracing) Starting kernel ... [stuck here] here for a more complete log: http://pastebin.ubuntu.com/8514108/plain/ Any idea what's going wrong? Did you try this board lately? It's a kernel with the DTB concatenated (and it works fine with Linaro 2012 uboot), but the same happens if i explicitely pass the dtb: U-Boot 2014.07 (Sep 30 2014 - 15:26:03) for ARNDALE CPU: Exynos5250@1000MHz Board: Arndale I2C: i2c_init: failed to init bus 0 for speed = 100000 ready DRAM: 2 GiB trace: copying 00085818 bytes of early data from 50000000 to beff0000 trace: enabled WARNING: Caches not enabled MMC: EXYNOS DWMMC: 0, EXYNOS DWMMC: 1 i2c_init: failed to init bus 0 for speed = 100000 In: serial Out: serial Err: serial Net: Net Initialization Skipped No ethernet found. Hit any key to stop autoboot: 0 ARNDALE # printenv baudrate=115200 bootargs=console=ttySAC2,115200n8 root=/dev/mmcblk1p1 rw rootwait debug earlyprintk bootcmd=run bootcmd_ubuntu bootcmd_ubuntu=run loadk; run loadf; run loadr; bootm ${kernel_addr_r} ${ramdisk_addr_r}:${filesize} ${fdt_addr_r} bootdelay=3 fdt_addr_r=0x41000000 filesize=5b9902 kernel_addr_r=0x40007000 loadf=ext2load mmc 1:1 ${fdt_addr_r} /boot/exynos5250-arndale.dtb loadk=ext2load mmc 1:1 ${kernel_addr_r} /boot/uImage loadr=ext2load mmc 1:1 ${ramdisk_addr_r} /boot/uInitrd ramdisk_addr_r=0x42000000 stderr=serial stdin=serial stdout=serial Environment size: 589/16380 bytes ARNDALE # run loadk 6002946 bytes read in 1114 ms (5.1 MiB/s) ARNDALE # run loadf 35450 bytes read in 34 ms (1017.6 KiB/s) ARNDALE # bootm ${kernel_addr_r} - ${fdt_addr_r} ## Booting kernel from Legacy Image at 40007000 ... Image Name: kernel 3.16.0-20-generic Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 6002882 Bytes = 5.7 MiB Load Address: 40008000 Entry Point: 40008000 Verifying Checksum ... OK ## Flattened Device Tree blob at 41000000 Booting using the fdt blob at 0x41000000 Loading Kernel Image ... OK Loading Device Tree to 4fff4000, end 4ffffa79 ... OK Starting kernel ...(fake run for tracing) Starting kernel ... [stuck again] (please cc: me as i'm off list) -- bye, p.

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[U-Boot] [PATCH] odroid: clock: set aclk_cores to 200MHz
by Przemyslaw Marczak 08 Oct '14

08 Oct '14

This change fixes suspend/resume issue in the kernel caused by the wrong 'aclk_cores' clock value expected by the kernel. Signed-off-by: Przemyslaw Marczak <p.marczak(a)samsung.com> Cc: Minkyu Kang <mk7.kang(a)samsung.com> --- board/samsung/odroid/odroid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index ac19527..5edb250 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -158,10 +158,10 @@ static void board_clock_init(void) * For MOUThpm = 1000 MHz (MOUTapll) * doutcopy = MOUThpm / (ratio + 1) = 200 (4) * sclkhpm = doutcopy / (ratio + 1) = 200 (4) - * cores_out = armclk / (ratio + 1) = 1000 (0) + * cores_out = armclk / (ratio + 1) = 200 (4) */ clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); - set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(0); + set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4); clrsetbits_le32(&clk->div_cpu1, clr, set); -- 1.9.1

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[U-Boot] [PATCH v2] exynos: update maintainer of Snow and SMDK5420 board
by Masahiro Yamada 08 Oct '14

08 Oct '14

The email address of Rajeshwari Shinde <rajeshwari.s(a)samsung.com> is not working. This commit gives Akshay the maintainership of Snow and SMDK5420 boards. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Akshay Saraswat <akshay.s(a)samsung.com> Cc: Minkyu Kang <mk7.kang(a)samsung.com> --- Changes in v2: - Pass the maintainership of Snow to Akshay based on his comment against v1. board/samsung/smdk5250/MAINTAINERS | 2 +- board/samsung/smdk5420/MAINTAINERS | 4 ---- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/board/samsung/smdk5250/MAINTAINERS b/board/samsung/smdk5250/MAINTAINERS index 8a2a4aa..070593e 100644 --- a/board/samsung/smdk5250/MAINTAINERS +++ b/board/samsung/smdk5250/MAINTAINERS @@ -6,7 +6,7 @@ F: include/configs/smdk5250.h F: configs/smdk5250_defconfig SNOW BOARD -M: Rajeshwari Shinde <rajeshwari.s(a)samsung.com> +M: Akshay Saraswat <akshay.s(a)samsung.com> S: Maintained F: include/configs/snow.h F: configs/snow_defconfig diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS index c8241a8..e0f5c7a 100644 --- a/board/samsung/smdk5420/MAINTAINERS +++ b/board/samsung/smdk5420/MAINTAINERS @@ -4,9 +4,5 @@ S: Maintained F: board/samsung/smdk5420/ F: include/configs/peach-pit.h F: configs/peach-pit_defconfig - -SMDK5420 BOARD -M: Rajeshwari Shinde <rajeshwari.s(a)samsung.com> -S: Maintained F: include/configs/smdk5420.h F: configs/smdk5420_defconfig -- 1.9.1

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[U-Boot] [PATCH] armv7: s5pc1xx: improve cache handling
by Robert Baldyga 08 Oct '14

08 Oct '14

Move cache handling code to C file, and add enable_caches() and disable_caches() functions. Signed-off-by: Robert Baldyga <r.baldyga(a)samsung.com> --- arch/arm/cpu/armv7/s5pc1xx/cache.S | 30 ------------------------ arch/arm/cpu/armv7/s5pc1xx/cache.c | 47 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 30 deletions(-) delete mode 100644 arch/arm/cpu/armv7/s5pc1xx/cache.S create mode 100644 arch/arm/cpu/armv7/s5pc1xx/cache.c diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S deleted file mode 100644 index 3089592..0000000 --- a/arch/arm/cpu/armv7/s5pc1xx/cache.S +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electronics - * Minkyu Kang <mk7.kang(a)samsung.com> - * - * based on arch/arm/cpu/armv7/omap3/cache.S - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -.align 5 - -#include <linux/linkage.h> - -#ifndef CONFIG_SYS_L2CACHE_OFF -ENTRY(v7_outer_cache_enable) - push {r0, r1, r2, lr} - mrc 15, 0, r3, cr1, cr0, 1 - orr r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - pop {r1, r2, r3, pc} -ENDPROC(v7_outer_cache_enable) - -ENTRY(v7_outer_cache_disable) - push {r0, r1, r2, lr} - mrc 15, 0, r3, cr1, cr0, 1 - bic r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - pop {r1, r2, r3, pc} -ENDPROC(v7_outer_cache_disable) -#endif diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.c b/arch/arm/cpu/armv7/s5pc1xx/cache.c new file mode 100644 index 0000000..51af299 --- /dev/null +++ b/arch/arm/cpu/armv7/s5pc1xx/cache.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Robert Baldyga <r.baldyga(a)samsung.com> + * + * based on arch/arm/cpu/armv7/omap3/cache.S + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + dcache_enable(); +} + +void disable_caches(void) +{ + dcache_disable(); +} +#endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +void v7_outer_cache_enable(void) +{ + __asm( + "push {r0, r1, r2, lr}\n\t" + "mrc 15, 0, r3, cr1, cr0, 1\n\t" + "orr r3, r3, #2\n\t" + "mcr 15, 0, r3, cr1, cr0, 1\n\t" + "pop {r1, r2, r3, pc}" + ); +} + +void v7_outer_cache_disable(void) +{ + __asm( + "push {r0, r1, r2, lr}\n\t" + "mrc 15, 0, r3, cr1, cr0, 1\n\t" + "bic r3, r3, #2\n\t" + "mcr 15, 0, r3, cr1, cr0, 1\n\t" + "pop {r1, r2, r3, pc}" + ); +} +#endif -- 1.9.1

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[U-Boot] [PATCH v6 0/15] samsung: Use common config files with Samsung boards
by Simon Glass 08 Oct '14

08 Oct '14

This series tries to unify the Samsung board configs into a few header files for exynos5 and exynos4. The purpose is to make it easier to move to driver model. In that case I would like things like the GPIO drivers and serial drivers to work in a standard way, and not need to support device tree and platform data at the same time. That would be quite painful. Another reason is that the Chrome OS EC drivers are currently included in boards that don't have a Chrome OS EC. This concern was raised by the Samsung maintainer (Minkyu) a while back. There are still a few boards that don't use CONFIG_OF_CONTROL so I have updated these rudimentary of device tree files based on feedback. This series has the side-effect of getting the EC interface working properly on Pit, so the keyboard works. It also provides access to the TPS65090 PMIC, which means that the backlight is enabled. Changes in v6: - Rebase on top of samsung/master and 'git pull upstream-arm master' Changes in v4: - Address review nits from Minkyu - Make this driver more like the one it came from - Rebase on top of master (CONFIG_OF settings moved to Kconfig) - Remove special FET_ERR_NOT_READY etc. as use standard errors Changes in v3: - Adjust device tree file based on Robert Baldyga's example Changes in v2: - Add new patch to enable keyboard on pit - Add new patch to split out cros_ec drivers - Add new patch to use 900MHz ARM frequeny in SPL for peach_pit - Avoid using a common file, and just add a device tree - Don't enable the cros_ec on smdk5420 - Fix 'cashe' typo in commit subject - Fix device tree base addresses - Leave CONFIG_SERIAL3 in the individual board files - Leave in a few configs which are not in fact common to all boards - Reduce the number of common elements to avoid needing #undefs later - Slightly reword the commit message Simon Glass (15): Exynos: Use 900MHz ARM frequency in SPL for peach_pit exynos5: Enable data cache cros_ec: power: Add a tunnelled version of the tps65090 driver cros_ec: exynos: Use the correct tps65090 driver in each case dm: exynos: Split out the cros_ec drivers exynos: dts: Add device tree node for cros_ec keyboard exynos: Rename -dt config files to -common exynos: Move common exynos settings into a common file exynos: Move common smdk5420 things to common file exynos: config: Move cros_ec and tps65090 out of smdk boards config: Move arndale to use common exynos5250 file config: Move smdkv310 to use common exynos4 file samsung: Enable device tree for s5p_goni samsung: Enable device tree for smdkc100 exynos: Enable pre-relocation malloc() arch/arm/Kconfig | 13 +- arch/arm/cpu/armv7/exynos/Kconfig | 1 + arch/arm/cpu/armv7/s5pc1xx/Kconfig | 25 +++ arch/arm/dts/Makefile | 3 + arch/arm/dts/exynos4210-smdkv310.dts | 21 ++ arch/arm/dts/exynos5420-peach-pit.dts | 57 +++++- arch/arm/dts/s5pc1xx-goni.dts | 28 +++ arch/arm/dts/s5pc1xx-smdkc100.dts | 29 +++ arch/arm/include/asm/arch-s5pc1xx/periph.h | 61 ++++++ arch/arm/include/asm/arch-s5pc1xx/pinmux.h | 50 +++++ configs/s5p_goni_defconfig | 2 + configs/smdkc100_defconfig | 2 + configs/smdkv310_defconfig | 1 + drivers/mmc/s5p_sdhci.c | 2 - drivers/power/pmic/Makefile | 3 +- drivers/power/pmic/pmic_tps65090_ec.c | 218 +++++++++++++++++++++ include/configs/arndale.h | 195 +----------------- include/configs/{exynos4-dt.h => exynos-common.h} | 110 +++-------- include/configs/exynos4-common.h | 68 +++++++ include/configs/{exynos5-dt.h => exynos5-common.h} | 126 ++---------- include/configs/exynos5-dt-common.h | 35 ++++ .../{exynos5250-dt.h => exynos5250-common.h} | 7 +- .../configs/{exynos5420.h => exynos5420-common.h} | 22 ++- include/configs/odroid.h | 4 +- include/configs/origen.h | 5 +- include/configs/peach-pit.h | 16 +- include/configs/s5p_goni.h | 9 +- include/configs/s5pc210_universal.h | 5 +- include/configs/smdk5250.h | 23 ++- include/configs/smdk5420.h | 5 +- include/configs/smdkc100.h | 6 + include/configs/smdkv310.h | 61 +----- include/configs/snow.h | 25 ++- include/configs/trats.h | 6 +- include/configs/trats2.h | 6 +- 35 files changed, 760 insertions(+), 490 deletions(-) create mode 100644 arch/arm/cpu/armv7/s5pc1xx/Kconfig create mode 100644 arch/arm/dts/exynos4210-smdkv310.dts create mode 100644 arch/arm/dts/s5pc1xx-goni.dts create mode 100644 arch/arm/dts/s5pc1xx-smdkc100.dts create mode 100644 arch/arm/include/asm/arch-s5pc1xx/periph.h create mode 100644 arch/arm/include/asm/arch-s5pc1xx/pinmux.h create mode 100644 drivers/power/pmic/pmic_tps65090_ec.c rename include/configs/{exynos4-dt.h => exynos-common.h} (51%) create mode 100644 include/configs/exynos4-common.h rename include/configs/{exynos5-dt.h => exynos5-common.h} (64%) create mode 100644 include/configs/exynos5-dt-common.h rename include/configs/{exynos5250-dt.h => exynos5250-common.h} (88%) rename include/configs/{exynos5420.h => exynos5420-common.h} (71%) -- 2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH 0/7] kconfig: Move CONFIG_SYS_HZ and CONFIG_USE_PRIVATE_LIBGCC, bug fixes
by Masahiro Yamada 08 Oct '14

08 Oct '14

Masahiro Yamada (7): kconfig: move CONFIG_SYS_HZ to lib/Kconfig x86: set CONFIG_USE_PRIVATE_LIBGCC to y kbuild: drop CONFIG_USE_PRIVATE_LIBGCC=<path/to/libgcc> syntax kconfig: move CONFIG_USE_PRIVATE_LIBGCC to Kconfig kbuild: fix a bug of the u-boot-spl link rule kconfig: invoke silentoldconfig if spl,tpl/.config is updated mips: enable CONFIG_USE_PRIVATE_LIBGCC by default Makefile | 4 ---- README | 7 ------- arch/Kconfig | 5 +++++ arch/arm/cpu/armv7/tegra-common/Kconfig | 3 +++ arch/mips/Kconfig | 3 +++ arch/x86/Kconfig | 3 +++ arch/x86/config.mk | 3 --- arch/x86/include/asm/config.h | 1 + arch/x86/lib/Makefile | 6 +++--- include/config_fallbacks.h | 4 ---- include/configs/cm_fx6.h | 1 - include/configs/edb93xx.h | 1 - include/configs/ks2_evm.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 1 - include/configs/ls2085a_common.h | 2 -- include/configs/sunxi-common.h | 2 -- include/configs/tegra-common.h | 4 ---- include/configs/tqma6.h | 1 - lib/Kconfig | 19 +++++++++++++++++++ lib/time.c | 4 ---- scripts/Makefile.spl | 8 ++++---- scripts/multiconfig.sh | 15 +++++++++++++++ 23 files changed, 56 insertions(+), 43 deletions(-) -- 1.9.1

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Re: [U-Boot] [PATCH 2/2] WIP2: Add support for pi
by Akshay Saraswat 08 Oct '14

08 Oct '14

Please, ignore this patch. Pushed by mistake. >Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> >--- > arch/arm/cpu/armv7/exynos/clock.c | 20 +++++++++++--------- > arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 2 +- > arch/arm/cpu/armv7/exynos/pinmux.c | 2 +- > arch/arm/include/asm/arch-exynos/cpu.h | 11 ++++++++++- > arch/arm/include/asm/arch-exynos/gpio.h | 4 ++-- > drivers/gpio/s5p_gpio.c | 2 +- > 6 files changed, 26 insertions(+), 15 deletions(-) > >diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c >index 7558eff..9c0d507 100644 >--- a/arch/arm/cpu/armv7/exynos/clock.c >+++ b/arch/arm/cpu/armv7/exynos/clock.c >@@ -118,7 +118,9 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) > div = PLL_DIV_1024; > else if (proid_is_exynos4412()) > div = PLL_DIV_65535; >- else if (proid_is_exynos5250() || proid_is_exynos5420()) >+ else if (proid_is_exynos5250() >+ || proid_is_exynos5420() >+ || proid_is_exynos5800()) > div = PLL_DIV_65536; > else > return 0; >@@ -1581,7 +1583,7 @@ static unsigned long exynos4_get_i2c_clk(void) > unsigned long get_pll_clk(int pllreg) > { > if (cpu_is_exynos5()) { >- if (proid_is_exynos5420()) >+ if (proid_is_exynos5420() || proid_is_exynos5800()) > return exynos5420_get_pll_clk(pllreg); > return exynos5_get_pll_clk(pllreg); > } else { >@@ -1617,7 +1619,7 @@ unsigned long get_i2c_clk(void) > unsigned long get_pwm_clk(void) > { > if (cpu_is_exynos5()) { >- if (proid_is_exynos5420()) >+ if (proid_is_exynos5420() || proid_is_exynos5800()) > return exynos5420_get_pwm_clk(); > return clock_get_periph_rate(PERIPH_ID_PWM0); > } else { >@@ -1630,7 +1632,7 @@ unsigned long get_pwm_clk(void) > unsigned long get_uart_clk(int dev_index) > { > if (cpu_is_exynos5()) { >- if (proid_is_exynos5420()) >+ if (proid_is_exynos5420() || proid_is_exynos5800()) > return exynos5420_get_uart_clk(dev_index); > return exynos5_get_uart_clk(dev_index); > } else { >@@ -1643,7 +1645,7 @@ unsigned long get_uart_clk(int dev_index) > unsigned long get_mmc_clk(int dev_index) > { > if (cpu_is_exynos5()) { >- if (proid_is_exynos5420()) >+ if (proid_is_exynos5420() || proid_is_exynos5800()) > return exynos5420_get_mmc_clk(dev_index); > return exynos5_get_mmc_clk(dev_index); > } else { >@@ -1654,7 +1656,7 @@ unsigned long get_mmc_clk(int dev_index) > void set_mmc_clk(int dev_index, unsigned int div) > { > if (cpu_is_exynos5()) { >- if (proid_is_exynos5420()) >+ if (proid_is_exynos5420() || proid_is_exynos5800()) > exynos5420_set_mmc_clk(dev_index, div); > else > exynos5_set_mmc_clk(dev_index, div); >@@ -1668,7 +1670,7 @@ unsigned long get_lcd_clk(void) > if (cpu_is_exynos4()) > return exynos4_get_lcd_clk(); > else { >- if (proid_is_exynos5420()) >+ if (proid_is_exynos5420() || proid_is_exynos5800()) > return exynos5420_get_lcd_clk(); > else > return exynos5_get_lcd_clk(); >@@ -1682,7 +1684,7 @@ void set_lcd_clk(void) > else { > if (proid_is_exynos5250()) > exynos5_set_lcd_clk(); >- else if (proid_is_exynos5420()) >+ else if (proid_is_exynos5420() || proid_is_exynos5800()) > exynos5420_set_lcd_clk(); > } > } >@@ -1696,7 +1698,7 @@ void set_mipi_clk(void) > int set_spi_clk(int periph_id, unsigned int rate) > { > if (cpu_is_exynos5()) { >- if (proid_is_exynos5420()) >+ if (proid_is_exynos5420() || proid_is_exynos5800()) > return exynos5420_set_spi_clk(periph_id, rate); > return exynos5_set_spi_clk(periph_id, rate); > } else { >diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c >index b6a9bc1..0aff3d0 100644 >--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c >+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c >@@ -971,7 +971,7 @@ static void exynos5420_system_clock_init(void) > > void system_clock_init(void) > { >- if (proid_is_exynos5420()) >+ if (proid_is_exynos5420() || proid_is_exynos5800()) > exynos5420_system_clock_init(); > else > exynos5250_system_clock_init(); >diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c >index b929486..17ae2e6 100644 >--- a/arch/arm/cpu/armv7/exynos/pinmux.c >+++ b/arch/arm/cpu/armv7/exynos/pinmux.c >@@ -834,7 +834,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags) > int exynos_pinmux_config(int peripheral, int flags) > { > if (cpu_is_exynos5()) { >- if (proid_is_exynos5420()) >+ if (proid_is_exynos5420() || proid_is_exynos5800()) > return exynos5420_pinmux_config(peripheral, flags); > else if (proid_is_exynos5250()) > return exynos5_pinmux_config(peripheral, flags); >diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h >index ba71714..9f3672b 100644 >--- a/arch/arm/include/asm/arch-exynos/cpu.h >+++ b/arch/arm/include/asm/arch-exynos/cpu.h >@@ -218,6 +218,13 @@ static inline void s5p_set_cpu_id(void) > /* Exynos5420 */ > s5p_cpu_id = 0x5420; > break; >+ case 0x422: >+ /* >+ * Exynos5800 is a variant of Exynos5422 >+ * and has the same product id >+ */ >+ s5p_cpu_id = 0x5800; >+ break; > } > } > >@@ -246,6 +253,7 @@ IS_EXYNOS_TYPE(exynos4210, 0x4210) > IS_EXYNOS_TYPE(exynos4412, 0x4412) > IS_EXYNOS_TYPE(exynos5250, 0x5250) > IS_EXYNOS_TYPE(exynos5420, 0x5420) >+IS_EXYNOS_TYPE(exynos5800, 0x5800) > > #define SAMSUNG_BASE(device, base) \ > static inline unsigned int __attribute__((no_instrument_function)) \ >@@ -256,7 +264,8 @@ static inline unsigned int __attribute__((no_instrument_function)) \ > return EXYNOS4X12_##base; \ > return EXYNOS4_##base; \ > } else if (cpu_is_exynos5()) { \ >- if (proid_is_exynos5420()) \ >+ if (proid_is_exynos5420() \ >+ || proid_is_exynos5800()) \ > return EXYNOS5420_##base; \ > return EXYNOS5_##base; \ > } \ >diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h >index 8fb5c23..32e045a 100644 >--- a/arch/arm/include/asm/arch-exynos/gpio.h >+++ b/arch/arm/include/asm/arch-exynos/gpio.h >@@ -1379,7 +1379,7 @@ static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = { > static inline struct gpio_info *get_gpio_data(void) > { > if (cpu_is_exynos5()) { >- if (proid_is_exynos5420()) >+ if (proid_is_exynos5420() || proid_is_exynos5800()) > return exynos5420_gpio_data; > else > return exynos5_gpio_data; >@@ -1396,7 +1396,7 @@ static inline struct gpio_info *get_gpio_data(void) > static inline unsigned int get_bank_num(void) > { > if (cpu_is_exynos5()) { >- if (proid_is_exynos5420()) >+ if (proid_is_exynos5420() || proid_is_exynos5800()) > return EXYNOS5420_GPIO_NUM_PARTS; > else > return EXYNOS5_GPIO_NUM_PARTS; >diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c >index db7b673..bcf44eb 100644 >--- a/drivers/gpio/s5p_gpio.c >+++ b/drivers/gpio/s5p_gpio.c >@@ -57,7 +57,7 @@ static inline int s5p_name_to_gpio(const char *name) > */ > #if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) > if (cpu_is_exynos5()) { >- if (proid_is_exynos5420()) { >+ if (proid_is_exynos5420() || proid_is_exynos5800()) { > tabp = exynos5420_gpio_table; > irregular_bank_name = 'y'; > irregular_set_number = '7'; >-- >1.9.1 > >_______________________________________________ >U-Boot mailing list >U-Boot(a)lists.denx.de >http://lists.denx.de/mailman/listinfo/u-boot Regards, Akshay Saraswat

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Re: [U-Boot] [PATCH 1/2] WIP: Add support for pi
by Akshay Saraswat 08 Oct '14

08 Oct '14

Please, ignore this patch. Pushed by mistake. > >Signed-off-by: Akshay Saraswat >--- >arch/arm/cpu/armv7/exynos/Kconfig | 5 +- >arch/arm/dts/Makefile | 3 +- >arch/arm/dts/exynos5800-peach-pi.dts | 157 +++++++++++++++++++++++++++++++++++ >board/samsung/smdk5420/Kconfig | 16 ++++ >board/samsung/smdk5420/MAINTAINERS | 2 + >configs/peach-pi_defconfig | 4 + >include/configs/exynos5420.h | 2 +- >include/configs/peach-pi.h | 35 ++++++++ >8 files changed, 221 insertions(+), 3 deletions(-) >create mode 100644 arch/arm/dts/exynos5800-peach-pi.dts >create mode 100644 configs/peach-pi_defconfig >create mode 100644 include/configs/peach-pi.h > >diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig >index b6a558b..76c0faf 100644 >--- a/arch/arm/cpu/armv7/exynos/Kconfig >+++ b/arch/arm/cpu/armv7/exynos/Kconfig >@@ -33,9 +33,12 @@ config TARGET_SNOW >config TARGET_SMDK5420 >bool "SMDK5420 board" > >-config TARGET_PEACH_PIT >+config TARGET_PEACH_PI >bool "Peach Pi board" > >+config TARGET_PEACH_PIT >+ bool "Peach Pit board" >+ >endchoice > >config SYS_CPU >diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile >index 1ccd827..36e68d7 100644 >--- a/arch/arm/dts/Makefile >+++ b/arch/arm/dts/Makefile >@@ -8,7 +8,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ >exynos5250-snow.dtb \ >exynos5250-smdk5250.dtb \ >exynos5420-smdk5420.dtb \ >- exynos5420-peach-pit.dtb >+ exynos5420-peach-pit.dtb \ >+ exynos5800-peach-pi.dtb >dtb-$(CONFIG_MX6) += imx6q-sabreauto.dtb >dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ >tegra20-medcom-wide.dtb \ >diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts >new file mode 100644 >index 0000000..1c6aa8f >--- /dev/null >+++ b/arch/arm/dts/exynos5800-peach-pi.dts >@@ -0,0 +1,157 @@ >+/* >+ * SAMSUNG/GOOGLE Peach-Pit board device tree source >+ * >+ * Copyright (c) 2013 Samsung Electronics Co., Ltd. >+ * http://www.samsung.com >+ * >+ * SPDX-License-Identifier: GPL-2.0+ >+ */ >+ >+/dts-v1/; >+/include/ "exynos54xx.dtsi" >+ >+/ { >+ model = "Samsung/Google Peach Pi board based on Exynos5800"; >+ >+ compatible = "google,pit-rev#", "google,pit", >+ "google,peach", "samsung,exynos5800", "samsung,exynos5"; >+ >+ config { >+ google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */ >+ hwid = "PIT TEST A-A 7848"; >+ lazy-init = <1>; >+ }; >+ >+ aliases { >+ serial0 = "/serial@12C30000"; >+ console = "/serial@12C30000"; >+ pmic = "/i2c@12ca0000"; >+ }; >+ >+ dmc { >+ mem-manuf = "samsung"; >+ mem-type = "ddr3"; >+ clock-frequency = <800000000>; >+ arm-frequency = <1700000000>; >+ }; >+ >+ tmu@10060000 { >+ samsung,min-temp = <25>; >+ samsung,max-temp = <125>; >+ samsung,start-warning = <95>; >+ samsung,start-tripping = <105>; >+ samsung,hw-tripping = <110>; >+ samsung,efuse-min-value = <40>; >+ samsung,efuse-value = <55>; >+ samsung,efuse-max-value = <100>; >+ samsung,slope = <274761730>; >+ samsung,dc-value = <25>; >+ }; >+ >+ /* MAX77802 is on i2c bus 4 */ >+ i2c@12ca0000 { >+ clock-frequency = <400000>; >+ power-regulator@9 { >+ compatible = "maxim,max77802-pmic"; >+ reg = <0x9>; >+ }; >+ }; >+ >+ i2c@12cd0000 { /* i2c7 */ >+ clock-frequency = <100000>; >+ soundcodec@20 { >+ reg = <0x20>; >+ compatible = "maxim,max98090-codec"; >+ }; >+ >+ edp-lvds-bridge@48 { >+ compatible = "parade,ps8625"; >+ reg = <0x48>; >+ }; >+ }; >+ >+ sound@3830000 { >+ samsung,codec-type = "max98090"; >+ }; >+ >+ i2c@12e10000 { /* i2c9 */ >+ clock-frequency = <400000>; >+ tpm@20 { >+ compatible = "infineon,slb9645-tpm"; >+ reg = <0x20>; >+ }; >+ }; >+ >+ spi@12d30000 { /* spi1 */ >+ spi-max-frequency = <50000000>; >+ firmware_storage_spi: flash@0 { >+ reg = <0>; >+ >+ /* >+ * A region for the kernel to store a panic event >+ * which the firmware will add to the log. >+ */ >+ elog-panic-event-offset = <0x01e00000 0x100000>; >+ >+ elog-shrink-size = <0x400>; >+ elog-full-threshold = <0xc00>; >+ }; >+ }; >+ >+ spi@12d40000 { /* spi2 */ >+ spi-max-frequency = <4000000>; >+ spi-deactivate-delay = <200>; >+ cros-ec@0 { >+ reg = <0>; >+ compatible = "google,cros-ec"; >+ spi-half-duplex; >+ spi-max-timeout-ms = <1100>; >+ spi-frame-header = <0xec>; >+ ec-interrupt = <&gpio 93 1>; /* GPX1_5 */ >+ >+ /* >+ * This describes the flash memory within the EC. Note >+ * that the STM32L flash erases to 0, not 0xff. >+ */ >+ #address-cells = <1>; >+ #size-cells = <1>; >+ flash@8000000 { >+ reg = <0x08000000 0x20000>; >+ erase-value = <0>; >+ }; >+ }; >+ }; >+ >+ xhci@12000000 { >+ samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */ >+ }; >+ >+ xhci@12400000 { >+ samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */ >+ }; >+ >+ fimd@14400000 { >+ samsung,vl-freq = <60>; >+ samsung,vl-col = <1920>; >+ samsung,vl-row = <1080>; >+ samsung,vl-width = <1920>; >+ samsung,vl-height = <1080>; >+ >+ samsung,vl-clkp; >+ samsung,vl-dp; >+ samsung,vl-bpix = <4>; >+ >+ samsung,vl-hspw = <80>; >+ samsung,vl-hbpd = <172>; >+ samsung,vl-hfpd = <60>; >+ samsung,vl-vspw = <10>; >+ samsung,vl-vbpd = <25>; >+ samsung,vl-vfpd = <10>; >+ samsung,vl-cmd-allow-len = <0xf>; >+ >+ samsung,winid = <3>; >+ samsung,interface-mode = <1>; >+ samsung,dp-enabled = <1>; >+ samsung,dual-lcd-enabled = <0>; >+ }; >+}; >diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig >index fb9bedd..b88722f 100644 >--- a/board/samsung/smdk5420/Kconfig >+++ b/board/samsung/smdk5420/Kconfig >@@ -1,3 +1,19 @@ >+if TARGET_PEACH_PI >+ >+config SYS_BOARD >+ string >+ default "smdk5420" >+ >+config SYS_VENDOR >+ string >+ default "samsung" >+ >+config SYS_CONFIG_NAME >+ string >+ default "peach-pi" >+ >+endif >+ >if TARGET_PEACH_PIT > >config SYS_BOARD >diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS >index c8241a8..25813d5 100644 >--- a/board/samsung/smdk5420/MAINTAINERS >+++ b/board/samsung/smdk5420/MAINTAINERS >@@ -2,7 +2,9 @@ SMDK5420 BOARD >M: Akshay Saraswat >S: Maintained >F: board/samsung/smdk5420/ >+F: include/configs/peach-pi.h >F: include/configs/peach-pit.h >+F: configs/peach-pi_defconfig >F: configs/peach-pit_defconfig > >SMDK5420 BOARD >diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig >new file mode 100644 >index 0000000..8cb3946 >--- /dev/null >+++ b/configs/peach-pi_defconfig >@@ -0,0 +1,4 @@ >+CONFIG_SPL=y >++S:CONFIG_ARM=y >++S:CONFIG_ARCH_EXYNOS=y >++S:CONFIG_TARGET_PEACH_PI=y >diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h >index d2a9556..9780050 100644 >--- a/include/configs/exynos5420.h >+++ b/include/configs/exynos5420.h >@@ -27,7 +27,7 @@ > >#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024) > >-#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420" >+#define CONFIG_DEVICE_TREE_LIST "exynos5800-peach-pi exynos5420-peach-pit exynos5420-smdk5420" > >#define CONFIG_MAX_I2C_NUM 11 > >diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h >new file mode 100644 >index 0000000..b66b781 >--- /dev/null >+++ b/include/configs/peach-pi.h >@@ -0,0 +1,35 @@ >+/* >+ * Copyright (C) 2014 Samsung Electronics >+ * >+ * Configuration settings for the SAMSUNG/GOOGLE PEACH-PI board. >+ * >+ * SPDX-License-Identifier: GPL-2.0+ >+ */ >+ >+#ifndef __CONFIG_PEACH_PI_H >+#define __CONFIG_PEACH_PI_H >+ >+#include >+ >+#include >+ >+#undef CONFIG_DEFAULT_DEVICE_TREE >+#define CONFIG_DEFAULT_DEVICE_TREE exynos5800-peach-pi >+ >+/* select serial console configuration */ >+#define CONFIG_SERIAL3 /* use SERIAL 3 */ >+ >+#define CONFIG_SYS_PROMPT "Peach-pi # " >+#define CONFIG_IDENT_STRING " for Peach-pi" >+ >+#define CONFIG_VIDEO_PARADE >+ >+/* Display */ >+#define CONFIG_LCD >+#ifdef CONFIG_LCD >+#define CONFIG_EXYNOS_FB >+#define CONFIG_EXYNOS_DP >+#define LCD_BPP LCD_COLOR16 >+#endif >+ >+#endif /* __CONFIG_PEACH_PI_H */ >-- >1.9.1 > >_______________________________________________ >U-Boot mailing list >U-Boot(a)lists.denx.de >http://lists.denx.de/mailman/listinfo/u-boot Regards, Akshay Saraswat

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[U-Boot] EXT4 slow boot problem
by Pendleton, Blair 08 Oct '14

08 Oct '14

We have discovered a significant performance problem in U-Boot accessing an EXT4 file system. If a large image file happens to be created with more than 4 extents, file read time increases from a few seconds to several minutes. The root cause is the indexed extent block is being re-read tens of thousands of times from the underlying device. In our case, the image file is ~44MB and the underlying device is a MMC SD card. Software updates are performed in Linux, and depending on a particular instance of EXT4 block allocations, the image file is created with 3, 4 or 5 extents. With 3 or 4 extents (tree depth 0), file reads are fast because the extent records are located in the cached i-node and the entire file is read with 3 or 4 large MMC block reads. With 5 extents (tree depth 1), extent records are in a separate block referenced by an extent index node. The current U-Boot implementation makes no attempt to cache this block and is forced to re-read it for every block of file data (EXT4 block size 1KB). This results in excess of 43000 MMC read operations and boot times so long that the system appears to be hung. Blair Pendleton Fluke Networks R&D Colorado Springs, CO, USA

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[U-Boot] [PATCH][v2] ls102x: configs - Add hash command in freescale LS1 platforms
by Ruchika Gupta 08 Oct '14

08 Oct '14

Hardware accelerated support for SHA-1 and SHA-256 has been added. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> --- Changes from v1: Rebased to HEAD of uboot Compilation warning fixed in ls1021atwr build arch/arm/include/asm/arch-ls102xa/config.h | 8 ++++++++ board/freescale/ls1021aqds/ls1021aqds.c | 10 ++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 10 ++++++++++ include/configs/ls1021aqds.h | 6 ++++++ include/configs/ls1021atwr.h | 6 ++++++ 5 files changed, 40 insertions(+) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index a500b5b..588f37b 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -20,6 +20,8 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) +#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) @@ -66,6 +68,7 @@ #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE #define CONFIG_SYS_FSL_DCU_BE +#define CONFIG_SYS_FSL_SEC_LE #define DCU_LAYER_MAX_NUM 16 @@ -76,8 +79,13 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 #else #error SoC not defined #endif +#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 +#define CONFIG_FSL_CAAM +#endif + #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 12e83f7..d6278b9 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -13,6 +13,7 @@ #include <mmc.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> +#include <fsl_sec.h> #include "../common/qixis.h" #include "ls1021aqds_qixis.h" @@ -213,6 +214,15 @@ int config_serdes_mux(void) return 0; } +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ + if (sec_init() < 0) + return -1; + return 0; +} +#endif + int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index b522ff2..469b502 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -16,6 +16,7 @@ #include <netdev.h> #include <fsl_mdio.h> #include <tsec.h> +#include <fsl_sec.h> DECLARE_GLOBAL_DATA_PTR; @@ -280,6 +281,15 @@ int board_init(void) return 0; } +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ + if (sec_init() < 0) + return -1; + return 0; +} +#endif + void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index bb47813..e1ca78a 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -388,4 +388,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_OF_BOARD_SETUP #define CONFIG_CMD_BOOTZ +#define CONFIG_MISC_INIT_R + +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 45b2272..7199c92 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -288,4 +288,10 @@ #define CONFIG_OF_BOARD_SETUP #define CONFIG_CMD_BOOTZ +#define CONFIG_MISC_INIT_R + +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + #endif -- 1.8.1.4

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