October 2014 - U-Boot

Re: [U-Boot] [PATCH 0/6] Addition of new board Peach-Pi
by Simon Glass 14 Oct '14

14 Oct '14

Hi Akshay, On 13 October 2014 23:05, Akshay Saraswat <akshay.s(a)samsung.com> wrote: > Hi Simon, > >> >>Hi Akshay, >> >>On 10 October 2014 05:50, Akshay Saraswat wrote: >>> >>> Hi Simon, >>> >>> > >>> >Hi Akshay, >>> > >>> >On 8 October 2014 02:10, Akshay Saraswat wrote: >>> >> Now we are adding a new Peach-Pi board which is a variant of Peach-Pit >>> >> and is based on Exynos5800. Exynos5800 itself is a variant of Exynos5420, >>> >> hence, most of the hardware config and settings are reused for this board. >>> >> >>> >> Akshay Saraswat (5): >>> >> Exynos5800: Introduce new proid for Exynos5800 >>> >> Exynos5800: Add DTS for new board Peach-Pi >>> >> Config: Exynos5800: Enable build for Peach-Pi >>> >> Config: Exynos5420: Refactor SDRAM Bank and Size >>> >> Exynos5: ddr3: Choose between single or double channel config >>> >> >>> >> Alim Akhtar (1): >>> >> DMC: Exynos5: Enable update mode for DREX controller >>> > >>> >I was not able to apply this to samsung/master. I fiddled a bit and >>> >>> Few patches got merged after I posted this patch-set. I will Rebase it. >>> >>> >got it to build (see u-boot-x86.git branch pi-working) but it would >>> >not boot over USB A-A. It hung in SPL. I may have used an incorrect >>> >>> I don't have the SMDK for Exynos5800 and my cros_write_firmware always fails to boot through USB. >>> I tested these patches with SD boot only. >>> >>> I could not find any difference between Pit and Pi. If Pit boots via USB then Pi should also boot. >>> Plus, for both USB boot and SD boot, path is same till the point where it starts loading U-Boot. >>> Please help me and let me know the steps for cros_write_firmware. I'll debug and post new patches. >>> >>> BL1 that I used has the following md5 sum - >>> 23b60e72992d839195d48335865dbabb >> >>Ah, mine is c33215481b579405fafb579e323b4a74 - I wonder if that is the >>problem? Where is this file available? >> > > Thanks for verifying. This could be any intermediate bl1. When we migrated from Pit to Pi we faced this issue. > So, we tested couple of binaries and one of them was able to do the USB recovery other was not. > > I have this u-boot.bl1.bin in my /build/peach_pi/firmware and it does flash firmware-pit-4482.B via USB. > Shall I send it to you ? or Will exynos-pre-boot download it ? Yes please send it. I don't seem to be getting the same version, but perhaps it is because it is only on that branch? Regards, Simon

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[U-Boot] [PATCH v8 0/12] Enable driver model for GPIOs on Tegra and Exynos
by Simon Glass 14 Oct '14

14 Oct '14

(Note: Tegra patches have been applied, I am resending with exynos only) Now that driver model is part of U-Boot, the task of converting drivers over to it begins. GPIO is one of the easiest to convert, since it already has a sandbox driver and a uclass driver. The Tegra GPIO driver is relatively simple since it has a linear numbering and already uses the generic GPIO framework. Each GPIO bank has a separate device. Some arguments have been made that a single device should support all the GPIO banks, but currently the driver model uclass does not work that way and it would require a second-level data structure to handle the bank feature. This driver has been tested on: - Seaboard (Tegra 20) - Beaver (Tegra 30) - Jetson-TK1 (Tegra 124). I don't have a Tegra 114 board (Dalmore seems to be the only one with U-Boot support) but I am quite confident that it works. For exynos, the pinctrl device tree files are brought in from the kernel and cut down to remove the groupings which we don't yet use. Very small additions are made to avoid replicating the awful tables that Linux has for every exynos SoC. This series sits on top of the exynos refactors. The 'gpio' command is updated to support display of only the allocated GPIOs. This is much more friendly than displaying a large table. A few related clean-ups are provided as well. This series is available at u-boot-dm.git, branch working. Changes in v8: - Adjust odroid device tree file to use #include instead of /include/ - Add missing special case reg property for exynos5420 GPX0 - Add patch containing pinctrl settings for s5p_goni - Add patch containing pinctrl settings for s5p_goni - Add new patch to move smdkc100 to generic board - Add new patch to move s5p_goni to generic board - Enable driver model for smdkc100 and s5p_goni separately Changes in v7: - Bring in patches from the SPI series to move post-reloc DM init earlier Changes in v6: - Fix typo in compatible string - Remove exynos5420.dtsi which is not used in U-Boot - Move U-Boot changes into their own file - Use exynos54xx everywhere instead of exynos5420 Changes in v5: - Put this patch before the others to avoid breaking bisectability - Add additional gpio_request() calls for other samsung boards - Use a mask instead of division in gpio_request() naming call - Remove RFC label now that build errors are fixed - Tidy up and update cover letter message - Avoid reordering functions Changes in v4: - Add patches for exynos GPIO support Simon Glass (12): dm: exynos: dts: Convert /include/ to #include dm: exynos: Bring in pinctrl dts files from Linux kernel dm: exynos: dts: Remove unused pinctrl information to save space dm: exynos: dts: Adjust device tree files for U-Boot dm: exynos: Add pinctrl settings for smdkc100 dm: exynos: Add pinctrl settings for s5p_goni dm: exynos: Move smdkc100 to generic board dm: exynos: Move s5p_goni to generic board dm: exynos: Tidy up GPIO headers dm: exynos: Tidy up GPIO defines dm: exynos: Make sure that GPIOs are requested dm: exynos: gpio: Convert to driver model arch/arm/cpu/armv7/exynos/pinmux.c | 5 +- arch/arm/dts/exynos4.dtsi | 9 +- arch/arm/dts/exynos4210-origen.dts | 4 +- arch/arm/dts/exynos4210-pinctrl-uboot.dtsi | 27 ++ arch/arm/dts/exynos4210-pinctrl.dtsi | 306 ++++++++++++++++++++ arch/arm/dts/exynos4210-smdkv310.dts | 2 +- arch/arm/dts/exynos4210-trats.dts | 2 +- arch/arm/dts/exynos4210-universal_c210.dts | 2 +- arch/arm/dts/exynos4210.dtsi | 155 ++++++++++ arch/arm/dts/exynos4412-odroid.dts | 2 +- arch/arm/dts/exynos4412-trats2.dts | 2 +- arch/arm/dts/exynos4412.dtsi | 38 +++ arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi | 46 +++ arch/arm/dts/exynos4x12-pinctrl.dtsi | 346 ++++++++++++++++++++++ arch/arm/dts/exynos4x12.dtsi | 114 ++++++++ arch/arm/dts/exynos5.dtsi | 56 +++- arch/arm/dts/exynos5250-pinctrl-uboot.dtsi | 40 +++ arch/arm/dts/exynos5250-pinctrl.dtsi | 333 ++++++++++++++++++++++ arch/arm/dts/exynos5250-smdk5250.dts | 2 +- arch/arm/dts/exynos5250-snow.dts | 2 +- arch/arm/dts/exynos5250.dtsi | 40 ++- arch/arm/dts/exynos5420-peach-pit.dts | 2 +- arch/arm/dts/exynos5420-smdk5420.dts | 2 +- arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi | 40 +++ arch/arm/dts/exynos54xx-pinctrl.dtsi | 305 ++++++++++++++++++++ arch/arm/dts/exynos54xx.dtsi | 44 ++- arch/arm/dts/s5pc100-pinctrl.dtsi | 180 ++++++++++++ arch/arm/dts/s5pc110-pinctrl.dtsi | 273 ++++++++++++++++++ arch/arm/dts/s5pc1xx-goni.dts | 7 + arch/arm/dts/s5pc1xx-smdkc100.dts | 7 + arch/arm/include/asm/arch-exynos/gpio.h | 5 - arch/arm/include/asm/arch-s5pc1xx/gpio.h | 4 - board/samsung/arndale/arndale.c | 4 +- board/samsung/common/board.c | 2 +- board/samsung/common/misc.c | 3 +- board/samsung/goni/goni.c | 4 +- board/samsung/origen/origen.c | 2 +- board/samsung/smdk5250/exynos5-dt.c | 7 + board/samsung/smdk5420/smdk5420.c | 6 +- board/samsung/smdkc100/smdkc100.c | 2 +- board/samsung/smdkv310/smdkv310.c | 2 +- board/samsung/trats/trats.c | 17 +- board/samsung/trats2/trats2.c | 27 +- board/samsung/universal_c210/universal.c | 4 +- drivers/gpio/s5p_gpio.c | 444 +++++++++++++++++++---------- drivers/mmc/s5p_sdhci.c | 7 +- include/configs/exynos-common.h | 4 + include/configs/s5p_goni.h | 5 + include/configs/smdkc100.h | 5 + 49 files changed, 2756 insertions(+), 191 deletions(-) create mode 100644 arch/arm/dts/exynos4210-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos4210-pinctrl.dtsi create mode 100644 arch/arm/dts/exynos4210.dtsi create mode 100644 arch/arm/dts/exynos4412.dtsi create mode 100644 arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos4x12-pinctrl.dtsi create mode 100644 arch/arm/dts/exynos4x12.dtsi create mode 100644 arch/arm/dts/exynos5250-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos5250-pinctrl.dtsi create mode 100644 arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi create mode 100644 arch/arm/dts/exynos54xx-pinctrl.dtsi create mode 100644 arch/arm/dts/s5pc100-pinctrl.dtsi create mode 100644 arch/arm/dts/s5pc110-pinctrl.dtsi -- 2.1.0.rc2.206.gedb03e5

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Re: [U-Boot] [PATCH 0/6] Addition of new board Peach-Pi
by Simon Glass 14 Oct '14

14 Oct '14

Hi Akshay, On 10 October 2014 05:50, Akshay Saraswat <akshay.s(a)samsung.com> wrote: > > Hi Simon, > > > > >Hi Akshay, > > > >On 8 October 2014 02:10, Akshay Saraswat wrote: > >> Now we are adding a new Peach-Pi board which is a variant of Peach-Pit > >> and is based on Exynos5800. Exynos5800 itself is a variant of Exynos5420, > >> hence, most of the hardware config and settings are reused for this board. > >> > >> Akshay Saraswat (5): > >> Exynos5800: Introduce new proid for Exynos5800 > >> Exynos5800: Add DTS for new board Peach-Pi > >> Config: Exynos5800: Enable build for Peach-Pi > >> Config: Exynos5420: Refactor SDRAM Bank and Size > >> Exynos5: ddr3: Choose between single or double channel config > >> > >> Alim Akhtar (1): > >> DMC: Exynos5: Enable update mode for DREX controller > > > >I was not able to apply this to samsung/master. I fiddled a bit and > > Few patches got merged after I posted this patch-set. I will Rebase it. > > >got it to build (see u-boot-x86.git branch pi-working) but it would > >not boot over USB A-A. It hung in SPL. I may have used an incorrect > > I don't have the SMDK for Exynos5800 and my cros_write_firmware always fails to boot through USB. > I tested these patches with SD boot only. > > I could not find any difference between Pit and Pi. If Pit boots via USB then Pi should also boot. > Plus, for both USB boot and SD boot, path is same till the point where it starts loading U-Boot. > Please help me and let me know the steps for cros_write_firmware. I'll debug and post new patches. > > BL1 that I used has the following md5 sum - > 23b60e72992d839195d48335865dbabb Ah, mine is c33215481b579405fafb579e323b4a74 - I wonder if that is the problem? Where is this file available? Regards, Simon

1 0

[U-Boot] [PATCH 1/2] imx: mx6sl: Add IOMUX setting for USDHC1-3
by Ye.Li 13 Oct '14

13 Oct '14

Set the USDHC1-3 IOMUX settings which are used for mx6slevk board. Signed-off-by: Ye.Li <B37916(a)freescale.com> --- arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h index 045ccc4..d9db58c 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -14,12 +14,31 @@ enum { MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0), MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0), MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0), + MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0), MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0), MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__GPIO_3_22 = IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, 0), MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0), MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0), -- 1.7.4.1

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[U-Boot] [PATCH 1/2] mmc: fsl_esdhc: Update esdhc driver for iMX6SX
by Ye.Li 13 Oct '14

13 Oct '14

The reset value of "uSDHCx_INT_STATUS_EN" register is changed to 0 on iMX6SX. So the fsl_esdhc driver must update to set the register, otherwise no state can be detected. Signed-off-by: Ye.Li <B37916(a)freescale.com> --- drivers/mmc/fsl_esdhc.c | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 97d0389..9c8a8d4 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -23,6 +23,11 @@ DECLARE_GLOBAL_DATA_PTR; +#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ + IRQSTATEN_CINT | \ + IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ + IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | IRQSTATEN_DEBE) + struct fsl_esdhc { uint dsaddr; /* SDMA system address register */ uint blkattr; /* Block attributes register */ @@ -492,8 +497,15 @@ static int esdhc_init(struct mmc *mmc) /* Set the initial clock speed */ mmc_set_clock(mmc, 400000); +#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO + /* Enable the BRR and BWR bits in IRQSTAT */ + esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_DINT); + esdhc_setbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); +#else /* Disable the BRR and BWR bits in IRQSTAT */ esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); + esdhc_setbits32(&regs->irqstaten, IRQSTATEN_DINT); +#endif /* Put the PROCTL reg back to the default */ esdhc_write32(&regs->proctl, PROCTL_INIT); @@ -558,6 +570,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); + writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten); memset(&cfg->cfg, 0, sizeof(cfg->cfg)); voltage_caps = 0; -- 1.7.4.1

2 1

[U-Boot] [PATCH fix for v2014.10] sunxi: axp152: dcdc3 scale is 50mV / step
by Hans de Goede 13 Oct '14

13 Oct '14

Hi Tom, Here is a last minute fix for v2014.10 to fix the axp152 code setting the DRAM voltage way too high on some sunxi boards (2.3V instead of 1.5V). I hope this can still make v2014.10, if not it is not too bad as most boards use the axp209, not the axp152, and the axp152 boards I've seem to work fine even with the 2.3V DRAM setting. Regards, Hans

2 2

[U-Boot] [PATCH] imx: mx6 sabreauto: Add board support for USB EHCI
by Ye.Li 13 Oct '14

13 Oct '14

On mx6 sabreauto board, there are two USB ports: 0: OTG 1: HOST The EHCI driver is enabled for this board, but the IOMUX and VBUS power control is not implemented, which cause both USB port failed to work. This patch fix the problem by adding the BSP support. Since the power control uses the GPIO pin from port expander MAX7310, the PCA953X driver is enabled for accessing the MAX7310. The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting its daisy chain. Add a new function "imx_iomux_set_gpr_register" to handle GPR register setting. Signed-off-by: Ye.Li <B37916(a)freescale.com> --- arch/arm/imx-common/iomux-v3.c | 17 +++++- arch/arm/include/asm/imx-common/iomux-v3.h | 7 ++- board/freescale/mx6qsabreauto/mx6qsabreauto.c | 89 ++++++++++++++++++++++++- include/configs/mx6qsabreauto.h | 5 +- 4 files changed, 114 insertions(+), 4 deletions(-) diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 22cd11a..2d96655 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -4,7 +4,7 @@ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, * <armlinux(a)phytec.de> * - * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -77,3 +77,18 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, p += stride; } } + +void imx_iomux_set_gpr_register(int group, int start_bit, + int num_bits, int value) +{ + int i = 0; + u32 reg; + reg = readl(base + group * 4); + while (num_bits) { + reg &= ~(1<<(start_bit + i)); + i++; + num_bits--; + } + reg |= (value << start_bit); + writel(reg, base + group * 4); +} diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index 70ee86c..bc090fd 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -3,7 +3,7 @@ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, * <armlinux(a)phytec.de> * - * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -180,6 +180,11 @@ typedef u64 iomux_v3_cfg_t; void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, unsigned count); +/* +* Set bits for general purpose registers +*/ +void imx_iomux_set_gpr_register(int group, int start_bit, + int num_bits, int value); /* macros for declaring and using pinmux array */ #if defined(CONFIG_MX6QDL) diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index dd6d2a6..e48b08a 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012-2014 Freescale Semiconductor, Inc. * * Author: Fabio Estevam <fabio.estevam(a)freescale.com> * @@ -23,6 +23,7 @@ #include <netdev.h> #include <asm/arch/sys_proto.h> #include <i2c.h> +#include <pca953x.h> DECLARE_GLOBAL_DATA_PTR; @@ -112,6 +113,41 @@ static iomux_v3_cfg_t const port_exp[] = { MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +/*Define for building port exp gpio, pin starts from 0*/ +#define PORTEXP_IO_NR(chip, pin) \ + ((chip << 5) + pin) + +/*Get the chip addr from a ioexp gpio*/ +#define PORTEXP_IO_TO_CHIP(gpio_nr) \ + (gpio_nr >> 5) + +/*Get the pin number from a ioexp gpio*/ +#define PORTEXP_IO_TO_PIN(gpio_nr) \ + (gpio_nr & 0x1f) + +static int port_exp_direction_output(unsigned gpio, int value) +{ + int ret; + + i2c_set_bus_num(2); + if (i2c_probe(PORTEXP_IO_TO_CHIP(gpio))) + return -ENXIO; + + ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio), + (1 << PORTEXP_IO_TO_PIN(gpio)), + (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio))); + + if (!ret) + ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio), + (1 << PORTEXP_IO_TO_PIN(gpio)), + (value << PORTEXP_IO_TO_PIN(gpio))); + + if (ret) + ret = -EIO; + + return ret; +} + static void setup_iomux_enet(void) { imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); @@ -295,3 +331,54 @@ int checkboard(void) return 0; } + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7) +#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1) + +iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); + + /*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/ + imx_iomux_set_gpr_register(1, 13, 1, 0); + break; + case 1: + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + return 0; +} + +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + if (on) + port_exp_direction_output(USB_OTG_PWR, 1); + else + port_exp_direction_output(USB_OTG_PWR, 0); + break; + case 1: + if (on) + port_exp_direction_output(USB_HOST1_PWR, 1); + else + port_exp_direction_output(USB_HOST1_PWR, 0); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + + return 0; +} +#endif diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 0ab3127..4c76db0 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012-2014 Freescale Semiconductor, Inc. * * Configuration settings for the Freescale i.MX6Q SabreAuto board. * @@ -32,6 +32,9 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } + #include "mx6sabre_common.h" #define CONFIG_SYS_FSL_USDHC_NUM 2 -- 1.7.4.1

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[U-Boot] [PATCH 2/2] imx: mx6sxsabresd: Add board support for USDHC2 and USDHC3
by Ye.Li 13 Oct '14

13 Oct '14

Add full support for USDHC2, USDHC3, USDHC4 on mx6sx sabresd board. The default boot socket is USDHC4, so the MMC environment is set to this device. Signed-off-by: Ye.Li <B37916(a)freescale.com> --- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 96 +++++++++++++++++++++++++-- include/configs/mx6sxsabresd.h | 6 ++- 2 files changed, 96 insertions(+), 6 deletions(-) diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 68d3718..6ba646a 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -68,6 +68,34 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD pin */ + MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* RST_B, used for power reset cycle */ + MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -255,23 +283,81 @@ int board_early_init_f(void) return 0; } -static struct fsl_esdhc_cfg usdhc_cfg[1] = { +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, {USDHC4_BASE_ADDR}, }; +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) +#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11) +#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21) + int board_mmc_getcd(struct mmc *mmc) { - return 1; /* Assume boot SD always present */ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = 1; /* Assume uSDHC2 is always present */ + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = !gpio_get_value(USDHC4_CD_GPIO); + break; + } + + return ret; } int board_mmc_init(bd_t *bis) { - imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + int i; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC2 + * mmc1 USDHC3 + * mmc2 USDHC4 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + gpio_direction_output(USDHC3_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + gpio_direction_input(USDHC4_CD_GPIO); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; } + int board_init(void) { /* Address of boot parameters */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index e02ea18..5bbc8da 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -214,7 +214,6 @@ #define CONFIG_ENV_OFFSET (6 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ @@ -223,4 +222,9 @@ #define CONFIG_CMD_CACHE #endif +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/ +#endif + #endif /* __CONFIG_H */ -- 1.7.4.1

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[U-Boot] [PATCH resend] kconfig: Fix compiler warning in menu.c
by Hans de Goede 13 Oct '14

13 Oct '14

Hi, This one seems to have fallen through the cracks. Regards, Hans

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[U-Boot] [RFC PATCH] genboardscfg.py: use Python2 from default path
by Wolfgang Denk 12 Oct '14

12 Oct '14

Instead of searching for Python2 in $PATH, use the one installed by the system (i. e. /usr/bin/python2). This prevents failures like this: -> ./MAKEALL m53evk Traceback (most recent call last): File "tools/genboardscfg.py", line 19, in <module> import fnmatch ImportError: No module named fnmatch Failed to generate boards.cfg This happens for example with all but the most recent versions of Yocto based tool chains (inclusing all currently existing versions of the ELDK), which provide a python2 binary in SYSROOT/usr/bin/python2, but do not include the "fnmatch" module. By using the system installed Python interpreter, the user is able to install any missing modules himself, without need to patch and rebuild the whole tool chain. Signed-off-by: Wolfgang Denk <wd(a)denx.de> Cc: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- tools/genboardscfg.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/genboardscfg.py b/tools/genboardscfg.py index 23c956b..fa0f49f 100755 --- a/tools/genboardscfg.py +++ b/tools/genboardscfg.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/python2 # # Author: Masahiro Yamada <yamada.m(a)jp.panasonic.com> # -- 1.8.3.1

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