October 2014 - U-Boot

[U-Boot] [PATCH] powerpc/t104xrdb: make T104x board compliant in u-boot
by Vijay Rai 14 Oct '14

14 Oct '14

When booted with upstream code, it shows error in u-boot that board is not compliant. This patch will make board compliant with upstream code changes in u-boot. Signed-off-by: Vijay Rai <vijay.rai(a)freescale.com> --- include/configs/T1040QDS.h | 2 ++ include/configs/T104xRDB.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index ebee89a..602cc94 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -28,6 +28,8 @@ */ #define CONFIG_T1040QDS #define CONFIG_PHYS_64BIT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index c4bf0d6..341dad9 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -12,6 +12,8 @@ */ #define CONFIG_T104xRDB #define CONFIG_PHYS_64BIT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg -- 1.7.9.5

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[U-Boot] [PATCH v3] powerpc/85xx: enable some P1/P2 boards mtdparts for nor flash
by Yangbo Lu 14 Oct '14

14 Oct '14

Enable these boards mtdparts for nor flash: p1020rdb-pd, p1021rdb-pc, p1022ds, p1025twr, and p2020rdb-pc. Signed-off-by: Xie Xiaobo <X.Xie(a)freescale.com> Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> Cc: York Sun <yorksun(a)freescale.com> Cc: Scott Wood <scottwood(a)freescale.com> --- Changes for v2: - changed commit message - fixed max line length problem in code Changes for v3: - added a Cc to York Sun --- include/configs/P1022DS.h | 12 ++++++++++++ include/configs/p1_p2_rdb_pc.h | 31 +++++++++++++++++++++++++++++++ include/configs/p1_twr.h | 12 ++++++++++++ 3 files changed, 55 insertions(+) diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 139d4fe..4480270 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -620,6 +620,18 @@ #endif /* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=e8000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ + "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ + "512k(dtb),768k(u-boot)" + +/* * Environment */ #ifdef CONFIG_SPIFLASH diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 07b6179..1ed8838 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -77,6 +77,16 @@ #define __SW_BOOT_NAND 0x44 #define __SW_BOOT_PCIE 0x74 #define CONFIG_SYS_L2_SIZE (256 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=ec000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ + "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" #endif #if defined(CONFIG_P1021RDB) @@ -95,6 +105,17 @@ #define __SW_BOOT_NAND 0xec #define __SW_BOOT_PCIE 0x6c #define CONFIG_SYS_L2_SIZE (256 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=ef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9728k(fs)," \ + "256k(qe-ucode-firmware),1280k(u-boot)" #endif #if defined(CONFIG_P1024RDB) @@ -142,6 +163,16 @@ #define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_PCIE 0xa8 #define CONFIG_SYS_L2_SIZE (512 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=ef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" #endif #ifdef CONFIG_SDCARD diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index c296a07..d3093f5 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -389,6 +389,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_TWR-P1025 */ /* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=ec000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),5632k(kernel),57856k(fs)," \ + "256k(qe-ucode-firmware),1280k(u-boot)" + +/* * Environment */ #ifdef CONFIG_SYS_RAMBOOT -- 1.8.5

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[U-Boot] [PATCH] km_kirkwood: remove KM_ENV_BUS and use CONFIG_I2C_ENV_EEPROM_BUS
by Valentin Longchamp 14 Oct '14

14 Oct '14

KM_ENV_BUS was used for nothing else than an direct assignment to CONFIG_I2C_ENV_EEPROM_BUS. To avoid this, directly use CONFIG_I2C_ENV_EEPROM_BUS instead. Signed-off-by: Valentin Longchamp <valentin.longchamp(a)keymile.com> --- include/configs/km/km_arm.h | 2 +- include/configs/km_kirkwood.h | 4 ---- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index d31e674..04cddb1 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -244,7 +244,7 @@ int get_scl(void); #define CONFIG_SYS_EEPROM_WREN #define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ #define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) -#define CONFIG_I2C_ENV_EEPROM_BUS KM_ENV_BUS +#define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */ #define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index dc26155..a445aaf 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -116,10 +116,6 @@ /* include common defines/options for all arm based Keymile boards */ #include "km/km_arm.h" -#ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR -#define KM_ENV_BUS 5 /* I2C2 (Mux-Port 5)*/ -#endif - #if defined(CONFIG_KM_PIGGY4_88E6352) /* * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via -- 1.8.0.1

2 1

[U-Boot] [PATCH] dm: serial: Fix breakage due to stdio changes
by Simon Glass 14 Oct '14

14 Oct '14

Commit 32d0192 broke the sandbox build - fix it. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- drivers/serial/serial-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index fd010ca..6dde4ea 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -198,7 +198,7 @@ static int serial_pre_remove(struct udevice *dev) #ifdef CONFIG_SYS_STDIO_DEREGISTER struct serial_dev_priv *upriv = dev->uclass_priv; - if (stdio_deregister_dev(upriv->sdev), 0) + if (stdio_deregister_dev(upriv->sdev, 0)) return -EPERM; #endif -- 2.1.0.rc2.206.gedb03e5

2 4

[U-Boot] [PATCH] Makefile: drop "tools-only" from no-dot-config-targets
by Tom Rini 14 Oct '14

14 Oct '14

With the introduction of CONFIG_LOCALVERSION support we cannot build tools without having a config file (as we won't know our PLAIN_VERSION until then). Reported-by: Otavio Salvador <otavio(a)ossystems.com.br> Signed-off-by: Tom Rini <trini(a)ti.com> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 8657417..4aa7cba 100644 --- a/Makefile +++ b/Makefile @@ -411,7 +411,7 @@ timestamp_h := include/generated/timestamp_autogenerated.h no-dot-config-targets := clean clobber mrproper distclean \ help %docs check% coccicheck \ - ubootversion backup tools-only + ubootversion backup config-targets := 0 mixed-targets := 0 -- 1.7.9.5

1 1

[U-Boot] Broken target
by Otavio Salvador 14 Oct '14

14 Oct '14

The 'tools-only' target seems to be broken. In a clean tree (no previous build) running: $: make tools-only fails with: CHK include/config/uboot.release /bin/sh: 1: cannot open include/config/auto.conf: No such file Makefile:1049: recipe for target 'include/config/uboot.release' failed make: *** [include/config/uboot.release] Error 2 Any idea about the root cause? it is a regression as 2014.07 works fine in this case. -- Otavio Salvador O.S. Systems http://www.ossystems.com.br http://code.ossystems.com.br Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750

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[U-Boot] [PATCH v2 2/2] imx: mx6sxsabresd: Add board support for USDHC2 and USDHC3
by Ye.Li 14 Oct '14

14 Oct '14

Add full support for USDHC2, USDHC3, USDHC4 on mx6sx sabresd board. The default boot socket is USDHC4, so the MMC environment is set to this device. Signed-off-by: Ye.Li <B37916(a)freescale.com> --- Changes since v1: - Modify the function return value board/freescale/mx6sxsabresd/mx6sxsabresd.c | 99 +++++++++++++++++++++++++-- include/configs/mx6sxsabresd.h | 6 ++- 2 files changed, 99 insertions(+), 6 deletions(-) diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 68d3718..f799998 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -68,6 +68,34 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD pin */ + MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* RST_B, used for power reset cycle */ + MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -255,23 +283,84 @@ int board_early_init_f(void) return 0; } -static struct fsl_esdhc_cfg usdhc_cfg[1] = { +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, {USDHC4_BASE_ADDR}, }; +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) +#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11) +#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21) + int board_mmc_getcd(struct mmc *mmc) { - return 1; /* Assume boot SD always present */ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = 1; /* Assume uSDHC2 is always present */ + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = !gpio_get_value(USDHC4_CD_GPIO); + break; + } + + return ret; } int board_mmc_init(bd_t *bis) { - imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + int i, ret; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC2 + * mmc1 USDHC3 + * mmc2 USDHC4 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + gpio_direction_output(USDHC3_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + gpio_direction_input(USDHC4_CD_GPIO); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; } + int board_init(void) { /* Address of boot parameters */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index e02ea18..5bbc8da 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -214,7 +214,6 @@ #define CONFIG_ENV_OFFSET (6 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ @@ -223,4 +222,9 @@ #define CONFIG_CMD_CACHE #endif +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/ +#endif + #endif /* __CONFIG_H */ -- 1.7.4.1

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[U-Boot] [PATCH v2 1/2] mmc: fsl_esdhc: Update esdhc driver for iMX6SX
by Ye.Li 14 Oct '14

14 Oct '14

The reset value of "uSDHCx_INT_STATUS_EN" register is changed to 0 on iMX6SX. So the fsl_esdhc driver must update to set the register, otherwise no state can be detected. Signed-off-by: Ye.Li <B37916(a)freescale.com> --- Changes since v1: - Remove codes which set INT_STATUS_EN register according PIO or DMA mode. drivers/mmc/fsl_esdhc.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 97d0389..bca86a8 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -23,6 +23,13 @@ DECLARE_GLOBAL_DATA_PTR; +#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ + IRQSTATEN_CINT | \ + IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ + IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ + IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ + IRQSTATEN_DINT) + struct fsl_esdhc { uint dsaddr; /* SDMA system address register */ uint blkattr; /* Block attributes register */ @@ -558,6 +565,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); + writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten); memset(&cfg->cfg, 0, sizeof(cfg->cfg)); voltage_caps = 0; -- 1.7.4.1

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[U-Boot] [PATCH v2 1/2] net: Add a command to access the EEPROM from ethernet devices
by Alban Bedel 14 Oct '14

14 Oct '14

Many ethernet devices use an EEPROM to store various settings, most commonly the device MAC address. But on some devices it can contains a lot more, for example USB device might also have many USB related parameters. This commit add a set of commands to read/write this EEPROM, write a default configuration and read/write the device MAC address. The defaults command allow priming the EEPROM for devices that need more than just a MAC address in the EEPROM. Signed-off-by: Alban Bedel <alban.bedel(a)avionic-design.de> --- v2: * No changes since v1 --- common/cmd_net.c | 134 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/net.h | 28 ++++++++++++ net/eth.c | 46 +++++++++++++++++++ 3 files changed, 208 insertions(+) diff --git a/common/cmd_net.c b/common/cmd_net.c index 09489d4..f4952d5 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -445,3 +445,137 @@ U_BOOT_CMD( ); #endif /* CONFIG_CMD_LINK_LOCAL */ + +#if defined(CONFIG_CMD_ETH_EEPROM) +static int do_eth_eeprom_rw(struct eth_device *dev, + int argc, char * const argv[]) +{ + ulong addr, offset, length = 1; + + if (argc < 4) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 16); + if (argc > 4) + length = simple_strtoul(argv[4], NULL, 16); + + if (!strcmp(argv[0], "write")) { + if (eth_eeprom_write(dev, offset, length, (void *)addr)) { + printf("EEPROM write failed\n"); + return CMD_RET_FAILURE; + } + return CMD_RET_SUCCESS; + } else if (!strcmp(argv[0], "read")) { + if (eth_eeprom_read(dev, offset, length, (void *)addr)) { + printf("EEPROM read failed\n"); + return CMD_RET_FAILURE; + } + return CMD_RET_SUCCESS; + } + + return CMD_RET_USAGE; +} + +static int do_eth_eeprom_defaults(struct eth_device *dev, + int argc, char * const argv[]) +{ + if (eth_eeprom_defaults(dev)) { + printf("EEPROM write failed\n"); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +static int do_eth_eeprom_set_mac(struct eth_device *dev, + int argc, char * const argv[]) +{ + u8 mac[6]; + + if (argc < 3) + return CMD_RET_USAGE; + + eth_parse_enetaddr(argv[2], mac); + if (!is_valid_ether_addr(mac)) { + printf("Invalid mac address given\n"); + return CMD_RET_FAILURE; + } + + printf("Writing MAC to EEPROM ....\n"); + if (eth_eeprom_write_mac(dev, mac)) { + printf("EEPROM write failed\n"); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +static int do_eth_eeprom_show_mac(struct eth_device *dev, + int argc, char * const argv[]) +{ + u8 data[6]; + + if (eth_eeprom_read_mac(dev, data)) { + printf("EEPROM read failed\n"); + return CMD_RET_FAILURE; + } + + printf("%pM\n", data); + if (!is_valid_ether_addr(data)) + printf("Warning: MAC address is not valid!\n"); + + return CMD_RET_SUCCESS; +} + +static int do_eth_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct eth_device *dev; + char *endp = NULL; + int index; + + if (argc < 3) + return CMD_RET_USAGE; + + /* Get the ethernet device, by ID or by name */ + index = (int) simple_strtoul(argv[2], &endp, 16); + if (endp > argv[2]) + dev = eth_get_dev_by_index(index); + else + dev = eth_get_dev_by_name(argv[2]); + + if (!dev) { + printf("Ethernet device not found\n"); + return CMD_RET_FAILURE; + } + + if (!strcmp(argv[1], "read") || !strcmp(argv[1], "write")) + return do_eth_eeprom_rw(dev, argc - 1, argv + 1); + if (!strcmp(argv[1], "defaults")) + return do_eth_eeprom_defaults(dev, argc - 1, argv + 1); + if (!strcmp(argv[1], "set_mac")) + return do_eth_eeprom_set_mac(dev, argc - 1, argv + 1); + if (!strcmp(argv[1], "show_mac")) + return do_eth_eeprom_show_mac(dev, argc - 1, argv + 1); + + printf("Unknown sub command: %s\n", argv[1]); + + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + eth_eeprom, 6, 0, do_eth_eeprom, + "access the EEPROM of ethernet devices", + "read dev addr off [size]\n" + " - read 'size' bytes starting at offset 'off' to memory address 'addr'.\n" + "eth_eeprom write dev addr off [size]\n" + " - write 'size' bytes starting at offset 'off' from memory address 'addr'.\n" + "eth_eeprom defaults dev\n" + " - write default settings in the EEPROM.\n" + "eth_eeprom set_mac dev mac\n" + " - set the MAC address in the EEPROM to 'mac'\n" + "eth_eeprom show_mac dev\n" + " - read the MAC address from the EEPROM." +); +#endif diff --git a/include/net.h b/include/net.h index 735b0b9..39ea848 100644 --- a/include/net.h +++ b/include/net.h @@ -92,6 +92,25 @@ struct eth_device { int (*mcast) (struct eth_device *, const u8 *enetaddr, u8 set); #endif int (*write_hwaddr) (struct eth_device *); +#ifdef CONFIG_CMD_ETH_EEPROM + /* Read data from the ethernet device eeprom */ + int (*eeprom_read)(struct eth_device *, + u32 offset, u32 length, u8 *data); + /* Write data to the ethernet device eeprom */ + int (*eeprom_write)(struct eth_device *, + u32 offset, u32 length, u8 *data); + /* Write the default settings to the eeprom */ + int (*eeprom_defaults)(struct eth_device *); + /* Read the MAC stored in the eeprom, if not implemented + * the MAC is assumed to be at the given offset. */ + int (*eeprom_read_mac)(struct eth_device *, u8 *enetaddr); + /* Write the MAC in the eeprom, if not implemented + * the MAC is assumed to be at the given offset. */ + int (*eeprom_write_mac)(struct eth_device *, u8 *enetaddr); + /* Offset of the MAC address for the default implementation. + * Set to a negative value if the MAC is not in the EEPROM. */ + int eeprom_mac_offset; +#endif struct eth_device *next; int index; void *priv; @@ -172,6 +191,15 @@ int eth_mcast_join(IPaddr_t mcast_addr, u8 join); u32 ether_crc(size_t len, unsigned char const *p); #endif +#ifdef CONFIG_CMD_ETH_EEPROM +int eth_eeprom_read(struct eth_device *dev, u32 offset, + u32 length, u8 *data); +int eth_eeprom_write(struct eth_device *dev, u32 offset, + u32 length, u8 *data); +int eth_eeprom_defaults(struct eth_device *dev); +int eth_eeprom_read_mac(struct eth_device *, u8 *enetaddr); +int eth_eeprom_write_mac(struct eth_device *, u8 *enetaddr); +#endif /**********************************************************************/ /* diff --git a/net/eth.c b/net/eth.c index 76ffa05..2cde72c 100644 --- a/net/eth.c +++ b/net/eth.c @@ -542,3 +542,49 @@ char *eth_get_name(void) { return eth_current ? eth_current->name : "unknown"; } + +#ifdef CONFIG_CMD_ETH_EEPROM +int eth_eeprom_read(struct eth_device *dev, u32 offset, + u32 length, u8 *data) +{ + return dev->eeprom_read ? + dev->eeprom_read(dev, offset, length, data) : + -ENOSYS; +} + +int eth_eeprom_write(struct eth_device *dev, u32 offset, + u32 length, u8 *data) +{ + return dev->eeprom_write ? + dev->eeprom_write(dev, offset, length, data) : + -ENOSYS; +} + +int eth_eeprom_defaults(struct eth_device *dev) +{ + return dev->eeprom_defaults ? dev->eeprom_defaults(dev) : + -ENOSYS; +} + +int eth_eeprom_read_mac(struct eth_device *dev, u8 *enetaddr) +{ + if (dev->eeprom_read_mac) + return dev->eeprom_read_mac(dev, enetaddr); + + return dev->eeprom_mac_offset >= 0 ? + eth_eeprom_read(dev, dev->eeprom_mac_offset, + 6, enetaddr) : + -ENOSYS; +} + +int eth_eeprom_write_mac(struct eth_device *dev, u8 *enetaddr) +{ + if (dev->eeprom_write_mac) + return dev->eeprom_write_mac(dev, enetaddr); + + return dev->eeprom_mac_offset >= 0 ? + eth_eeprom_write(dev, dev->eeprom_mac_offset, + 6, enetaddr) : + -ENOSYS; +} +#endif -- 2.1.1

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[U-Boot] [PATCH v3 1/4] QuadSPI: use QSPI_CMD_xx instead of flash opcodes
by Peng Fan 14 Oct '14

14 Oct '14

Use QSPI_CMD_xx instead of flash opcodes Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> --- Changelog v3: Use QSPI_CMD_XX instead of flash opcodes. To fsl qspi controller, the LUT should be pre programmed with QSPI CMD. Changelog v2: none drivers/spi/fsl_qspi.c | 64 ++++++++++++++++++++++++++------------------------ 1 file changed, 33 insertions(+), 31 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index ba20bef..61490c9 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -29,19 +29,19 @@ #define SEQID_PP 6 #define SEQID_RDID 7 -/* Flash opcodes */ -#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ -#define OPCODE_RDSR 0x05 /* Read status register */ -#define OPCODE_WREN 0x06 /* Write enable */ -#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ -#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ -#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ -#define OPCODE_RDID 0x9f /* Read JEDEC ID */ - -/* 4-byte address opcodes - used on Spansion and some Macronix flashes */ -#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ -#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */ -#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */ +/* QSPI CMD */ +#define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */ +#define QSPI_CMD_RDSR 0x05 /* Read status register */ +#define QSPI_CMD_WREN 0x06 /* Write enable */ +#define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */ +#define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */ +#define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */ +#define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */ + +/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */ +#define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ +#define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */ +#define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */ #ifdef CONFIG_SYS_FSL_QSPI_LE #define qspi_read32 in_le32 @@ -94,7 +94,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi) /* Write Enable */ lut_base = SEQID_WREN * 4; - qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_WREN) | + qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); qspi_write32(&regs->lut[lut_base + 1], 0); qspi_write32(&regs->lut[lut_base + 2], 0); @@ -103,13 +103,15 @@ static void qspi_set_lut(struct fsl_qspi *qspi) /* Fast Read */ lut_base = SEQID_FAST_READ * 4; if (FSL_QSPI_FLASH_SIZE <= SZ_16M) - qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_FAST_READ) | + qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); else - qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_FAST_READ_4B) | - PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | - PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + qspi_write32(&regs->lut[lut_base], + OPRND0(QSPI_CMD_FAST_READ_4B) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | + OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | + INSTR1(LUT_ADDR)); qspi_write32(&regs->lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); @@ -118,7 +120,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi) /* Read Status */ lut_base = SEQID_RDSR * 4; - qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_RDSR) | + qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); qspi_write32(&regs->lut[lut_base + 1], 0); @@ -128,11 +130,11 @@ static void qspi_set_lut(struct fsl_qspi *qspi) /* Erase a sector */ lut_base = SEQID_SE * 4; if (FSL_QSPI_FLASH_SIZE <= SZ_16M) - qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_SE) | + qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); else - qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_SE_4B) | + qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); qspi_write32(&regs->lut[lut_base + 1], 0); @@ -141,7 +143,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi) /* Erase the whole chip */ lut_base = SEQID_CHIP_ERASE * 4; - qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_CHIP_ERASE) | + qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_CHIP_ERASE) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); qspi_write32(&regs->lut[lut_base + 1], 0); qspi_write32(&regs->lut[lut_base + 2], 0); @@ -150,11 +152,11 @@ static void qspi_set_lut(struct fsl_qspi *qspi) /* Page Program */ lut_base = SEQID_PP * 4; if (FSL_QSPI_FLASH_SIZE <= SZ_16M) - qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_PP) | + qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); else - qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_PP_4B) | + qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); qspi_write32(&regs->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) | @@ -164,7 +166,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi) /* READ ID */ lut_base = SEQID_RDID * 4; - qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_RDID) | + qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); qspi_write32(&regs->lut[lut_base + 1], 0); @@ -454,22 +456,22 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, return 0; } - if (qspi->cur_seqid == OPCODE_FAST_READ) { + if (qspi->cur_seqid == QSPI_CMD_FAST_READ) { qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; - } else if (qspi->cur_seqid == OPCODE_SE) { + } else if (qspi->cur_seqid == QSPI_CMD_SE) { qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; qspi_op_se(qspi); - } else if (qspi->cur_seqid == OPCODE_PP) { + } else if (qspi->cur_seqid == QSPI_CMD_PP) { pp_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK; } } if (din) { - if (qspi->cur_seqid == OPCODE_FAST_READ) + if (qspi->cur_seqid == QSPI_CMD_FAST_READ) qspi_op_read(qspi, din, bytes); - else if (qspi->cur_seqid == OPCODE_RDID) + else if (qspi->cur_seqid == QSPI_CMD_RDID) qspi_op_rdid(qspi, din, bytes); - else if (qspi->cur_seqid == OPCODE_RDSR) + else if (qspi->cur_seqid == QSPI_CMD_RDSR) qspi_op_rdsr(qspi, din); } -- 1.8.4

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