January 2014 - U-Boot

[U-Boot] [PATCH v6 11/12] sf: Divide flash register ops from QEB code
by Jagannadha Sutradharudu Teki 06 Jan '14

06 Jan '14

QEB code comprises of couple of flash register read/write operations, this patch moved flash register operations on to sf_op Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- drivers/mtd/spi/sf_internal.h | 11 ++++--- drivers/mtd/spi/sf_ops.c | 75 +++++++++++++++---------------------------- drivers/mtd/spi/sf_probe.c | 44 +++++++++++++++++++++++++ 3 files changed, 77 insertions(+), 53 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index c69b53d..c77961f 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -101,14 +101,17 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, /* Flash erase(sectors) operation, support all possible erase commands */ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); +/* Read the status register */ +int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs); + /* Program the status register */ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr); -/* Set quad enbale bit for macronix flashes */ -int spi_flash_set_qeb_mxic(struct spi_flash *flash); +/* Read the config register */ +int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc); -/* Set quad enbale bit for winbond and spansion flashes */ -int spi_flash_set_qeb_winspan(struct spi_flash *flash); +/* Program the config register */ +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc); /* Enable writing on the SPI flash */ static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 9681042..658294c 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -24,94 +24,71 @@ static void spi_flash_addr(u32 addr, u8 *cmd) cmd[3] = addr >> 0; } -int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) +int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs) { - u8 cmd; int ret; + u8 cmd; - cmd = CMD_WRITE_STATUS; - ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1); + cmd = CMD_READ_STATUS; + ret = spi_flash_read_common(flash, &cmd, 1, rs, 1); if (ret < 0) { - debug("SF: fail to write status register\n"); + debug("SF: fail to read status register\n"); return ret; } return 0; } -#ifdef CONFIG_SPI_FLASH_MACRONIX -int spi_flash_set_qeb_mxic(struct spi_flash *flash) +int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) { - u8 qeb_status; u8 cmd; int ret; - cmd = CMD_READ_STATUS; - ret = spi_flash_read_common(flash, &cmd, 1, &qeb_status, 1); + cmd = CMD_WRITE_STATUS; + ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1); if (ret < 0) { - debug("SF: fail to read status register\n"); + debug("SF: fail to write status register\n"); return ret; } - if (qeb_status & STATUS_QEB_MXIC) { - debug("SF: Quad enable bit is already set\n"); - } else { - ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC); - if (ret < 0) - return ret; - } - - return ret; + return 0; } -#endif #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) -static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr) +int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc) { - u8 data[2]; - u8 cmd; int ret; + u8 cmd; - cmd = CMD_READ_STATUS; - ret = spi_flash_read_common(flash, &cmd, 1, &data[0], 1); + cmd = CMD_READ_CONFIG; + ret = spi_flash_read_common(flash, &cmd, 1, rc, 1); if (ret < 0) { - debug("SF: fail to read status register\n"); - return ret; - } - - cmd = CMD_WRITE_STATUS; - data[1] = cr; - ret = spi_flash_write_common(flash, &cmd, 1, &data, 2); - if (ret) { - debug("SF: fail to write config register\n"); + debug("SF: fail to read config register\n"); return ret; } return 0; } -int spi_flash_set_qeb_winspan(struct spi_flash *flash) +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc) { - u8 qeb_status; + u8 data[2]; u8 cmd; int ret; - cmd = CMD_READ_CONFIG; - ret = spi_flash_read_common(flash, &cmd, 1, &qeb_status, 1); - if (ret < 0) { - debug("SF: fail to read config register\n"); + ret = spi_flash_cmd_read_status(flash, &data[0]); + if (ret < 0) return ret; - } - if (qeb_status & STATUS_QEB_WINSPAN) { - debug("SF: Quad enable bit is already set\n"); - } else { - ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN); - if (ret < 0) - return ret; + cmd = CMD_WRITE_STATUS; + data[1] = wc; + ret = spi_flash_write_common(flash, &cmd, 1, &data, 2); + if (ret) { + debug("SF: fail to write config register\n"); + return ret; } - return ret; + return 0; } #endif diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index cbde350..8715b7c 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -28,6 +28,50 @@ static u8 spi_read_cmds_array[] = { CMD_READ_QUAD_IO_FAST, }; +#ifdef CONFIG_SPI_FLASH_MACRONIX +static int spi_flash_set_qeb_mxic(struct spi_flash *flash) +{ + u8 qeb_status; + int ret; + + ret = spi_flash_cmd_read_status(flash, &qeb_status); + if (ret < 0) + return ret; + + if (qeb_status & STATUS_QEB_MXIC) { + debug("SF: mxic: QEB is already set\n"); + } else { + ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC); + if (ret < 0) + return ret; + } + + return ret; +} +#endif + +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) +static int spi_flash_set_qeb_winspan(struct spi_flash *flash) +{ + u8 qeb_status; + int ret; + + ret = spi_flash_cmd_read_config(flash, &qeb_status); + if (ret < 0) + return ret; + + if (qeb_status & STATUS_QEB_WINSPAN) { + debug("SF: winspan: QEB is already set\n"); + } else { + ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN); + if (ret < 0) + return ret; + } + + return ret; +} +#endif + static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0) { switch (idcode0) { -- 1.8.3

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[U-Boot] [PATCH v6 00/12] sf: Add Extended read and quad read/write commands support
by Jagannadha Sutradharudu Teki 06 Jan '14

06 Jan '14

This a suffix series for http://u-boot.10912.n7.nabble.com/PATCH-v4-00-36-sf-Add-common-probe-and-ex… for adding extended read and quad read/write commands support. Concept: "Implementation will discover the fastest command by taking the supported commands from flash and a controller. Controller supported commands will always been a priority." The above concept is changed in this series as couple of reviews from earlier ones. - Implementation concept will apply on read commands. - As we have two write commands as of now – so this series is not trying to discover the fastest write command - The respective command modes are given to the controller driver side as a form of SPI RX/RX operation modes - so sf definitions will not be part of SPI driver side. Testing branch: $ git clone git://git.denx.de/u-boot-spi.git $ cd u-boot-spi $ git checkout -b master-quad origin/master-quad REQUEST FOR ALL SPI CODE CONTRIBUTORS/USERS, PLEASE TEST THESE CHANGES W.R.T YOUR HW IF POSSIBLE. Please let me know for any issues/concerns/questions. -- Thanks, Jagan. Changes for v6: - Divided flash reg ops code - sf_ops.c clean Changes for v5: - Re-implemented write command log - not trying to discover the fastest write - Added SPI RX/TX operation modes - SPI flash parts are moved into sf_params.c file - Added QUAD_IO_FAST read support - Discovred the read dummy_cycles based on configured read cmd - Added set QEB support for macronix flash - Enabled quad read/write cmd support for macronix flash Changes for v4: Changes for v3: Changes for v2: - none Jagannadha Sutradharudu Teki (12): sf: Add extended read commands support sf: Add quad read/write commands support sf: ops: Add configuration register writing support sf: Set quad enable bit support sf: probe: Enable RD_FULL and WR_QPP sf: Separate the flash params table sf: Add QUAD_IO_FAST read support sf: Discover read dummy_cycles sf: Add macronix set QEB support sf: probe: Enable macronix quad read/write cmds support sf: Divide flash register ops from QEB code sf: Code cleanups drivers/mtd/spi/Makefile | 4 +- drivers/mtd/spi/sf_internal.h | 31 +++++- drivers/mtd/spi/sf_ops.c | 71 ++++++++++-- drivers/mtd/spi/sf_params.c | 130 ++++++++++++++++++++++ drivers/mtd/spi/sf_probe.c | 246 +++++++++++++++++++----------------------- include/spi.h | 17 +++ include/spi_flash.h | 43 ++++++++ 7 files changed, 393 insertions(+), 149 deletions(-) create mode 100644 drivers/mtd/spi/sf_params.c -- 1.8.3

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[U-Boot] How to make Loading and Decompression parallel in u-boot
by Ramappa 06 Jan '14

06 Jan '14

Hi, I'm having latest u-boot. I'm using DMA support to transfer images from NAND to RAM. So now I want to make Loading and decompression parallel. How to do this. Kindly give some suggestions on this. Thanks Ramappa -- View this message in context: http://u-boot.10912.n7.nabble.com/How-to-make-Loading-and-Decompression-par… Sent from the U-Boot mailing list archive at Nabble.com.

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[U-Boot] [PATCH] sh: delete redundant CONFIG_SH definition
by Masahiro Yamada 06 Jan '14

06 Jan '14

CONFIG_SH is defined in arch/sh/config.mk. It is not necessary to define it in each board header config header file. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> --- include/configs/MigoR.h | 1 - include/configs/ap325rxa.h | 1 - include/configs/ap_sh4a_4a.h | 1 - include/configs/ecovec.h | 1 - include/configs/espt.h | 1 - include/configs/mpr2.h | 1 - include/configs/ms7720se.h | 1 - include/configs/ms7722se.h | 1 - include/configs/ms7750se.h | 1 - include/configs/r0p7734.h | 1 - include/configs/r2dplus.h | 1 - include/configs/r7780mp.h | 1 - include/configs/rsk7203.h | 1 - include/configs/rsk7264.h | 1 - include/configs/rsk7269.h | 1 - include/configs/sh7752evb.h | 1 - include/configs/sh7753evb.h | 1 - include/configs/sh7757lcr.h | 1 - include/configs/sh7763rdp.h | 1 - include/configs/sh7785lcr.h | 1 - include/configs/shmin.h | 1 - 21 files changed, 21 deletions(-) diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index 9fd4551..47e3322 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -10,7 +10,6 @@ #define __MIGO_R_H #undef DEBUG -#define CONFIG_SH 1 #define CONFIG_SH4 1 #define CONFIG_CPU_SH7722 1 #define CONFIG_MIGO_R 1 diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h index 933de52..a3c6b2b 100644 --- a/include/configs/ap325rxa.h +++ b/include/configs/ap325rxa.h @@ -11,7 +11,6 @@ #define __AP325RXA_H #undef DEBUG -#define CONFIG_SH 1 #define CONFIG_SH4 1 #define CONFIG_CPU_SH7723 1 #define CONFIG_AP325RXA 1 diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h index 83a5c37..7478386 100644 --- a/include/configs/ap_sh4a_4a.h +++ b/include/configs/ap_sh4a_4a.h @@ -10,7 +10,6 @@ #define __AP_SH4A_4A_H #undef DEBUG -#define CONFIG_SH 1 #define CONFIG_SH4 1 #define CONFIG_SH4A 1 #define CONFIG_CPU_SH7734 1 diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h index 3483cf1..a8f6dc9 100644 --- a/include/configs/ecovec.h +++ b/include/configs/ecovec.h @@ -23,7 +23,6 @@ */ #undef DEBUG -#define CONFIG_SH 1 #define CONFIG_SH4 1 #define CONFIG_SH4A 1 #define CONFIG_CPU_SH7724 1 diff --git a/include/configs/espt.h b/include/configs/espt.h index 1bd7eec..8493c24 100644 --- a/include/configs/espt.h +++ b/include/configs/espt.h @@ -10,7 +10,6 @@ #ifndef __ESPT_H #define __ESPT_H -#define CONFIG_SH 1 #define CONFIG_SH4 1 #define CONFIG_CPU_SH7763 1 #define CONFIG_ESPT 1 diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h index fcf237e..47ed694 100644 --- a/include/configs/mpr2.h +++ b/include/configs/mpr2.h @@ -24,7 +24,6 @@ #define CONFIG_VERSION_VARIABLE /* CPU and platform */ -#define CONFIG_SH 1 #define CONFIG_SH3 1 #define CONFIG_CPU_SH7720 1 #define CONFIG_MPR2 1 diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h index ec8523e..029f0e7 100644 --- a/include/configs/ms7720se.h +++ b/include/configs/ms7720se.h @@ -9,7 +9,6 @@ #ifndef __MS7720SE_H #define __MS7720SE_H -#define CONFIG_SH 1 #define CONFIG_SH3 1 #define CONFIG_CPU_SH7720 1 #define CONFIG_MS7720SE 1 diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index 54fb7c3..20f8226 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -9,7 +9,6 @@ #ifndef __MS7722SE_H #define __MS7722SE_H -#define CONFIG_SH 1 #define CONFIG_SH4 1 #define CONFIG_CPU_SH7722 1 #define CONFIG_MS7722SE 1 diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h index eea3bd1..d7285fd 100644 --- a/include/configs/ms7750se.h +++ b/include/configs/ms7750se.h @@ -9,7 +9,6 @@ #ifndef __MS7750SE_H #define __MS7750SE_H -#define CONFIG_SH 1 #define CONFIG_SH4 1 #define CONFIG_CPU_SH7750 1 /* #define CONFIG_CPU_SH7751 1 */ diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h index dd26a71..766d9b7 100644 --- a/include/configs/r0p7734.h +++ b/include/configs/r0p7734.h @@ -10,7 +10,6 @@ #define __R0P7734_H #undef DEBUG -#define CONFIG_SH 1 #define CONFIG_SH4 1 #define CONFIG_SH4A 1 #define CONFIG_CPU_SH7734 1 diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index ddcc975..264abeb 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -3,7 +3,6 @@ #undef DEBUG -#define CONFIG_SH 1 #define CONFIG_SH4 1 #define CONFIG_CPU_SH7751 1 #define CONFIG_CPU_SH_TYPE_R 1 diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index f5e4daa..3574c52 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -11,7 +11,6 @@ #define __R7780RP_H #undef DEBUG -#define CONFIG_SH 1 #define CONFIG_SH4A 1 #define CONFIG_CPU_SH7780 1 #define CONFIG_R7780MP 1 diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h index acee4e8..d64579f 100644 --- a/include/configs/rsk7203.h +++ b/include/configs/rsk7203.h @@ -11,7 +11,6 @@ #define __RSK7203_H #undef DEBUG -#define CONFIG_SH 1 #define CONFIG_SH2 1 #define CONFIG_SH2A 1 #define CONFIG_CPU_SH7203 1 diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h index a5dbb64..62b0618 100644 --- a/include/configs/rsk7264.h +++ b/include/configs/rsk7264.h @@ -12,7 +12,6 @@ #define __RSK7264_H #undef DEBUG -#define CONFIG_SH 1 #define CONFIG_SH2 1 #define CONFIG_SH2A 1 #define CONFIG_CPU_SH7264 1 diff --git a/include/configs/rsk7269.h b/include/configs/rsk7269.h index 9f54160..452f5b4 100644 --- a/include/configs/rsk7269.h +++ b/include/configs/rsk7269.h @@ -11,7 +11,6 @@ #define __RSK7269_H #undef DEBUG -#define CONFIG_SH 1 #define CONFIG_SH2 1 #define CONFIG_SH2A 1 #define CONFIG_CPU_SH7269 1 diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h index ebdc5c8..d4d45b4 100644 --- a/include/configs/sh7752evb.h +++ b/include/configs/sh7752evb.h @@ -10,7 +10,6 @@ #define __SH7752EVB_H #undef DEBUG -#define CONFIG_SH 1 #define CONFIG_SH4A 1 #define CONFIG_SH_32BIT 1 #define CONFIG_CPU_SH7752 1 diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h index f7eb86d..fa6e74a 100644 --- a/include/configs/sh7753evb.h +++ b/include/configs/sh7753evb.h @@ -10,7 +10,6 @@ #define __SH7753EVB_H #undef DEBUG -#define CONFIG_SH 1 #define CONFIG_SH4A 1 #define CONFIG_SH_32BIT 1 #define CONFIG_CPU_SH7753 1 diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index ce1add2..5752dbb 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -10,7 +10,6 @@ #define __SH7757LCR_H #undef DEBUG -#define CONFIG_SH 1 #define CONFIG_SH4A 1 #define CONFIG_SH_32BIT 1 #define CONFIG_CPU_SH7757 1 diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index a137788..0b19e05 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -10,7 +10,6 @@ #ifndef __SH7763RDP_H #define __SH7763RDP_H -#define CONFIG_SH 1 #define CONFIG_SH4 1 #define CONFIG_CPU_SH7763 1 #define CONFIG_SH7763RDP 1 diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h index 4acbcab..95f5a28 100644 --- a/include/configs/sh7785lcr.h +++ b/include/configs/sh7785lcr.h @@ -10,7 +10,6 @@ #define __SH7785LCR_H #undef DEBUG -#define CONFIG_SH 1 #define CONFIG_SH4A 1 #define CONFIG_CPU_SH7785 1 #define CONFIG_SH7785LCR 1 diff --git a/include/configs/shmin.h b/include/configs/shmin.h index 5c990fc..4f333b0 100644 --- a/include/configs/shmin.h +++ b/include/configs/shmin.h @@ -9,7 +9,6 @@ #ifndef __SHMIN_H #define __SHMIN_H -#define CONFIG_SH 1 #define CONFIG_SH3 1 #define CONFIG_CPU_SH7706 1 /* T-SH7706LAN */ -- 1.8.3.2

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[U-Boot] [PATCH] Remove obsolte _LINUX_CONFIG_H macro
by Masahiro Yamada 06 Jan '14

06 Jan '14

Commit 643aae1406c93ddc64fcf8c136b47cdffd9c8ccd deleted include/linux/config.h but missed to delete _LINUX_CONFIG_H macro. It is no longer used at all. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- arch/powerpc/cpu/mpc5xx/start.S | 1 - arch/powerpc/cpu/mpc5xxx/start.S | 1 - arch/powerpc/cpu/mpc824x/start.S | 2 -- arch/powerpc/cpu/mpc8260/kgdb.S | 1 - arch/powerpc/cpu/mpc8260/start.S | 1 - arch/powerpc/cpu/mpc83xx/start.S | 1 - arch/powerpc/cpu/mpc85xx/release.S | 2 -- arch/powerpc/cpu/mpc85xx/start.S | 2 -- arch/powerpc/cpu/mpc8xx/kgdb.S | 1 - arch/powerpc/cpu/mpc8xx/start.S | 1 - arch/powerpc/cpu/ppc4xx/dcr.S | 2 -- arch/powerpc/cpu/ppc4xx/kgdb.S | 1 - arch/powerpc/cpu/ppc4xx/start.S | 2 -- board/cray/L1/init.S | 2 -- board/csb272/init.S | 2 -- board/csb472/init.S | 2 -- board/mpl/mip405/init.S | 1 - board/mpl/pip405/init.S | 1 - board/sc3/init.S | 2 -- board/w7o/init.S | 2 -- board/w7o/post1.S | 2 -- include/common.h | 3 --- 22 files changed, 35 deletions(-) diff --git a/arch/powerpc/cpu/mpc5xx/start.S b/arch/powerpc/cpu/mpc5xx/start.S index 92f956d..22fb274 100644 --- a/arch/powerpc/cpu/mpc5xx/start.S +++ b/arch/powerpc/cpu/mpc5xx/start.S @@ -20,7 +20,6 @@ #include <version.h> #define CONFIG_5xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S index 517b580..84ab41e 100644 --- a/arch/powerpc/cpu/mpc5xxx/start.S +++ b/arch/powerpc/cpu/mpc5xxx/start.S @@ -15,7 +15,6 @@ #include <version.h> #define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S index 6f397a4..b1fb062 100644 --- a/arch/powerpc/cpu/mpc824x/start.S +++ b/arch/powerpc/cpu/mpc824x/start.S @@ -26,8 +26,6 @@ #include <mpc824x.h> #include <version.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc8260/kgdb.S b/arch/powerpc/cpu/mpc8260/kgdb.S index 5a298f9..dd04d6b 100644 --- a/arch/powerpc/cpu/mpc8260/kgdb.S +++ b/arch/powerpc/cpu/mpc8260/kgdb.S @@ -10,7 +10,6 @@ #include <version.h> #define CONFIG_8260 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S index 1269291..65510fa 100644 --- a/arch/powerpc/cpu/mpc8260/start.S +++ b/arch/powerpc/cpu/mpc8260/start.S @@ -15,7 +15,6 @@ #include <version.h> #define CONFIG_8260 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index b4fafe6..a487bcc 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -20,7 +20,6 @@ #include <version.h> #define CONFIG_83XX 1 /* needed for Linux kernel header files*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index c15e83b..fcfba7e 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -10,8 +10,6 @@ #include <mpc85xx.h> #include <version.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index db84d10..dbbd8e5 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -17,8 +17,6 @@ #include <mpc85xx.h> #include <version.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc8xx/kgdb.S b/arch/powerpc/cpu/mpc8xx/kgdb.S index ea27d59..ac1fe8f 100644 --- a/arch/powerpc/cpu/mpc8xx/kgdb.S +++ b/arch/powerpc/cpu/mpc8xx/kgdb.S @@ -10,7 +10,6 @@ #include <version.h> #define CONFIG_8xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index 9869bbd..99cafbd 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -27,7 +27,6 @@ #include <version.h> #define CONFIG_8xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/ppc4xx/dcr.S b/arch/powerpc/cpu/ppc4xx/dcr.S index 0d99391..6b13528 100644 --- a/arch/powerpc/cpu/ppc4xx/dcr.S +++ b/arch/powerpc/cpu/ppc4xx/dcr.S @@ -10,8 +10,6 @@ #include <asm/ppc4xx.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/ppc4xx/kgdb.S b/arch/powerpc/cpu/ppc4xx/kgdb.S index dbc4a6c..f274c5d 100644 --- a/arch/powerpc/cpu/ppc4xx/kgdb.S +++ b/arch/powerpc/cpu/ppc4xx/kgdb.S @@ -10,7 +10,6 @@ #include <version.h> #define CONFIG_405GP 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 38bbc5a..e72c37c 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -31,8 +31,6 @@ #include <asm/ppc4xx.h> #include <version.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S index 44c688d..d4723c7 100644 --- a/board/cray/L1/init.S +++ b/board/cray/L1/init.S @@ -22,8 +22,6 @@ /*-----------------------------------------------------------------------------#include <config.h> */ #include <asm/ppc4xx.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/board/csb272/init.S b/board/csb272/init.S index 5961978..bf1d986 100644 --- a/board/csb272/init.S +++ b/board/csb272/init.S @@ -4,8 +4,6 @@ #include <config.h> #include <asm/ppc4xx.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/board/csb472/init.S b/board/csb472/init.S index 1ebc9ea..7383a70 100644 --- a/board/csb472/init.S +++ b/board/csb472/init.S @@ -4,8 +4,6 @@ #include <config.h> #include <asm/ppc4xx.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S index 642f17c..2ea2e29 100644 --- a/board/mpl/mip405/init.S +++ b/board/mpl/mip405/init.S @@ -19,7 +19,6 @@ * Bank 6 - not used * Bank 7 - PLD Register *-----------------------------------------------------------------------------*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <configs/MIP405.h> #include <ppc_asm.tmpl> diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S index 95fed34..292393e 100644 --- a/board/mpl/pip405/init.S +++ b/board/mpl/pip405/init.S @@ -19,7 +19,6 @@ * Bank 6 - used to switch on the 12V for the Multipurpose socket * Bank 7 - Config Register *-----------------------------------------------------------------------------*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <configs/PIP405.h> #include <ppc_asm.tmpl> diff --git a/board/sc3/init.S b/board/sc3/init.S index 46323d2..097aa4a 100644 --- a/board/sc3/init.S +++ b/board/sc3/init.S @@ -4,8 +4,6 @@ #include <config.h> #include <asm/ppc4xx.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/board/w7o/init.S b/board/w7o/init.S index 54eda32..dfde149 100644 --- a/board/w7o/init.S +++ b/board/w7o/init.S @@ -4,8 +4,6 @@ #include <config.h> #include <asm/ppc4xx.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/board/w7o/post1.S b/board/w7o/post1.S index 7a411a4..aae5387 100644 --- a/board/w7o/post1.S +++ b/board/w7o/post1.S @@ -13,8 +13,6 @@ #include <config.h> #include <asm/ppc4xx.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/include/common.h b/include/common.h index d49c514..d5ebb25 100644 --- a/include/common.h +++ b/include/common.h @@ -8,9 +8,6 @@ #ifndef __COMMON_H_ #define __COMMON_H_ 1 -#undef _LINUX_CONFIG_H -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #ifndef __ASSEMBLY__ /* put C only stuff in this section */ typedef unsigned char uchar; -- 1.8.3.2

1 0

[U-Boot] [PATCH 1/7 V4] mmc: Add some usefull macro definition
by Haijun Zhang 06 Jan '14

06 Jan '14

From: Haijun Zhang <Haijun.Zhang(a)freescale.com> Add command class define. Add mmc erase and secure erase define. Add secure erase and trim support bit define. Signed-off-by: Haijun Zhang <haijun.zhang(a)freescale.com> --- changes for V4: - no changes changes for V3: - No changes include/mmc.h | 50 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/include/mmc.h b/include/mmc.h index cb558da..08f0f3e 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -53,6 +53,7 @@ #define COMM_ERR -18 /* Communications Error */ #define TIMEOUT -19 #define IN_PROGRESS -20 /* operation is in progress */ +#define NOT_SUPPORT -21 /* Operation is not support */ #define MMC_CMD_GO_IDLE_STATE 0 #define MMC_CMD_SEND_OP_COND 1 @@ -105,6 +106,39 @@ #define OCR_VOLTAGE_MASK 0x007FFF80 #define OCR_ACCESS_MODE 0x60000000 +/* + * Card Command Classes (CCC) + * + * (0) Basic protocol functions (CMD0,1,2,3,4,7,9,10,12,13,15) + * (and for SPI, CMD58,59) + * (1) Stream read commands (CMD11) + * (2) Block read commands (CMD16,17,18) + * (3) Stream write commands (CMD20) + * (4) Block write commands (CMD16,24,25,26,27) + * (5) Ability to erase blocks (CMD32,33,34,35,36,37,38,39) + * (6) Able to write protect blocks (CMD28,29,30) + * (7) Able to lock down card (CMD16,CMD42) + * (8) Application specific (CMD55,56,57,ACMD*) + * (9) I/O mode (CMD5,39,40,52,53) + * (10) High speed switch (CMD6,34,35,36,37,50) + */ +#define CCC_BASIC (1<<0) +#define CCC_STREAM_READ (1<<1) +#define CCC_BLOCK_READ (1<<2) +#define CCC_STREAM_WRITE (1<<3) +#define CCC_BLOCK_WRITE (1<<4) +#define CCC_ERASE (1<<5) +#define CCC_WRITE_PROT (1<<6) +#define CCC_LOCK_CARD (1<<7) +#define CCC_APP_SPEC (1<<8) +#define CCC_IO_MODE (1<<9) +#define CCC_SWITCH (1<<10) + +#define MMC_ERASE_ARG 0x00000000 +#define MMC_SECURE_ERASE_ARG 0x80000000 +#define MMC_TRIM_ARG 0x00000001 +#define MMC_DISCARD_ARG 0x00000003 + #define SECURE_ERASE 0x80000000 #define MMC_STATUS_MASK (~0x0206BF7F) @@ -160,8 +194,12 @@ #define EXT_CSD_CARD_TYPE 196 /* RO */ #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ +#define EXT_CSD_REL_WR_SEC_C 222 /* RO */ +#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */ #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ #define EXT_CSD_BOOT_MULT 226 /* RO */ +#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */ +#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ /* * EXT_CSD field definitions @@ -178,6 +216,12 @@ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ +/* EXT_CSD[231] */ +#define EXT_CSD_SEC_ER_EN (1<<0) +#define EXT_CSD_SEC_BD_BLK_EN (1<<2) +#define EXT_CSD_SEC_GB_CL_EN (1<<4) +#define EXT_CSD_SEC_SANITIZE (1<<6) /* v4.5 later */ + #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) @@ -187,7 +231,6 @@ #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) - #define R1_ILLEGAL_COMMAND (1 << 22) #define R1_APP_CMD (1 << 5) @@ -268,10 +311,15 @@ struct mmc { ushort rca; char part_config; char part_num; + ushort cmdclass; uint tran_speed; uint read_bl_len; uint write_bl_len; uint erase_grp_size; + uint erase_timeout_mult; + char sec_feature_support; + uint sec_erase_mult; + uint sec_erase_timeout; u64 capacity; u64 capacity_user; u64 capacity_boot; -- 1.8.4.1

4 10

[U-Boot] [PATCH v2 4/4] sf: Add CONFIG_SF_NR_FLASH
by Jagannadha Sutradharudu Teki 05 Jan '14

05 Jan '14

This config will use for defining greater than single flash support. currently - DUAL_STACKED and DUAL_PARALLEL. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- README | 6 ++++++ drivers/mtd/spi/sf.c | 3 ++- drivers/mtd/spi/sf_ops.c | 14 ++++++++++---- drivers/mtd/spi/sf_probe.c | 2 ++ 4 files changed, 20 insertions(+), 5 deletions(-) diff --git a/README b/README index 895fef3..20c1f92 100644 --- a/README +++ b/README @@ -2751,6 +2751,12 @@ CBFS (Coreboot Filesystem) support Define this option to use the Bank addr/Extended addr support on SPI flashes which has size > 16Mbytes. + CONFIG_SF_NR_FLASH Greater than single flash + + Define this option to use greater than single flash connected + with a given cs line from controller - currently Xilinx Zynq + qspi support dual/two flashes can be connected from single cs. + - SystemACE Support: CONFIG_SYSTEMACE diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c index c780a81..d947d47 100644 --- a/drivers/mtd/spi/sf.c +++ b/drivers/mtd/spi/sf.c @@ -18,9 +18,10 @@ static int spi_flash_read_write(struct spi_slave *spi, unsigned long flags = SPI_XFER_BEGIN; int ret; +#ifdef CONFIG_SF_NR_FLASH if (spi->flags & SPI_XFER_U_PAGE) flags |= SPI_XFER_U_PAGE; - +#endif if (data_len == 0) flags |= SPI_XFER_END; diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 4fafbc6..914c1b6 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -131,6 +131,7 @@ static int spi_flash_bank(struct spi_flash *flash, u32 offset) } #endif +#ifdef CONFIG_SF_NR_FLASH static void spi_flash_nr_flash(struct spi_flash *flash, u32 *addr) { switch (flash->nr_flash) { @@ -150,6 +151,7 @@ static void spi_flash_nr_flash(struct spi_flash *flash, u32 *addr) break; } } +#endif int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) { @@ -167,9 +169,10 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) check_status = poll_bit; } +#ifdef CONFIG_SF_NR_FLASH if (spi->flags & SPI_XFER_U_PAGE) flags |= SPI_XFER_U_PAGE; - +#endif ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN); if (ret) { debug("SF: fail to read %s status register\n", @@ -257,9 +260,10 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) while (len) { erase_addr = offset; +#ifdef CONFIG_SF_NR_FLASH if (flash->nr_flash > SF_NRF_SINGLE) spi_flash_nr_flash(flash, &erase_addr); - +#endif #ifdef CONFIG_SPI_FLASH_BAR ret = spi_flash_bank(flash, erase_addr); if (ret < 0) @@ -298,9 +302,10 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, for (actual = 0; actual < len; actual += chunk_len) { write_addr = offset; +#ifdef CONFIG_SF_NR_FLASH if (flash->nr_flash > SF_NRF_SINGLE) spi_flash_nr_flash(flash, &write_addr); - +#endif #ifdef CONFIG_SPI_FLASH_BAR ret = spi_flash_bank(flash, write_addr); if (ret < 0) @@ -382,9 +387,10 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, while (len) { read_addr = offset; +#ifdef CONFIG_SF_NR_FLASH if (flash->nr_flash > SF_NRF_SINGLE) spi_flash_nr_flash(flash, &read_addr); - +#endif #ifdef CONFIG_SPI_FLASH_BAR bank_sel = spi_flash_bank(flash, read_addr); if (bank_sel < 0) diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 0dc20f9..351a523 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -150,8 +150,10 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash->page_size = ((ext_jedec == 0x4d00) ? 512 : 256) << flash->shift; flash->sector_size = params->sector_size << flash->shift; flash->size = flash->sector_size * params->nr_sectors << flash->shift; +#ifdef CONFIG_SF_NR_FLASH if (flash->nr_flash & SF_NRF_DUAL_STACKED) flash->size <<= 1; +#endif /* Compute erase sector and command */ if (params->flags & SECT_4K) { -- 1.8.3

1 0

[U-Boot] [PATCH v2 3/4] sf: Add dual memories support - DUAL_PARALLEL
by Jagannadha Sutradharudu Teki 05 Jan '14

05 Jan '14

This patch added support for accessing dual memories in parallel connection with single chipselect line from controller. For more info - see doc/SPI/README.nr-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- doc/SPI/README.nr-flash | 27 +++++++++++++++++++++++++++ drivers/mtd/spi/sf_ops.c | 8 ++++++-- drivers/mtd/spi/sf_probe.c | 11 ++++++----- include/spi.h | 3 ++- include/spi_flash.h | 5 ++++- 5 files changed, 45 insertions(+), 9 deletions(-) diff --git a/doc/SPI/README.nr-flash b/doc/SPI/README.nr-flash index 65a5370..e8b099e 100644 --- a/doc/SPI/README.nr-flash +++ b/doc/SPI/README.nr-flash @@ -54,6 +54,33 @@ SF_NRF_DUAL_STACKED: by default, if U_PAGE is unset lower memory should accessible, once user wants to access upper memory need to set U_PAGE. +SPI_FLASH_CONN_DUALPARALLEL: + - dual spi/qspi flash memories are connected with a single chipselect + line and these two memories are operating parallel with separate buses. + - xilinx zynq qspi controller has implemented this feature [1] + + +-------------+ CS +---------------+ + | |---------------------->| | + | | I0[3:0] | Upper Flash | + | |<=====================>| memory | + | | CLK | (SPI/QSPI) | + | |---------------------->| | + | Controller | CS +---------------+ + | SPI/QSPI |---------------------->| | + | | I0[3:0] | Lower Flash | + | |<=====================>| memory | + | | CLK | (SPI/QSPI) | + | |---------------------->| | + +-------------+ +---------------+ + + - two memory flash devices should has same hw part attributes (like size, + vendor..etc) + - Configurations: + Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register. + - Operation: + Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory + and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory. + Note: Technically there is only one CS line from the controller, but zynq qspi controller has an internal hw logic to enable additional CS when controller is configured for dual memories. diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index d96a69e..4fafbc6 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -119,7 +119,7 @@ static int spi_flash_bank(struct spi_flash *flash, u32 offset) u8 bank_sel; int ret; - bank_sel = offset / SPI_FLASH_16MB_BOUN; + bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift); ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); if (ret) { @@ -142,6 +142,9 @@ static void spi_flash_nr_flash(struct spi_flash *flash, u32 *addr) flash->spi->flags &= ~SPI_XFER_U_PAGE; } break; + case SF_NRF_DUAL_PARALLEL: + *addr >>= flash->shift; + break; default: debug("SF: Unsupported nr_flash=%d\n", flash->nr_flash); break; @@ -387,7 +390,8 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, if (bank_sel < 0) return ret; #endif - remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset; + remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * + (bank_sel + 1)) - offset; if (len < remain_len) read_len = len; else diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 248050c..0dc20f9 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -146,19 +146,20 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash->read = spi_flash_cmd_read_ops; /* Compute the flash size */ - flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256; - flash->sector_size = params->sector_size; - flash->size = flash->sector_size * params->nr_sectors; + flash->shift = (flash->nr_flash & SF_NRF_DUAL_PARALLEL) ? 1 : 0; + flash->page_size = ((ext_jedec == 0x4d00) ? 512 : 256) << flash->shift; + flash->sector_size = params->sector_size << flash->shift; + flash->size = flash->sector_size * params->nr_sectors << flash->shift; if (flash->nr_flash & SF_NRF_DUAL_STACKED) flash->size <<= 1; /* Compute erase sector and command */ if (params->flags & SECT_4K) { flash->erase_cmd = CMD_ERASE_4K; - flash->erase_size = 4096; + flash->erase_size = 4096 << flash->shift; } else if (params->flags & SECT_32K) { flash->erase_cmd = CMD_ERASE_32K; - flash->erase_size = 32768; + flash->erase_size = 32768 << flash->shift; } else { flash->erase_cmd = CMD_ERASE_64K; flash->erase_size = flash->sector_size; diff --git a/include/spi.h b/include/spi.h index d214d82..ffd6647 100644 --- a/include/spi.h +++ b/include/spi.h @@ -47,6 +47,7 @@ /* SPI bus connection options */ #define SPI_CONN_DUAL_SHARED 1 << 0 +#define SPI_CONN_DUAL_SEPARATED 1 << 1 /* Header byte that marks the start of the message */ #define SPI_PREAMBLE_END_BYTE 0xec @@ -66,7 +67,7 @@ * @max_write_size: If non-zero, the maximum number of bytes which can * be written at once, excluding command bytes. * @memory_map: Address of read-only SPI flash access. - * @option: Varies SPI bus options - separate bus. + * @option: Varies SPI bus options - separate, shared bus. * @flags: Indication of SPI flags. */ struct spi_slave { diff --git a/include/spi_flash.h b/include/spi_flash.h index bb6eb0c..4f99ea6 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -37,6 +37,7 @@ enum spi_read_cmds { enum spi_nr_flash { SF_NRF_SINGLE = 0, SF_NRF_DUAL_STACKED = 1 << 0, + SF_NRF_DUAL_PARALLEL = 1 << 1, }; /** @@ -67,7 +68,8 @@ extern const struct spi_flash_params spi_flash_params_table[]; * * @spi: SPI slave * @name: Name of SPI flash - * @nr_flash: Indicates no.of flash memories - dual stacked + * @nr_flash: Indicates no.of flash memories - dual stacked, parallel + * @shift: Flash shift useful in dual parallel * @size: Total flash size * @page_size: Write (page) size * @sector_size: Sector size @@ -93,6 +95,7 @@ struct spi_flash { struct spi_slave *spi; const char *name; u8 nr_flash; + u8 shift; u32 size; u32 page_size; -- 1.8.3

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[U-Boot] [PATCH v2 2/4] sf: Add dual memories support - DUAL_STACKED
by Jagannadha Sutradharudu Teki 05 Jan '14

05 Jan '14

This patch added support for accessing dual memories in stacked connection with single chipselect line from controller. For more info - see doc/SPI/README.nr-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- doc/SPI/README.nr-flash | 65 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/mtd/spi/sf.c | 3 +++ drivers/mtd/spi/sf_ops.c | 55 ++++++++++++++++++++++++++++++++------- drivers/mtd/spi/sf_probe.c | 8 +++++- include/spi.h | 8 ++++++ include/spi_flash.h | 8 ++++++ 6 files changed, 137 insertions(+), 10 deletions(-) create mode 100644 doc/SPI/README.nr-flash diff --git a/doc/SPI/README.nr-flash b/doc/SPI/README.nr-flash new file mode 100644 index 0000000..65a5370 --- /dev/null +++ b/doc/SPI/README.nr-flash @@ -0,0 +1,65 @@ +SPI/QSPI No.of flash connection modes: +===================================== + +This describes how SPI/QSPI flash memories are connected to a given +controller in a single chip select line. + +Current spi_flash framework supports, single flash memory connected +to a given controller with single chip select line, but there are some +hw logics(ex: xilinx zynq qspi) that describes two/dual memories are +connected with a single chip select line from a controller. + +"nr_flash" from include/spi.h describes these types of connection mode + +Possible connections: +-------------------- +SF_NRF_SINGLE: + - single spi flash memory connected with single chip select line. + + +------------+ CS +---------------+ + | |----------------------->| | + | Controller | I0[3:0] | Flash memory | + | SPI/QSPI |<======================>| (SPI/QSPI) | + | | CLK | | + | |----------------------->| | + +------------+ +---------------+ + +SF_NRF_DUAL_STACKED: + - dual spi/qspi flash memories are connected with a single chipselect + line and these two memories are operating stacked fasion with shared buses. + - xilinx zynq qspi controller has implemented this feature [1] + + +------------+ CS +---------------+ + | |---------------------->| | + | | I0[3:0] | Upper Flash | + | | +=========>| memory | + | | | CLK | (SPI/QSPI) | + | | | +---->| | + | Controller | CS | | +---------------+ + | SPI/QSPI |------------|----|---->| | + | | I0[3:0] | | | Lower Flash | + | |<===========+====|====>| memory | + | | CLK | | (SPI/QSPI) | + | |-----------------+---->| | + +------------+ +---------------+ + + - two memory flash devices should has same hw part attributes (like size, + vendor..etc) + - Configurations: + on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG + Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory + Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory + - Operation: + accessing memories serially like one after another. + by default, if U_PAGE is unset lower memory should accessible, + once user wants to access upper memory need to set U_PAGE. + +Note: Technically there is only one CS line from the controller, but +zynq qspi controller has an internal hw logic to enable additional CS +when controller is configured for dual memories. + +[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM… + +-- +Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> +05-01-2014. diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c index d5e175c..c780a81 100644 --- a/drivers/mtd/spi/sf.c +++ b/drivers/mtd/spi/sf.c @@ -18,6 +18,9 @@ static int spi_flash_read_write(struct spi_slave *spi, unsigned long flags = SPI_XFER_BEGIN; int ret; + if (spi->flags & SPI_XFER_U_PAGE) + flags |= SPI_XFER_U_PAGE; + if (data_len == 0) flags |= SPI_XFER_END; diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 633a203..d96a69e 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -131,10 +131,28 @@ static int spi_flash_bank(struct spi_flash *flash, u32 offset) } #endif +static void spi_flash_nr_flash(struct spi_flash *flash, u32 *addr) +{ + switch (flash->nr_flash) { + case SF_NRF_DUAL_STACKED: + if (*addr >= (flash->size >> 1)) { + *addr -= flash->size >> 1; + flash->spi->flags |= SPI_XFER_U_PAGE; + } else { + flash->spi->flags &= ~SPI_XFER_U_PAGE; + } + break; + default: + debug("SF: Unsupported nr_flash=%d\n", flash->nr_flash); + break; + } +} + int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) { struct spi_slave *spi = flash->spi; unsigned long timebase; + unsigned long flags = SPI_XFER_BEGIN; int ret; u8 status; u8 check_status = 0x0; @@ -146,6 +164,9 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) check_status = poll_bit; } + if (spi->flags & SPI_XFER_U_PAGE) + flags |= SPI_XFER_U_PAGE; + ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN); if (ret) { debug("SF: fail to read %s status register\n", @@ -219,7 +240,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) { - u32 erase_size; + u32 erase_size, erase_addr; u8 cmd[SPI_FLASH_CMD_LEN]; int ret = -1; @@ -231,15 +252,20 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) cmd[0] = flash->erase_cmd; while (len) { + erase_addr = offset; + + if (flash->nr_flash > SF_NRF_SINGLE) + spi_flash_nr_flash(flash, &erase_addr); + #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_bank(flash, offset); + ret = spi_flash_bank(flash, erase_addr); if (ret < 0) return ret; #endif - spi_flash_addr(offset, cmd); + spi_flash_addr(erase_addr, cmd); debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], - cmd[2], cmd[3], offset); + cmd[2], cmd[3], erase_addr); ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); if (ret < 0) { @@ -258,6 +284,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { unsigned long byte_addr, page_size; + u32 write_addr; size_t chunk_len, actual; u8 cmd[SPI_FLASH_CMD_LEN]; int ret = -1; @@ -266,8 +293,13 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, cmd[0] = flash->write_cmd; for (actual = 0; actual < len; actual += chunk_len) { + write_addr = offset; + + if (flash->nr_flash > SF_NRF_SINGLE) + spi_flash_nr_flash(flash, &write_addr); + #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_bank(flash, offset); + ret = spi_flash_bank(flash, write_addr); if (ret < 0) return ret; #endif @@ -277,7 +309,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, if (flash->spi->max_write_size) chunk_len = min(chunk_len, flash->spi->max_write_size); - spi_flash_addr(offset, cmd); + spi_flash_addr(write_addr, cmd); debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -322,7 +354,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data) { u8 *cmd; - u32 remain_len, read_len; + u32 remain_len, read_len, read_addr; int bank_sel = 0; int ret = -1; @@ -345,8 +377,13 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, cmd[0] = flash->read_cmd; while (len) { + read_addr = offset; + + if (flash->nr_flash > SF_NRF_SINGLE) + spi_flash_nr_flash(flash, &read_addr); + #ifdef CONFIG_SPI_FLASH_BAR - bank_sel = spi_flash_bank(flash, offset); + bank_sel = spi_flash_bank(flash, read_addr); if (bank_sel < 0) return ret; #endif @@ -356,7 +393,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, else read_len = remain_len; - spi_flash_addr(offset, cmd); + spi_flash_addr(read_addr, cmd); ret = spi_flash_read_common(flash, cmd, sizeof(cmd), data, read_len); diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 98fc271..248050c 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -134,6 +134,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash->spi = spi; flash->name = params->name; flash->memory_map = spi->memory_map; + flash->nr_flash = flash->spi->option; /* Assign spi_flash ops */ flash->write = spi_flash_cmd_write_ops; @@ -148,6 +149,8 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256; flash->sector_size = params->sector_size; flash->size = flash->sector_size * params->nr_sectors; + if (flash->nr_flash & SF_NRF_DUAL_STACKED) + flash->size <<= 1; /* Compute erase sector and command */ if (params->flags & SECT_4K) { @@ -317,7 +320,10 @@ static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi) puts("\n"); #endif #ifndef CONFIG_SPI_FLASH_BAR - if (flash->size > SPI_FLASH_16MB_BOUN) { + if (((flash->nr_flash == SF_NRF_SINGLE) && + (flash->size > SPI_FLASH_16MB_BOUN)) || + ((flash->nr_flash != SF_NRF_SINGLE) && + (flash->size > SPI_FLASH_16MB_BOUN << 1))) { puts("SF: Warning - Only lower 16MiB accessible,"); puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); } diff --git a/include/spi.h b/include/spi.h index c8a9d87..d214d82 100644 --- a/include/spi.h +++ b/include/spi.h @@ -30,6 +30,7 @@ #define SPI_XFER_MMAP 0x08 /* Memory Mapped start */ #define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */ #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) +#define SPI_XFER_U_PAGE (1 << 5) /* SPI TX operation modes */ #define SPI_OPM_TX_QPP 1 << 0 @@ -44,6 +45,9 @@ SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \ SPI_OPM_RX_QIOF +/* SPI bus connection options */ +#define SPI_CONN_DUAL_SHARED 1 << 0 + /* Header byte that marks the start of the message */ #define SPI_PREAMBLE_END_BYTE 0xec @@ -62,6 +66,8 @@ * @max_write_size: If non-zero, the maximum number of bytes which can * be written at once, excluding command bytes. * @memory_map: Address of read-only SPI flash access. + * @option: Varies SPI bus options - separate bus. + * @flags: Indication of SPI flags. */ struct spi_slave { unsigned int bus; @@ -71,6 +77,8 @@ struct spi_slave { unsigned int wordlen; unsigned int max_write_size; void *memory_map; + u8 option; + u8 flags; }; /** diff --git a/include/spi_flash.h b/include/spi_flash.h index bdd4141..bb6eb0c 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -33,6 +33,12 @@ enum spi_read_cmds { #define RD_EXTN ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST #define RD_FULL RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST +/* No.of SPI flash memories */ +enum spi_nr_flash { + SF_NRF_SINGLE = 0, + SF_NRF_DUAL_STACKED = 1 << 0, +}; + /** * struct spi_flash_params - SPI/QSPI flash device params structure * @@ -61,6 +67,7 @@ extern const struct spi_flash_params spi_flash_params_table[]; * * @spi: SPI slave * @name: Name of SPI flash + * @nr_flash: Indicates no.of flash memories - dual stacked * @size: Total flash size * @page_size: Write (page) size * @sector_size: Sector size @@ -85,6 +92,7 @@ extern const struct spi_flash_params spi_flash_params_table[]; struct spi_flash { struct spi_slave *spi; const char *name; + u8 nr_flash; u32 size; u32 page_size; -- 1.8.3

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[U-Boot] [PATCH v2 1/4] sf: ops: Unify read_ops bank configuration
by Jagannadha Sutradharudu Teki 05 Jan '14

05 Jan '14

Unified the bar code from read_ops into a spi_flash_bar() Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- drivers/mtd/spi/sf_ops.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 7a499d5..633a203 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -127,7 +127,7 @@ static int spi_flash_bank(struct spi_flash *flash, u32 offset) return ret; } - return 0; + return bank_sel; } #endif @@ -321,8 +321,9 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data) { - u8 *cmd, bank_sel = 0; + u8 *cmd; u32 remain_len, read_len; + int bank_sel = 0; int ret = -1; /* Handle memory-mapped SPI */ @@ -345,13 +346,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, while (len) { #ifdef CONFIG_SPI_FLASH_BAR - bank_sel = offset / SPI_FLASH_16MB_BOUN; - - ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); - if (ret) { - debug("SF: fail to set bank%d\n", bank_sel); + bank_sel = spi_flash_bank(flash, offset); + if (bank_sel < 0) return ret; - } #endif remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset; if (len < remain_len) -- 1.8.3

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