January 2014 - U-Boot

[U-Boot] [PATCH][v2] board/freescale:Remove use of CONFIG_SPL_NAND_MINIMAL
by Prabhakar Kushwaha 03 Jan '14

03 Jan '14

CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary review purpose. So, use CONFIG_SPL_NAND_BOOT config. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Changes for v2: Incorporated Scott's comments - Add CONFIG_SPL_NAND_BOOT in README README | 3 +++ board/freescale/bsc9131rdb/tlb.c | 2 +- board/freescale/bsc9132qds/tlb.c | 2 +- board/freescale/p1010rdb/tlb.c | 2 +- include/configs/BSC9131RDB.h | 2 +- include/configs/BSC9132QDS.h | 2 +- include/configs/P1010RDB.h | 2 +- 7 files changed, 9 insertions(+), 6 deletions(-) diff --git a/README b/README index 265e81e..88a4722 100644 --- a/README +++ b/README @@ -3245,6 +3245,9 @@ FIT uImage format: Defines the size and behavior of the NAND that SPL uses to read U-Boot + CONFIG_SPL_NAND_BOOT + Add support NAND boot + CONFIG_SYS_NAND_U_BOOT_OFFS Location in NAND to read U-Boot from diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c index 669fe8a..c8ecf5d 100644 --- a/board/freescale/bsc9131rdb/tlb.c +++ b/board/freescale/bsc9131rdb/tlb.c @@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_MINIMAL +#ifdef CONFIG_SPL_NAND_BOOT SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_4K, 1), diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c index 02655e9..07febc2 100644 --- a/board/freescale/bsc9132qds/tlb.c +++ b/board/freescale/bsc9132qds/tlb.c @@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_MINIMAL +#ifdef CONFIG_SPL_NAND_BOOT SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_4K, 1), diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index a7af0f6..a3d36b3 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_MINIMAL +#ifdef CONFIG_SPL_NAND_BOOT SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_4K, 1), diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 499d8c2..783d996 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -29,7 +29,7 @@ #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_NAND_BOOT #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index a6601fe..f7cd955 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -38,7 +38,7 @@ #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_NAND_BOOT #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index eab386a..22538fc 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -37,7 +37,7 @@ #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_NAND_BOOT #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -- 1.7.9.5

3 2

[U-Boot] [PATCH] board/t1040qds: Relax IFC FPGA timings
by Prabhakar Kushwaha 03 Jan '14

03 Jan '14

Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion) is 0 i.e. 0 ns hold time on writes. This may not work on higher clock freqencies. So, Increase TCH as 0x8 i.e. 8 ip_clk. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- include/configs/T1040QDS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 74f4bde..521a0dc 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -247,7 +247,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 -- 1.7.9.5

2 1

[U-Boot] [PATCH] board/t1040qds: Fix typo in t1040_pbi.cfg file
by Prabhakar Kushwaha 03 Jan '14

03 Jan '14

T1040QDS has 256KB SRAM. Comment is showing wrong information. So update the comment. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- board/freescale/t1040qds/t1040_pbi.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg index 624398a..10b1a6d 100644 --- a/board/freescale/t1040qds/t1040_pbi.cfg +++ b/board/freescale/t1040qds/t1040_pbi.cfg @@ -3,7 +3,7 @@ 09010000 00200400 09138000 00000000 091380c0 00000100 -#Configure CPC1 as 512KB SRAM +#Configure CPC1 as 256KB SRAM 09010100 00000000 09010104 fffc0007 09010f00 08000000 -- 1.7.9.5

2 1

[U-Boot] [PATCH][v2] powerpc/t1040qds: Update DDR initialization related settings
by Priyanka Jain 02 Jan '14

02 Jan '14

Update following DDR related settings for T1040QDS -Correct number of chip selects to two as t1040qds supports two Chip selects. -Update board_specific_parameters udimm structure with settings derived via calibration. -Reduced I2C speed to 50KHz as DDR-SPD does not get reliably read at 400KHz. Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- Changes for v2: Reduced I2C speed to 50KHz. board/freescale/t1040qds/ddr.h | 22 ++++++++++++---------- include/configs/T1040QDS.h | 6 +++--- 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h index 8ee206e..afa72af 100644 --- a/board/freescale/t1040qds/ddr.h +++ b/board/freescale/t1040qds/ddr.h @@ -31,16 +31,18 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, - {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {2, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, + {2, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, + {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, + {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, + {1, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, + {1, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, + {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, + {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, {} }; diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 43a5778..484b237 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -167,7 +167,7 @@ unsigned long get_board_ddr_clk(void); /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR3 @@ -413,9 +413,9 @@ unsigned long get_board_ddr_clk(void); /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ -#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 -- 1.7.4.1

2 1

[U-Boot] [PATCH v3] t2080qds/ddr: update ddr parameters
by Shengzhou Liu 02 Jan '14

02 Jan '14

- Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s. - Remove unused patameters: 'cpo', 'wrdata delay', '2T', which are unrelated to DDR3/3L. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- Against master branch of git://git.denx.de/u-boot-mpc85xx.git v3: remain old RDIMM code without updating for now. v2: throw an error in case of RDIMM. board/freescale/t2080qds/ddr.c | 11 ++----- board/freescale/t2080qds/ddr.h | 65 +++++++++++++++++------------------------- 2 files changed, 28 insertions(+), 48 deletions(-) diff --git a/board/freescale/t2080qds/ddr.c b/board/freescale/t2080qds/ddr.c index 5db5d21..4a4d570 100644 --- a/board/freescale/t2080qds/ddr.c +++ b/board/freescale/t2080qds/ddr.c @@ -24,7 +24,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; - if (ctrl_num > 2) { + if (ctrl_num > 1) { printf("Not supported controller number %d\n", ctrl_num); return; } @@ -40,8 +40,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, else pbsp = udimms[0]; - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; @@ -49,9 +48,6 @@ void fsl_ddr_board_options(memctl_options_t *popts, if (pbsp->n_ranks == pdimm->n_ranks && (pdimm->rank_density >> 30) >= pbsp->rank_gb) { if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; @@ -69,13 +65,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, printf("for data rate %lu MT/s\n", ddr_freq); printf("Trying to use the highest speed (%u) parameters\n", pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } diff --git a/board/freescale/t2080qds/ddr.h b/board/freescale/t2080qds/ddr.h index 964eaad..5828596 100644 --- a/board/freescale/t2080qds/ddr.h +++ b/board/freescale/t2080qds/ddr.h @@ -14,9 +14,6 @@ struct board_specific_parameters { u32 wrlvl_start; u32 wrlvl_ctl_2; u32 wrlvl_ctl_3; - u32 cpo; - u32 write_data_delay; - u32 force_2t; }; /* @@ -28,58 +25,48 @@ struct board_specific_parameters { static const struct board_specific_parameters udimm0[] = { /* * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1800, 2, 5, 6, 0x06070709, 0x110a0b08, 0xff, 2, 0}, - {1, 1866, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0}, - {1, 1900, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0}, - {1, 2000, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0}, - {1, 2133, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0}, + {2, 1500, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, + {2, 1700, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, + {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {2, 2140, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b}, + {1, 1500, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, + {1, 1700, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, + {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {1, 2140, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {1, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b}, {} }; static const struct board_specific_parameters rdimm0[] = { /* * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, - {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, - {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, - {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + /* TODO: need tuning these parameters if RDIMM is used */ + {4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, + {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, + {2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, + {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, + {1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, + {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, {} }; -/* - * The three slots have slightly different timing. The center values are good - * for all slots. We use identical speed tables for them. In future use, if - * DIMMs require separated tables, make more entries as needed. - */ static const struct board_specific_parameters *udimms[] = { udimm0, }; -/* - * The three slots have slightly different timing. See comments above. - */ static const struct board_specific_parameters *rdimms[] = { rdimm0, }; - - #endif -- 1.8.0

2 1

[U-Boot] [PATCH v3 1/2] doc: README.fuse: Add an example on how to use the fuse API on mx6q
by Fabio Estevam 02 Jan '14

02 Jan '14

From: Fabio Estevam <fabio.estevam(a)freescale.com> When using the fuse API in U-boot user must calculate the 'bank' and 'word' values. Provide a real example on how to calculate such values for the mx6q. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v2: - Also mention that the bank/row values can be retrieved from the manual - Add the 'fuse read 4 2 2' example Changes since v1: - Move the example into doc/README.imx6 doc/README.imx6 | 76 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/doc/README.imx6 b/doc/README.imx6 index 513a06e..a6b9158 100644 --- a/doc/README.imx6 +++ b/doc/README.imx6 @@ -8,3 +8,79 @@ SoC. 1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the 16 msbs in word 3. + +Example: + +For reading the MAC address fuses on a MX6Q: + +- The MAC address is stored in two fuse addresses (the fuse addresses are +described in the Fusemap Descriptions table from the mx6q Reference Manual): + +0x620[31:0] - MAC_ADDR[31:0] +0x630[15:0] - MAC_ADDR[47:32] + +In order to use the fuse API, we need to pass the bank and word values, which +are calculated as below: + +Fuse address for the lower MAC address: 0x620 +Base address for the fuses: 0x400 + +(0x620 - 0x400)/0x10 = 0x22 = 34 decimal + +As the fuses are arranged in banks of 8 words: + +34 / 8 = 4 and the remainder is 2, so in this case: + +bank = 4 +word = 2 + +And the U-boot command would be: + +=> fuse read 4 2 +Reading bank 4: + +Word 0x00000002: 9f027772 + +Doing the same for the upper MAC address: + +Fuse address for the upper MAC address: 0x630 +Base address for the fuses: 0x400 + +(0x630 - 0x400)/0x10 = 0x23 = 35 decimal + +As the fuses are arranged in banks of 8 words: + +35 / 8 = 4 and the remainder is 3, so in this case: + +bank = 4 +word = 3 + +And the U-boot command would be: + +=> fuse read 4 3 +Reading bank 4: + +Word 0x00000003: 00000004 + +,which matches the ethaddr value: +=> echo ${ethaddr} +00:04:9f:02:77:72 + +Some other useful hints: + +- The 'bank' and 'word' numbers can be easily obtained from the mx6 Reference +Manual. For the mx6quad case, please check the "46.5 OCOTP Memory Map/Register +Definition" from the "i.MX 6Dual/6Quad Applications Processor Reference Manual, +Rev. 1, 04/2013" document. For example, for the MAC fuses we have: + +Address: +21B_C620 Value of OTP Bank4 Word2 (MAC Address)(OCOTP_MAC0) + +21B_C630 Value of OTP Bank4 Word3 (MAC Address)(OCOTP_MAC1) + +- The command '=> fuse read 4 2 2' reads the whole MAC addresses at once: + +=> fuse read 4 2 2 +Reading bank 4: + +Word 0x00000002: 9f027772 00000004 -- 1.8.1.2

3 4

[U-Boot] [PATCH V2 0/7] SMDK5420: Add support for FIMD and DP
by Ajay Kumar 02 Jan '14

02 Jan '14

This patchset adds support for FIMD and DP on SMDK5420. This patchset is rebased on Rajeshwari's latest SMDK5420 patchset: [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/172653 For testing we need: Naveen's i2c patchset: i2c: improve s3c24x0 with High-speed and new SYS_I2C framework support http://www.mail-archive.com/u-boot@lists.denx.de/msg122679.html Leela's PMIC patchset: [PATCH V3 0/6] SMDK5420: Add S2MPS11 pmic support to SMDK5420 http://www.mail-archive.com/u-boot@lists.denx.de/msg125733.html Changes since V1: [PATCH V2 4/7] - Read FIMD sysmmu addresses from DT instead of hardcoding them. [PATCH V2 5/7] - Remove hardcoded i2c setting for enabling VDD_28IO_DP [PATCH V2 6/7] - Enable VDD_28IO_DP in standard PMIC way Ajay Kumar (7): [PATCH V2 1/7] exynos_fb: Remove usage of static defines [PATCH V2 2/7] arm: exynos: Add RPLL for Exynos5420 [PATCH V2 3/7] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 [PATCH V2 4/7] video: exynos_fimd: Add framework to disable FIMD sysmmu [PATCH V2 5/7] smdk5420: Implement callbacks needed by exynos_fb driver [PATCH V2 6/7] exynos: s2mps11_pmic: Enable LDO38 for SMDK5420 [PATCH V2 7/7] CONFIG: SMDK5420: Enable FIMD and DP arch/arm/cpu/armv7/exynos/clock.c | 74 +++++++++++++++++- arch/arm/cpu/armv7/exynos/clock_init.h | 3 + arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 ++++ arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +- arch/arm/dts/exynos5420.dtsi | 7 ++ arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/system.h | 1 + board/samsung/common/board.c | 18 +++++ board/samsung/smdk5420/smdk5420.c | 102 +++++-------------------- doc/device-tree-bindings/video/exynos-fb.txt | 4 + drivers/video/exynos_fb.c | 20 ++--- drivers/video/exynos_fimd.c | 24 ++++++ include/configs/exynos5250-dt.h | 2 - include/configs/smdk5420.h | 8 ++ include/power/s2mps11_pmic.h | 3 + 15 files changed, 177 insertions(+), 105 deletions(-) -- 1.7.12.4

5 19

[U-Boot] [PATCH 0/4] Add support for TI TPS65090
by Simon Glass 02 Jan '14

02 Jan '14

This series adds support for the TPS65090 PMIC as used on the Samsung ARM Chromebook. It is plumbed into smdk5250 for now, while we await the exynos5-dt board being applied upstream. Aaron Durbin (3): exynos5: Enable tps65090 on smdk5250 power: Explicitly select pmic device's bus exynos5: support tps65090 pmic Tom Wai-Hong Tam (1): power: Add support for TPS65090 PMU chip. board/samsung/smdk5250/smdk5250.c | 33 +++- doc/device-tree-bindings/power/tps65090.txt | 21 ++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps65090.c | 296 ++++++++++++++++++++++++++++ drivers/power/power_i2c.c | 4 + include/configs/exynos5250-dt.h | 1 + include/fdtdec.h | 1 + include/power/tps65090_pmic.h | 83 ++++++++ lib/fdtdec.c | 1 + 9 files changed, 433 insertions(+), 8 deletions(-) create mode 100644 doc/device-tree-bindings/power/tps65090.txt create mode 100644 drivers/power/pmic/pmic_tps65090.c create mode 100644 include/power/tps65090_pmic.h -- 1.8.1.3

3 7

Re: [U-Boot] [PATCH V3 3/7] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
by Minkyu Kang 02 Jan '14

02 Jan '14

On 12/11/13 21:27, Ajay Kumar wrote: > Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by I think, they are not callback functions. > exynos video driver. > Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL. > > Signed-off-by: Ajay Kumar <ajaykumar.rs(a)samsung.com> > --- > arch/arm/cpu/armv7/exynos/clock.c | 74 +++++++++++++++++++++++++++++-- > arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +- > arch/arm/include/asm/arch-exynos/clk.h | 1 + > 3 files changed, 73 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c > index b52e61a..60ca7ea 100644 > --- a/arch/arm/cpu/armv7/exynos/clock.c > +++ b/arch/arm/cpu/armv7/exynos/clock.c > @@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) > * VPLL_CON: MIDV [24:16] > * BPLL_CON: MIDV [25:16]: Exynos5 > */ > - if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) > + if (pllreg == APLL || pllreg == MPLL || > + pllreg == BPLL || pllreg == SPLL) > mask = 0x3ff; > else > mask = 0x1ff; > @@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg) > r = readl(&clk->rpll_con0); > k = readl(&clk->rpll_con1); > break; > + case SPLL: > + r = readl(&clk->spll_con0); > + break; > default: > printf("Unsupported PLL (%d)\n", pllreg); > return 0; > @@ -1038,6 +1042,40 @@ static unsigned long exynos5_get_lcd_clk(void) > return pclk; > } > > +static unsigned long exynos5420_get_lcd_clk(void) > +{ > + struct exynos5420_clock *clk = > + (struct exynos5420_clock *)samsung_get_base_clock(); > + unsigned long pclk, sclk; > + unsigned int sel; > + unsigned int ratio; > + > + /* > + * CLK_SRC_DISP10 > + * FIMD1_SEL [4] > + * 0: SCLK_RPLL > + * 1: SCLK_SPLL > + */ > + sel = readl(&clk->src_disp10); > + sel &= (1 << 4); > + > + if (sel) > + sclk = get_pll_clk(SPLL); > + else > + sclk = get_pll_clk(RPLL); > + > + /* > + * CLK_DIV_DISP10 > + * FIMD1_RATIO [3:0] > + */ > + ratio = readl(&clk->div_disp10); > + ratio = ratio & 0xf; > + > + pclk = sclk / (ratio + 1); > + > + return pclk; > +} > + > void exynos4_set_lcd_clk(void) > { > struct exynos4_clock *clk = > @@ -1162,6 +1200,33 @@ void exynos5_set_lcd_clk(void) > writel(cfg, &clk->div_disp1_0); > } > > +void exynos5420_set_lcd_clk(void) > +{ > + struct exynos5420_clock *clk = > + (struct exynos5420_clock *)samsung_get_base_clock(); > + unsigned int cfg; > + > + /* > + * CLK_SRC_DISP10 > + * FIMD1_SEL [4] > + * 0: SCLK_RPLL > + * 1: SCLK_SPLL > + */ > + cfg = readl(&clk->src_disp10); > + cfg &= ~(0x1 << 4); > + cfg |= (0 << 4); > + writel(cfg, &clk->src_disp10); > + > + /* > + * CLK_DIV_DISP10 > + * FIMD1_RATIO [3:0] > + */ > + cfg = readl(&clk->div_disp10); > + cfg &= ~(0xf << 0); > + cfg |= (0 << 0); > + writel(cfg, &clk->div_disp10); > +} > + > void exynos4_set_mipi_clk(void) > { > struct exynos4_clock *clk = > @@ -1657,14 +1722,17 @@ unsigned long get_lcd_clk(void) > { > if (cpu_is_exynos4()) > return exynos4_get_lcd_clk(); > - else > - return exynos5_get_lcd_clk(); > + else if (proid_is_exynos5420()) please don't mix cpu_is... and proid_is.. please refer other functions. > + return exynos5420_get_lcd_clk(); > + return exynos5_get_lcd_clk(); > } > > void set_lcd_clk(void) > { > if (cpu_is_exynos4()) > exynos4_set_lcd_clk(); > + else if (proid_is_exynos5420()) > + exynos5420_set_lcd_clk(); ditto. > else > exynos5_set_lcd_clk(); > } > diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h > index 8e05a00..70b1c04 100644 > --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h > +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h > @@ -780,7 +780,7 @@ > #define CLK_SRC_TOP2_VAL 0x11101000 > #define CLK_SRC_TOP3_VAL 0x11111111 > #define CLK_SRC_TOP4_VAL 0x11110111 > -#define CLK_SRC_TOP5_VAL 0x11111100 > +#define CLK_SRC_TOP5_VAL 0x11111101 > #define CLK_SRC_TOP6_VAL 0x11110111 > #define CLK_SRC_TOP7_VAL 0x00022200 > > diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h > index cdeef32..98faae7 100644 > --- a/arch/arm/include/asm/arch-exynos/clk.h > +++ b/arch/arm/include/asm/arch-exynos/clk.h > @@ -15,6 +15,7 @@ > #define VPLL 4 > #define BPLL 5 > #define RPLL 6 > +#define SPLL 7 > > enum pll_src_bit { > EXYNOS_SRC_MPLL = 6, > Thanks, Minkyu Kang.

2 1

Re: [U-Boot] [PATCH V2 7/7] CONFIG: SMDK5420: Enable FIMD and DP
by Minkyu Kang 02 Jan '14

02 Jan '14

On 12/11/13 21:27, Ajay Kumar wrote: > Enable FIMD and DP drivers on SMDK5420 so that we get to > see the LCD console on eDP panel. > > Signed-off-by: Ajay Kumar <ajaykumar.rs(a)samsung.com> > --- > include/configs/smdk5420.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h > index 46aeec0..d3fa49b 100644 > --- a/include/configs/smdk5420.h > +++ b/include/configs/smdk5420.h > @@ -57,4 +57,12 @@ > #define CONFIG_POWER_I2C > #define CONFIG_POWER_S2MPS11 > > +/* Display */ > +#define CONFIG_LCD > +#ifdef CONFIG_LCD > +#define CONFIG_EXYNOS_FB > +#define CONFIG_EXYNOS_DP > +#define LCD_BPP LCD_COLOR16 please use space. > +#endif > + > #endif /* __CONFIG_5420_H */ > Thanks, Minkyu Kang.

2 1