January 2014 - U-Boot

[U-Boot] [PATCH] ARM: fdt support: Add usbethaddr as an acceptable MAC
by Dan Murphy 19 Jun '14

19 Jun '14

A board that has a USB ethernet device only may set the usbetheraddr and not the ethaddr. ethaddr will be the default MAC address that is chosen and if that is not populated then the usbethaddr is looked at. If neither are set then then device tree blob is not modified. Signed-off-by: Dan Murphy <dmurphy(a)ti.com> --- common/fdt_support.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index b034c98..fef7e60 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -450,8 +450,18 @@ void fdt_fixup_ethernet(void *fdt) if (node < 0) return; + if (!getenv("ethaddr")) { + if (getenv("usbethaddr")) { + strcpy(mac, "usbethaddr"); + } else { + debug("No ethernet MAC Address defined\n"); + return; + } + } else { + strcpy(mac, "ethaddr"); + } + i = 0; - strcpy(mac, "ethaddr"); while ((tmp = getenv(mac)) != NULL) { sprintf(enet, "ethernet%d", i); path = fdt_getprop(fdt, node, enet, NULL); -- 1.7.9.5

2 6

[U-Boot] [PATCH 1/3] net: sh-eth: Add support R7S72100 of rmobile
by Nobuhiro Iwamatsu 12 Jun '14

12 Jun '14

The R7S72100 of ARM SoC that Renesas manufactured has one Ether port. This has the same IP SH-Ether. This patch adds support of the R7S72100 in SH-Ether. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> --- drivers/net/sh_eth.c | 10 ++++--- drivers/net/sh_eth.h | 81 +++++++++++++++++++++++++++++++++++++++++++++------- 2 files changed, 77 insertions(+), 14 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 5e132f2..0cb963f 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -148,7 +148,7 @@ int sh_eth_recv(struct eth_device *dev) static int sh_eth_reset(struct sh_eth_dev *eth) { -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) int ret = 0, i; /* Start e-dmac transmitter and receiver */ @@ -218,7 +218,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) /* Point the controller to the tx descriptor list. Must use physical addresses */ sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR); sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */ @@ -288,7 +288,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) /* Point the controller to the rx descriptor list */ sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR); sh_eth_write(eth, RDFFR_RDLF, RDFFR); @@ -384,7 +384,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) sh_eth_write(eth, 0, TFTR); sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); sh_eth_write(eth, RMCR_RST, RMCR); -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) sh_eth_write(eth, 0, RPADIR); #endif sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); @@ -403,6 +403,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) sh_eth_write(eth, RFLR_RFL_MIN, RFLR); #if defined(SH_ETH_TYPE_GETHER) sh_eth_write(eth, 0, PIPR); +#endif +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) sh_eth_write(eth, APR_AP, APR); sh_eth_write(eth, MPR_MP, MPR); sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER); diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 331c07c..0925759 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -230,6 +230,61 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { [RMII_MII] = 0x0790, }; +#if defined(SH_ETH_TYPE_RZ) +static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = { + [EDSR] = 0x0000, + [EDMR] = 0x0400, + [EDTRR] = 0x0408, + [EDRRR] = 0x0410, + [EESR] = 0x0428, + [EESIPR] = 0x0430, + [TDLAR] = 0x0010, + [TDFAR] = 0x0014, + [TDFXR] = 0x0018, + [TDFFR] = 0x001c, + [RDLAR] = 0x0030, + [RDFAR] = 0x0034, + [RDFXR] = 0x0038, + [RDFFR] = 0x003c, + [TRSCER] = 0x0438, + [RMFCR] = 0x0440, + [TFTR] = 0x0448, + [FDR] = 0x0450, + [RMCR] = 0x0458, + [RPADIR] = 0x0460, + [FCFTR] = 0x0468, + [CSMR] = 0x04E4, + + [ECMR] = 0x0500, + [ECSR] = 0x0510, + [ECSIPR] = 0x0518, + [PSR] = 0x0528, + [PIPR] = 0x052c, + [RFLR] = 0x0508, + [APR] = 0x0554, + [MPR] = 0x0558, + [PFTCR] = 0x055c, + [PFRCR] = 0x0560, + [TPAUSER] = 0x0564, + [GECMR] = 0x05b0, + [BCULR] = 0x05b4, + [MAHR] = 0x05c0, + [MALR] = 0x05c8, + [TROCR] = 0x0700, + [CDCR] = 0x0708, + [LCCR] = 0x0710, + [CEFCR] = 0x0740, + [FRECR] = 0x0748, + [TSFRCR] = 0x0750, + [TLFRCR] = 0x0758, + [RFCR] = 0x0760, + [CERCR] = 0x0768, + [CEECR] = 0x0770, + [MAFCR] = 0x0778, + [RMII_MII] = 0x0790, +}; +#endif + static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { [ECMR] = 0x0100, [RFLR] = 0x0108, @@ -306,13 +361,16 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) #define SH_ETH_TYPE_ETHER #define BASE_IO_ADDR 0xEE700200 +#elif defined(CONFIG_R7S72100) +#define SH_ETH_TYPE_RZ +#define BASE_IO_ADDR 0xE8203000 #endif /* * Register's bits * Copy from Linux driver source code */ -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) /* EDSR */ enum EDSR_BIT { EDSR_ENT = 0x01, EDSR_ENR = 0x02, @@ -323,7 +381,7 @@ enum EDSR_BIT { /* EDMR */ enum DMAC_M_BIT { EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) EDMR_SRST = 0x03, /* Receive/Send reset */ EMDR_DESC_R = 0x30, /* Descriptor reserve size */ EDMR_EL = 0x40, /* Litte endian */ @@ -349,7 +407,7 @@ enum DMAC_M_BIT { /* EDTRR */ enum DMAC_T_BIT { -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) EDTRR_TRNS = 0x03, #else EDTRR_TRNS = 0x01, @@ -424,7 +482,7 @@ enum EESR_BIT { }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define TX_CHECK (EESR_TC1 | EESR_FTC) # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) @@ -484,7 +542,8 @@ enum FCFTR_BIT { /* Transfer descriptor bit */ enum TD_STS_BIT { -#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \ + defined(SH_ETH_TYPE_RZ) TD_TACT = 0x80000000, #else TD_TACT = 0x7fffffff, @@ -500,7 +559,7 @@ enum TD_STS_BIT { enum RECV_RST_BIT { RMCR_RST = 0x01, }; /* ECMR */ enum FELIC_MODE_BIT { -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, ECMR_RZPF = 0x00100000, #endif @@ -517,7 +576,7 @@ enum FELIC_MODE_BIT { }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ ECMR_TXF | ECMR_MCT) #elif defined(SH_ETH_TYPE_ETHER) @@ -535,7 +594,7 @@ enum ECSR_STATUS_BIT { ECSR_MPD = 0x02, ECSR_ICD = 0x01, }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) #else # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ @@ -556,7 +615,7 @@ enum ECSIPR_STATUS_MASK_BIT { ECSIPR_ICDIP = 0x01, }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) #else # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ @@ -587,7 +646,7 @@ enum RPADIR_BIT { RPADIR_PADR = 0x0003f, }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define RPADIR_INIT (0x00) #else # define RPADIR_INIT (RPADIR_PADS1) @@ -605,6 +664,8 @@ static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth, const u16 *reg_offset = sh_eth_offset_gigabit; #elif defined(SH_ETH_TYPE_ETHER) const u16 *reg_offset = sh_eth_offset_fast_sh4; +#elif defined(SH_ETH_TYPE_RZ) + const u16 *reg_offset = sh_eth_offset_rz; #else #error #endif -- 1.8.5

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[U-Boot] [PATCH] Separate EBV Socrates board from Altera Cyclone 5 board
by Pavel Machek 05 Jun '14

05 Jun '14

Altera Cyclone 5 board is very different board (big, rectangular, expensive) than EBV Socrates (small, circular, cheap) board. Different parts are used there, too, but same configuration of u-boot works on both. Nevertheless, printing wrong name confuses users. Therefore this splits the configuration so that u-boot knows they are different. So far it is only used for correcting the puts, but there may be other uses in future. Signed-off-by: Pavel Machek <pavel(a)denx.de> diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 576066b..4540b1b 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -26,7 +26,7 @@ int print_cpuinfo(void) */ int checkboard(void) { - puts("BOARD : Altera SOCFPGA Cyclone5 Board\n"); + puts("BOARD : " ALTERA_BOARD_NAME "\n"); return 0; } diff --git a/boards.cfg b/boards.cfg index 375f2d4..20534c3 100644 --- a/boards.cfg +++ b/boards.cfg @@ -340,6 +340,7 @@ Active arm armv7 rmobile kmc kzm9g Active arm armv7 s5pc1xx samsung goni s5p_goni - Minkyu Kang <mk7.kang(a)samsung.com> Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang(a)samsung.com> Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - +Active arm armv7 socfpga altera socfpga socfpga_socrates - - Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier(a)linaro.org> Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965(a)freescale.com> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h new file mode 100644 index 0000000..6d4dfcf --- /dev/null +++ b/include/configs/socfpga_common.h @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_COMMON_H +#define __CONFIG_COMMON_H + +#include <asm/arch/socfpga_base_addrs.h> +#include "../../board/altera/socfpga/pinmux_config.h" + +/* + * High level configuration + */ +/* Virtual target or real hardware */ +#define CONFIG_SOCFPGA_VIRTUAL_TARGET + +#define CONFIG_ARMV7 +#define CONFIG_L2_OFF +#define CONFIG_SYS_DCACHE_OFF +#undef CONFIG_USE_IRQ + +#define CONFIG_MISC_INIT_R +#define CONFIG_SINGLE_BOOTLOADER +#define CONFIG_SOCFPGA + +/* base address for .text section */ +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_SYS_TEXT_BASE 0x08000040 +#else +#define CONFIG_SYS_TEXT_BASE 0x01000040 +#endif +#define CONFIG_SYS_LOAD_ADDR 0x7fc0 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Display CPU and Board Info + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* + * Enable early stage initialization at C environment + */ +#define CONFIG_BOARD_EARLY_INIT_F + +/* flat device tree */ +#define CONFIG_OF_LIBFDT +/* skip updating the FDT blob */ +#define CONFIG_FDT_BLOB_SKIP_UPDATE +/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ +#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) + +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) +#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) + +/* + * Memory allocation (MALLOC) + */ +/* Room required on the stack for the environment data */ +#define CONFIG_ENV_SIZE 1024 +/* Size of DRAM reserved for malloc() use */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) + +/* SP location before relocation, must use scratch RAM */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +/* Reserving 0x100 space at back of scratch RAM for debug info */ +#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) +/* Stack pointer prior relocation, must situated at on-chip RAM */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + + +/* + * Command line configuration. + */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +/* FAT file system support */ +#define CONFIG_CMD_FAT + + +/* + * Misc + */ +#define CONFIG_DOS_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_PARTITIONS +#endif + +/* + * Environment setup + */ + +/* Delay before automatically booting the default image */ +#define CONFIG_BOOTDELAY 3 +/* Enable auto completion of commands using TAB */ +#define CONFIG_AUTO_COMPLETE +/* use "hush" command parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMD_RUN + +#define CONFIG_BOOTCOMMAND "run ramboot" + +/* + * arguments passed to the bootm command. The value of + * CONFIG_BOOTARGS goes into the environment value "bootargs". + * Do note the value will overide also the chosen node in FDT blob. + */ +#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=uImage\0" \ + "fdt_addr=100\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* using environment setting for stdin, stdout, stderr */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +/* Enable the call to overwrite_console() */ +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +/* Enable overwrite of previous console environment settings */ +#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + + +/* + * Hardware drivers + */ + +/* + * SDRAM Memory Map + */ +/* We have 1 bank of DRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +/* SDRAM Bank #1 */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +/* SDRAM memory size */ +#define PHYS_SDRAM_1_SIZE 0x40000000 + +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE + +/* + * NS16550 Configuration + */ +#define UART0_BASE SOCFPGA_UART0_ADDRESS +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 UART0_BASE +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define V_NS16550_CLK 1000000 +#else +#define V_NS16550_CLK 100000000 +#endif +#define CONFIG_BAUDRATE 115200 + +/* + * FLASH + */ +#define CONFIG_SYS_NO_FLASH + +/* + * L4 OSC1 Timer 0 + */ +/* This timer use eosc1 where the clock frequency is fixed + * throughout any condition */ +#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS +/* reload value when timer count to zero */ +#define TIMER_LOAD_VAL 0xFFFFFFFF +/* Timer info */ +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_SYS_TIMER_RATE 2400000 +#else +#define CONFIG_SYS_TIMER_RATE 25000000 +#endif +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) + +#define CONFIG_ENV_IS_NOWHERE + +/* + * SPL "Second Program Loader" aka Initial Software + */ + +/* Enable building of SPL globally */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK + +/* TEXT_BASE for linking the SPL binary */ +#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 + +/* Stack size for SPL */ +#define CONFIG_SPL_STACK_SIZE (4 * 1024) + +/* MALLOC size for SPL */ +#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) + +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT + +#define CHUNKSZ_CRC32 (1 * 1024) + +#define CONFIG_CRC32_VERIFY + +/* Linker script for SPL */ +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" + +/* Support for common/libcommon.o in SPL binary */ +#define CONFIG_SPL_LIBCOMMON_SUPPORT +/* Support for lib/libgeneric.o in SPL binary */ +#define CONFIG_SPL_LIBGENERIC_SUPPORT + +#endif /* __CONFIG_COMMON_H */ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 980636c..87de4d2 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -6,235 +6,12 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/socfpga_base_addrs.h> -#include "../../board/altera/socfpga/pinmux_config.h" +#include <configs/socfpga_common.h> -/* - * High level configuration - */ -/* Virtual target or real hardware */ -#define CONFIG_SOCFPGA_VIRTUAL_TARGET - -#define CONFIG_ARMV7 -#define CONFIG_L2_OFF -#define CONFIG_SYS_DCACHE_OFF -#undef CONFIG_USE_IRQ - -#define CONFIG_MISC_INIT_R -#define CONFIG_SINGLE_BOOTLOADER -#define CONFIG_SOCFPGA - -/* base address for .text section */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_TEXT_BASE 0x08000040 +#define ALTERA_BOARD_NAME "Altera VTDEV5XS1 Virtual Board" #else -#define CONFIG_SYS_TEXT_BASE 0x01000040 -#endif -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* - * Display CPU and Board Info - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -/* - * Enable early stage initialization at C environment - */ -#define CONFIG_BOARD_EARLY_INIT_F - -/* flat device tree */ -#define CONFIG_OF_LIBFDT -/* skip updating the FDT blob */ -#define CONFIG_FDT_BLOB_SKIP_UPDATE -/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ -#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) - -#define CONFIG_SPL_RAM_DEVICE -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) -#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) - -/* - * Memory allocation (MALLOC) - */ -/* Room required on the stack for the environment data */ -#define CONFIG_ENV_SIZE 1024 -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* SP location before relocation, must use scratch RAM */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -/* Reserving 0x100 space at back of scratch RAM for debug info */ -#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) -/* Stack pointer prior relocation, must situated at on-chip RAM */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - - -/* - * Command line configuration. - */ -#define CONFIG_SYS_NO_FLASH -#include <config_cmd_default.h> -/* FAT file system support */ -#define CONFIG_CMD_FAT - - -/* - * Misc - */ -#define CONFIG_DOS_PARTITION 1 - -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_PARTITIONS +#define ALTERA_BOARD_NAME "Altera SOCFPGA Cyclone 5 Board" #endif -/* - * Environment setup - */ - -/* Delay before automatically booting the default image */ -#define CONFIG_BOOTDELAY 3 -/* Enable auto completion of commands using TAB */ -#define CONFIG_AUTO_COMPLETE -/* use "hush" command parser */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_CMD_RUN - -#define CONFIG_BOOTCOMMAND "run ramboot" - -/* - * arguments passed to the bootm command. The value of - * CONFIG_BOOTARGS goes into the environment value "bootargs". - * Do note the value will overide also the chosen node in FDT blob. - */ -#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=uImage\0" \ - "fdt_addr=100\0" \ - "fsloadcmd=ext2load\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ - "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" - -/* using environment setting for stdin, stdout, stderr */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -/* Enable the call to overwrite_console() */ -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -/* Enable overwrite of previous console environment settings */ -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE - -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 - - -/* - * Hardware drivers - */ - -/* - * SDRAM Memory Map - */ -/* We have 1 bank of DRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -/* SDRAM Bank #1 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* SDRAM memory size */ -#define PHYS_SDRAM_1_SIZE 0x40000000 - -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - -/* - * NS16550 Configuration - */ -#define UART0_BASE SOCFPGA_UART0_ADDRESS -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 UART0_BASE -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define V_NS16550_CLK 1000000 -#else -#define V_NS16550_CLK 100000000 -#endif -#define CONFIG_BAUDRATE 115200 - -/* - * FLASH - */ -#define CONFIG_SYS_NO_FLASH - -/* - * L4 OSC1 Timer 0 - */ -/* This timer use eosc1 where the clock frequency is fixed - * throughout any condition */ -#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -/* reload value when timer count to zero */ -#define TIMER_LOAD_VAL 0xFFFFFFFF -/* Timer info */ -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_TIMER_RATE 2400000 -#else -#define CONFIG_SYS_TIMER_RATE 25000000 -#endif -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) - -#define CONFIG_ENV_IS_NOWHERE - -/* - * SPL "Second Program Loader" aka Initial Software - */ - -/* Enable building of SPL globally */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK - -/* TEXT_BASE for linking the SPL binary */ -#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 - -/* Stack size for SPL */ -#define CONFIG_SPL_STACK_SIZE (4 * 1024) - -/* MALLOC size for SPL */ -#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) - -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_BOARD_INIT - -#define CHUNKSZ_CRC32 (1 * 1024) - -#define CONFIG_CRC32_VERIFY - -/* Linker script for SPL */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" - -/* Support for common/libcommon.o in SPL binary */ -#define CONFIG_SPL_LIBCOMMON_SUPPORT -/* Support for lib/libgeneric.o in SPL binary */ -#define CONFIG_SPL_LIBGENERIC_SUPPORT - #endif /* __CONFIG_H */ diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h new file mode 100644 index 0000000..2f1c3a4 --- /dev/null +++ b/include/configs/socfpga_socrates.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/socfpga_common.h> + +#define ALTERA_BOARD_NAME "EBV SoCrates - Cyclone V SoC FPGA Board" + +#endif /* __CONFIG_H */ -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

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[U-Boot] [PATCH 0/9] ARMv7: add PSCI support to u-boot
by Marc Zyngier 04 Jun '14

04 Jun '14

PSCI is an ARM standard that provides a generic interface that supervisory software can use to manage power in the following situations: - Core idle management - CPU hotplug - big.LITTLE migration models - System shutdown and reset It basically allows the kernel to offload these tasks to the firmware, and rely on common kernel side code. More importantly, it gives a way to ensure that CPUs enter the kernel at the appropriate exception level (ie HYP mode, to allow the use of the virtualization extensions), even across events like CPUs being powered off/on or suspended. The main idea here is to reuse some of the existing u-boot code to create a separate blob that can live in SRAM (or a reserved page of memory), containing a secure monitor that will implement the PSCI operations. This code will still be alive when u-boot is long gone, hence the need for a piece of memory that will not be touched by the OS. This patch series contains 3 parts: - the first four patches are just bug fixes - the next three contain the generic PSCI code and build infrastructure - the last two implement the CPU_ON method of the Allwinner A20 (aka sun7i). I realize the A20 u-boot code is not upstream yet (BTW is anyone actively working on that?), but hopefully that should give a good idea of how things are structured so far. The patches are against a merge of u-boot mainline and the sunxi tree as of ten days ago. As for using this code, it goes like this: sun7i# ext2load mmc 0:1 0x40000000 /boot/sunxi-psci.bin 908 bytes read in 18 ms (48.8 KiB/s) sun7i# cp 0x40000000 0x4000 0x1000 sun7i# ext2load mmc 0:1 40008000 /boot/zImage 3415087 bytes read in 184 ms (17.7 MiB/s) sun7i# setenv bootargs console=ttyS0,115200 earlyprintk root=/dev/nfs nfsroot=10.1.203.35:/export/roots/bobby-brown,tcp,v3 rw ip=dhcp sun7i# bootz 40008000 The kernel now boots in HYP mode, finds its secondary CPU without any additional SMP code, and runs KVM out of the box. Hopefully, the Xen/ARM guys can do the same fairly easily. I'm wildly cross-posting this patch series, including to lists I'm not subscribed to. Please keep me on Cc for any comment you may have. Cheers, M. Marc Zyngier (9): ARM: HYP/non-sec: fix alignment requirements for vectors ARM: HYP/non-sec: move switch to non-sec to the last boot phase ARM: HYP/non-sec: add a barrier after setting SCR.NS==1 ARM: non-sec: reset CNTVOFF to zero ARM: HYP/non-sec: add generic ARMv7 PSCI code ARM: HYP/non-sec: make pen code sections depend on !ARMV7_PSCI ARM: HYP/non-sec: add the option for a second-stage monitor sunxi: HYP/non-sec: add sun7i PSCI backend sunxi: HYP/non-sec: configure CNTFRQ on all CPUs Makefile | 5 ++ arch/arm/cpu/armv7/Makefile | 4 ++ arch/arm/cpu/armv7/nonsec_virt.S | 21 +++++- arch/arm/cpu/armv7/psci.S | 109 ++++++++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/Makefile | 3 + arch/arm/cpu/armv7/sunxi/config.mk | 6 +- arch/arm/cpu/armv7/sunxi/psci.S | 119 +++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/u-boot-psci.lds | 63 ++++++++++++++++ arch/arm/cpu/armv7/virt-v7.c | 2 + arch/arm/lib/bootm.c | 5 +- include/configs/sun7i.h | 7 ++ psci/Makefile | 67 +++++++++++++++++ 12 files changed, 406 insertions(+), 5 deletions(-) create mode 100644 arch/arm/cpu/armv7/psci.S create mode 100644 arch/arm/cpu/armv7/sunxi/psci.S create mode 100644 arch/arm/cpu/armv7/sunxi/u-boot-psci.lds create mode 100644 psci/Makefile -- 1.8.2.3

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[U-Boot] [PATCH 1/3] tools: mxsboot: Staticize functions
by Marek Vasut 24 May '14

24 May '14

Make remaining non-static functions static and the same for vars. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> Cc: Stefano Babic <sbabic(a)denx.de> --- tools/mxsboot.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tools/mxsboot.c b/tools/mxsboot.c index 3d9cc10..1060cbf 100644 --- a/tools/mxsboot.c +++ b/tools/mxsboot.c @@ -28,14 +28,14 @@ * * TWEAK this if you have different kind of NAND chip. */ -uint32_t nand_writesize = 2048; -uint32_t nand_oobsize = 64; -uint32_t nand_erasesize = 128 * 1024; +static uint32_t nand_writesize = 2048; +static uint32_t nand_oobsize = 64; +static uint32_t nand_erasesize = 128 * 1024; /* * Sector on which the SigmaTel boot partition (0x53) starts. */ -uint32_t sd_sector = 2048; +static uint32_t sd_sector = 2048; /* * Each of the U-Boot bootstreams is at maximum 1MB big. @@ -434,7 +434,7 @@ static int mx28_nand_write_firmware(struct mx28_nand_fcb *fcb, int infd, return 0; } -void usage(void) +static void usage(void) { printf( "Usage: mxsboot [ops] <type> <infile> <outfile>\n" @@ -575,7 +575,7 @@ err0: return ret; } -int parse_ops(int argc, char **argv) +static int parse_ops(int argc, char **argv) { int i; int tmp; -- 1.7.10.4

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[U-Boot] [PATCH 1/9] mmc: mmc header fix
by Mateusz Zalega 16 May '14

16 May '14

Structure definition used type block_dev_desc_t, defined in part.h, which wasn't included in mmc.h. It worked only in circumstances when common.h, or another header using part.h was incuded in implementation files. Change-Id: I3ccf56ce1e5334c32a7bc061e8bd9a5054ccb7f5 Signed-off-by: Mateusz Zalega <m.zalega(a)samsung.com> Cc: Minkyu Kang <mk7.kang(a)samsung.com> Cc: Kyungmin Park <kyungmin.park(a)samsung.com> --- include/mmc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/mmc.h b/include/mmc.h index cb558da..e490a06 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -12,6 +12,7 @@ #include <linux/list.h> #include <linux/compiler.h> +#include <part.h> #define SD_VERSION_SD 0x20000 #define SD_VERSION_3 (SD_VERSION_SD | 0x300) -- 1.8.2.1

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[U-Boot] [PATCH 0/3] mpc83xx: add support for the ids8313 board
by Heiko Schocher 25 Apr '14

25 Apr '14

add support for the ids8313 board. CPU: e300c3, MPC8313, Rev: 2.1 at 396 MHz, CSB: 132 MHz I2C: ready SPI: ready DRAM: 128 MiB (DDR2, 32-bit, ECC off, 264 MHz) Flash: 8 MiB NAND: 128 MiB Net: TSEC0, TSEC1 [PRIME] This board uses signed fit images, signed with sha256,rsa4096 algorithm. Following patches are needed for this board support: [U-Boot] common, ubi: add ubi check volumename command http://patchwork.ozlabs.org/patch/314116/ [U-Boot] common, itest: pass u-boot env variables to itest.s http://patchwork.ozlabs.org/patch/314118/ [U-Boot] i2c, bootcount: add support for bootcounter on i2c devices http://patchwork.ozlabs.org/patch/314117/ Patchserie FIT Images Enhancements [U-Boot,1/7] tools/image-host: fix sign-images bug http://patchwork.ozlabs.org/patch/314125/ [U-Boot,2/7] fdt: add "fdt sign" command http://patchwork.ozlabs.org/patch/314120/ [U-Boot,3/7] fit: add sha256 support http://patchwork.ozlabs.org/patch/314126/ [U-Boot,4/7] rsa: add sha256-rsa2048 algorithm http://patchwork.ozlabs.org/patch/314124/ [U-Boot,5/7] rsa: add sha256,rsa4096 algorithm http://patchwork.ozlabs.org/patch/314121/ [U-Boot,6/7] tools, fit: add fit_info host command http://patchwork.ozlabs.org/patch/314122/ [U-Boot,7/7] tools, fit_check_sign: verify a signed fit image http://patchwork.ozlabs.org/patch/314123/ Heiko Schocher (3): powerpc, ids8247: create vendor board dir ids mpc8313, bootcount: mpc8313 has no qe muram mpc83xx: add ids8313 support arch/powerpc/cpu/mpc83xx/cpu.c | 2 +- arch/powerpc/cpu/mpc83xx/fdt.c | 5 +- board/{ => ids}/ids8247/Makefile | 0 board/{ => ids}/ids8247/ids8247.c | 0 board/ids/ids8313/Makefile | 11 + board/ids/ids8313/ids8313.c | 208 ++++++++++++++ boards.cfg | 3 +- include/configs/ids8313.h | 587 ++++++++++++++++++++++++++++++++++++++ 8 files changed, 812 insertions(+), 4 deletions(-) rename board/{ => ids}/ids8247/Makefile (100%) rename board/{ => ids}/ids8247/ids8247.c (100%) create mode 100644 board/ids/ids8313/Makefile create mode 100644 board/ids/ids8313/ids8313.c create mode 100644 include/configs/ids8313.h Cc: Wolfgang Denk <wd(a)denx.de> Cc: Kim Phillips <kim.phillips(a)freescale.com> -- 1.8.3.1

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[U-Boot] [PATCH] fsl/usb: Fix phy type for Second USB controller
by Nikhil Badola 24 Apr '14

24 Apr '14

Set correct phy_type value for second USB controller. This is required for supporting SOCs having 2 USB controllers working simultaneously, one with UTMI phy and other with ULPI phy Signed-off-by: Nikhil Badola <B46172(a)freescale.com> --- drivers/usb/host/ehci-fsl.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 45e5d6a..0d19daa 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -41,11 +41,14 @@ int ehci_hcd_init(int index, enum usb_init_type init, struct usb_ehci *ehci = NULL; const char *phy_type = NULL; size_t len; + char current_usb_controller[5]; #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY char usb_phy[5]; usb_phy[0] = '\0'; #endif + memset(current_usb_controller, '\0', 5); + snprintf(current_usb_controller, 4, "usb%d", index+1); switch (index) { case 0: @@ -70,8 +73,9 @@ int ehci_hcd_init(int index, enum usb_init_type init, out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); /* Init phy */ - if (hwconfig_sub("usb1", "phy_type")) - phy_type = hwconfig_subarg("usb1", "phy_type", &len); + if (hwconfig_sub(current_usb_controller, "phy_type")) + phy_type = hwconfig_subarg(current_usb_controller, + "phy_type", &len); else phy_type = getenv("usb_phy_type"); -- 1.7.11.7

2 1

[U-Boot] [PATCH 2/3] powerpc/p1010rdb: SECURE BOOT- enable workaround for IFC errata A003399
by Aneesh Bansal 24 Apr '14

24 Apr '14

The workaround for IFC errata A003399 was not enabled in case of secure boot. So, secure boot from NOR was not working. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- include/configs/P1010RDB.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index c21cf07..b0e51fb 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -455,8 +455,7 @@ extern unsigned long get_sdram_size(void); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 -#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\ - && !defined(CONFIG_SECURE_BOOT) +#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_A003399_NOR_WORKAROUND #endif #endif -- 1.8.1.4

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[U-Boot] [PATCH v2 1/8] SPL: Add CONFIG_SUPPORT_EMMC_BOOT support to CONFIG_SPL_FRAMEWORK
by Tom Rini 22 Apr '14

22 Apr '14

We use the switch CONFIG_SUPPORT_EMMC_BOOT today to enable some additional features of the eMMC boot partitions. Add support for being told that we have booted from one of these partitions to the spl framework and implement this on TI OMAP/related. Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> Signed-off-by: Tom Rini <trini(a)ti.com> --- arch/arm/cpu/armv7/omap-common/boot-common.c | 8 +++++++- common/spl/spl_mmc.c | 24 ++++++++++++++++++++++++ include/spl.h | 1 + 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 69fff32..ec0f936 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -66,7 +66,13 @@ u32 spl_boot_device(void) u32 spl_boot_mode(void) { - return gd->arch.omap_boot_params.omap_bootmode; + u32 val = gd->arch.omap_boot_params.omap_bootmode; + +#ifdef CONFIG_SUPPORT_EMMC_BOOT + if (val == 0) + val = MMCSD_MODE_EMMCBOOT; +#endif + return val; } void spl_board_init(void) diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 13fbff0..fa6f891 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -111,6 +111,30 @@ void spl_mmc_load_image(void) CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION, CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME); #endif +#ifdef CONFIG_SUPPORT_EMMC_BOOT + } else if (boot_mode == MMCSD_MODE_EMMCBOOT) { + /* + * We need to check what the partition is configured to. + * 1 and 2 match up to boot0 / boot1 and 7 is user data + * which is the first physical partition (0). + */ + int part = (mmc->part_config >> 3) & PART_ACCESS_MASK; + + if (part == 7) + part = 0; + + if (mmc_switch_part(0, part)) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + puts("MMC partition switch failed\n"); +#endif + hang(); + } +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || mmc_load_image_raw_os(mmc)) +#endif + err = mmc_load_image_raw(mmc, + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); +#endif } else { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT puts("spl: wrong MMC boot mode\n"); diff --git a/include/spl.h b/include/spl.h index 5e24856..dad00c0 100644 --- a/include/spl.h +++ b/include/spl.h @@ -16,6 +16,7 @@ #define MMCSD_MODE_UNDEFINED 0 #define MMCSD_MODE_RAW 1 #define MMCSD_MODE_FAT 2 +#define MMCSD_MODE_EMMCBOOT 3 struct spl_image_info { const char *name; -- 1.7.9.5

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