January 2014 - U-Boot

[U-Boot] Please pull u-boot-ti/master
by Tom Rini 29 Jan '14

29 Jan '14

Hey, The following changes since commit c71b4dd2da0dcddabd7c29e6c3dc8a495d4bd928: arm: koelsch: Add support QSPI device and enable boot from SPI flash (2014-01-16 08:07:20 +0900) are available in the git repository at: git://git.denx.de/u-boot-ti master for you to fetch changes up to b1cde7e21f950e05d18c102976c3b7d232b65e13: am43xx_evm.h: Correct SPL max size (2014-01-24 11:41:17 -0500) ---------------------------------------------------------------- Enric Balletbò i Serra (7): ARM: OMAP4: Rename to ti_omap4_common.h ARM: OMAP5: Rename to ti_omap5_common.h TI: armv7: Move ELM support to SoC configuration file. TI: armv7: Do not define the number DRAM banks if is already defined. ARM: OMAP3: Rename OMAP3_PUBLIC_SRAM_* to NON_SECURE_SRAM_* TI: OMAP3: Create common config files for TI OMAP3 platforms. OMAP3: igep00x0: Convert to ti_omap3_common.h. Jassi Brar (2): ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL ARM: OMAP4/5: Remove dead code against CONFIG_SYS_ENABLE_PADS_ALL Lokesh Vutla (1): ARM: AM43xx: Enable DDR dynamic IO power down for DDR3 Nishanth Menon (2): DRA7: Add support for ES1.1 silicon ID code DRA7: add ABB setup for MPU voltage domain Satyanarayana, Sandhya (1): ARM: AM335x: Enable DDR dynamic IO power down Tom Rini (2): feature-removal-schedule.txt: Drop CONFIG_SYS_ENABLE_PADS_ALL/CLOCKS_ENABLE_ALL am43xx_evm.h: Correct SPL max size arch/arm/cpu/armv7/omap-common/clocks-common.c | 53 ----- arch/arm/cpu/armv7/omap-common/emif-common.c | 5 +- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 6 - arch/arm/cpu/armv7/omap4/hw_data.c | 85 ------- arch/arm/cpu/armv7/omap5/abb.c | 13 +- arch/arm/cpu/armv7/omap5/hw_data.c | 90 +------- arch/arm/cpu/armv7/omap5/hwinit.c | 3 + arch/arm/cpu/armv7/omap5/prcm-regs.c | 8 + arch/arm/cpu/armv7/omap5/sdram.c | 4 + arch/arm/include/asm/arch-am33xx/ddr_defs.h | 8 +- arch/arm/include/asm/arch-omap3/omap3.h | 6 +- arch/arm/include/asm/arch-omap4/sys_proto.h | 1 - arch/arm/include/asm/arch-omap5/omap.h | 3 + arch/arm/include/asm/arch-omap5/sys_proto.h | 1 - arch/arm/include/asm/omap_common.h | 2 +- board/ti/am43xx/board.c | 2 +- board/ti/omap5_uevm/evm.c | 13 -- board/ti/omap5_uevm/mux_data.h | 234 -------------------- board/ti/panda/panda.c | 30 --- board/ti/panda/panda_mux_data.h | 186 ---------------- board/ti/sdp4430/sdp.c | 20 -- board/ti/sdp4430/sdp4430_mux_data.h | 197 ---------------- doc/feature-removal-schedule.txt | 16 -- include/configs/am43xx_evm.h | 2 +- include/configs/dra7xx_evm.h | 4 +- include/configs/omap3_igep00x0.h | 189 +--------------- include/configs/omap4_panda.h | 4 +- include/configs/omap4_sdp4430.h | 4 +- include/configs/omap5_uevm.h | 4 +- include/configs/ti_am335x_common.h | 4 + include/configs/ti_armv7_common.h | 11 +- include/configs/ti_omap3_common.h | 73 ++++++ .../configs/{omap4_common.h => ti_omap4_common.h} | 10 +- .../configs/{omap5_common.h => ti_omap5_common.h} | 10 +- 34 files changed, 157 insertions(+), 1144 deletions(-) create mode 100644 include/configs/ti_omap3_common.h rename include/configs/{omap4_common.h => ti_omap4_common.h} (95%) rename include/configs/{omap5_common.h => ti_omap5_common.h} (95%) Thanks! -- Tom

2 2

[U-Boot] Pull request: u-boot-nds32
by uboot＠andestech.com 29 Jan '14

29 Jan '14

Hi Tom, Please pull the following patch from u-boot-nds32 into your tree. Thanks! The following changes since commit 0876703cf2ee107372b56037d4eeeb7604c56796: boards.cfg: Keep the entries sorted (2014-01-27 08:28:35 -0500) are available in the git repository at: git://git.denx.de/u-boot-nds32.git master for you to fetch changes up to f889cc81c1572f4af0be950fd49bb6b67bc580fb: nds32: add support for leopard and orca board boot flow auto detect (2014-01-28 19:23:01 +0800) ---------------------------------------------------------------- rick (1): nds32: add support for leopard and orca board boot flow auto detect arch/nds32/cpu/n1213/ag101/asm-offsets.c | 1 + arch/nds32/cpu/n1213/ag101/lowlevel_init.S | 88 ++++++++++++++++++++++++++- 2 files changed, 85 insertions(+), 4 deletions(-)

2 1

[U-Boot] [uBoot 1/2] common: spl: Add spl sata boot support
by Dan Murphy 29 Jan '14

29 Jan '14

Add spl_sata to read a fat partition from a bootable SATA drive. Signed-off-by: Dan Murphy <dmurphy(a)ti.com> --- common/Makefile | 3 +++ common/cmd_scsi.c | 2 ++ common/spl/Makefile | 1 + common/spl/spl.c | 5 +++++ common/spl/spl_sata.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++ include/spl.h | 3 +++ spl/Makefile | 1 + 7 files changed, 66 insertions(+) create mode 100644 common/spl/spl_sata.c diff --git a/common/Makefile b/common/Makefile index 4d99ecd..b0f5b62 100644 --- a/common/Makefile +++ b/common/Makefile @@ -201,6 +201,9 @@ ifdef CONFIG_SPL_USB_HOST_SUPPORT obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o obj-$(CONFIG_USB_STORAGE) += usb_storage.o endif +ifdef CONFIG_SPL_SATA_SUPPORT +obj-$(CONFIG_CMD_SCSI) += cmd_scsi.o +endif ifneq ($(CONFIG_SPL_NET_SUPPORT),y) obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index 7b97dc9..b3f7687 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -168,7 +168,9 @@ removable: scsi_curr_dev = -1; printf("Found %d device(s).\n", scsi_max_devs); +#ifndef CONFIG_SPL_BUILD setenv_ulong("scsidevs", scsi_max_devs); +#endif } int scsi_get_disk_count(void) diff --git a/common/spl/Makefile b/common/spl/Makefile index 65a1484f..64569c2 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -18,4 +18,5 @@ obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o +obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o endif diff --git a/common/spl/spl.c b/common/spl/spl.c index 0645cee..774fdad 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -210,6 +210,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2) spl_usb_load_image(); break; #endif +#ifdef CONFIG_SPL_SATA_SUPPORT + case BOOT_DEVICE_SATA: + spl_sata_load_image(); + break; +#endif default: debug("SPL: Un-supported Boot Device\n"); hang(); diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c new file mode 100644 index 0000000..88d6b06 --- /dev/null +++ b/common/spl/spl_sata.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2013 + * Texas Instruments, <www.ti.com> + * + * Dan Murphy <dmurphy(a)ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Derived work from spl_usb.c + */ + +#include <common.h> +#include <spl.h> +#include <asm/u-boot.h> +#include <sata.h> +#include <fat.h> +#include <version.h> +#include <image.h> + +DECLARE_GLOBAL_DATA_PTR; + +void spl_sata_load_image(void) +{ + int err; + block_dev_desc_t *stor_dev; + + err = init_sata(CONFIG_SPL_SATA_BOOT_DEVICE); + if (err) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("spl: sata init failed: err - %d\n", err); +#endif + hang(); + } else { + /* try to recognize storage devices immediately */ + stor_dev = scsi_get_dev(0); + } + + debug("boot mode - FAT\n"); + +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || spl_load_image_fat_os(stor_dev, + CONFIG_SYS_SATA_FAT_BOOT_PARTITION)) +#endif + err = spl_load_image_fat(stor_dev, + CONFIG_SYS_SATA_FAT_BOOT_PARTITION, + CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME); + if (err) { + puts("Error loading sata device\n"); + hang(); + } +} diff --git a/include/spl.h b/include/spl.h index 5e24856..ee09fb6 100644 --- a/include/spl.h +++ b/include/spl.h @@ -64,6 +64,9 @@ void spl_net_load_image(const char *device); /* USB SPL functions */ void spl_usb_load_image(void); +/* SATA SPL functions */ +void spl_sata_load_image(void); + /* SPL FAT image functions */ int spl_load_image_fat(block_dev_desc_t *block_dev, int partition, const char *filename); int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition); diff --git a/spl/Makefile b/spl/Makefile index 4143e38..28fcfdd 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -85,6 +85,7 @@ LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/ LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/ LIBS-$(CONFIG_SPL_USB_HOST_SUPPORT) += drivers/usb/host/ LIBS-$(CONFIG_OMAP_USB_PHY) += drivers/usb/phy/ +LIBS-$(CONFIG_SPL_SATA_SUPPORT) += drivers/block/ ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) LIBS-y += arch/$(ARCH)/imx-common/ -- 1.7.9.5

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[U-Boot] [PATCH] initial support for pengwyn board
by Lothar Felten 29 Jan '14

29 Jan '14

Signed-off-by: Lothar Felten <lothar.felten(a)gmail.com> --- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 16 ++ board/silica/pengwyn/Makefile | 13 ++ board/silica/pengwyn/board.c | 216 +++++++++++++++++++++ board/silica/pengwyn/board.h | 15 ++ board/silica/pengwyn/mux.c | 107 +++++++++++ boards.cfg | 1 + include/configs/pengwyn.h | 274 +++++++++++++++++++++++++++ 7 files changed, 642 insertions(+) create mode 100644 board/silica/pengwyn/Makefile create mode 100644 board/silica/pengwyn/board.c create mode 100644 board/silica/pengwyn/board.h create mode 100644 board/silica/pengwyn/mux.c create mode 100644 include/configs/pengwyn.h diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index c1777df..60cb098 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -58,6 +58,22 @@ #define MT41J128MJT125_PHY_FIFO_WE 0x100 #define MT41J128MJT125_IOCTRL_VALUE 0x18B +/* Micron MT41K128M16JT-187E */ +#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06 +#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB +#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA +#define MT41K128MJT187E_EMIF_TIM3 0x501F830F +#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2 +#define MT41K128MJT187E_EMIF_SDREF 0x0000093B +#define MT41K128MJT187E_ZQ_CFG 0x50074BE4 +#define MT41K128MJT187E_RATIO 0x40 +#define MT41K128MJT187E_INVERT_CLKOUT 0x1 +#define MT41K128MJT187E_RD_DQS 0x3B +#define MT41K128MJT187E_WR_DQS 0x85 +#define MT41K128MJT187E_PHY_WR_DATA 0xC1 +#define MT41K128MJT187E_PHY_FIFO_WE 0x100 +#define MT41K128MJT187E_IOCTRL_VALUE 0x18B + /* Micron MT41J64M16JT-125 */ #define MT41J64MJT125_EMIF_SDCFG 0x61C04A32 diff --git a/board/silica/pengwyn/Makefile b/board/silica/pengwyn/Makefile new file mode 100644 index 0000000..c8b4f9a --- /dev/null +++ b/board/silica/pengwyn/Makefile @@ -0,0 +1,13 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c new file mode 100644 index 0000000..d5dbd3b --- /dev/null +++ b/board/silica/pengwyn/board.c @@ -0,0 +1,216 @@ +/* + * board.c + * + * Copyright (C) 2013 Lothar Felten <lothar.felten(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> +#include <phy.h> +#include <cpsw.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) + +/* DDR3 RAM timings */ +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K128MJT187E_RD_DQS, + .datawdsratio0 = MT41K128MJT187E_WR_DQS, + .datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE, + .datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K128MJT187E_RATIO, + .cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT, + .cmd1csratio = MT41K128MJT187E_RATIO, + .cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT, + .cmd2csratio = MT41K128MJT187E_RATIO, + .cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K128MJT187E_EMIF_SDCFG, + .ref_ctrl = MT41K128MJT187E_EMIF_SDREF, + .sdram_tim1 = MT41K128MJT187E_EMIF_TIM1, + .sdram_tim2 = MT41K128MJT187E_EMIF_TIM2, + .sdram_tim3 = MT41K128MJT187E_EMIF_TIM3, + .zq_config = MT41K128MJT187E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, +}; + +const struct ctrl_ioregs ddr3_ioregs = { + .cm0ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .cm1ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .cm2ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .dt0ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .dt1ioctl = MT41K128MJT187E_IOCTRL_VALUE, +}; + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr_266 = { + 266, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_303 = { + 303, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_400 = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + /* the pengwyn board uses the TPS650250 PMIC without I2C */ + /* interface and will output the following fixed voltages: */ + /* DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu) */ + /* VLDO1=1V8 (IO) VLDO2=1V8(IO) */ + /* Vcore=1V1 is fixed, generated by TPS62231 */ + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* 720MHz cpu, this might change on newer board revisions */ + dpll_mpu_opp100.m = MPUPLL_M_720; + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + /* future configs can return other clock settings */ + return &dpll_ddr_303; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +void sdram_init(void) +{ + config_ddr(303, &ddr3_ioregs, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); +} +#endif /* if CONFIG_SPL_BUILD */ + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + return 0; +} + +#ifdef CONFIG_DRIVER_TI_CPSW +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_MII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + .phy_if = PHY_INTERFACE_MODE_MII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif + +#if defined(CONFIG_DRIVER_TI_CPSW) +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; +#ifdef CONFIG_DRIVER_TI_CPSW + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + printf("<ethaddr> not set. Reading from E-fuse\n"); + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + else + return n; + } + + writel(MII_MODE_ENABLE, &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +#endif + return n; +} +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + return 0; +} +#endif diff --git a/board/silica/pengwyn/board.h b/board/silica/pengwyn/board.h new file mode 100644 index 0000000..05addf6 --- /dev/null +++ b/board/silica/pengwyn/board.h @@ -0,0 +1,15 @@ +/* + * board.h + * + * Copyright (C) 2013 Lothar Felten <lothar.felten(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_board_pin_mux(void); + +#endif diff --git a/board/silica/pengwyn/mux.c b/board/silica/pengwyn/mux.c new file mode 100644 index 0000000..16e8b42 --- /dev/null +++ b/board/silica/pengwyn/mux.c @@ -0,0 +1,107 @@ +/* + * mux.c + * + * Copyright (C) 2013 Lothar Felten <lothar.felten(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include "board.h" + +/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */ +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */ + +/* I2C pins C16(scl)/C17(sda) */ +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */ + {-1}, +}; + +/* MMC0 pins */ +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; + +/* SPI0 pins A17(sclk),B17(d0),B16(d1),A16(cs0) [C15(cs1)] */ +static struct module_pin_mux spi0_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */ + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | + PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */ + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */ + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | + PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */ + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_board_pin_mux() +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(uart0_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(nand_pin_mux); +} diff --git a/boards.cfg b/boards.cfg index 2dfd2b4..808bfa9 100644 --- a/boards.cfg +++ b/boards.cfg @@ -255,6 +255,7 @@ Active arm armv7 am33xx phytec pcm051 Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier(a)siemens.com> Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier(a)siemens.com> Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier(a)siemens.com> +Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten <lothar.felten(a)gmail.com> Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini <trini(a)ti.com> Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini <trini(a)ti.com> Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini <trini(a)ti.com> diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h new file mode 100644 index 0000000..7a41151 --- /dev/null +++ b/include/configs/pengwyn.h @@ -0,0 +1,274 @@ +/* + * pengwyn.h + * + * Copyright (C) 2013 Lothar Felten <lothar.felten(a)gmail.com> + * + * based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_PENGWYN_H +#define __CONFIG_PENGWYN_H + +#define CONFIG_NAND +#define CONFIG_SERIAL1 +#define CONFIG_CONS_INDEX 1 + +#include <configs/ti_am335x_common.h> + +/* Clock Defines */ +#define V_OSCK 24000000 +#define V_SCLK (V_OSCK) + +/* set env size */ +#define CONFIG_ENV_SIZE (0x4000) + +#ifdef CONFIG_NAND +#define NANDARGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandsrcaddr=0x280000\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \ + "bootz ${loadaddr}\0" \ + "nandimgsize=0x500000\0" +#else +#define NANDARGS "" +#endif + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "fdtaddr=0x80F80000\0" \ + "fdt_high=0xffffffff\0" \ + "boot_fdt=try\0" \ + "rdaddr=0x81000000\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "fdtfile=undefined\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "rootpath=/export/rootfs\0" \ + "nfsopts=nolock\0" \ + "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ + "::off\0" \ + "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ + "ramrootfstype=ext2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "spiroot=/dev/mtdblock4 rw\0" \ + "spirootfstype=jffs2\0" \ + "spisrcaddr=0xe0000\0" \ + "spiimgsize=0x362000\0" \ + "spibusno=0\0" \ + "spiargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${spiroot} " \ + "rootfstype=${spirootfstype}\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcloados=run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run mmcloados;" \ + "fi;" \ + "fi;\0" \ + "spiboot=echo Booting from spi ...; " \ + "run spiargs; " \ + "sf probe ${spibusno}:0; " \ + "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \ + "bootz ${loadaddr}\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "tftp ${fdtaddr} ${fdtfile}; " \ + "run netargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "ramboot=echo Booting from ramdisk ...; " \ + "run ramargs; " \ + "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ + "findfdt="\ + "if test $board_name = A335BONE; then " \ + "setenv fdtfile am335x-bone.dtb; fi; " \ + "if test $board_name = A335BNLT; then " \ + "setenv fdtfile am335x-boneblack.dtb; fi; " \ + "if test $board_name = A33515BB; then " \ + "setenv fdtfile am335x-evm.dtb; fi; " \ + "if test $board_name = A335X_SK; then " \ + "setenv fdtfile am335x-evmsk.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: no device tree found; fi; \0" \ + NANDARGS +#endif + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run mmcboot;" \ + "setenv mmcdev 1; " \ + "setenv bootpart 1:2; " \ + "run mmcboot;" \ + "run nandboot;" + +/* NS16550 Configuration: primary UART via FDTI */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 +#define CONFIG_BAUDRATE 115200 + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + +/* SPL */ +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT + + + +/* General network SPL, both CPSW and USB gadget RNDIS */ +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" + +/* NAND support */ +#ifdef CONFIG_NAND +#define CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +#define GPMC_NAND_ECC_LP_x8_LAYOUT 1 +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ + "128k(SPL.backup1)," \ + "128k(SPL.backup2)," \ + "128k(SPL.backup3),1792k(u-boot)," \ + "128k(u-boot-spl-os)," \ + "128k(u-boot-env),5m(kernel),-(rootfs)" +#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#else +#define CONFIG_ENV_IS_NOWHERE +#endif /* NAND */ + + +/* + * USB configuration. We enable MUSB support, both for host and for + * gadget. We set USB0 as peripheral and USB1 as host, based on the + * board schematic and physical port wired to each. Then for host we + * add mass storage support. + */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_GADGET +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_MUSB_HOST +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +#ifdef CONFIG_MUSB_HOST +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) +/* disable host part of MUSB in SPL */ +#undef CONFIG_MUSB_HOST +/* Disable CPSW SPL support so we fit within the 101KiB limit. */ +#undef CONFIG_SPL_ETH_SUPPORT +#endif + +/* Network */ +#define CONFIG_CMD_MII +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY_RESET 1 +#define CONFIG_PHY_NATSEMI + +/* CPSW support */ +#define CONFIG_SPL_ETH_SUPPORT + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#endif /* ! __CONFIG_PENGWYN_H */ + -- 1.7.9.5

2 1

[U-Boot] [PATCH v7 0/38] Switch over to real Kbuild
by Masahiro Yamada 29 Jan '14

29 Jan '14

We switched to Kbuild style makefiles at v2014.01-rc1 release. With that modification, we can write makefiles simpler. But it is NOT real Kbuild. We need more progress. As the next step, this series imports (+ adjusts) build scripts from Linux Kernel under scripts/ directory. By applying this series, we can get more advantages: - short log - perfect dependency tracking - preparation to the next step, Kconfig - other things... Kbuild without Kconfig ---------------------- First of all, to make things clearer, let me explain the difference between "Kbuild" and "Kconfig". They are, I think, sometimes confusing. Kbuild - build system used for Linux Kernel. Some features of Kbuild are: (a) We can describe makefiles simply. Just add objects to "obj-y" like this: obj-$(CONFIG_FOO) += foo.o (b) We can describe directory descending nicely. Add directories with a slash to "obj-y" like this: obj-$(CONFIG_BAR) += bar/ (c) Short log like follows: CC common/foo.o CC common/bar.o LD common/built-in.o (d) Perfect dependency tracking I think this is the biggest advantage. To be honest, the dependency tracing of U-Boot build system was not reliable. Kconfig - A tool to manage CONFIG macros. We can handle the dependency among CONFIG macros. Kconfig allows us to modify CONFIG settings easily by "make config". GUI interface are also available by "make menuconfig" All defined CONFIG macros are stored into ".config" file I think most of U-boot developers are already familiar with above. (In most cases, they are Linux Kernel developers too.) I definitely want to port both of these, but I want to do them separately: Kbuild first. (If we do Kbuild and Kconfig at the same time, it might be messed up.) So, I want to do "Kbuild without Kconfig" in this series. The conventional tool (mkconfig + boards.cfg file) is used for board configuration. Prerequisite ------------ You need to apply the followings beforehand to use this series. [1] sandbox: Use system headers first for sandbox's os.c in a different way http://patchwork.ozlabs.org/patch/294233/ [2] board: tec-ng: Do not make directories in a board Makefile http://patchwork.ozlabs.org/patch/310825/ How to Build ? -------------- We can build the same as before. Do board configuraton first and then run "make". $ make omap4_panda_config Configuring for omap4_panda board... $ make CROSS_COMPILE=arm-linux-gnueabi- GEN include/autoconf.mk.dep GEN include/autoconf.mk CC lib/asm-offsets.s GEN include/generated/generic-asm-offsets.h CC arch/arm/cpu/armv7/omap4/asm-offsets.s GEN include/generated/asm-offsets.h HOSTCC scripts/basic/fixdep ... You will find a difference at a glance: short log. If you need detail log message, please add "V=1". (You can also use "V=2") Please note we can no longer use $ make omap4_panda CROSS_COMPILE=arm-linux-gnueabi- to do board configuration and "make" at the same time. Instead, we can use Kbuild-ish way for that purpose: $ make omap4_panda_config all CROSS_COMPILE=arm-linux-gnuabi- This series keeps the other features: - Support out-of-tree build You can use "O=<dir_name>" like this $ mkdir build_dir $ make omap4_panda_config all O=build_dir CROSS_COMPILE=arm-linux-gnueabi- - Works with parallel make option Add "-j" option for this. Compiling will get faster. - Of cource, SPL, TPL build are supported (nand_spl also works. But "nand_spl" is obsolete and we should switch to "spl". Until when should we continue to maintain nand_spl?) - Breaks no boards (except some boards which are already broken) I built all target boards to prove correctness of this series at least for compile test. My Next Plan ------------ - Import Kconfig Use "make config", "make menuconfig", "make defconfig", etc. in U-Boot. - More refactoring Some parts of makefiles are still dirty. I want to refactor more makefiles in follow-up patches. - Use "obj-m" for standalone program?? Loadable module?? I have not deceided about this yet. Note ---- - I marked dirty parts with "FIX ME". In some board-specific config.mk files. # FIX ME ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) ccflags-y := -O2 endif In the top Makefile # FIX ME cpp_flags := $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(UBOOTINCLUDE) $(NOSTDINC_FLAGS) c_flags := $(KBUILD_CFLAGS) $(cpp_flags) I will re-write them more nicely after other parts are prepared. Changes for v7: - Fix a bug in spl build: In v6, build failed if we try to build another SPL board without doing "make clobber". For example, $ make omap3_beagle_config $ make CROSS_COMPILE=<your_gcc_prefix> $ make am335x_evm_config $ make CROSS_COMPILE=<your_gcc_prefix> This failed in v6. We needed either "make clobber" or "make mrproper" before switching to another board. Now, we can two or more boards continuously. Changes for v6: - Rebase on the current u-boot/master - Linux Kernel 3.13 was released on Jan. 20, so import build scripts from v3.13 to be breeding edge. - Minor change in post/lib_powerpc/fpu/Makefile - Include cmd_files under nand_spl/board/*/*/Makefile Changes for v5: - Fix a bug reported by Gerhard Sittig: "make tools" before running "make" failed at v4. - Revive "env" target so that we can build only under tools/env/. - Add a new patch at the tail: 38/38 "tools/env: cross-compile fw_printenv without setting HOSTCC" - Describe "clobber" target shortly by deleteing "*.imx" and "*.map" with wildcard matching. - Rebase on the current u-boot/master Changes for v4: - Add a new patch at the tail: 37/37 "kbuild: Do not generate .*.su files at the top directory" - Change "checkstack" target to Kbuild style - Move the line where U_BOOT_VERSION is defined Changes for v3: - Rebase on the current u-boot/master - Add a new patch at the tail: 36/36 "board: sandburst: delete FORCEBUILD" Changes for v2: - At version 1, nand_spl boards got broken at 12 and fixed at 14. Fix this problem - At version 1, sandbox got broken at 17 and fixed at 21. Fix this problem - Add a new patch at the tail: 35/35 "Kbuild: chech clean source and generate Makefile for out-of-tree build" - Rebase on v2014.01-rc2 tag Masahiro Yamada (38): .gitignore: ingore files generated by Kbuild Makefile.host.tmp: add a new script to refactor tools tools: convert makefiles to kbuild style board: samsung: refactor host programs examples: Use scripts/Makefile.build nand-spl: Use scripts/Makefile.build Makfile: move suffix rules to Makefile.build Makefile: move some variable definitions to the top Makefile Makefile: move BFD_ROOT_DIR to tools/gdb/Makefile kbuild: import Kbuild.include from linux v3.13 tag kbuild: Use Kbuild.include Makefile: move more flags to the top Makefile Makefile: refactor include path settings Makefile: move more stuff to top Makefile Makefile: move some flags to spl/Makefile Makefile: move some flags to examples makefiles kbuild: change out-of-tree build kbuild: add dummy obj-y to create built-in.o Makefile: rename scripts/Makefile.build to scripts/Makefile.build.tmp kbuild: import more build scripts from Linux v3.13 tag kbuild: use Linux Kernel build scripts kbuild: delete temporary build scripts kbuild: move some lines to more suitable place kbuild: convert some make rules to Kbuild style kbuild: move include directives of board configuration files kbuild: generate {spl,tpl}-autoconf.mk only when it is necessary Makefile: remove a cleaning target "tidy" kbuild: change the top Makefile to more Kbuild-ish structure examples: move api/ and standalone/ entry to examples/Makefile kbuild: refactor Makefile and spl/Makefile more Makefile: Do not pass MTD_VERSION from the top Makefile Makefile: refactor tools-all targets kbuild: use scripts/Makefile.clean kbuild: support simultaneous board configuration and "make all" kbuild: check clean source and generate Makefile for out-of-tree build board: sandburst: delete FORCEBUILD kbuild: Do not generate .*.su files at the top directory tools/env: cross-compile fw_printenv without setting HOSTCC .gitignore | 30 +- MAKEALL | 8 +- Makefile | 1311 +++++++++++++------- arch/arm/cpu/arm1136/config.mk | 2 +- arch/arm/cpu/arm926ejs/config.mk | 2 +- arch/arm/cpu/arm926ejs/davinci/config.mk | 2 +- arch/arm/cpu/armv7/am33xx/config.mk | 2 +- arch/arm/cpu/armv7/config.mk | 2 +- arch/arm/cpu/armv7/omap3/config.mk | 2 +- arch/arm/cpu/armv7/omap4/config.mk | 2 +- arch/arm/cpu/armv7/omap5/config.mk | 2 +- arch/arm/cpu/armv7/socfpga/config.mk | 2 +- arch/arm/cpu/armv7/tegra114/Makefile | 3 +- arch/arm/cpu/armv7/tegra30/Makefile | 3 +- arch/arm/imx-common/Makefile | 2 +- arch/blackfin/config.mk | 10 +- arch/blackfin/cpu/Makefile | 10 +- arch/blackfin/lib/Makefile | 5 +- arch/m68k/cpu/mcf5227x/Makefile | 2 +- arch/m68k/cpu/mcf523x/Makefile | 2 +- arch/m68k/cpu/mcf52x2/Makefile | 2 +- arch/m68k/cpu/mcf532x/Makefile | 2 +- arch/m68k/cpu/mcf5445x/Makefile | 2 +- arch/m68k/cpu/mcf547x_8x/Makefile | 2 +- arch/mips/cpu/mips32/config.mk | 2 +- arch/mips/cpu/mips64/config.mk | 2 +- arch/mips/cpu/xburst/config.mk | 2 +- arch/nds32/config.mk | 2 +- arch/nds32/cpu/n1213/Makefile | 3 + arch/powerpc/cpu/mpc8xx/Makefile | 2 +- arch/powerpc/lib/Makefile | 4 +- arch/sandbox/cpu/Makefile | 11 +- arch/sparc/config.mk | 3 +- arch/x86/lib/Makefile | 2 +- board/ait/cam_enc_4xx/config.mk | 2 +- board/avionic-design/medcom-wide/Makefile | 2 +- board/avionic-design/plutux/Makefile | 2 +- board/avionic-design/tec-ng/Makefile | 2 +- board/avionic-design/tec/Makefile | 2 +- board/bct-brettl2/config.mk | 7 +- board/bf518f-ezbrd/config.mk | 7 +- board/bf526-ezbrd/config.mk | 7 +- board/bf527-ad7160-eval/config.mk | 7 +- board/bf527-ezkit/config.mk | 7 +- board/bf527-sdp/config.mk | 7 +- board/bf533-ezkit/config.mk | 7 +- board/bf533-stamp/config.mk | 7 +- board/bf537-stamp/config.mk | 7 +- board/bf538f-ezkit/config.mk | 7 +- board/bf548-ezkit/config.mk | 7 +- board/bf561-acvilon/config.mk | 7 +- board/bf561-ezkit/config.mk | 7 +- board/br4/config.mk | 7 +- board/cm-bf527/config.mk | 7 +- board/cm-bf533/config.mk | 7 +- board/cm-bf537e/config.mk | 7 +- board/cm-bf537u/config.mk | 7 +- board/cm-bf548/config.mk | 7 +- board/cm-bf561/config.mk | 7 +- board/compal/paz00/Makefile | 2 +- board/compulab/trimslice/Makefile | 2 +- board/cray/L1/Makefile | 10 +- board/freescale/common/Makefile | 5 +- board/h2200/Makefile | 2 +- board/ip04/config.mk | 7 +- board/matrix_vision/mvblm7/Makefile | 4 +- board/matrix_vision/mvblx/Makefile | 2 +- board/matrix_vision/mvsmr/Makefile | 2 +- board/nvidia/common/Makefile | 2 +- board/pcs440ep/config.mk | 2 +- board/pr1/config.mk | 7 +- board/samsung/origen/Makefile | 23 +- .../origen/tools/{mkv310_image.c => mkorigenspl.c} | 0 board/samsung/smdkv310/Makefile | 16 +- .../tools/{mkv310_image.c => mksmdkv310spl.c} | 0 board/sandburst/karef/Makefile | 6 +- board/sandburst/metrobox/Makefile | 6 +- board/spear/common/Makefile | 5 +- board/spear/x600/Makefile | 5 +- board/st-ericsson/snowball/Makefile | 2 +- board/st-ericsson/u8500/Makefile | 2 +- board/tcm-bf518/config.mk | 7 +- board/tcm-bf537/config.mk | 7 +- common/Makefile | 11 +- config.mk | 333 +---- disk/Makefile | 2 +- doc/DocBook/Makefile | 73 +- drivers/bios_emulator/Makefile | 5 +- drivers/hwmon/Makefile | 2 +- drivers/net/npe/Makefile | 4 +- drivers/rtc/Makefile | 2 +- drivers/usb/musb-new/Makefile | 7 +- dts/Makefile | 20 +- examples/Makefile | 9 + examples/api/Makefile | 44 +- examples/standalone/Makefile | 74 +- fs/ubifs/Makefile | 2 +- fs/yaffs2/Makefile | 9 +- lib/Makefile | 2 +- lib/lzma/Makefile | 2 +- mkconfig | 2 +- nand_spl/board/amcc/acadia/Makefile | 45 +- nand_spl/board/amcc/bamboo/Makefile | 45 +- nand_spl/board/amcc/canyonlands/Makefile | 45 +- nand_spl/board/amcc/kilauea/Makefile | 43 +- nand_spl/board/amcc/sequoia/Makefile | 47 +- nand_spl/board/freescale/mpc8315erdb/Makefile | 47 +- nand_spl/board/freescale/mpc8536ds/Makefile | 59 +- nand_spl/board/freescale/mpc8569mds/Makefile | 59 +- nand_spl/board/freescale/mpc8572ds/Makefile | 59 +- nand_spl/board/freescale/p1023rds/Makefile | 60 +- nand_spl/board/freescale/p1_p2_rdb/Makefile | 59 +- nand_spl/board/sheldon/simpc8313/Makefile | 48 +- net/Makefile | 2 +- post/lib_powerpc/fpu/Makefile | 29 +- rules.mk | 51 - scripts/Kbuild.include | 284 +++++ scripts/Makefile | 2 + scripts/Makefile.build | 519 +++++++- scripts/Makefile.clean | 108 ++ scripts/Makefile.host | 170 +++ scripts/Makefile.lib | 375 ++++++ scripts/basic/.gitignore | 1 + scripts/basic/Makefile | 15 + scripts/basic/fixdep.c | 462 +++++++ scripts/mkmakefile | 59 + spl/Makefile | 193 +-- tools/.gitignore | 3 +- tools/Makefile | 373 ++---- tools/crc32.c | 1 + tools/easylogo/Makefile | 12 +- tools/env/.gitignore | 2 + tools/env/Makefile | 39 +- tools/env/README | 5 +- tools/env/crc32.c | 1 + tools/env/ctype.c | 1 + tools/env/env_attr.c | 1 + tools/env/env_flags.c | 1 + tools/env/linux_string.c | 1 + tools/env_embedded.c | 1 + tools/fdt.c | 1 + tools/fdt_ro.c | 1 + tools/fdt_rw.c | 1 + tools/fdt_strerror.c | 1 + tools/fdt_wip.c | 1 + tools/gdb/Makefile | 64 +- tools/image-fit.c | 1 + tools/image-sig.c | 1 + tools/image.c | 1 + tools/kernel-doc/Makefile | 21 +- tools/md5.c | 1 + tools/rsa-sign.c | 1 + tools/sha1.c | 1 + 153 files changed, 3692 insertions(+), 2055 deletions(-) rename board/samsung/origen/tools/{mkv310_image.c => mkorigenspl.c} (100%) rename board/samsung/smdkv310/tools/{mkv310_image.c => mksmdkv310spl.c} (100%) create mode 100644 examples/Makefile delete mode 100644 rules.mk create mode 100644 scripts/Kbuild.include create mode 100644 scripts/Makefile create mode 100644 scripts/Makefile.clean create mode 100644 scripts/Makefile.host create mode 100644 scripts/Makefile.lib create mode 100644 scripts/basic/.gitignore create mode 100644 scripts/basic/Makefile create mode 100644 scripts/basic/fixdep.c create mode 100644 scripts/mkmakefile create mode 100644 tools/crc32.c create mode 100644 tools/env/.gitignore create mode 100644 tools/env/crc32.c create mode 100644 tools/env/ctype.c create mode 100644 tools/env/env_attr.c create mode 100644 tools/env/env_flags.c create mode 100644 tools/env/linux_string.c create mode 100644 tools/env_embedded.c create mode 100644 tools/fdt.c create mode 100644 tools/fdt_ro.c create mode 100644 tools/fdt_rw.c create mode 100644 tools/fdt_strerror.c create mode 100644 tools/fdt_wip.c create mode 100644 tools/image-fit.c create mode 100644 tools/image-sig.c create mode 100644 tools/image.c create mode 100644 tools/md5.c create mode 100644 tools/rsa-sign.c create mode 100644 tools/sha1.c -- 1.8.3.2

2 45

[U-Boot] [PATCH 0/9] Add support for the ARC700 architecture
by Alexey Brodkin 29 Jan '14

29 Jan '14

This patch series adds support for the Synopsys DesignWare ARC700 architecture. DesignWare ARC700 is family of 32-bit CPUs developed by Synopsys, Inc. Since version 3.9 ARC architecture is supported in mainline Linux developemnt. And now to get better support in commonly used boot-loader we are introducing port of U-Boot for ARC700 CPUs. Patches included in this series are also available on GitHub in the 'for-upstream-v1' branch: git@github.com:foss-for-synopsys-dwc-arc-processors/u-boot.git Also browsable here: https://github.com/foss-for-synopsys-dwc-arc-processors/u-boot/tree/for-ups… NOTE: there's an acked by Tom Rini prerequisite for Arcangel4 board: http://patchwork.ozlabs.org/patch/300901/ For those who are interested in building this port please download pre-built toolchains for x86_64 hosts. For RedHat-based distros: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/… For Debian-based distros: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/… Alexey Brodkin (9): arc: add architecture header files arc: add cpu files arc: add library functions arc: bdinfo and image support arc: add support for standalone programs arc: add Arcangel4 board support arc: add AXS101 board support arc: add architecture to MAKEALL arc: add README for architecture MAKEALL | 6 + arch/arc/config.mk | 31 +++ arch/arc/cpu/arc700/Makefile | 13 ++ arch/arc/cpu/arc700/cache.c | 161 ++++++++++++++ arch/arc/cpu/arc700/config.mk | 7 + arch/arc/cpu/arc700/cpu.c | 37 ++++ arch/arc/cpu/arc700/interrupts.c | 211 ++++++++++++++++++ arch/arc/cpu/arc700/reset.c | 19 ++ arch/arc/cpu/arc700/start.S | 262 ++++++++++++++++++++++ arch/arc/cpu/arc700/timer.c | 28 +++ arch/arc/cpu/arc700/u-boot.lds | 72 +++++++ arch/arc/include/asm/arch-arc700/hardware.h | 0 arch/arc/include/asm/arcregs.h | 324 ++++++++++++++++++++++++++++ arch/arc/include/asm/bitops.h | 19 ++ arch/arc/include/asm/byteorder.h | 23 ++ arch/arc/include/asm/cache.h | 23 ++ arch/arc/include/asm/config.h | 12 ++ arch/arc/include/asm/errno.h | 1 + arch/arc/include/asm/global_data.h | 19 ++ arch/arc/include/asm/io.h | 287 ++++++++++++++++++++++++ arch/arc/include/asm/posix_types.h | 73 +++++++ arch/arc/include/asm/processor.h | 0 arch/arc/include/asm/ptrace.h | 101 +++++++++ arch/arc/include/asm/sections.h | 1 + arch/arc/include/asm/string.h | 0 arch/arc/include/asm/types.h | 55 +++++ arch/arc/include/asm/u-boot.h | 15 ++ arch/arc/include/asm/unaligned.h | 1 + arch/arc/lib/Makefile | 9 + arch/arc/lib/bootm.c | 106 +++++++++ arch/arc/lib/relocate.c | 74 +++++++ arch/arc/lib/sections.c | 21 ++ board/synopsys/arcangel4/Makefile | 7 + board/synopsys/arcangel4/arcangel4.c | 25 +++ board/synopsys/axs101/Makefile | 8 + board/synopsys/axs101/axs101.c | 61 ++++++ board/synopsys/axs101/nand.c | 224 +++++++++++++++++++ boards.cfg | 2 + common/cmd_bdinfo.c | 18 ++ common/image.c | 1 + doc/README.ARC | 27 +++ examples/standalone/stubs.c | 13 ++ include/configs/arcangel4.h | 96 +++++++++ include/configs/axs101.h | 194 +++++++++++++++++ include/image.h | 1 + 45 files changed, 2688 insertions(+) create mode 100644 arch/arc/config.mk create mode 100644 arch/arc/cpu/arc700/Makefile create mode 100644 arch/arc/cpu/arc700/cache.c create mode 100644 arch/arc/cpu/arc700/config.mk create mode 100644 arch/arc/cpu/arc700/cpu.c create mode 100644 arch/arc/cpu/arc700/interrupts.c create mode 100644 arch/arc/cpu/arc700/reset.c create mode 100644 arch/arc/cpu/arc700/start.S create mode 100644 arch/arc/cpu/arc700/timer.c create mode 100644 arch/arc/cpu/arc700/u-boot.lds create mode 100644 arch/arc/include/asm/arch-arc700/hardware.h create mode 100644 arch/arc/include/asm/arcregs.h create mode 100644 arch/arc/include/asm/bitops.h create mode 100644 arch/arc/include/asm/byteorder.h create mode 100644 arch/arc/include/asm/cache.h create mode 100644 arch/arc/include/asm/config.h create mode 100644 arch/arc/include/asm/errno.h create mode 100644 arch/arc/include/asm/global_data.h create mode 100644 arch/arc/include/asm/io.h create mode 100644 arch/arc/include/asm/posix_types.h create mode 100644 arch/arc/include/asm/processor.h create mode 100644 arch/arc/include/asm/ptrace.h create mode 100644 arch/arc/include/asm/sections.h create mode 100644 arch/arc/include/asm/string.h create mode 100644 arch/arc/include/asm/types.h create mode 100644 arch/arc/include/asm/u-boot.h create mode 100644 arch/arc/include/asm/unaligned.h create mode 100644 arch/arc/lib/Makefile create mode 100644 arch/arc/lib/bootm.c create mode 100644 arch/arc/lib/relocate.c create mode 100644 arch/arc/lib/sections.c create mode 100644 board/synopsys/arcangel4/Makefile create mode 100644 board/synopsys/arcangel4/arcangel4.c create mode 100644 board/synopsys/axs101/Makefile create mode 100644 board/synopsys/axs101/axs101.c create mode 100644 board/synopsys/axs101/nand.c create mode 100644 doc/README.ARC create mode 100644 include/configs/arcangel4.h create mode 100644 include/configs/axs101.h -- 1.8.5.3

2 13

[U-Boot] [PATCH] ventana: Add Gateworks Ventana family support
by Tim Harvey 29 Jan '14

29 Jan '14

Gateworks Ventana is a product family based on the i.MX6. This patch adds support for all boards in the Ventana family. Where possible, data from the boards EEPROM is used to determine various details about the board at runtime. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- board/gateworks/gw_ventana/1066mhz_4x128mx16.cfg | 42 + board/gateworks/gw_ventana/800mhz_2x128mx16.cfg | 42 + board/gateworks/gw_ventana/800mhz_4x128mx16.cfg | 42 + board/gateworks/gw_ventana/Makefile | 10 + board/gateworks/gw_ventana/README | 49 + board/gateworks/gw_ventana/clocks.cfg | 41 + board/gateworks/gw_ventana/ddr-setup.cfg | 96 ++ board/gateworks/gw_ventana/gw_ventana.c | 1729 ++++++++++++++++++++++ board/gateworks/gw_ventana/gw_ventana.cfg | 42 + board/gateworks/gw_ventana/ventana_eeprom.h | 107 ++ boards.cfg | 7 +- include/configs/gw_ventana.h | 409 +++++ 12 files changed, 2615 insertions(+), 1 deletion(-) create mode 100644 board/gateworks/gw_ventana/1066mhz_4x128mx16.cfg create mode 100644 board/gateworks/gw_ventana/800mhz_2x128mx16.cfg create mode 100644 board/gateworks/gw_ventana/800mhz_4x128mx16.cfg create mode 100644 board/gateworks/gw_ventana/Makefile create mode 100644 board/gateworks/gw_ventana/README create mode 100644 board/gateworks/gw_ventana/clocks.cfg create mode 100644 board/gateworks/gw_ventana/ddr-setup.cfg create mode 100644 board/gateworks/gw_ventana/gw_ventana.c create mode 100644 board/gateworks/gw_ventana/gw_ventana.cfg create mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h create mode 100644 include/configs/gw_ventana.h diff --git a/board/gateworks/gw_ventana/1066mhz_4x128mx16.cfg b/board/gateworks/gw_ventana/1066mhz_4x128mx16.cfg new file mode 100644 index 0000000..6c68146 --- /dev/null +++ b/board/gateworks/gw_ventana/1066mhz_4x128mx16.cfg @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7974 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42720306 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026F0266 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4273030A +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02740240 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45393B3E +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x403A3747 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40434541 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x473E4A3B +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0011000E +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x000E001B +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00190015 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00070018 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/gateworks/gw_ventana/800mhz_2x128mx16.cfg b/board/gateworks/gw_ventana/800mhz_2x128mx16.cfg new file mode 100644 index 0000000..e005a64 --- /dev/null +++ b/board/gateworks/gw_ventana/800mhz_2x128mx16.cfg @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 +DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/gateworks/gw_ventana/800mhz_4x128mx16.cfg b/board/gateworks/gw_ventana/800mhz_4x128mx16.cfg new file mode 100644 index 0000000..1069342 --- /dev/null +++ b/board/gateworks/gw_ventana/800mhz_4x128mx16.cfg @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420F020F +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x01760175 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x41640171 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015E0160 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45464B4A +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x49484A46 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40402E32 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3A3A3231 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x003A003A +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0030002F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x002F0038 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00270039 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile new file mode 100644 index 0000000..b8b94b6 --- /dev/null +++ b/board/gateworks/gw_ventana/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg(a)denx.de> +# (C) Copyright 2012-2013 Freescale Semiconductor, Inc. +# Copyright (C) 2013, Gateworks Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := gw_ventana.o + diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README new file mode 100644 index 0000000..9de55ba --- /dev/null +++ b/board/gateworks/gw_ventana/README @@ -0,0 +1,49 @@ +U-Boot for the Gateworks Ventana Product Family boards + +This file contains information for the port of U-Boot to the Gateworks +Ventana Product family boards. + +1. Boot source, boot from NAND +------------------------------ + +The i.MX6 BOOT ROM expects some headers that provide details of NAND layout +and bad block information (referred to as 'bootstreams') which are replicated +multiple times in NAND. The number of replications is configurable through +board strapping options and eFUSE settings. The Freescale 'kobs-ng' +application from the Freescale LTIB BSP, which runs under Linux, must be used +to program the bootstream in order to setup the replicated headers correctly. + +The Gateworks Ventana boards with NAND flash have been factory programmed +such that their eFUSE settings expect 2 copies of the boostream (this is +specified by providing kobs-ng with the --search_exponent=1 argument). Once in +Linux with MTD support for the NAND on /dev/mtd0 you can program the boostream +with: + +kobs-ng init -v -x --search_exponent=1 u-boot.imx + +This information is taken from + +https://trac.gateworks.com/wiki/ventana%3Abuild_uboot + +2. Build +-------- + +There are several Gateworks Ventana boards that share a simliar design but +vary based on CPU, Memory configuration, and subloaded devices. Although +the subloaded devices are handled dynamically in the bootloader using +factory configured EEPROM data to modify the device-tree, the CPU choice +(IMX6Q vs IMX6DL) and memory configurations are currently compile-time +options. + +The following Gateworks Ventana configurations exist: + gwventanaq1gspi: MX6Q,1GB,SPI FLASH + gwventanaq : MX6Q,512MB,NAND FLASH + gwventanaq1g : MX6Q,1GB,NAND FLASH + gwventanadl : MX6DL,512MB,NAND FLASH + gwventanadl1g : MX6DL,1GB,NAND FLASH + +To build U-Boot for the MX6Q,1GB,NAND FLASH for example: + + make gwventanaq1g_config + make u-boot.imx + diff --git a/board/gateworks/gw_ventana/clocks.cfg b/board/gateworks/gw_ventana/clocks.cfg new file mode 100644 index 0000000..31790e7 --- /dev/null +++ b/board/gateworks/gw_ventana/clocks.cfg @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/gateworks/gw_ventana/ddr-setup.cfg b/board/gateworks/gw_ventana/ddr-setup.cfg new file mode 100644 index 0000000..2748d40 --- /dev/null +++ b/board/gateworks/gw_ventana/ddr-setup.cfg @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits x16/x32 + */ +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + +/* + * MDMISC mirroring interleaved (row/bank/col) + */ +DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 + +/* + * MDSCR con_req + */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c new file mode 100644 index 0000000..418d1f8 --- /dev/null +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -0,0 +1,1729 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/sys_proto.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/sata.h> +#include <linux/list.h> +#include <linux/ctype.h> +#include <linux/fb.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <micrel.h> +#include <miiphy.h> +#include <netdev.h> +#include <ipu_pixfmt.h> +#include <i2c.h> +#include <fdt_support.h> +#include <jffs2/load_kernel.h> +#include <mtd_node.h> +#include <spi_flash.h> +#include <hwconfig.h> +#include <fuse.h> + +#include "ventana_eeprom.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) + +#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) + +/* UART1, RS485 */ +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +/* UART2, Console */ +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* I2C1, GSC */ +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; + +/* I2C2, PFUSE, PCIe Switch/Clock/Mezz */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* I2C3, Accel, Audio Codec, Video Decoder, Video Encoder, MIPI, LVDS, DIO */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; + +/* MMC */ +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +/* ENET */ +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* PHY nRST */ + MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* NAND */ +iomux_v3_cfg_t const nfc_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_CMD_NAND +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* toggle PHY_RST# */ + gpio_direction_output(IMX_GPIO_NR(1, 30), 0); + mdelay(2); + gpio_set_value(IMX_GPIO_NR(1, 30), 1); +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +#ifdef CONFIG_USB_EHCI_MX6 +iomux_v3_cfg_t const usb_pads[] = { + MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM), +}; + +int board_ehci_hcd_init(int port) +{ + /* Reset USB hub */ + imx_iomux_v3_setup_pad(MX6_PAD_SD1_DAT0__GPIO1_IO16 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 16), 0); + mdelay(2); + gpio_set_value(IMX_GPIO_NR(1, 16), 1); + + return 0; +} + +int board_ehci_power(int port, int on) +{ + if (port) + return 0; + gpio_set_value(IMX_GPIO_NR(3, 22), on); + return 0; +} +#endif /* CONFIG_USB_EHCI_MX6 */ + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC3_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) { + /* Card Detect */ + gpio_direction_input(IMX_GPIO_NR(7, 0)); + ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 4; + + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } + + return status; +} +#endif /* CONFIG_FSL_ESDHC */ + +/* Gateworks System Controller I2C access may NAK when busy - use + * retries. + */ +int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int retry = 3; + int n = 0; + int ret; + + while (n++ < retry) { + ret = i2c_read(chip, addr, alen, buf, len); + if (!ret) + break; + printf("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, + n, ret); + if (ret != -ENODEV) + break; + mdelay(10); + } + return ret; +} + +int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int retry = 3; + int n = 0; + int ret; + + while (n++ < retry) { + ret = i2c_write(chip, addr, alen, buf, len); + if (!ret) + break; + printf("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, + n, ret); + if (ret != -ENODEV) + break; + mdelay(10); + } + mdelay(1); + return ret; +} + +/* + * For SPL boot some boards need i2c before SDRAM is initialized so force + * variables to live in SRAM + */ +static struct ventana_board_info __attribute__((section(".data"))) ventana_info; + +/* read ventana EEPROM and return structure or NULL on error + * should be called once, the first time eeprom data is needed + */ +static void +read_eeprom(void) +{ + int i; + int chksum; + struct ventana_board_info *info = &ventana_info; + unsigned char *buf = (unsigned char *)&ventana_info; + int n = 0; + + memset(info, 0, sizeof(ventana_info)); + + /* wait for bus and device exist - we will not boot w/o our EEPROM */ + while (1) { + if (0 == i2c_set_bus_num(0) && 0 == i2c_probe(0x51)) + break; + mdelay(1); + n++; + } + + /* read eeprom config section */ + if (gsc_i2c_read(0x51, 0x00, 1, buf, sizeof(ventana_info))) { + printf("EEPROM: Failed to read EEPROM\n"); + info->model[0] = 0; + return; + } + + /* sanity checks */ + if (info->model[0] != 'G' || info->model[1] != 'W') { + printf("EEPROM: Invalid Model in EEPROM\n"); + info->model[0] = 0; + return; + } + + /* validate checksum */ + for (chksum = 0, i = 0; i < sizeof(*info)-2; i++) + chksum += buf[i]; + if ((info->chksum[0] != chksum>>8) || + (info->chksum[1] != (chksum&0xff))) { + printf("EEPROM: Failed EEPROM checksum\n"); + info->model[0] = 0; + return; + } +} + +#ifdef CONFIG_CMD_GSC +int read_hwmon(const char *name, uint reg, uint size, uint low, uint high) +{ + unsigned char buf[3]; + uint ui; + int ret; + + printf("%-8s:", name); + memset(buf, 0, sizeof(buf)); + if (gsc_i2c_read(0x29, reg, 1, buf, size)) { + printf("fRD\n"); + ret = -1; + } else { + ret = 0; + ui = buf[0] | (buf[1]<<8) | (buf[2]<<16); + if (ui == 0xffffff) { + printf("fVL"); + } else if (ui < low) { + printf("%d fLO", ui); + ret = -2; + } else if (ui > high) { + printf("%d fHI", ui); + ret = -3; + } else { + printf("%d", ui); + } + } + printf("\n"); + + return ret; +} + +int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct ventana_board_info *info = &ventana_info; + + i2c_set_bus_num(0); + if ((strncasecmp((const char *)info->model, "GW51", 4) == 0)) { + read_hwmon("Temp", 0x00, 2, 0, 9000); + read_hwmon("VIN", 0x02, 3, 8000, 60000); + read_hwmon("VDD_3P3", 0x05, 3, 3300*0.9, 3300*1.1); + read_hwmon("VBATT", 0x08, 3, 2000*0.9, 3000*1.1); + read_hwmon("VDD_CORE", 0x0e, 3, 1175*0.9, 1175*1.1); + read_hwmon("VDD_SOC", 0x11, 3, 1175*0.9, 1175*1.1); + read_hwmon("VDD_HIGH", 0x14, 3, 3000*0.9, 3000*1.1); + read_hwmon("VDD_DDR", 0x17, 3, 1500*0.9, 1500*1.1); + read_hwmon("VDD_5P0", 0x0b, 3, 5000*0.9, 5000*1.1); + read_hwmon("VDD_2P5", 0x23, 3, 2500*0.9, 2500*1.1); + read_hwmon("VDD_1P8", 0x1d, 3, 1800*0.9, 1800*1.1); + } else if ((strncasecmp((const char *)info->model, "GW52", 4) == 0)) { + read_hwmon("Temp", 0x00, 2, 0, 9000); + read_hwmon("VIN", 0x02, 3, 8000, 60000); + read_hwmon("VDD_3P3", 0x05, 3, 3300*0.9, 3300*1.1); + read_hwmon("VBATT", 0x08, 3, 2000*0.9, 3000*1.1); + read_hwmon("VDD_CORE", 0x0e, 3, 1175*0.9, 1175*1.1); + read_hwmon("VDD_SOC", 0x11, 3, 1175*0.9, 1175*1.1); + read_hwmon("VDD_HIGH", 0x14, 3, 3000*0.9, 3000*1.1); + read_hwmon("VDD_DDR", 0x17, 3, 1500*0.9, 1500*1.1); + read_hwmon("VDD_5P0", 0x0b, 3, 5000*0.9, 5000*1.1); + read_hwmon("VDD_2P5", 0x23, 3, 2500*0.9, 2500*1.1); + read_hwmon("VDD_1P8", 0x1d, 3, 1800*0.9, 1800*1.1); + read_hwmon("VDD_1P0", 0x20, 3, 1000*0.9, 1000*1.1); + } else if ((strncasecmp((const char *)info->model, "GW53", 4) == 0)) { + read_hwmon("Temp", 0x00, 2, 0, 9000); + read_hwmon("VIN", 0x02, 3, 8000, 60000); + read_hwmon("VDD_3P3", 0x05, 3, 3300*0.9, 3300*1.1); + read_hwmon("VBATT", 0x08, 3, 2000*0.9, 3000*1.1); + read_hwmon("VDD_CORE", 0x0e, 3, 1175*0.9, 1175*1.1); + read_hwmon("VDD_SOC", 0x11, 3, 1175*0.9, 1175*1.1); + read_hwmon("VDD_HIGH", 0x14, 3, 3000*0.9, 3000*1.1); + read_hwmon("VDD_DDR", 0x17, 3, 1500*0.9, 1500*1.1); + read_hwmon("VDD_5P0", 0x0b, 3, 5000*0.9, 5000*1.1); + read_hwmon("VDD_2P5", 0x23, 3, 2500*0.9, 2500*1.1); + read_hwmon("VDD_1P8", 0x1d, 3, 1800*0.9, 1800*1.1); + read_hwmon("VDD_1P0", 0x20, 3, 1000*0.9, 1000*1.1); + } else if ((strncasecmp((const char *)info->model, "GW54", 4) == 0)) { + read_hwmon("Temp", 0x00, 2, 0, 9000); + read_hwmon("VIN", 0x02, 3, 8000, 60000); + read_hwmon("VDD_3P3", 0x05, 3, 3300*0.9, 3300*1.1); + read_hwmon("VBATT", 0x08, 3, 2000*0.9, 3000*1.1); + read_hwmon("VDD_CORE", 0x0e, 3, 1375*0.9, 1375*1.1); + read_hwmon("VDD_SOC", 0x11, 3, 1375*0.9, 1375*1.1); + read_hwmon("VDD_HIGH", 0x14, 3, 3000*0.9, 3000*1.1); + read_hwmon("VDD_DDR", 0x17, 3, 1500*0.9, 1500*1.1); + read_hwmon("VDD_5P0", 0x0b, 3, 5000*0.9, 5000*1.1); + read_hwmon("VDD_2P5", 0x23, 3, 2500*0.9, 2500*1.1); + read_hwmon("VDD_1P8", 0x1d, 3, 1800*0.9, 1800*1.1); + read_hwmon("VDD_1P0", 0x20, 3, 1000*0.9, 1000*1.1); + } + return 0; +} + +U_BOOT_CMD(gsc, 1, 1, do_gsc, + "GSC test", + "" +); +#endif /* CONFIG_CMD_GSC */ + + +/* get_mac from env string, with default + */ +static void get_mac(char *envvar, unsigned char *def) +{ + char str[20]; + char *env = getenv(envvar); + + if (!env) { + sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", + def[0], def[1], def[2], def[3], def[4], def[5]); + setenv(envvar, str); + } +} + +#ifdef CONFIG_SERIAL_TAG +/* called when setting up ATAGS before booting kernel + * populate serialnum from the following (in order of priority): + * serial# env var + * eeprom + */ +void get_board_serial(struct tag_serialnr *serialnr) +{ + char *serial = getenv("serial#"); + + if (serial) { + serialnr->high = 0; + serialnr->low = simple_strtoul(serial, NULL, 10); + } else if (ventana_info.model[0]) { + serialnr->high = 0; + serialnr->low = ventana_info.serial; + } else { + serialnr->high = 0; + serialnr->low = 0; + } +} +#endif + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + /* SS1 */ + MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; + +static void setup_spi(void) +{ + gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + unsigned short val; + + /* Marvel 88E1510 */ + if (phydev->phy_id == 0x1410dd1) { + /* Errata 3.1 - PHY initialization */ + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214b); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0c28); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb233); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214d); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xcc0c); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159); + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fb); + phy_write(phydev, MDIO_DEVAD_NONE, 7, 0xc00d); + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); + + /* LED configuration (See datasheet section 2.26.4) + * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link + * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity + */ + phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); + val = phy_read(phydev, MDIO_DEVAD_NONE, 16); + val &= 0xff00; + val |= 0x0017; + phy_write(phydev, MDIO_DEVAD_NONE, 16, val); + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + ret = cpu_eth_init(bis); + if (ret) + printf("FEC MXC: %s:failed\n", __func__); +#endif + +#ifdef CONFIG_MV_UDC + /* For otg ethernet*/ + usb_eth_initialize(bis); +#endif + + return 0; +} + +static void setup_board_gpio(const char *model) +{ + const char *s; + char arg[10]; + size_t len; + int i; + enum { + GW51xx, + GW52xx, + GW53xx, + GW54xx, + UNKNOWN, + }; + struct dio_cfg { + iomux_v3_cfg_t gpio_padmux; + unsigned gpio_param; + iomux_v3_cfg_t pwm_padmux; + unsigned pwm_param; + }; + int board_type = UNKNOWN; + struct dio_cfg dio_cfg[] = { + /* GW51xx */ + { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16), + 0, 0 }, + { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), + MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, + { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17), + MX6_PAD_SD1_DAT1__PWM3_OUT, 3 }, + { MX6_PAD_SD1_CMD__GPIO1_IO18, IMX_GPIO_NR(1, 18), + MX6_PAD_SD1_CMD__PWM4_OUT, 4 }, + + /* GW52xx */ + { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16), + 0, 0 }, + { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), + MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, + { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17), + MX6_PAD_SD1_DAT1__PWM3_OUT, 3 }, + { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20), + 0, 0 }, + + /* GW53xx */ + { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16), + 0, 0 }, + { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), + MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, + { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17), + MX6_PAD_SD1_DAT1__PWM3_OUT, 3 }, + { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20), + 0, 0 }, + + /* GW54xx */ + { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9), + MX6_PAD_GPIO_9__PWM1_OUT, 1 }, + { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), + MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, + { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9), + MX6_PAD_SD4_DAT1__PWM3_OUT, 3 }, + { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10), + MX6_PAD_SD4_DAT2__PWM4_OUT, 4 }, + }; + + if (strncasecmp(model, "GW51", 4) == 0) { + board_type = GW51xx; + + /* PANLEDG# (GRN off) */ + imx_iomux_v3_setup_pad(MX6_PAD_KEY_COL0__GPIO4_IO06 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 6), 1); + + /* PANLEDR# (RED off) */ + imx_iomux_v3_setup_pad(MX6_PAD_KEY_ROW0__GPIO4_IO07 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 7), 1); + + /* GPS_SHDN */ + imx_iomux_v3_setup_pad(MX6_PAD_GPIO_2__GPIO1_IO02 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 2), 1); + + /* Analog video codec power enable */ + imx_iomux_v3_setup_pad(MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(5, 20), 1); + + /* Expansion IO0 - PWREN# */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A19__GPIO2_IO19 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(2, 19), 0); + + /* Expansion IO1 - IRQ# */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A20__GPIO2_IO18 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_input(IMX_GPIO_NR(2, 18)); + } /* end GW51xx */ + + else if (strncasecmp(model, "GW52", 4) == 0) { + board_type = GW52xx; + + /* PANLEDG# (GRN off) */ + imx_iomux_v3_setup_pad(MX6_PAD_KEY_COL0__GPIO4_IO06 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 6), 1); + + /* PANLEDR# (RED off) */ + imx_iomux_v3_setup_pad(MX6_PAD_KEY_ROW0__GPIO4_IO07 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 7), 1); + + /* MX6_LOCLED# (off) */ + imx_iomux_v3_setup_pad(MX6_PAD_KEY_ROW4__GPIO4_IO15 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 15), 1); + + /* GPS_SHDN */ + imx_iomux_v3_setup_pad(MX6_PAD_ENET_RXD0__GPIO1_IO27 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 27), 1); + + /* Expansion IO0 - PWREN# */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A19__GPIO2_IO19 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(2, 19), 0); + + /* Expansion IO1 - IRQ# */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A20__GPIO2_IO18 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_input(IMX_GPIO_NR(2, 18)); + + /* MSATA Enable */ + imx_iomux_v3_setup_pad(MX6_PAD_SD4_DAT0__GPIO2_IO08 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + if (is_cpu_type(MXC_CPU_MX6Q)) { + gpio_direction_output(IMX_GPIO_NR(2, 8), + (hwconfig("msata")) ? 1 : 0); + printf("MSATA: %s\n", (hwconfig("msata") ? + "enabled" : "disabled")); + } else { + gpio_direction_output(IMX_GPIO_NR(2, 8), 0); + } + + /* USBOTG Select (PCISKT or FrontPanel) */ + imx_iomux_v3_setup_pad(MX6_PAD_GPIO_2__GPIO1_IO02 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 2), 0); + + /* Analog video codec power enable */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_D31__GPIO3_IO31 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(3, 31), 1); + + /* UART2_EN# */ + imx_iomux_v3_setup_pad(MX6_PAD_SD4_DAT3__GPIO2_IO11 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + printf("RS232: %s\n", (hwconfig("rs232")) ? + "enabled" : "disabled"); + gpio_direction_output(IMX_GPIO_NR(2, 11), + (hwconfig("rs232")) ? 0 : 1); + /* TODO: flush UART RX FIFO after disable */ + } /* end GW52xx */ + + else if (strncasecmp(model, "GW53", 4) == 0) { + board_type = GW53xx; + + /* PANLEDG# (GRN off) */ + imx_iomux_v3_setup_pad(MX6_PAD_KEY_COL0__GPIO4_IO06 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 6), 1); + + /* PANLEDR# (RED off) */ + imx_iomux_v3_setup_pad(MX6_PAD_KEY_ROW0__GPIO4_IO07 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 7), 1); + + /* MX6_LOCLED# (off) */ + imx_iomux_v3_setup_pad(MX6_PAD_KEY_ROW4__GPIO4_IO15 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 15), 1); + + /* GPS_SHDN */ + imx_iomux_v3_setup_pad(MX6_PAD_ENET_RXD0__GPIO1_IO27 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 27), 1); + + /* Expansion IO0 - PWREN# */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A19__GPIO2_IO19 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(2, 19), 0); + + /* Expansion IO1 - IRQ# */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A20__GPIO2_IO18 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_input(IMX_GPIO_NR(2, 18)); + + /* MSATA Enable */ + imx_iomux_v3_setup_pad(MX6_PAD_SD4_DAT0__GPIO2_IO08 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + if (is_cpu_type(MXC_CPU_MX6Q)) { + gpio_direction_output(IMX_GPIO_NR(2, 8), + (hwconfig("msata")) ? 1 : 0); + printf("MSATA: %s\n", (hwconfig("msata") ? + "enabled" : "disabled")); + } else { + gpio_direction_output(IMX_GPIO_NR(2, 8), 0); + } + + /* Analog video codec power enable */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_D31__GPIO3_IO31 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(3, 31), 1); + + /* UART2_EN# */ + imx_iomux_v3_setup_pad(MX6_PAD_SD4_DAT3__GPIO2_IO11 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + printf("RS232: %s\n", (hwconfig("rs232")) ? + "enabled" : "disabled"); + gpio_direction_output(IMX_GPIO_NR(2, 11), + (hwconfig("rs232")) ? 0 : 1); + /* TODO: flush UART RX FIFO after disable */ + } /* end GW53xx */ + + else if (strncasecmp(model, "GW54", 4) == 0) { + board_type = GW54xx; + if (strncasecmp(model, "GW5400-A", 8) == 0) { + /* PANLEDG# (GRN off) */ + imx_iomux_v3_setup_pad(MX6_PAD_KEY_COL0__GPIO4_IO06 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 6), 1); + + /* PANLEDR# (RED off) */ + imx_iomux_v3_setup_pad(MX6_PAD_KEY_COL2__GPIO4_IO10 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 10), 1); + + /* MX6_LOCLED# (off) */ + imx_iomux_v3_setup_pad(MX6_PAD_KEY_ROW4__GPIO4_IO15 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 15), 1); + + /* MIPI DIO */ + imx_iomux_v3_setup_pad(MX6_PAD_SD1_DAT3__GPIO1_IO21 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + + /* RS485 Transmit Enable */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_D24__GPIO3_IO24 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(3, 24), 0); + + /* Expansion IO0 - PWREN# */ + imx_iomux_v3_setup_pad(MX6_PAD_KEY_ROW0__GPIO4_IO07 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 7), 0); + + /* Expansion IO1 - IRQ# */ + imx_iomux_v3_setup_pad(MX6_PAD_KEY_ROW1__GPIO4_IO09 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_input(IMX_GPIO_NR(4, 9)); + } + + else if ((strncasecmp(model, "GW5400", 6) == 0) || + (strncasecmp(model, "GW5410", 6) == 0) + ) { + /* PANLEDG# (GRN off) */ + imx_iomux_v3_setup_pad(MX6_PAD_KEY_COL0__GPIO4_IO06 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 6), 1); + + /* PANLEDR# (RED off) */ + imx_iomux_v3_setup_pad(MX6_PAD_KEY_ROW0__GPIO4_IO07 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 7), 1); + + /* MX6_LOCLED# (off) */ + imx_iomux_v3_setup_pad(MX6_PAD_KEY_ROW4__GPIO4_IO15 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 15), 1); + + /* RS485 Transmit Enable */ + imx_iomux_v3_setup_pad(MX6_PAD_SD3_DAT4__GPIO7_IO01 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(7, 1), 0); + + /* Expansion IO0 - PWREN# */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A19__GPIO2_IO19 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(2, 19), 0); + + /* Expansion IO1 - IRQ# */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A20__GPIO2_IO18 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_input(IMX_GPIO_NR(2, 18)); + + /* MSATA Enable */ + imx_iomux_v3_setup_pad(MX6_PAD_SD4_DAT0__GPIO2_IO08 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + if (is_cpu_type(MXC_CPU_MX6Q)) { + gpio_direction_output(IMX_GPIO_NR(2, 8), + (hwconfig("msata")) ? + 1 : 0); + printf("MSATA: %s\n", (hwconfig("msata") ? + "enabled" : "disabled")); + } else { + gpio_direction_output(IMX_GPIO_NR(2, 8), 0); + } + + /* Analog video codec power enable */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_D31__GPIO3_IO31 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(3, 31), 1); + } + + /* UART2_EN# */ + imx_iomux_v3_setup_pad(MX6_PAD_SD4_DAT3__GPIO2_IO11 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + printf("RS232: %s\n", (hwconfig("rs232")) ? + "enabled" : "disabled"); + gpio_direction_output(IMX_GPIO_NR(2, 11), + (hwconfig("rs232")) ? 0 : 1); + /* TODO: flush UART RX FIFO after disable */ + + /* DIOI2C_DIS# */ + imx_iomux_v3_setup_pad(MX6_PAD_GPIO_19__GPIO4_IO05 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(4, 5), 0); + } /* end GW54xx */ + + /* Configure DIO pinmux/padctl registers + * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions + */ + if (board_type > UNKNOWN) + return; + for (i = 0; i < 4; i++) { + struct dio_cfg *cfg = &dio_cfg[(4*board_type)+i]; + unsigned ctrl = DIO_PAD_CTRL; + + sprintf(arg, "dio%d", i); + if (hwconfig(arg)) { + s = hwconfig_subarg(arg, "padctrl", &len); + if (s) + ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff; + if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { + printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, + (cfg->gpio_param/32)+1, + cfg->gpio_param%32, + cfg->gpio_param); + imx_iomux_v3_setup_pad(cfg->gpio_padmux | + MUX_PAD_CTRL(ctrl)); + gpio_direction_input(cfg->gpio_param); + } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && + cfg->pwm_padmux) { + printf("DIO%d: pwm%d\n", i, cfg->pwm_param); + imx_iomux_v3_setup_pad(cfg->pwm_padmux | + MUX_PAD_CTRL(ctrl)); + } + } + } +} + +static int setup_pcie(void) +{ + struct ventana_board_info *info = &ventana_info; + + if ((strncasecmp((const char *)info->model, "GW51", 4) == 0)) { + /* assert PCI_RST# + * (will be released by OS when clock is valid) */ + imx_iomux_v3_setup_pad(MX6_PAD_GPIO_0__GPIO1_IO00 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 0), 0); + } else if ((strncasecmp((const char *)info->model, "GW52", 4) == 0)) { + /* assert PCI_RST# + * (will be released by OS when clock is valid) */ + imx_iomux_v3_setup_pad(MX6_PAD_ENET_TXD1__GPIO1_IO29 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 29), 0); + } else if ((strncasecmp((const char *)info->model, "GW53", 4) == 0)) { + /* assert PCI_RST# + * (will be released by OS when clock is valid) */ + imx_iomux_v3_setup_pad(MX6_PAD_ENET_TXD1__GPIO1_IO29 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 29), 0); + } else if ((strncasecmp((const char *)info->model, "GW54", 4) == 0)) { + /* PCICK_SSON: disable spread-spectrum clock */ + imx_iomux_v3_setup_pad(MX6_PAD_SD1_CLK__GPIO1_IO20 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 20), 0); + + /* assert PCI_RST# + * (will be released by OS when clock is valid) */ + imx_iomux_v3_setup_pad(MX6_PAD_ENET_TXD1__GPIO1_IO29 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 29), 0); + } + + return 0; +} + +#if defined(CONFIG_VIDEO_IPUV3) + +static iomux_v3_cfg_t const backlight_pads[] = { + /* Backlight on MIPI connector: J16 */ + MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* Backlight CABEN on LVDS connector: J6 */ + MX6_PAD_SD2_CLK__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +struct display_info_t { + int bus; + int addr; + int pixfmt; + int (*detect)(struct display_info_t const *dev); + void (*enable)(struct display_info_t const *dev); + struct fb_videomode mode; +}; + + +static int detect_hdmi(struct display_info_t const *dev) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD; +} + +static void do_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +static int detect_i2c(struct display_info_t const *dev) +{ + return ((0 == i2c_set_bus_num(dev->bus)) && + (0 == i2c_probe(dev->addr))); +} + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + + /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */ + u32 reg = readl(&iomux->gpr[2]); + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + writel(reg, &iomux->gpr[2]); + + /* Disable CABC: + * when enabled this feature sets backlight automatically according + * to content which may cause annoying unstable backlight issue + */ + gpio_direction_output(IMX_GPIO_NR(1, 10), 0); + + /* Enable Backlight */ + imx_iomux_v3_setup_pad(MX6_PAD_SD1_CMD__GPIO1_IO18 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 18), 1); +} + +static struct display_info_t const displays[] = {{ + /* HDMI Output */ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + /* HannStar HSD100PXN1-A00 with egalx_ts controller + * (aka Freescale MXC-LVDS1 10" 1024x768 60Hz LCD touchscreen) + */ + .bus = 2, + .addr = 0x4, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; + +int board_video_skip(void) +{ + int i; + int ret; + char const *panel = getenv("panel"); + if (!panel) { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + struct display_info_t const *dev = displays+i; + if (dev->detect(dev)) { + panel = dev->mode.name; + printf("auto-detected panel %s\n", panel); + break; + } + } + if (!panel) { + panel = displays[0].mode.name; + i = 0; + printf("No panel detected: default to %s\n", panel); + } + } else { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + if (!strcmp(panel, displays[i].mode.name)) + break; + } + } + if (i < ARRAY_SIZE(displays)) { + ret = ipuv3_fb_init(&displays[i].mode, 0, + displays[i].pixfmt); + if (!ret) { + displays[i].enable(displays+i); + printf("DISP: %s (%ux%u)\n", + displays[i].mode.name, + displays[i].mode.xres, + displays[i].mode.yres); + } else + printf("LCD %s cannot be configured: %d\n", + displays[i].mode.name, ret); + } else { + printf("unsupported panel %s\n", panel); + ret = -EINVAL; + } + return (0 != ret); +} + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); + + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); + + /* backlights off until needed */ + imx_iomux_v3_setup_multiple_pads(backlight_pads, + ARRAY_SIZE(backlight_pads)); + gpio_direction_input(IMX_GPIO_NR(1, 10)); /* LVDS */ + gpio_direction_input(IMX_GPIO_NR(1, 11)); /* MIPI */ +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +static int setup_pmic_voltages(void) +{ + int ret; + unsigned char value, rev_id = 0; + + ret = i2c_set_bus_num(1); + if (ret) + return ret; + if (!i2c_probe(0x8)) { + if (i2c_read(0x8, 0, 1, &value, 1)) { + printf("Read device ID error!\n"); + return -1; + } + if (i2c_read(0x8, 3, 1, &rev_id, 1)) { + printf("Read Rev ID error!\n"); + return -1; + } + printf("PMIC: deviceid=%x, revid=%x\n", value, rev_id); + /*set VGEN1 to 1.5V and enable*/ + if (i2c_read(0x8, 0x6c, 1, &value, 1)) { + printf("Read VGEN1 error!\n"); + return -1; + } + value &= ~0x1f; + value |= 0x1e; + if (i2c_write(0x8, 0x6c, 1, &value, 1)) { + printf("Set VGEN1 error!\n"); + return -1; + } + /*set SWBST to 5.0V and enable */ + if (i2c_read(0x8, 0x66, 1, &value, 1)) { + printf("Read SWBST error!\n"); + return -1; + } + value &= ~0xf; + value |= 0x8; + if (i2c_write(0x8, 0x66, 1, &value, 1)) { + printf("Set SWBST error!\n"); + return -1; + } + } + return 0; +} + +#ifdef CONFIG_CMD_BMODE +/* BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4 + * see Table 8-11 and Table 5-9 + * BOOT_CFG1[7] = 1 (boot from NAND) + * BOOT_CFG1[5] = 0 - raw NAND + * BOOT_CFG1[4] = 0 - default pad settings + * BOOT_CFG1[3:2] = 00 - devices = 1 + * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3 + * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2 + * BOOT_CFG2[2:1] = 01 - Pages In Block = 64 + * BOOT_CFG2[0] = 0 - Reset time 12ms + */ +static const struct boot_mode board_boot_modes[] = { + /* NAND: raw, 64pages per block, 3 row addr cycles, + * 2 copies of FCB/DBBT */ + { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, + { NULL, 0 }, +}; +#endif + +/* + * Board Support + */ + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + + +/* + * very early in the call chain - setup SoC peripherals + * (NB: Can not printf from here) + */ +int board_early_init_f(void) +{ + setup_iomux_uart(); +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + gpio_direction_output(IMX_GPIO_NR(3, 22), 0); /* OTG power off */ + + /* Note this gets called again later, + * but needed in case i2c bus is stuck */ + timer_init(); + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + + return 0; +} + +#if defined(CONFIG_DISPLAY_BOARDINFO) +/* Identify board and display banner/info + */ +#define SRC_SBMR1 0x020d8004 /* holds BOOT_CFG1-BOOT_CFG4 from eFuse/pins */ +#define SRC_SBMR2 0x020d801c +#define SRC_GPR9 0x020d8040 /* holds copy of BOOT_CFG1-BOOT_CFG4 acted on */ +#define SRC_GPR10 0x020d8044 + +/* this reads boot_cfg efuse/pins - does not reflect what actually booted + */ +void show_boot_mode(uint boot_cfg) +{ + switch ((boot_cfg & 0x000000ff) >> 4) { + case 0x2: + printf("SATA"); + break; + case 0x3: + printf("SPI NOR"); + break; + case 0x4: + case 0x5: + /* BOOT_CFG2[3:4] is devno */ + printf(" SD%d", (boot_cfg & 0x00001800) >> 11); + break; + case 0x6: + case 0x7: + /* BOOT_CFG2[3:4] is devno */ + printf(" MMC%d", (boot_cfg & 0x00001800) >> 11); + break; + case 0x8 ... 0xf: + printf("NAND"); + break; + default: + printf("Unknown"); + break; + } + printf(" 0x%08x\n", boot_cfg); +} + + +int checkboard(void) +{ + struct ventana_board_info *info = &ventana_info; + uint src_sbmr2 = readl(SRC_SBMR2); + uint src_gpr10 = readl(SRC_GPR10); + + /* check for valid i2c busses - if one was 'stuck' it did not get + * initialized + */ + if (i2c_set_bus_num(0)) + printf("invalid /dev/i2c-0\n"); + if (i2c_set_bus_num(1)) + printf("invalid /dev/i2c-1\n"); + if (i2c_set_bus_num(2)) + printf("invalid /dev/i2c-2\n"); + read_eeprom(); + if (!(src_sbmr2 & 1<<4)) { + /* can consider this 'manufacturing mode' if needed */ + printf("First boot - eFUSE not blown\n"); + } + + printf("APP_IMAGE: %s\n", (src_gpr10 & 1<<30) ? + "Secondary" : "Primary"); + if (src_gpr10 & 1<<29) + printf("NAND: bad blocks in application image\n"); + +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) + printf("Env: SPI FLASH\n"); +#elif defined(CONFIG_ENV_IS_IN_MMC) + printf("Env: MMC\n"); +#elif defined(CONFIG_ENV_IS_IN_NAND) + printf("Env: NAND FLASH\n"); +#endif + + /* SRC_SBMR1 reflects eFUSE/pin */ + printf("BOOT_CFG: "); + show_boot_mode(readl(SRC_SBMR1)); + /* SRC_GPR9 reflects what was actually booted off of if not 0 + * (ie if bmode was used) */ + if (readl(SRC_GPR9)) { + printf("BMODE: "); + show_boot_mode(readl(SRC_GPR9)); + } + printf("\n"); + printf("Gateworks Corporation Copyright 2014\n"); + if (info->model[0]) { + printf("Model: %s\n", info->model); + printf("MFGDate: %02x-%02x-%02x%02x\n", + info->mfgdate[0], info->mfgdate[1], + info->mfgdate[2], info->mfgdate[3]); + printf("Serial:%d\n", info->serial); + } else { + printf("Invalid EEPROM - board will not function fully\n"); + } + + return 0; +} +#endif + +/* Set gd->ram_size + */ +int dram_init(void) +{ + struct ventana_board_info *info = &ventana_info; + + gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); + if (info->model[0] && info->sdram_size > 0 && info->sdram_size < 9) { + int i = info->sdram_size; + gd->ram_size = 32*1024*1024; + while (--i) + gd->ram_size *= 2; + } + + return 0; +} + +/* initialize periperhals + */ +int board_init(void) +{ + int ret = 0; + struct iomuxc_base_regs *const iomuxc_regs + = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; + +#ifdef CONFIG_CMD_NAND + setup_gpmi_nand(); +#endif + + clrsetbits_le32(&iomuxc_regs->gpr[1], + IOMUXC_GPR1_OTG_ID_MASK, + IOMUXC_GPR1_OTG_ID_GPIO1); + + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + + /* address of linux boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C_MXC + ret = setup_pmic_voltages(); + if (ret) + return -1; +#endif + + setup_pcie(); + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + + if (!i2c_set_bus_num(0)) { + unsigned char buf[4]; + if (!gsc_i2c_read(0x20, 14, 1, buf, 1)) { + printf("GSC: v%d", buf[0]); + if (!gsc_i2c_read(0x20, 10, 1, buf, 4)) { + /* show firmware revision and CRC */ + printf(" 0x%04x", buf[2] | buf[3]<<8); + /* show status register */ + printf(" 0x%02x", buf[0]); + /* GSC watchdog timeout */ + if (buf[0] & 0x40) { + printf(" WD_TIMEOUT"); + /* clear flag */ + buf[0] &= ~0x40; + gsc_i2c_write(0x20, 10, 1, buf, 1); + } + } + printf("\n"); + } + if (!gsc_i2c_read(0x68, 0x00, 1, buf, 4)) + printf("RTC: %d\n", + buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24); + } + +#ifdef CONFIG_CMD_GSC + /* if eFUSE not blown show GSC HWMON info */ + if (!(readl(SRC_SBMR2) & 1<<4)) { + mdelay(1500); + do_gsc(NULL, 0, 0, NULL); + } +#endif + + return ret; +} + +/* late init + */ +int misc_init_r(void) +{ + /* set env vars based on board model from EEPROM */ + if (ventana_info.model[0]) { + char str[sizeof(ventana_info.model)]; + char fdt[sizeof(ventana_info.model)+20]; + char *p; + int i; + const char *prefix = ""; + + if (is_cpu_type(MXC_CPU_MX6Q)) + prefix = "imx6q"; + else if (is_cpu_type(MXC_CPU_MX6DL)) + prefix = "imx6dl"; + + memset(str, 0, sizeof(str)); + for (i = 0; i < (sizeof(ventana_info.model)-1) && + ventana_info.model[i]; i++) + str[i] = tolower(ventana_info.model[i]); + if (!getenv("model")) + setenv("model", str); + if (!getenv("fdt_file")) { + sprintf(fdt, "%s-%s.dtb", prefix, str); + setenv("fdt_file", fdt); + } + p = strchr(str, '-'); + if (p) { + *p++ = 0; + + setenv("model_base", str); + if (!getenv("fdt_file1")) { + sprintf(fdt, "%s-%s.dtb", prefix, str); + setenv("fdt_file1", fdt); + } + str[4] = 'x'; + str[5] = 'x'; + str[6] = 0; + if (!getenv("fdt_file2")) { + sprintf(fdt, "%s-%s.dtb", prefix, str); + setenv("fdt_file2", fdt); + } + } + get_mac("ethaddr", ventana_info.mac0); + get_mac("eth1addr", ventana_info.mac1); + sprintf(str, "%6d", ventana_info.serial); + setenv("serial#", str); + setup_board_gpio(getenv("model")); + } + + /* generate a random eth mac if no EEPROM (1st boot - mfg mode) */ + else { + u32 ethaddr_low, ethaddr_high; + char str[20]; + + /* use Device Unique ID bits 0-64 from eFUSE + * (OCOTP_CFG1/OCOTP_CFG2) */ + fuse_read(0, 1, &ethaddr_low); + fuse_read(0, 2, &ethaddr_high); + + /* + * setting the 2nd LSB in the most significant byte of + * the address makes it a locally administered ethernet + * address + */ + ethaddr_high &= 0xfeff; + ethaddr_high |= 0x0200; + sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", + ethaddr_high >> 8, ethaddr_high & 0xff, + ethaddr_low >> 24, (ethaddr_low >> 16) & 0xff, + (ethaddr_low >> 8) & 0xff, ethaddr_low & 0xff); + printf("### Setting random MAC address = \"%s\"\n", str); + setenv("ethaddr", str); + } + +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + /* disable GSC boot watchdog + * + * The Gateworks System Controller implements a boot + * watchdog (always enabled) to cover things like ERR006282 which can + * lead to random boot failures. + */ + if (!i2c_set_bus_num(0)) { + unsigned char val; + if (!gsc_i2c_read(0x20, 1, 1, &val, 1)) { + val |= 0x80; + if (gsc_i2c_write(0x20, 1, 1, &val, 1)) + printf("Error: could not disable GSC Watchdog\n"); + } else { + printf("Error: could not disable GSC Watchdog\n"); + } + } + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + struct ventana_board_info *info = &ventana_info; + struct node_info nodes[] = { + { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */ + { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ + }; + const char *model = getenv("model"); + + if (getenv("fdt_noauto")) { + printf(" Skiping ft_board_setup (fdt_noauto defined)\n"); + return; + } + + /* MTD partitions + * Update partition nodes using info from mtdparts env var + */ + printf(" Updating MTD partitions...\n"); + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + + if (!model) { + printf("invalid board info: Leaving FDT fully enabled\n"); + return; + } + printf(" Adjusting FDT per EEPROM for %s...\n", model); + + /* Note that fdt_fixup_ethernet is called in arm/lib/bootm before this + * which sets mac-address and local-mac-address properties of + * ethernet<n> aliases to ethaddr...eth<n>addr env + */ + + /* board serial number */ + fdt_setprop(blob, 0, "system-serial", getenv("serial#"), + strlen(getenv("serial#") + 1)); + + /* board (model contains model from device-tree) */ + fdt_setprop(blob, 0, "board", info->model, + strlen((const char *)info->model) + 1); + + /* Peripheral Config */ + if (!info->config_eth0) + fdt_del_node_and_alias(blob, "ethernet0"); + if (!info->config_eth1) + fdt_del_node_and_alias(blob, "ethernet1"); + if (!info->config_hdmi_out) + fdt_del_node_and_alias(blob, "hdmi_out"); + if (!info->config_sata) + fdt_del_node_and_alias(blob, "ahci0"); + if (!info->config_pcie) + fdt_del_node_and_alias(blob, "pcie"); + if (!info->config_ssi0) + fdt_del_node_and_alias(blob, "ssi0"); + if (!info->config_ssi1) + fdt_del_node_and_alias(blob, "ssi1"); + if (!info->config_lcd) + fdt_del_node_and_alias(blob, "lcd0"); + if (!info->config_lvds0) + fdt_del_node_and_alias(blob, "lvds0"); + if (!info->config_lvds1) + fdt_del_node_and_alias(blob, "lvds1"); + if (!info->config_usb0) + fdt_del_node_and_alias(blob, "usb0"); + if (!info->config_usb1) + fdt_del_node_and_alias(blob, "usb1"); + if (!info->config_sd0) + fdt_del_node_and_alias(blob, "usdhc0"); + if (!info->config_sd1) + fdt_del_node_and_alias(blob, "usdhc1"); + if (!info->config_sd2) + fdt_del_node_and_alias(blob, "usdhc2"); + if (!info->config_sd3) + fdt_del_node_and_alias(blob, "usdhc3"); + if (!info->config_uart0) + fdt_del_node_and_alias(blob, "serial0"); + if (!info->config_uart1) + fdt_del_node_and_alias(blob, "serial1"); + if (!info->config_uart2) + fdt_del_node_and_alias(blob, "serial2"); + if (!info->config_uart3) + fdt_del_node_and_alias(blob, "serial3"); + if (!info->config_uart4) + fdt_del_node_and_alias(blob, "serial4"); + if (!info->config_ipu0) + fdt_del_node_and_alias(blob, "ipu0"); + if (!info->config_ipu1) + fdt_del_node_and_alias(blob, "ipu1"); + if (!info->config_flexcan) + fdt_del_node_and_alias(blob, "can0"); + if (!info->config_mipi_dsi) + fdt_del_node_and_alias(blob, "mipi_dsi"); + if (!info->config_mipi_csi) + fdt_del_node_and_alias(blob, "mipi_csi"); + if (!info->config_tzasc0) + fdt_del_node_and_alias(blob, "tzasc0"); + if (!info->config_tzasc1) + fdt_del_node_and_alias(blob, "tzasc1"); + if (!info->config_i2c0) + fdt_del_node_and_alias(blob, "i2c0"); + if (!info->config_i2c1) + fdt_del_node_and_alias(blob, "i2c1"); + if (!info->config_i2c2) + fdt_del_node_and_alias(blob, "i2c2"); + if (!info->config_vpu) + fdt_del_node_and_alias(blob, "vpu"); + if (!info->config_csi0) + fdt_del_node_and_alias(blob, "csi0"); + if (!info->config_csi1) + fdt_del_node_and_alias(blob, "csi1"); + if (!info->config_caam) + fdt_del_node_and_alias(blob, "caam"); + if (!info->config_espci0) + fdt_del_node_and_alias(blob, "spi0"); + if (!info->config_espci1) + fdt_del_node_and_alias(blob, "spi1"); + if (!info->config_espci2) + fdt_del_node_and_alias(blob, "spi2"); + if (!info->config_espci3) + fdt_del_node_and_alias(blob, "spi3"); + if (!info->config_espci4) + fdt_del_node_and_alias(blob, "spi4"); + if (!info->config_espci5) + fdt_del_node_and_alias(blob, "spi5"); + if (!info->config_hdmi_in) + fdt_del_node_and_alias(blob, "hdmi_in"); + if (!info->config_vid_out) + fdt_del_node_and_alias(blob, "cvbs_out"); + if (!info->config_vid_in) + fdt_del_node_and_alias(blob, "cvbs_in"); + if (!info->config_nand) + fdt_del_node_and_alias(blob, "nand"); + if (!info->config_gps) + fdt_del_node_and_alias(blob, "pps"); +} +#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ + diff --git a/board/gateworks/gw_ventana/gw_ventana.cfg b/board/gateworks/gw_ventana/gw_ventana.cfg new file mode 100644 index 0000000..4e07528 --- /dev/null +++ b/board/gateworks/gw_ventana/gw_ventana.cfg @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd, nand, sata + */ +#ifdef CONFIG_SPI_FLASH +BOOT_FROM spi +#else +BOOT_FROM nand +#endif + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* Memory configuration (size is overridden via eeprom config) */ +#include "ddr-setup.cfg" +#if defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 1024 + #include "1066mhz_4x128mx16.cfg" +#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 1024 + #include "800mhz_4x128mx16.cfg" +#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 512 + #include "800mhz_2x128mx16.cfg" +#else + #error "Unsupported CPU/Memory configuration" +#endif +#include "clocks.cfg" diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h new file mode 100644 index 0000000..ea6524a --- /dev/null +++ b/board/gateworks/gw_ventana/ventana_eeprom.h @@ -0,0 +1,107 @@ +/* + * ventana_eeprom.h - Gateworks Ventana EEPROM Configuration + * v1.00 + */ +#ifndef _VENTANA_EEPROM_ +#define _VENTANA_EEPROM_ + +struct ventana_board_info { + u8 mac0[6]; /* 0x00: MAC1 */ + u8 mac1[6]; /* 0x06: MAC2 */ + u8 res0[12]; /* 0x0C: reserved */ + u32 serial; /* 0x18: Serial Number (read only) */ + u8 res1[4]; /* 0x1C: reserved */ + u8 mfgdate[4]; /* 0x20: MFG date (read only) */ + u8 res2[7]; /* 0x24 */ + /* sdram config */ + u8 sdram_size; /* 0x2B: enum (512,1024,2048) MB */ + u8 sdram_speed; /* 0x2C: enum (100,133,166,200,267,333,400) MHz */ + u8 sdram_width; /* 0x2D: enum (32,64) bit */ + /* cpu config */ + u8 cpu_speed; /* 0x2E: enum (800,1000,1200) MHz */ + u8 cpu_type; /* 0x2F: enum (imx6q,imx6d,imx6dl,imx6s) */ + u8 model[16]; /* 0x30: model string */ + /* FLASH config */ + u8 nand_flash_size; /* 0x40: enum (4,8,16,32,64,128) MB */ + u8 spi_flash_size; /* 0x41: enum (4,8,16,32,64,128) MB */ + + /* Config1: SoC Peripherals */ + u8 config_eth0:1; /* 0: 0x42 */ + u8 config_eth1:1; /* 1 */ + u8 config_hdmi_out:1;/* 2 */ + u8 config_sata:1; /* 3 */ + u8 config_pcie:1; /* 4 */ + u8 config_ssi0:1; /* 5 */ + u8 config_ssi1:1; /* 6 */ + u8 config_lcd:1; /* 7 */ + + u8 config_lvds0:1; /* 0: 0x43 */ + u8 config_lvds1:1; /* 1 */ + u8 config_usb0:1; /* 2 (USB EHCI) */ + u8 config_usb1:1; /* 3 (USB OTG) */ + u8 config_sd0:1; /* 4 */ + u8 config_sd1:1; /* 5 */ + u8 config_sd2:1; /* 6 */ + u8 config_sd3:1; /* 7 */ + + u8 config_uart0:1; /* 0: 0x44 */ + u8 config_uart1:1; /* 1 */ + u8 config_uart2:1; /* 2 */ + u8 config_uart3:1; /* 3 */ + u8 config_uart4:1; /* 4 */ + u8 config_ipu0:1; /* 5 */ + u8 config_ipu1:1; /* 6 */ + u8 config_flexcan:1; /* 7 */ + + u8 config_mipi_dsi:1;/* 0: 0x45 */ + u8 config_mipi_csi:1;/* 1 */ + u8 config_tzasc0:1; /* 2 */ + u8 config_tzasc1:1; /* 3 */ + u8 config_i2c0:1; /* 4 */ + u8 config_i2c1:1; /* 5 */ + u8 config_i2c2:1; /* 6 */ + u8 config_vpu:1; /* 7 */ + + u8 config_csi0:1; /* 0: 0x46 */ + u8 config_csi1:1; /* 1 */ + u8 config_caam:1; /* 2 */ + u8 config_mezz:1; /* 3 */ + u8 config_res1:1; /* 4 */ + u8 config_res2:1; /* 5 */ + u8 config_res3:1; /* 6 */ + u8 config_res4:1; /* 7 */ + + u8 config_espci0:1; /* 0: 0x47 */ + u8 config_espci1:1; /* 1 */ + u8 config_espci2:1; /* 2 */ + u8 config_espci3:1; /* 3 */ + u8 config_espci4:1; /* 4 */ + u8 config_espci5:1; /* 5 */ + u8 config_res5:1; /* 6 */ + u8 config_res6:1; /* 7 */ + + /* Config2: Other Peripherals */ + u8 config_gps:1; /* 0: 0x48 */ + u8 config_spifl0:1; /* 1 */ + u8 config_spifl1:1; /* 2 */ + u8 config_gspbatt:1; /* 3 */ + u8 config_hdmi_in:1; /* 4 */ + u8 config_vid_out:1; /* 5 */ + u8 config_vid_in:1; /* 6 */ + u8 config_nand:1; /* 7 */ + + u8 config_res8:1; /* 0: 0x49 */ + u8 config_res9:1; /* 1 */ + u8 config_res10:1; /* 2 */ + u8 config_res11:1; /* 3 */ + u8 config_res12:1; /* 4 */ + u8 config_res13:1; /* 5 */ + u8 config_res14:1; /* 6 */ + u8 config_res15:1; /* 7 */ + + u8 res3[4]; /* 0x4A */ + + u8 chksum[2]; /* 0x4E */ +}; + +#endif diff --git a/boards.cfg b/boards.cfg index a8336cc..7784b3a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -295,6 +295,7 @@ Active arm armv7 mx6 - udoo udoo_qua Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fabio.estevam(a)freescale.com> Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam(a)freescale.com> Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam <fabio.estevam(a)freescale.com> +Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese <sr(a)denx.de> Active arm armv7 mx6 boundary nitrogen6x mx6qsabrelite nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE Eric Nelson <eric.nelson(a)boundarydevices.com> Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Eric Nelson <eric.nelson(a)boundarydevices.com> Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 Eric Nelson <eric.nelson(a)boundarydevices.com> @@ -308,7 +309,11 @@ Active arm armv7 mx6 freescale mx6qsabreauto Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam(a)freescale.com> Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam(a)freescale.com> Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam(a)freescale.com> -Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese <sr(a)denx.de> +Active arm armv7 mx6 gateworks gw_ventana gwventanaq1gspi gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024,SPI_FLASH Tim Harvey <tharvey(a)gateworks.com> +Active arm armv7 mx6 gateworks gw_ventana gwventanaq gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=512 Tim Harvey <tharvey(a)gateworks.com> +Active arm armv7 mx6 gateworks gw_ventana gwventanaq1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024 Tim Harvey <tharvey(a)gateworks.com> +Active arm armv7 mx6 gateworks gw_ventana gwventanadl gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=512 Tim Harvey <tharvey(a)gateworks.com> +Active arm armv7 mx6 gateworks gw_ventana gwventanadl1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=1024 Tim Harvey <tharvey(a)gateworks.com> Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton(a)gmail.com> Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman(a)gmail.com> Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas(a)gmail.com> diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h new file mode 100644 index 0000000..17877ed --- /dev/null +++ b/include/configs/gw_ventana.h @@ -0,0 +1,409 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" +#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO /* display cpu info */ +#define CONFIG_DISPLAY_BOARDINFO /* display board info */ + +#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */ + +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> + +/* ATAGs */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SERIAL_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +/* Init Functions */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R + +/* GPIO */ +#define CONFIG_MXC_GPIO + +/* Serial */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE + +#ifdef CONFIG_SPI_FLASH + +/* SPI */ +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF + #define CONFIG_MXC_SPI + #define CONFIG_SPI_FLASH_MTD + #define CONFIG_SPI_FLASH_BAR + #define CONFIG_SPI_FLASH_WINBOND + #define CONFIG_SPI_FLASH_WINBOND_ERASESIZE 64*1024 /* 4,32,64K for W26Q256 */ + #define CONFIG_SF_DEFAULT_BUS 0 + #define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8)) + /* GPIO 3-19 (21248) */ + #define CONFIG_SF_DEFAULT_SPEED 30000000 + #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif + +/* Flattened Image Tree Suport */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE + +#else +/* Enable NAND support */ +#define CONFIG_CMD_TIME +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS +#ifdef CONFIG_CMD_NAND + #define CONFIG_NAND_MXS + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_BASE 0x40000000 + #define CONFIG_SYS_NAND_5_ADDR_CYCLE + #define CONFIG_SYS_NAND_ONFI_DETECTION + + /* DMA stuff, needed for GPMI/MXS NAND support */ + #define CONFIG_APBH_DMA + #define CONFIG_APBH_DMA_BURST + #define CONFIG_APBH_DMA_BURST8 +#endif + +#endif /* CONFIG_SPI_FLASH */ + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER + +/* Filesystem support */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_UBIFS +#define CONFIG_DOS_PARTITION + +/* Network config - Allow larger/faster download for TFTP/NFS */ +#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE 4096 +#define CONFIG_NFS_READ_SIZE 4096 + +#ifdef CONFIG_MX6Q +#define CONFIG_CMD_SATA +#endif + +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA + #define CONFIG_DWC_AHSATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_DWC_AHSATA_PORT_ID 0 + #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR + #define CONFIG_LBA48 + #define CONFIG_LIBATA +#endif + +/* Various command support */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_BMODE /* set eFUSE shadow for a boot dev and reset */ +#define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */ +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_GSC +#define CONFIG_CMD_UBI +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_FUSE /* eFUSE read/write support */ +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + + +/* Ethernet support */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_ARP_TIMEOUT 200UL + +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_KEYBOARD +#define CONFIG_MV_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_CDC +#define CONFIG_NETCONSOLE +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP +#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 1200 + +/* Framebuffer and LCD */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CONSOLE_MUX +#define CONFIG_IMX_HDMI + +/* serial console (ttymxc1,115200) */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "Ventana > " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_HWCONFIG + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Memory configuration */ +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 +#define CONFIG_SYS_LOAD_ADDR 0x12000000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH /* no NOR flash */ + +/* + * MTD Command for mtdparts + */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#ifdef CONFIG_SPI_FLASH +#define MTDIDS_DEFAULT "nor0=nor" +#define MTDPARTS_DEFAULT "mtdparts=nor:512k(uboot),64k(env),2m(kernel),-(rootfs)" +#else +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)" +#endif + +/* Persistent Environment Config */ +#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ +#ifdef CONFIG_SPI_FLASH +#define CONFIG_ENV_IS_IN_SPI_FLASH +#else +#define CONFIG_ENV_IS_IN_NAND +#endif +#if defined(CONFIG_ENV_IS_IN_MMC) + #define CONFIG_ENV_OFFSET (6 * 64 * 1024) + #define CONFIG_ENV_SIZE (8 * 1024) + #define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_ENV_IS_IN_NAND) + #define CONFIG_ENV_OFFSET (16 << 20) + #define CONFIG_ENV_SECT_SIZE (128 << 10) + #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 << 10)) + #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) + #define CONFIG_ENV_OFFSET (512 * 1024) + #define CONFIG_ENV_SECT_SIZE (64 * 1024) + #define CONFIG_ENV_SIZE (8 * 1024) + #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS + #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS + #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE + #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +/* Environment */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_IPADDR 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.146 + +#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "console=ttymxc1\0" \ + "bootdevs=usb mmc sata flash\0" \ + "hwconfig=rs232;dio0:mode=gpio;dio1:mode=gpio;dio2:mode=gpio;dio3:mode=gpio\0" \ + "video=\0" \ + \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + \ + "fdt_high=0xffffffff\0" \ + "fdt_addr=0x18000000\0" \ + "loadfdt=" \ + "if ${fsload} ${fdt_addr} boot/${fdt_file}; then " \ + "echo Loaded DTB from boot/${fdt_file}; " \ + "elif ${fsload} ${fdt_addr} boot/${fdt_file1}; then " \ + "echo Loaded DTB from boot/${fdt_file1}; " \ + "elif ${fsload} ${fdt_addr} boot/${fdt_file2}; then " \ + "echo Loaded DTB from boot/${fdt_file2}; " \ + "fi\0" \ + \ + "script=boot/6x_bootscript-ventana\0" \ + "loadscript=" \ + "if ${fsload} ${loadaddr} ${script}; then " \ + "source; " \ + "fi\0" \ + \ + "uimage=boot/uImage\0" \ + "mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \ + "mmc_boot=" \ + "setenv fsload 'ext2load mmc 0:1'; " \ + "mmc dev 0 && mmc rescan && " \ + "run loadscript; " \ + "if ${fsload} ${loadaddr} ${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw ${video} ${extra}; " \ + "if run loadfdt && fdt addr ${fdt_addr}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "bootm; " \ + "fi; " \ + "fi\0" \ + \ + "sata_boot=" \ + "setenv fsload 'ext2load sata 0:1'; sata init && " \ + "run loadscript; " \ + "if ${fsload} ${loadaddr} ${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/sda1 rootfstype=ext4 rootwait rw ${video} ${extra}; " \ + "if run loadfdt && fdt addr ${fdt_addr}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "bootm; " \ + "fi; " \ + "fi\0" \ + "usb_boot=" \ + "setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \ + "run loadscript; " \ + "if ${fsload} ${loadaddr} ${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/sda1 rootfstype=ext4 rootwait rw ${video} ${extra}; " \ + "if run loadfdt && fdt addr ${fdt_addr}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "bootm; " \ + "fi; " \ + "fi\0" + +#ifdef CONFIG_SPI_FLASH + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \ + "image_uboot=ventana/u-boot_spi.imx\0" \ + \ + "spi_koffset=0x90000\0" \ + "spi_klen=0x200000\0" \ + \ + "spi_updateuboot=echo Updating uboot from ${serverip}:${image_uboot} ...; " \ + "tftpboot ${loadaddr} ${image_uboot} && " \ + "sf probe && sf erase 0 80000 && sf write ${loadaddr} 400 ${filesize}\0" \ + "spi_update=echo Updating OS from ${serverip}:${image_os} to ${spi_koffset} ...; " \ + "tftp ${loadaddr} ${image_os} && " \ + "sf probe && sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \ + \ + "flash_boot=" \ + "if sf probe && sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/mtdblock3 rootfstype=squashfs,jffs2 ${video} ${extra}; " \ + "bootm; " \ + "fi\0" +#else + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ + \ + "nand_update=echo Updating NAND from ${serverip}:${image_rootfs} ...; " \ + "tftp ${loadaddr} ${image_rootfs} && " \ + "nand erase.part rootfs && " \ + "nand write ${loadaddr} rootfs ${filesize}\0" \ + \ + "flash_boot=" \ + "setenv fsload 'ubifsload'; " \ + "ubi part rootfs && ubifsmount ubi0:rootfs; " \ + "run loadscript; " \ + "if ${fsload} ${loadaddr} ${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=ubi0:rootfs ubi.mtd=2 rootfstype=ubifs ${video} ${extra}; " \ + "if run loadfdt && fdt addr ${fdt_addr}; then " \ + "ubifsumount; bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "ubifsumount; bootm; " \ + "fi; " \ + "fi\0" +#endif + +#define CONFIG_BOOTCOMMAND \ + "for btype in ${bootdevs}; do " \ + "echo; echo Attempting ${btype} boot...; " \ + "if run ${btype}_boot; then; fi; " \ + "done" + +/* Device Tree Support */ +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_LIBFDT +#define CONFIG_FDT_FIXUP_PARTITIONS + +#ifndef CONFIG_SYS_DCACHE_OFF + #define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H */ -- 1.8.4.2

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[U-Boot] [PATCH] net/bootp: add CONFIG_BOOTP_BOOTFILE
by Christian Gmeiner 29 Jan '14

29 Jan '14

In some cases the TFTP server provides a bootfile name, which does not expects our requirements. Make it possible to not store the TFTP provided bootfile in the environment. Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- README | 4 ++++ net/bootp.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/README b/README index aea82be..dc5c153 100644 --- a/README +++ b/README @@ -1921,6 +1921,10 @@ CBFS (Coreboot Filesystem) support CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip environment variable, not the BOOTP server. + CONFIG_BOOTP_BOOTFILE - TFTP bootfile will be the bootfile + environment variable, not the filename provided by + BOOTP server. + CONFIG_BOOTP_MAY_FAIL - If the DHCP server is not found after the configured retry count, the call will fail instead of starting over. This can be used to fail over diff --git a/net/bootp.c b/net/bootp.c index 4300f1c..5e76827 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -106,6 +106,7 @@ static void BootpCopyNetParams(struct Bootp_t *bp) memcpy(NetServerEther, ((struct ethernet_hdr *)NetRxPacket)->et_src, 6); #endif NetCopyIP(&NetOurIP, &bp->bp_yiaddr); +#if !defined(CONFIG_BOOTP_BOOTFILE) if (strlen(bp->bp_file) > 0) copy_filename(BootFile, bp->bp_file, sizeof(BootFile)); @@ -117,6 +118,7 @@ static void BootpCopyNetParams(struct Bootp_t *bp) */ if (*BootFile) setenv("bootfile", BootFile); +#endif } static int truncate_sz(const char *name, int maxlen, int curlen) -- 1.7.10.4

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Re: [U-Boot] MAKEALL
by Anatolij Gustschin 29 Jan '14

29 Jan '14

first, please keep mailing list in CC. On Wed, 29 Jan 2014 12:56:55 +0530 JYOTI DUBEY <jyoti0801(a)gmail.com> wrote: > How can I compile u-boot for arm processor and nitrogen6x board? install armv7a cross toolchain and setup the environment for cross compiling, then run ./MAKEALL nitrogen6q There are another targets for nitrogen6 board variants with more DRAM and/or dual or solo CPU: nitrogen6q2g, nitrogen6dl, nitrogen6dl2g, nitrogen6s, nitrogen6s1g. So, use what is suitable for your board variant. HTH, Anatolij

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[U-Boot] MAKEALL
by JYOTI DUBEY 29 Jan '14

29 Jan '14

What is the use of executing MAKEALL file available in u-boot folder?

2 1