September 2013 - U-Boot

[U-Boot] [PATCH 0/5] ARM: Exynos5250: consolidate configuration files
by Andre Przywara 05 Dec '13

05 Dec '13

Hi, while working on HYP mode support for Exynos 5250 based boards, I fixed some shortcomings in their configuration files. The purpose of this series is to get rid of the elaborate arndale.h and replace it mostly by an include of exynos5250-dt.h, which currently has an about 90% overlap. I couldn't find any prior art, please bear with me if I have missed something on the list. * Patch 1 fixes a bug, where PMIC support would not have been included in the Arndale build. * Patch 2 removes double definitions. Those two should be considered regardless of the others. * Patch 3 prepares the consolidation of the config files by moving board specific defines out of the generic file. * Patch 4 makes keyboard and LCD support board dependent, please have a closer look at this. I guess SMDK5250 does not have the EC, but it breaks compilation if that is excluded. * Patch 5 then finally removes the now redundant defines in arndale.h and replaces them with an include of exynos5250-dt.h. This series is mostly refactoring, though the config options change a bit for some boards. I could only compile test it, so please test it if you have the hardware. Thanks! Andre Signed-off-by: Andre Przywara <andre.przywara(a)linaro.org> Andre Przywara (5): ARM: Exynos5250: rename obsoleted CONFIG_PMIC defines ARM: Exynos5250: remove redundant defines in exynos5250-dt.h ARM: Exynos5250: move feature defines out of generic config file ARM: snow: move defines for Chromebook embedded controller ARM: Arndale: include generic exynos5250-dt.h in arndale.h drivers/power/power_fsl.c | 2 +- include/configs/arndale.h | 242 +--------------------------------------- include/configs/exynos5250-dt.h | 63 ++++------- include/configs/smdk5250.h | 11 +- include/configs/snow.h | 11 +- 5 files changed, 47 insertions(+), 282 deletions(-) -- 1.7.12.1

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[U-Boot] [PATCH] powerpc/c29xpcie: Getting DDR SPD image from 16-bit sub-address EEPROM
by Po Liu 05 Dec '13

05 Dec '13

Currently, there is only one EEPROM on c29xpcie board which isAT24C1024. We program the SPD data at beginning of the AT24C1024.But the AT24C1024 has a 16-bit sub-address mode. This patch is tomake it work when getting SPD in a 16-bit sub-address EEPROM. Signed-off-by: Po Liu <Po.Liu(a)freescale.com> --- board/freescale/c29xpcie/ddr.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c index 3337d6c..28f1bd2 100644 --- a/board/freescale/c29xpcie/ddr.c +++ b/board/freescale/c29xpcie/ddr.c @@ -84,3 +84,15 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; } } + +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret = i2c_read(i2c_address, 0, 2, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); + + if (ret) { + printf("DDR: failed to read SPD from address %u\n", + i2c_address); + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +} -- 1.8.0

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[U-Boot] [PATCH v4] socfpga: Adding Freeze Controller driver
by Chin Liang See 02 Dec '13

02 Dec '13

Adding Freeze Controller driver. All HPS IOs need to be in freeze state during pin mux or IO buffer configuration. It is to avoid any glitch which might happen during the configuration from propagating to external devices. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Wolfgang Denk <wd(a)denx.de> CC: Pavel Machek <pavel(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)altera.com> --- Changes for v4 - Removed additional lines - Single function call to freeze and thaw all channels Changes for v3 - Removed unused macro in freeze_controller.h Changes for v2 - Removed FREEZE_CONTROLLER_FSM_HW - Removed the get_timer_count_masked and convert to use delay in us - Used shorter local variables --- arch/arm/cpu/armv7/socfpga/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/freeze_controller.c | 216 ++++++++++++++++++++ arch/arm/cpu/armv7/socfpga/spl.c | 9 + .../include/asm/arch-socfpga/freeze_controller.h | 50 +++++ 4 files changed, 276 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/freeze_controller.c create mode 100644 arch/arm/include/asm/arch-socfpga/freeze_controller.h diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 0859e44..10d20f2 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -14,7 +14,7 @@ LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o COBJS-y := misc.o timer.o reset_manager.o system_manager.o -COBJS-$(CONFIG_SPL_BUILD) += spl.o +COBJS-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/arch/arm/cpu/armv7/socfpga/freeze_controller.c new file mode 100644 index 0000000..330b4aa --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c @@ -0,0 +1,216 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/freeze_controller.h> +#include <asm/arch/timer.h> +#include <asm/errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_freeze_controller *freeze_controller_base = + (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS); + +/* + * Default state from cold reset is FREEZE_ALL; the global + * flag is set to TRUE to indicate the IO banks are frozen + */ +static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM] + = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN, + FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN}; + +/* Freeze HPS IOs */ +void sys_mgr_frzctrl_freeze_req(void) +{ + u32 ioctrl_reg_offset; + u32 reg_value; + u32 reg_cfg_mask; + u32 channel_id; + + /* select software FSM */ + writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); + + /* Freeze channel 0 to 2 */ + for (channel_id = 0; channel_id <= 2; channel_id++) { + ioctrl_reg_offset = (u32)( + &freeze_controller_base->vioctrl + + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + + /* + * Assert active low enrnsl, plniotri + * and niotri signals + */ + reg_cfg_mask = + SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK + | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK; + clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * Assert active low bhniotri signal and de-assert + * active high csrdone + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK; + clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* Set global flag to indicate channel is frozen */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN; + } + + /* Freeze channel 3 */ + /* + * Assert active low enrnsl, plniotri and + * niotri signals + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK + | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK; + clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); + + /* + * assert active low bhniotri & nfrzdrv signals, + * de-assert active high csrdone and assert + * active high frzreg and nfrzdrv signals + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK; + reg_value + = (reg_value & ~reg_cfg_mask) + | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK + | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* + * assert active high reinit signal and de-assert + * active high pllbiasen signals + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_value + = (reg_value & + ~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK) + | SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* Set global flag to indicate channel is frozen */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN; +} + +/* Unfreeze/Thaw HPS IOs */ +void sys_mgr_frzctrl_thaw_req(void) +{ + u32 ioctrl_reg_offset; + u32 reg_cfg_mask; + u32 reg_value; + u32 channel_id; + + /* select software FSM */ + writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); + + /* Thaw channel 0 to 2 */ + for (channel_id = 0; channel_id <= 2; channel_id++) { + ioctrl_reg_offset + = (u32)(&freeze_controller_base->vioctrl + + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + + /* + * Assert active low bhniotri signal and + * de-assert active high csrdone + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK; + setbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * de-assert active low plniotri and niotri signals + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK; + setbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * de-assert active low enrnsl signal + */ + setbits_le32(ioctrl_reg_offset, + SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK); + + /* Set global flag to indicate channel is thawed */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED; + } + + /* Thaw channel 3 */ + /* de-assert active high reinit signal */ + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK); + + /* + * Note: Delay for 40ns at min + * assert active high pllbiasen signals + */ + setbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK); + + /* + * Delay 1000 intosc. intosc is based on eosc1 + * Use worst case which is fatest eosc1=50MHz, delay required + * is 1/50MHz * 1000 = 20us + */ + udelay(20); + + /* + * de-assert active low bhniotri signals, + * assert active high csrdone and nfrzdrv signal + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_value = (reg_value + | SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK) + & ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* + * Delay 33 intosc + * Use worst case which is fatest eosc1=50MHz, delay required + * is 1/50MHz * 33 = 660ns ~= 1us + */ + udelay(1); + + /* de-assert active low plniotri and niotri signals */ + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK; + + setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); + + /* + * Note: Delay for 40ns at min + * de-assert active high frzreg signal + */ + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK); + + /* + * Note: Delay for 40ns at min + * de-assert active low enrnsl signal + */ + setbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK); + + /* Set global flag to indicate channel is thawed */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED; +} + diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 74bceab..36a00c3 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -13,6 +13,7 @@ #include <asm/arch/reset_manager.h> #include <spl.h> #include <asm/arch/system_manager.h> +#include <asm/arch/freeze_controller.h> DECLARE_GLOBAL_DATA_PTR; @@ -27,6 +28,10 @@ u32 spl_boot_device(void) void spl_board_init(void) { #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET + debug("Freezing all I/O banks\n"); + /* freeze all IO banks */ + sys_mgr_frzctrl_freeze_req(); + /* configure the pin muxing through system manager */ sysmgr_pinmux_init(); #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ @@ -34,6 +39,10 @@ void spl_board_init(void) /* de-assert reset for peripherals and bridges based on handoff */ reset_deassert_peripherals_handoff(); + debug("Unfreezing/Thaw all I/O banks\n"); + /* unfreeze / thaw all IO banks */ + sys_mgr_frzctrl_thaw_req(); + /* enable console uart printing */ preloader_console_init(); } diff --git a/arch/arm/include/asm/arch-socfpga/freeze_controller.h b/arch/arm/include/asm/arch-socfpga/freeze_controller.h new file mode 100644 index 0000000..120f20e --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/freeze_controller.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FREEZE_CONTROLLER_H_ +#define _FREEZE_CONTROLLER_H_ + +struct socfpga_freeze_controller { + u32 vioctrl; + u32 padding[3]; + u32 hioctrl; + u32 src; + u32 hwctrl; +}; + +#define FREEZE_CHANNEL_NUM (4) + +typedef enum { + FREEZE_CTRL_FROZEN = 0, + FREEZE_CTRL_THAWED = 1 +} FREEZE_CTRL_CHAN_STATE; + +#define SYSMGR_FRZCTRL_ADDRESS 0x40 +#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0 +#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1 +#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010 +#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008 +#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004 +#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002 +#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010 +#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008 +#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004 +#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002 +#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080 +#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040 +#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100 +#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1 +#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2 + +void sys_mgr_frzctrl_freeze_req(void); +void sys_mgr_frzctrl_thaw_req(void); + +#endif /* _FREEZE_CONTROLLER_H_ */ -- 1.7.9.5

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[U-Boot] Pull request for u-boot-marvell.git
by Prafulla Wadaskar 01 Dec '13

01 Dec '13

Hi Albert, Please kindly pull The following changes since commit 12eba1b49380988fd87cc0b3af44014cca8b71c4: Jeroen Hofstee (1): README: update ARM register usage are available in the git repository at: u-boot-marvell.git master branch. Holger Brunck (2): arm/km: drop unneeded define arm/km: make local function startup_allowed static Karlheinz Jerg (1): arm/km: add support for km_kirkwood_128m16 board board/keymile/km_arm/km_arm.c | 6 +----- boards.cfg | 1 + include/configs/km_kirkwood.h | 10 ++++++++++ 3 files changed, 12 insertions(+), 5 deletions(-) Regards... Prafulla . . .

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[U-Boot] Getting U-Boot running on Toradex Colibri T20 on Iris board
by Andrzej Telszewski 25 Nov '13

25 Nov '13

Hi, I'm trying to get the U-Boot running on the Iris board with the Toradex Colibri T20 module. I was able to flash the U-Boot and it starts but then immediately stops with the only message being: U-Boot 2013.07 (Aug 06 2013 - 17:47:43) TEGRA20 Board: Toradex Colibri T20 on Iris DRAM: The Colibri T20 board used is: 256MB RAM V1.2A Could you please give me any idea what I might be doing wrong? -- Best regards, Andrzej Telszewski Embedded Systems Developer Versa Design S.L. phone: +34 633 535 308 e-mail: atelszewski(a)versades.com

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[U-Boot] [PATCH] p1010rdb: enable mtdparts for NAND
by Zhao Qiang 25 Nov '13

25 Nov '13

The default partition table matches the .dts files for these boards in Linux. This allows these partitions to be used by name with U-Boot's "nand" command. Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- include/configs/P1010RDB.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f0d6c8b..5864402 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -329,6 +329,13 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #endif +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITION +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nand0=ff800000.flash" +#define MTDPARTS_DEFAULT \ + "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" + #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ -- 1.8.0

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[U-Boot] Pull request - arm/zynq v3
by Michal Simek 24 Nov '13

24 Nov '13

Hi Albert, please pull these 3 zynq patches to your arm tree. I have rebased the tree on the 2013.07 to remove that new nds32 patches. There is still pending the arm: lds: Remove libgcc eabi exception handling tables patch. Have you considered to also add it? v3: - Rebase on the v2013.07 because Albert didn't want to nds32 stuff v2: - Changed email address, - There was incorrect rebase which I have fixed - correct sha1 now Thanks. Michal The following changes since commit 62c175fbb8a0f9a926c88294ea9f7e88eb898f6c: Prepare v2013.07 (2013-07-23 07:58:13 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git zynq for you to fetch changes up to 037e0d25c6ee6367beca3062759993d10759dff2: zynq: Enable axi ethernet and emaclite driver initialization (2013-08-19 09:32:00 +0200) ---------------------------------------------------------------- Michal Simek (3): zynq: Add new ddrc driver for ECC support zynq: slcr: Wait 100ms till clk is properly setup zynq: Enable axi ethernet and emaclite driver initialization arch/arm/cpu/armv7/zynq/Makefile | 1 + arch/arm/cpu/armv7/zynq/ddrc.c | 50 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/zynq/slcr.c | 2 +- arch/arm/include/asm/arch-zynq/hardware.h | 8 +++++ arch/arm/include/asm/arch-zynq/sys_proto.h | 1 + board/xilinx/zynq/board.c | 19 ++++++++++++ 6 files changed, 80 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/zynq/ddrc.c -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform

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[U-Boot] FW: [PATCH 1/2] drivers/net/designware, do an explicit memory access instead of implicit, re-written assignments to use readl() and writel(), all of this as preperation for making the driver able to work in a cached environment (I$D$ support).
by Frank Dols 22 Nov '13

22 Nov '13

[[ ... to get attention again ... see below ...]] On 2/8/2013 6:22 PM, Frank Dols wrote: > Good afternoon Vipin and Albert, > I where wondering, is there any review/update news on the patches I submitted a short while ago? > Regards, Frank. > Sorry, first excluded " u-boot(a)lists.denx.de" from this email to prevent from noice on mailing list. > There is no reason to remove the list. This is not noise I believe. Infact by including the list, you are intimating other developers that such work would be available soon Albert, do you think any different. > Sorry, I have to clarify here a bit more. > The descriptors are 16 bytes in length and a cache line is in most architectures more than 16 bytes in length (in our case either 32 or 64). > This means that cached accesses is not an option for these descriptors. Background, two adjacent descriptors as be on one cache line may be owned by different entities (host cpu / network ip). Yes, this is a problem and I can't think of a clean solution. Specially because u-boot (as of today) does not support non-cached memory Albert? > Explicit cache calls that we are added in patch 2/2 are meant for payload of the package. And these are made cache line aligned with patch 1/2. Yes, that is what I thought > Unfortunately we can't align the descriptors on cache line boundaries due to hardware limitations (for architectures with cache line longer than 16 bytes) ! Yes, I know that. The descriptors are 16 bytes and they need to be contiguous in memory PS: I have not added the list but I strongly feel that this mail should also go to the uboot list -Vipin > With kind regards, greetings, Frank. > >

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[U-Boot] [PATCH] mii: dump: parameter choice
by Stephan Bauroth 21 Nov '13

21 Nov '13

Hi all, since no one commented on my prior mail, i just took the liberty to write a little patch that chooses regs 0-5 if none are specified for 'mii dump'. Also fixes some alignment issues, typos and introduces the 'Selector Field' to the register description of PHY regs 4 and 5. On top, 'mii dump' now prints the PHY address in front of a register dump. this is my first patch, if anything is wrong, plese tell me :) diff --git a/common/cmd_mii.c b/common/cmd_mii.c index d3dd6b1..1856c5b 100644 --- a/common/cmd_mii.c +++ b/common/cmd_mii.c @@ -78,9 +78,9 @@ static const MII_field_desc_t reg_3_desc_tbl[] = { static const MII_field_desc_t reg_4_desc_tbl[] = { { 15, 15, 0x01, "next page able" }, - { 14, 14, 0x01, "reserved" }, + { 14, 14, 0x01, "(reserved)" }, { 13, 13, 0x01, "remote fault" }, - { 12, 12, 0x01, "reserved" }, + { 12, 12, 0x01, "(reserved)" }, { 11, 11, 0x01, "asymmetric pause" }, { 10, 10, 0x01, "pause enable" }, { 9, 9, 0x01, "100BASE-T4 able" }, @@ -88,7 +88,7 @@ static const MII_field_desc_t reg_4_desc_tbl[] = { { 7, 7, 0x01, "100BASE-TX able" }, { 6, 6, 0x01, "10BASE-T full duplex able" }, { 5, 5, 0x01, "10BASE-T able" }, - { 4, 0, 0x1f, "xxx to do" }, + { 4, 0, 0x1f, "Selector Field" }, }; static const MII_field_desc_t reg_5_desc_tbl[] = { @@ -103,7 +103,7 @@ static const MII_field_desc_t reg_5_desc_tbl[] = { { 7, 7, 0x01, "100BASE-TX able" }, { 6, 6, 0x01, "10BASE-T full duplex able" }, { 5, 5, 0x01, "10BASE-T able" }, - { 4, 0, 0x1f, "xxx to do" }, + { 4, 0, 0x1f, "Selctor Field" }, }; typedef struct _MII_field_desc_and_len_t { const MII_field_desc_t *pdesc; @@ -130,6 +130,7 @@ static int special_field( ushort regval); static void MII_dump_0_to_5( + unsigned char addr, ushort regvals[6], uchar reglo, uchar reghi) @@ -138,6 +139,7 @@ static void MII_dump_0_to_5( for (i = 0; i < 6; i++) { if ((reglo <= i) && (i <= reghi)) + printf("%02x.", addr); dump_reg(regvals[i], &reg_0_5_desc_tbl[i], &desc_and_len_tbl[i]); } @@ -218,7 +220,7 @@ static int special_field( else if ((regno == MII_ADVERTISE) && (pdesc->lo == 0)) { ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask; - printf("%2u-%2u = %5u selector = %s", + printf("%2u-%2u = %5u Selector Field = %s", pdesc->hi, pdesc->lo, sel_bits, sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3" : @@ -230,7 +232,7 @@ static int special_field( else if ((regno == MII_LPA) && (pdesc->lo == 0)) { ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask; - printf("%2u-%2u = %u selector = %s", + printf("%2u-%2u = %5u Selector Field = %s", pdesc->hi, pdesc->lo, sel_bits, sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3" : @@ -384,6 +386,10 @@ static int do_mii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) "standard MII registers, 0-5.\n"); return 1; } + if (argc < 4){ /* no reg-range given -> dump 0 to 5 */ + reglo = 0; + reghi = 5; + } for (addr = addrlo; addr <= addrhi; addr++) { for (reg = reglo; reg < reghi + 1; reg++) { if (miiphy_read(devname, addr, reg, &regs[reg]) != 0) { @@ -394,8 +400,9 @@ static int do_mii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) rcode = 1; } } - if (ok) - MII_dump_0_to_5(regs, reglo, reghi); + if (ok) { + MII_dump_0_to_5(addr, regs, reglo, reghi); + } printf("\n"); } } else if (strncmp(op, "de", 2) == 0) {

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[U-Boot] [PATCH v2 0/3] mtd: nand: omap: add support for BCH16_ECC
by Pekon Gupta 20 Nov '13

20 Nov '13

*changes in v2* - rebased for http://lists.denx.de/pipermail/u-boot/2013-September/162107.html - minor code cleanup *original v1* This patch series add support of BCH16_ECC scheme. As BCH16_ECC scheme generates 26bytes of ECC syndrome per 512B data, hence this scheme is usable only for NAND devices having 4K or above page-size, as their OOB/spare area has enough space to accomodate ECC. This patch series is applicable over an above following series: http://lists.denx.de/pipermail/u-boot/2013-September/161859.html Pekon Gupta (3): [PATCH 1/3] am33xx: elm: add support for BCH16_ECC - ELM driver updates [PATCH 2/3] mtd: nand: omap: add support for BCH16_ECC - NAND driver updates [PATCH 3/3] am335x: update README for BCH16 arch/arm/cpu/armv7/am33xx/elm.c | 95 ++++++++++++++++++---------- arch/arm/include/asm/arch-am33xx/cpu.h | 15 ++++- arch/arm/include/asm/arch-am33xx/elm.h | 16 ++--- arch/arm/include/asm/arch-am33xx/omap_gpmc.h | 4 +- board/ti/am335x/README | 43 ++++++++++++- drivers/mtd/nand/omap_gpmc.c | 87 ++++++++++++++++++++----- include/mtd/mtd-abi.h | 3 +- 7 files changed, 200 insertions(+), 63 deletions(-) -- 1.8.1

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