September 2013 - U-Boot

[U-Boot] [PATCH] drivers/net/designware - respect "bus mode" register contents on SW reset
by Alexey Brodkin 26 Sep '13

26 Sep '13

"bus mode" register contains lots of fields and some of them don't expect to be written with 0 (zero). So since we're only interested in resetting MAC (which is done with setting the least significant bit of this register with "0") I believe it's better to modify only 1 bit of the register. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> --- drivers/net/designware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 46f6601..f11cb0b 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -112,7 +112,7 @@ static int mac_reset(struct eth_device *dev) ulong start; int timeout = CONFIG_MACRESET_TIMEOUT; - writel(DMAMAC_SRST, &dma_p->busmode); + writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); if (priv->interface != PHY_INTERFACE_MODE_RGMII) writel(MII_PORTSELECT, &mac_p->conf); -- 1.8.1.2

2 1

[U-Boot] NAND crazy behavior - mtd->size changing without clear reason
by Otavio Salvador 26 Sep '13

26 Sep '13

Hello, I am using a K9LBG08U0D-PCB0 NAND IC with the i.MX28EVK board. I tested it with 2013.04 and current imx tree tip. Both same results. I am having problems to use mtdparts with it as it thinks the NAND has size as 0 when it gets there. /However/ it properly detects it initially and the mtd->size variable is magically changes on the fly. I added following patch in my local tree to debug the issue: diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index 4cf4c1c..03faf10 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -66,11 +66,14 @@ int nand_register(int devnum) add_mtd_device(mtd); #endif + printf("%s (%d) mtd->size: %d\n", __FUNCTION__, __LINE__, mtd->size); total_nand_size += mtd->size / 1024; + printf("%s (%d) mtd->size: %d\n", __FUNCTION__, __LINE__, mtd->size); if (nand_curr_device == -1) nand_curr_device = devnum; + printf("%s (%d) mtd->size: %d\n", __FUNCTION__, __LINE__, mtd->size); return 0; } @@ -94,7 +97,9 @@ static void nand_init_chip(int i) if (nand_scan(mtd, maxchips)) return; + printf("%s (%d) mtd->size: %d\n", __FUNCTION__, __LINE__, mtd->size); nand_register(i); + printf("%s (%d) mtd->size: %d\n", __FUNCTION__, __LINE__, mtd->size); } #endif diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 07f88ca..1083a88 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -90,6 +90,8 @@ #define CONFIG_LZO #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEBUG +#define CONFIG_MTD_DEBUG_VERBOSE 1 #define MTDIDS_DEFAULT "nand0=gpmi-nand" #define MTDPARTS_DEFAULT \ "mtdparts=gpmi-nand:" \ and what surprises me is the U-Boot log using the above patch: U-Boot 2013.10-rc2-00159-g06f700a-dirty (Sep 25 2013 - 09:17:17) CPU: Freescale i.MX28 rev1.2 at 454 MHz BOOT: NAND, 3V3 DRAM: 128 MiB NAND: NAND device: Manufacturer ID: 0xec, Chip ID: 0xd7 (Samsung NAND 4GiB 3,3V 8-bit), page size: 4096, OOB size: 218 nand_init_chip (100) mtd->size: 1 nand_register (69) mtd->size: 0 nand_register (71) mtd->size: 4194304 nand_register (76) mtd->size: 1 nand_init_chip (102) mtd->size: 1 4096 MiB MMC: MXS MMC: 0 Video: MXSFB: 'videomode' variable not set! In: serial Out: serial Err: serial Net: FEC0 [PRIME], FEC1 So the mtd->size value has change from 0 to 4194304 in the code: int nand_register(int devnum) { ... printf("%s (%d) mtd->size: %d\n", __FUNCTION__, __LINE__, mtd->size); total_nand_size += mtd->size / 1024; printf("%s (%d) mtd->size: %d\n", __FUNCTION__, __LINE__, mtd->size); ... } and when it gets in the mtdparts code it is '0' thus resulting in the error: MX28EVK U-Boot > mtdparts default gpmi-nand: partitioning exceeds flash size Does someone has a clue about what is going on? -- Otavio Salvador O.S. Systems http://www.ossystems.com.br http://code.ossystems.com.br Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750

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[U-Boot] [PATCH 1/1] am33xx: add CONFIG_SYS_NAND_DEVICE_WIDTH to determine NAND device bus-width
by Pekon Gupta 26 Sep '13

26 Sep '13

NAND driver needs to know bus-width of the connected NAND device, in order to perform proper I/O and initialize itself. Currently there is no CONFIG option to provide this information to NAND driver. - SPL NAND driver does not have framework to parse ONFI parameter page. - NAND drivers which cannot self initialize !defined(CONFIG_SYS_NAND_SELF_INIT) do not have any information about device bus-width during board_nand_init(), So, any device-width specific configurations are not possible there. - There should be some mechanism to pass device bus-width information for non-ONFI compliant devices. This patch (1) adds CONFIG_SYS_NAND_DEVICE_WIDTH which can take following value 16: NAND device with x16 bus-width 8: NAND device with x8 bus-width (2) removes GPMC_NAND_ECC_LP_x16_LAYOUT, as NAND layout is determined based on ecc-scheme and oobsize during initialization in board_nand_init(). Thus this config is redundant. Signed-off-by: Pekon Gupta <pekon(a)ti.com> --- doc/README.nand | 9 +++++++++ drivers/mtd/nand/omap_gpmc.c | 18 +++++++++++------- include/configs/am335x_evm.h | 2 +- include/configs/am3517_crane.h | 2 +- include/configs/am3517_evm.h | 2 +- include/configs/cm_t35.h | 2 -- include/configs/devkit8000.h | 3 +-- include/configs/dig297.h | 2 -- include/configs/igep0033.h | 8 ++++---- include/configs/igep00x0.h | 2 +- include/configs/mcx.h | 2 +- include/configs/omap3_beagle.h | 3 +-- include/configs/omap3_evm_common.h | 1 - include/configs/omap3_logic.h | 1 - include/configs/omap3_overo.h | 3 +-- include/configs/omap3_pandora.h | 2 -- include/configs/omap3_zoom1.h | 2 -- include/configs/omap3_zoom2.h | 1 - include/configs/siemens-am33x-common.h | 8 ++++---- include/configs/tam3517-common.h | 2 +- include/configs/tricorder.h | 3 +-- 21 files changed, 38 insertions(+), 40 deletions(-) diff --git a/doc/README.nand b/doc/README.nand index f9c921e..5726ff2 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -179,6 +179,15 @@ Configuration Options: This is used by SoC platforms which do not have built-in ELM hardware engine required for BCH ECC correction. + CONFIG_SYS_NAND_DEVICE_WIDTH + Specifies bus-width of the default NAND device connected to SoC. + This config is useful for driver which cannot self initialize or + parse ONFI parameter (like SPL drivers), or for supporting non-ONFI + compliant devices. + This config can take following values: + - 8: NAND devices has bus-width=x8 + - 16: NAND device has bus-width=x16 + Platform specific options ========================= diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 68786f9..584e33e 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -214,11 +214,7 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00; u32 ecc_size_config_val = 0; u32 ecc_config_val = 0; - u32 cs_config1_val; - /* reconfigure GPMC device-width */ - cs_config1_val = readl(&gpmc_cfg->cs[cs].config1); - writel((cs_config1_val | dev_width << 12), &gpmc_cfg->cs[cs].config1); /* configure GPMC for specific ecc-scheme */ switch (bch->ecc_scheme) { case OMAP_ECC_HAM1_CODE_SW: @@ -772,10 +768,10 @@ int board_nand_init(struct nand_chip *nand) nand->priv = &bch_priv; nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; - /* If we are 16 bit dev, our gpmc config tells us that */ - if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) + if (CONFIG_SYS_NAND_DEVICE_WIDTH == 16) nand->options |= NAND_BUSWIDTH_16; - + else + nand->options &= ~NAND_BUSWIDTH_16; nand->chip_delay = 100; nand->ecc.layout = &omap_ecclayout; @@ -795,5 +791,13 @@ int board_nand_init(struct nand_chip *nand) nand->dev_ready = omap_spl_dev_ready; #endif + /* reconfigure GPMC.CONFIG1 register with correct device-width */ + gpmc_config = readl(&gpmc_cfg->cs[cs].config1); + if (nand->options & NAND_BUSWIDTH_16) + gpmc_config |= (0x1 << 12); + else + gpmc_config &= ~(0x1 << 12); + writel(gpmc_config, &gpmc_cfg->cs[cs].config1); + return 0; } diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 978bca7..c92cb2f 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -216,6 +216,7 @@ #ifdef CONFIG_NAND #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_BLOCK_SIZE 131072 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 @@ -366,7 +367,6 @@ /* NAND support */ #ifdef CONFIG_NAND #define CONFIG_CMD_NAND -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT) #define MTDIDS_DEFAULT "nand0=omap2-nand.0" #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 1fd2508..0985221 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -269,7 +269,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ @@ -332,6 +331,7 @@ /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 6500878..8593d44 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -263,7 +263,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ @@ -326,6 +325,7 @@ /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index bc5b66c..1e3dd0d 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -164,8 +164,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x8_LAYOUT - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ /* Environment information */ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index cb79b4e..d6c64a3 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -116,8 +116,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_JFFS2_NAND @@ -318,6 +316,7 @@ /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/dig297.h b/include/configs/dig297.h index 30e3908..f69bcec 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -143,8 +143,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ #if defined(CONFIG_CMD_NET) diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h index 3e18a65..ce6b9be 100644 --- a/include/configs/igep0033.h +++ b/include/configs/igep0033.h @@ -188,7 +188,6 @@ /* NAND support */ #define CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION 1 @@ -248,11 +247,12 @@ #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC #define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index 9982cf6..7e5bc9b 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -268,7 +268,6 @@ #define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */ #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_BASE NAND_BASE -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ @@ -354,6 +353,7 @@ /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 5e27ab2..d508978 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -322,7 +322,6 @@ #define PISMO1_NAND_SIZE GPMC_SIZE_128M #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ @@ -385,6 +384,7 @@ #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" /* NAND boot config */ +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index c1245e7..9050f55 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -184,8 +184,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ @@ -424,6 +422,7 @@ /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index edf6543..564af9a 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -210,7 +210,6 @@ #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #elif defined(CONFIG_CMD_ONENAND) #define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index ee6db51..e198c4c 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -298,7 +298,6 @@ #if defined(CONFIG_CMD_NAND) #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #endif diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 88380a4..de06e20 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -120,8 +120,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand */ /* at CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_JFFS2_NAND @@ -317,6 +315,7 @@ /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 91a2568..6ea106d 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -131,8 +131,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand */ /* at CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index c747d52..1dd7b9c 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -138,8 +138,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_JFFS2_NAND diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index cb8c7ec..9ca7fbe 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -158,7 +158,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Environment information */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 5426ee8..197accc 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -182,11 +182,12 @@ #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC #define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ @@ -433,7 +434,6 @@ "\0" #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ /* to access nand at */ /* CS0 */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 60dd8ff..1f31a87 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -188,7 +188,6 @@ #define PISMO1_NAND_SIZE GPMC_SIZE_128M #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ @@ -252,6 +251,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* NAND boot config */ +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 6daea50..95bbbaa 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -106,8 +106,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_BCH @@ -284,6 +282,7 @@ /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 -- 1.8.1

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[U-Boot] [PATCH 3/3] board/c29xpcie: Add support of 8K page size NAND flash
by Prabhakar Kushwaha 25 Sep '13

25 Sep '13

Defines constants required to support 8K page size NAND flash. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot.git branch master include/configs/C29XPCIE.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 83779ef..6a1e145 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -189,13 +189,14 @@ | CSPR_MSEL_NAND \ | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2k */ \ - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ + | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ + | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ FTIM0_NAND_TWP(0x0c) | \ FTIM0_NAND_TWCHT(0x08) | \ @@ -222,6 +223,7 @@ #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -- 1.7.9.5

3 3

[U-Boot] [RFC 4/5] SPL:Defines function required to env read for IFC & env_nand
by Prabhakar Kushwaha 25 Sep '13

25 Sep '13

fsl_ifs_spl.c reads data from NAND and store at a memory location in raw mode. It does not used MTD layer. To read env variable from NAND MTD layer read/write required. Hence, add mtd_block_isbad & nand_read_skip_bad function required during env variable read. Also, avoid nand_info during env read for SPL Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- common/env_nand.c | 7 ++++--- drivers/mtd/nand/Makefile | 2 +- drivers/mtd/nand/fsl_ifc_spl.c | 22 ++++++++++++++++++++++ 3 files changed, 27 insertions(+), 4 deletions(-) diff --git a/common/env_nand.c b/common/env_nand.c index 7530962..7a7107f 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -246,11 +246,13 @@ int readenv(size_t offset, u_char *buf) u_char *char_ptr; blocksize = nand_info[0].erasesize; +#ifndef CONFIG_SPL_BUILD if (!blocksize) return 1; - len = min(blocksize, CONFIG_ENV_SIZE); - +#else + len = CONFIG_ENV_SIZE; +#endif while (amount_loaded < CONFIG_ENV_SIZE && offset < end) { if (nand_block_isbad(&nand_info[0], offset)) { offset += blocksize; @@ -396,7 +398,6 @@ void env_relocate_spec(void) return; } #endif - ret = readenv(CONFIG_ENV_OFFSET, (u_char *)buf); if (ret) { set_default_env("!readenv() failed"); diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 366dee6..06d5d14 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -24,6 +24,7 @@ COBJS-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o COBJS-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o COBJS-$(CONFIG_SPL_NAND_BASE) += nand_base.o COBJS-$(CONFIG_SPL_NAND_INIT) += nand.o +COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o else # not spl @@ -68,7 +69,6 @@ COBJS-$(CONFIG_NAND_DOCG4) += docg4.o else # minimal SPL drivers COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o -COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o COBJS-$(CONFIG_NAND_MXC) += mxc_nand_spl.o endif # drivers diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index d462265..e7edacf 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -11,6 +11,28 @@ #include <asm/io.h> #include <asm/fsl_ifc.h> #include <linux/mtd/nand.h> +#ifndef CONFIG_SPL_INIT_MINIMAL +#include <linux/mtd/mtd.h> +#endif + +static void nand_load(unsigned int offs, int uboot_size, uchar *dst); + +#ifndef CONFIG_SPL_INIT_MINIMAL +struct mtd_info nand_info[CONFIG_SYS_MAX_NAND_DEVICE]; + +int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs) +{ + return 0; +} + +int nand_read_skip_bad(struct mtd_info *nand, loff_t offset, size_t *length, + size_t *actual, loff_t lim, u_char *buffer) +{ + nand_load(offset, *length, buffer); + return 0; +} +#endif + static inline int is_blank(uchar *addr, int page_size) { -- 1.7.9.5

2 5

Re: [U-Boot] [PATCH] powerpc/c29xpcie: add DDR ECC on off config setting
by Scott Wood 25 Sep '13

25 Sep '13

On Tue, 2013-09-24 at 22:19 -0500, Liu Po-B43644 wrote: > Hi Wood Scott, > > 1. Do you mean it is better to set the hwconfig=fsl_ddr:ecc=on as default setting? > 2. Do you mean keep the CONFIG_DEF_HWCONFIG define as below is better? > > #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on > "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" Yes to both. There's no reason to change this just because one board revision can't do ECC (which is handled elsewhere). -Scott

1 0

[U-Boot] BUG: fastmap and u-boot's ubi write command
by Richard Genoud 25 Sep '13

25 Sep '13

[CC u-boot ML since it may not be a kernel only related bug(s)] Hi Richard, Artem, I'm still playing with fastmap and I ran into something. It's involving u-boot's "ubi write" command and fastmap. What I'm doing is: - Flashing a mtd partition with a userspace.ubi image via u-boot - Booting linux one or to times - Flashing the UBI volume rootfs with a rootfs.ubifs image via u-boot - Booting linux one or to times. And, depending on fastmap not compiled/disable/auto I've got an ubi_assert that fails and a slowpath warning. Here's the story: U-Boot 2013.07 Kernel 3.11.1 NAND: - 128KiB PEB - 2KiB page - 2048 PEB - no subpage mapping is: 0x000000000000-0x000000020000 : "dtb" (128KiB) 0x000000020000-0x000000a00000 : "Kernel" (9.875KiB) 0x000000a00000-0x00000ff80000 : "UBI" (245.5 KiB) 0x00000ff80000-0x000010000000 : "BBT" (512KiB) 1- With Fastmap NOT compiled - Flashing the UBI mtd partition under u-boot: >fatload usb 0 0x20008000 /userspace.ubi >nand device ubi >nand erase.part ubi NAND erase.part: device 0 offset 0xa00000, size 0xf580000 OK > nand write.trimffs 0x20008000 ubi 35a0000 NAND write: device 0 offset 0xa00000, size 0x35a0000 56229888 bytes written: OK Booting a non-FASTMAP kernel: [...] [ 0.789062] UBI: attaching mtd2 to ubi0 [ 1.351562] UBI: scanning is finished [ 1.367187] UBI: attached mtd2 (name "UBI", size 245 MiB) to ubi0 [ 1.375000] UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes [ 1.382812] UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048 [ 1.390625] UBI: VID header offset: 2048 (aligned 2048), data offset: 4096 [ 1.398437] UBI: good PEBs: 1964, bad PEBs: 0, corrupted PEBs: 0 [ 1.398437] UBI: user volume: 3, internal volumes: 1, max. volumes count: 128 [ 1.406250] UBI: max/mean erase counter: 0/0, WL threshold: 4096, image sequence number: 891983656 [ 1.414062] UBI: available PEBs: 2, total reserved PEBs: 1962, PEBs reserved for bad PEB handling: 40 [ 1.421875] UBI: background thread "ubi_bgt0d" started, PID 354 [ 1.437500] UBIFS: background thread "ubifs_bgt0_0" started, PID 356 [ 1.523437] UBIFS: mounted UBI device 0, volume 0, name "rootfs" [ 1.523437] UBIFS: LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes [ 1.531250] UBIFS: FS size: 63614976 bytes (60 MiB, 501 LEBs), journal size 8634368 bytes (8 MiB, 68 LEBs) [ 1.539062] UBIFS: reserved for root: 0 bytes (0 KiB) [ 1.546875] UBIFS: media format: w4/r0 (latest is w4/r0), UUID 47FE5308-55FD-4F1C-BD13-C23AED232326, small LPT model => OK Now, under u-boot, flashing only the ubi volume "rootfs": > fatload usb 0 0x20008000 /rootfs.ubifs 54218752 bytes read in 3259 ms (15.9 MiB/s) > ubi part ubi UBI: attaching mtd1 to ubi0 UBI: physical eraseblock size: 131072 bytes (128 KiB) UBI: logical eraseblock size: 126976 bytes UBI: smallest flash I/O unit: 2048 UBI: VID header offset: 2048 (aligned 2048) UBI: data offset: 4096 UBI: attached mtd1 to ubi0 UBI: MTD device name: "mtd=2" UBI: MTD device size: 245 MiB UBI: number of good PEBs: 1964 UBI: number of bad PEBs: 0 UBI: max. allowed volumes: 128 UBI: wear-leveling threshold: 4096 UBI: number of internal volumes: 1 UBI: number of user volumes: 3 UBI: available PEBs: 23 UBI: total number of reserved PEBs: 1941 UBI: number of PEBs reserved for bad PEB handling: 19 UBI: max/mean erase counter: 2/0 > ubi write 0x20008000 rootfs 33b5000 54218752 bytes written to volume rootfs Booting the same kernel: [ 0.812500] UBI: attaching mtd2 to ubi0 [ 1.664062] UBI: scanning is finished [ 1.687500] UBI: attached mtd2 (name "UBI", size 245 MiB) to ubi0 [ 1.687500] UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes [ 1.695312] UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048 [ 1.703125] UBI: VID header offset: 2048 (aligned 2048), data offset: 4096 [ 1.710937] UBI: good PEBs: 1964, bad PEBs: 0, corrupted PEBs: 0 [ 1.718750] UBI: user volume: 3, internal volumes: 1, max. volumes count: 128 [ 1.718750] UBI: max/mean erase counter: 3/1, WL threshold: 4096, image sequence number: 891983656 [ 1.726562] UBI: available PEBs: 2, total reserved PEBs: 1962, PEBs reserved for bad PEB handling: 40 [ 1.734375] UBI: background thread "ubi_bgt0d" started, PID 354 [ 1.750000] UBIFS: background thread "ubifs_bgt0_0" started, PID 356 [ 1.789062] UBIFS: mounted UBI device 0, volume 0, name "rootfs" [ 1.796875] UBIFS: LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes [ 1.804687] UBIFS: FS size: 63614976 bytes (60 MiB, 501 LEBs), journal size 8634368 bytes (8 MiB, 68 LEBs) [ 1.812500] UBIFS: reserved for root: 0 bytes (0 KiB) [ 1.812500] UBIFS: media format: w4/r0 (latest is w4/r0), UUID 47FE5308-55FD-4F1C-BD13-C23AED232326, small LPT model => all OK 2- With Fastmap compiled and ubi.fm_autoconvert=0 - Flashing the UBI mtd partition under u-boot: >fatload usb 0 0x20008000 /userspace.ubi >nand device ubi >nand erase.part ubi NAND erase.part: device 0 offset 0xa00000, size 0xf580000 OK > nand write.trimffs 0x20008000 ubi 35a0000 NAND write: device 0 offset 0xa00000, size 0x35a0000 56229888 bytes written: OK Booting a FASTMAP kernel: [...] [ 0.812500] UBI: default fastmap pool size: 95 [ 0.820312] UBI: default fastmap WL pool size: 25 [ 0.820312] UBI: attaching mtd2 to ubi0 [ 1.289062] UBI: scanning is finished [ 1.304687] UBI: attached mtd2 (name "UBI", size 245 MiB) to ubi0 [ 1.312500] UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes [ 1.320312] UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048 [ 1.328125] UBI: VID header offset: 2048 (aligned 2048), data offset: 4096 [ 1.328125] UBI: good PEBs: 1964, bad PEBs: 0, corrupted PEBs: 0 [ 1.335937] UBI: user volume: 3, internal volumes: 1, max. volumes count: 128 [ 1.343750] UBI: max/mean erase counter: 0/0, WL threshold: 4096, image sequence number: 891983656 [ 1.351562] UBI: available PEBs: 0, total reserved PEBs: 1964, PEBs reserved for bad PEB handling: 40 [ 1.359375] UBI: background thread "ubi_bgt0d" started, PID 355 [ 1.453125] UBIFS: background thread "ubifs_bgt0_0" started, PID 357 [ 1.515625] UBIFS: mounted UBI device 0, volume 0, name "rootfs" [ 1.515625] UBIFS: LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes [ 1.523437] UBIFS: FS size: 63614976 bytes (60 MiB, 501 LEBs), journal size 8634368 bytes (8 MiB, 68 LEBs) [ 1.531250] UBIFS: reserved for root: 0 bytes (0 KiB) [ 1.539062] UBIFS: media format: w4/r0 (latest is w4/r0), UUID 47FE5308-55FD-4F1C-BD13-C23AED232326, small LPT model => OK Rebooting: : [ 0.812500] UBI: default fastmap pool size: 95 [ 0.820312] UBI: default fastmap WL pool size: 25 [ 0.820312] UBI: attaching mtd2 to ubi0 [ 1.578125] UBI: scanning is finished [ 1.601562] UBI: attached mtd2 (name "UBI", size 245 MiB) to ubi0 [ 1.609375] UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes [ 1.617187] UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048 [ 1.617187] UBI: VID header offset: 2048 (aligned 2048), data offset: 4096 [ 1.625000] UBI: good PEBs: 1964, bad PEBs: 0, corrupted PEBs: 0 [ 1.632812] UBI: user volume: 3, internal volumes: 1, max. volumes count: 128 [ 1.640625] UBI: max/mean erase counter: 2/0, WL threshold: 4096, image sequence number: 891983656 [ 1.648437] UBI: available PEBs: 0, total reserved PEBs: 1964, PEBs reserved for bad PEB handling: 40 [ 1.656250] UBI: background thread "ubi_bgt0d" started, PID 355 Still ok. Now, under u-boot, flashing only the ubi volume "rootfs": > fatload usb 0 0x20008000 /rootfs.ubifs 54218752 bytes read in 3259 ms (15.9 MiB/s) > ubi part ubi UBI: attaching mtd1 to ubi0 UBI: physical eraseblock size: 131072 bytes (128 KiB) UBI: logical eraseblock size: 126976 bytes UBI: smallest flash I/O unit: 2048 UBI: VID header offset: 2048 (aligned 2048) UBI: data offset: 4096 UBI: attached mtd1 to ubi0 UBI: MTD device name: "mtd=2" UBI: MTD device size: 245 MiB UBI: number of good PEBs: 1964 UBI: number of bad PEBs: 0 UBI: max. allowed volumes: 128 UBI: wear-leveling threshold: 4096 UBI: number of internal volumes: 1 UBI: number of user volumes: 3 UBI: available PEBs: 23 UBI: total number of reserved PEBs: 1941 UBI: number of PEBs reserved for bad PEB handling: 19 UBI: max/mean erase counter: 2/0 > ubi write 0x20008000 rootfs 33b5000 54218752 bytes written to volume rootfs Booting the same kernel: [ 0.804687] UBI: default fastmap pool size: 95 [ 0.812500] UBI: default fastmap WL pool size: 25 [ 0.812500] UBI: attaching mtd2 to ubi0 [ 1.570312] UBI: scanning is finished [ 1.593750] UBI: attached mtd2 (name "UBI", size 245 MiB) to ubi0 [ 1.601562] UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes [ 1.609375] UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048 [ 1.609375] UBI: VID header offset: 2048 (aligned 2048), data offset: 4096 [ 1.617187] UBI: good PEBs: 1964, bad PEBs: 0, corrupted PEBs: 0 [ 1.625000] UBI: user volume: 3, internal volumes: 1, max. volumes count: 128 [ 1.632812] UBI: max/mean erase counter: 3/1, WL threshold: 4096, image sequence number: 891983656 [ 1.640625] UBI: available PEBs: 0, total reserved PEBs: 1964, PEBs reserved for bad PEB handling: 40 [ 1.648437] UBI: background thread "ubi_bgt0d" started, PID 355 [ 1.664062] UBIFS: background thread "ubifs_bgt0_0" started, PID 357 [ 1.703125] UBIFS: mounted UBI device 0, volume 0, name "rootfs" [ 1.710937] UBIFS: LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes [ 1.718750] UBIFS: FS size: 63614976 bytes (60 MiB, 501 LEBs), journal size 8634368 bytes (8 MiB, 68 LEBs) [ 1.726562] UBIFS: reserved for root: 0 bytes (0 KiB) [ 1.734375] UBIFS: media format: w4/r0 (latest is w4/r0), UUID 47FE5308-55FD-4F1C-BD13-C23AED232326, small LPT model => All OK (I rebooted one or two times, no problem showing up) Now, booting with ubi.fm_autoconvert=1: [ 0.812500] UBI: default fastmap pool size: 95 [ 0.820312] UBI: default fastmap WL pool size: 25 [ 0.820312] UBI: attaching mtd2 to ubi0 [ 1.578125] UBI: scanning is finished [ 1.601562] UBI: attached mtd2 (name "UBI", size 245 MiB) to ubi0 [ 1.609375] UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes [ 1.609375] UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048 [ 1.617187] UBI: VID header offset: 2048 (aligned 2048), data offset: 4096 [ 1.625000] UBI: good PEBs: 1964, bad PEBs: 0, corrupted PEBs: 0 [ 1.632812] UBI: user volume: 3, internal volumes: 1, max. volumes count: 128 [ 1.640625] UBI: max/mean erase counter: 3/1, WL threshold: 4096, image sequence number: 891983656 [ 1.648437] UBI: available PEBs: 0, total reserved PEBs: 1964, PEBs reserved for bad PEB handling: 40 [ 1.656250] UBI: background thread "ubi_bgt0d" started, PID 355 [ 1.671875] UBIFS: background thread "ubifs_bgt0_0" started, PID 357 [ 1.710937] UBIFS: mounted UBI device 0, volume 0, name "rootfs" [ 1.718750] UBIFS: LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes [ 1.726562] UBIFS: FS size: 63614976 bytes (60 MiB, 501 LEBs), journal size 8634368 bytes (8 MiB, 68 LEBs) [ 1.734375] UBIFS: reserved for root: 0 bytes (0 KiB) [ 1.742187] UBIFS: media format: w4/r0 (latest is w4/r0), UUID 47FE5308-55FD-4F1C-BD13-C23AED232326, small LPT model => Still OK Rebooting again with ubi.fm_autoconvert=1: [ 0.812500] UBI: default fastmap pool size: 95 [ 0.820312] UBI: default fastmap WL pool size: 25 [ 0.820312] UBI: attaching mtd2 to ubi0 [ 0.851562] UBI error: ubi_scan_fastmap: Attach by fastmap failed, doing a full scan! [ 1.593750] UBI: scanning is finished [ 1.601562] UBI assert failed in ubi_wl_init at 1967 (pid 1) [ 1.609375] CPU: 0 PID: 1 Comm: swapper Not tainted 3.11.1 #5 [ 1.617187] [<c0012e20>] (unwind_backtrace+0x0/0xe0) from [<c0010bb8>] (show_stack+0x10/0x14) [ 1.625000] [<c0010bb8>] (show_stack+0x10/0x14) from [<c01a0704>] (ubi_wl_init+0x3d0/0x4b8) [ 1.632812] [<c01a0704>] (ubi_wl_init+0x3d0/0x4b8) from [<c01a2cd4>] (ubi_attach+0x270/0x34c) [ 1.640625] [<c01a2cd4>] (ubi_attach+0x270/0x34c) from [<c0197678>] (ubi_attach_mtd_dev+0x2b8/0x86c) [ 1.648437] [<c0197678>] (ubi_attach_mtd_dev+0x2b8/0x86c) from [<c0346630>] (ubi_init+0x1d8/0x29c) [ 1.656250] [<c0346630>] (ubi_init+0x1d8/0x29c) from [<c0008810>] (do_one_initcall+0x94/0x144) [ 1.664062] [<c0008810>] (do_one_initcall+0x94/0x144) from [<c0335a9c>] (kernel_init_freeable+0xe8/0x1ac) [ 1.671875] [<c0335a9c>] (kernel_init_freeable+0xe8/0x1ac) from [<c0251500>] (kernel_init+0x8/0xe4) [ 1.679687] [<c0251500>] (kernel_init+0x8/0xe4) from [<c000e590>] (ret_from_fork+0x14/0x24) [ 1.695312] UBI: attached mtd2 (name "UBI", size 245 MiB) to ubi0 [ 1.703125] UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes [ 1.703125] UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048 [ 1.710937] UBI: VID header offset: 2048 (aligned 2048), data offset: 4096 [ 1.718750] UBI: good PEBs: 1964, bad PEBs: 0, corrupted PEBs: 0 [ 1.726562] UBI: user volume: 3, internal volumes: 1, max. volumes count: 128 [ 1.726562] UBI: max/mean erase counter: 3/1, WL threshold: 4096, image sequence number: 891983656 [ 1.734375] UBI: available PEBs: 0, total reserved PEBs: 1964, PEBs reserved for bad PEB handling: 40 [ 1.742187] UBI: background thread "ubi_bgt0d" started, PID 355 [ 1.757812] UBIFS: background thread "ubifs_bgt0_0" started, PID 357 [ 1.796875] UBIFS: mounted UBI device 0, volume 0, name "rootfs" [ 1.804687] UBIFS: LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes [ 1.812500] UBIFS: FS size: 63614976 bytes (60 MiB, 501 LEBs), journal size 8634368 bytes (8 MiB, 68 LEBs) [ 1.820312] UBIFS: reserved for root: 0 bytes (0 KiB) [ 1.820312] UBIFS: media format: w4/r0 (latest is w4/r0), UUID 47FE5308-55FD-4F1C-BD13-C23AED232326, small LPT model [ 1.828125] VFS: Mounted root (ubifs filesystem) on device 0:11. [ 1.835937] devtmpfs: mounted [ 1.835937] Freeing unused kernel memory: 112K (c0335000 - c0351000) [ 2.187500] UBI error: ubi_update_fastmap: could not find any anchor PEB [ 2.195312] UBI warning: ubi_update_fastmap: Unable to write new fastmap, err=-28 => If I reboot again, I still have those error messages. 3- With Fastmap compiled and ubi.fm_autoconvert=1 - Flashing the UBI mtd partition under u-boot: >fatload usb 0 0x20008000 /userspace.ubi >nand device ubi >nand erase.part ubi NAND erase.part: device 0 offset 0xa00000, size 0xf580000 OK > nand write.trimffs 0x20008000 ubi 35a0000 NAND write: device 0 offset 0xa00000, size 0x35a0000 56229888 bytes written: OK Booting a FASTMAP kernel with ubi.fm_autoconvert=1: [...] [ 0.812500] UBI: default fastmap pool size: 95 [ 0.820312] UBI: default fastmap WL pool size: 25 [ 0.820312] UBI: attaching mtd2 to ubi0 [ 1.289062] UBI: scanning is finished [ 1.304687] UBI: attached mtd2 (name "UBI", size 245 MiB) to ubi0 [ 1.312500] UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes [ 1.320312] UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048 [ 1.328125] UBI: VID header offset: 2048 (aligned 2048), data offset: 4096 [ 1.328125] UBI: good PEBs: 1964, bad PEBs: 0, corrupted PEBs: 0 [ 1.335937] UBI: user volume: 3, internal volumes: 1, max. volumes count: 128 [ 1.343750] UBI: max/mean erase counter: 0/0, WL threshold: 4096, image sequence number: 891983656 [ 1.351562] UBI: available PEBs: 0, total reserved PEBs: 1964, PEBs reserved for bad PEB handling: 40 [ 1.359375] UBI: background thread "ubi_bgt0d" started, PID 355 [ 1.437500] UBI error: ubi_update_fastmap: could not find any anchor PEB [ 1.445312] UBI warning: ubi_update_fastmap: Unable to write new fastmap, err=-28 =>OK Rebooting 2 times to let FASTMAP show its power: [ 0.812500] UBI: default fastmap pool size: 95 [ 0.820312] UBI: default fastmap WL pool size: 25 [ 0.820312] UBI: attaching mtd2 to ubi0 [ 0.929687] UBI: attached by fastmap [ 0.937500] UBI: fastmap pool size: 95 [ 0.937500] UBI: fastmap WL pool size: 25 [ 0.960937] UBI: attached mtd2 (name "UBI", size 245 MiB) to ubi0 GREAT ! Now, under u-boot, flashing only the ubi volume "rootfs": > fatload usb 0 0x20008000 /rootfs.ubifs 54218752 bytes read in 3259 ms (15.9 MiB/s) > ubi part ubi UBI: attaching mtd1 to ubi0 UBI: physical eraseblock size: 131072 bytes (128 KiB) UBI: logical eraseblock size: 126976 bytes UBI: smallest flash I/O unit: 2048 UBI: VID header offset: 2048 (aligned 2048) UBI: data offset: 4096 UBI: "delete" compatible internal volume 2147479552:0 found, remove it UBI: attached mtd1 to ubi0 UBI: MTD device name: "mtd=2" UBI: MTD device size: 245 MiB UBI: number of good PEBs: 1964 UBI: number of bad PEBs: 0 UBI: max. allowed volumes: 128 UBI: wear-leveling threshold: 4096 UBI: number of internal volumes: 1 UBI: number of user volumes: 3 UBI: available PEBs: 23 UBI: total number of reserved PEBs: 1941 UBI: number of PEBs reserved for bad PEB handling: 19 UBI: max/mean erase counter: 2/0 > ubi write 0x20008000 rootfs 33b5000 54218752 bytes written to volume rootfs =>FASTMAP internal volume has been erased, which is the expected behaviour. Booting the same kernel, still with ubi.fm_autoconvert=1: [...] [ 0.812500] UBI: default fastmap pool size: 95 [ 0.820312] UBI: default fastmap WL pool size: 25 [ 0.820312] UBI: attaching mtd2 to ubi0 [ 1.585937] UBI: scanning is finished [ 1.601562] UBI: attached mtd2 (name "UBI", size 245 MiB) to ubi0 [ 1.609375] UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes [ 1.617187] UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048 [ 1.625000] UBI: VID header offset: 2048 (aligned 2048), data offset: 4096 [ 1.625000] UBI: good PEBs: 1964, bad PEBs: 0, corrupted PEBs: 0 [ 1.632812] UBI: user volume: 3, internal volumes: 1, max. volumes count: 128 [ 1.640625] UBI: max/mean erase counter: 4/1, WL threshold: 4096, image sequence number: 891983656 [ 1.648437] UBI: available PEBs: 0, total reserved PEBs: 1964, PEBs reserved for bad PEB handling: 40 [ 1.656250] UBI: background thread "ubi_bgt0d" started, PID 355 [ 1.703125] UBIFS: background thread "ubifs_bgt0_0" started, PID 357 [ 1.734375] UBIFS: mounted UBI device 0, volume 0, name "rootfs" [ 1.742187] UBIFS: LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes [ 1.750000] UBIFS: FS size: 63614976 bytes (60 MiB, 501 LEBs), journal size 8634368 bytes (8 MiB, 68 LEBs) [ 1.757812] UBIFS: reserved for root: 0 bytes (0 KiB) [ 1.765625] UBIFS: media format: w4/r0 (latest is w4/r0), UUID 47FE5308-55FD-4F1C-BD13-C23AED232326, small LPT model =>OK this time, let's reboot: [ 0.812500] UBI: default fastmap pool size: 95 [ 0.820312] UBI: default fastmap WL pool size: 25 [ 0.820312] UBI: attaching mtd2 to ubi0 [ 0.914062] UBI error: scan_pool: bad image seq: 0x0, expected: 0x352a9728 [ 0.921875] ------------[ cut here ]------------ [ 0.929687] WARNING: CPU: 0 PID: 1 at drivers/mtd/ubi/fastmap.c:829 ubi_attach_fastmap+0xd38/0xda0() [ 0.937500] Modules linked in: [ 0.937500] CPU: 0 PID: 1 Comm: swapper Not tainted 3.11.1 #5 [ 0.945312] [<c0012e20>] (unwind_backtrace+0x0/0xe0) from [<c0010bb8>] (show_stack+0x10/0x14) [ 0.953125] [<c0010bb8>] (show_stack+0x10/0x14) from [<c001ab2c>] (warn_slowpath_common+0x60/0x80) [ 0.960937] [<c001ab2c>] (warn_slowpath_common+0x60/0x80) from [<c001ab64>] (warn_slowpath_null+0x18/0x1c) [ 0.968750] [<c001ab64>] (warn_slowpath_null+0x18/0x1c) from [<c01a5c8c>] (ubi_attach_fastmap+0xd38/0xda0) [ 0.976562] [<c01a5c8c>] (ubi_attach_fastmap+0xd38/0xda0) from [<c01a62d4>] (ubi_scan_fastmap+0x5b4/0x7b8) [ 0.984375] [<c01a62d4>] (ubi_scan_fastmap+0x5b4/0x7b8) from [<c01a2c2c>] (ubi_attach+0x1c8/0x34c) [ 0.992187] [<c01a2c2c>] (ubi_attach+0x1c8/0x34c) from [<c0197678>] (ubi_attach_mtd_dev+0x2b8/0x86c) [ 1.000000] [<c0197678>] (ubi_attach_mtd_dev+0x2b8/0x86c) from [<c0346630>] (ubi_init+0x1d8/0x29c) [ 1.007812] [<c0346630>] (ubi_init+0x1d8/0x29c) from [<c0008810>] (do_one_initcall+0x94/0x144) [ 1.015625] [<c0008810>] (do_one_initcall+0x94/0x144) from [<c0335a9c>] (kernel_init_freeable+0xe8/0x1ac) [ 1.023437] [<c0335a9c>] (kernel_init_freeable+0xe8/0x1ac) from [<c0251500>] (kernel_init+0x8/0xe4) [ 1.031250] [<c0251500>] (kernel_init+0x8/0xe4) from [<c000e590>] (ret_from_fork+0x14/0x24) [ 1.039062] ---[ end trace 313a7957427257d8 ]--- [ 1.039062] UBI error: ubi_scan_fastmap: Attach by fastmap failed, doing a full scan! [ 1.781250] UBI: scanning is finished [ 1.796875] UBI assert failed in ubi_wl_init at 1967 (pid 1) [ 1.796875] CPU: 0 PID: 1 Comm: swapper Tainted: G W 3.11.1 #5 [ 1.804687] [<c0012e20>] (unwind_backtrace+0x0/0xe0) from [<c0010bb8>] (show_stack+0x10/0x14) [ 1.812500] [<c0010bb8>] (show_stack+0x10/0x14) from [<c01a0704>] (ubi_wl_init+0x3d0/0x4b8) [ 1.820312] [<c01a0704>] (ubi_wl_init+0x3d0/0x4b8) from [<c01a2cd4>] (ubi_attach+0x270/0x34c) [ 1.828125] [<c01a2cd4>] (ubi_attach+0x270/0x34c) from [<c0197678>] (ubi_attach_mtd_dev+0x2b8/0x86c) [ 1.835937] [<c0197678>] (ubi_attach_mtd_dev+0x2b8/0x86c) from [<c0346630>] (ubi_init+0x1d8/0x29c) [ 1.843750] [<c0346630>] (ubi_init+0x1d8/0x29c) from [<c0008810>] (do_one_initcall+0x94/0x144) [ 1.851562] [<c0008810>] (do_one_initcall+0x94/0x144) from [<c0335a9c>] (kernel_init_freeable+0xe8/0x1ac) [ 1.859375] [<c0335a9c>] (kernel_init_freeable+0xe8/0x1ac) from [<c0251500>] (kernel_init+0x8/0xe4) [ 1.867187] [<c0251500>] (kernel_init+0x8/0xe4) from [<c000e590>] (ret_from_fork+0x14/0x24) [ 1.882812] UBI: attached mtd2 (name "UBI", size 245 MiB) to ubi0 [ 1.890625] UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes [ 1.898437] UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048 [ 1.898437] UBI: VID header offset: 2048 (aligned 2048), data offset: 4096 [ 1.906250] UBI: good PEBs: 1964, bad PEBs: 0, corrupted PEBs: 0 [ 1.914062] UBI: user volume: 3, internal volumes: 1, max. volumes count: 128 [ 1.921875] UBI: max/mean erase counter: 4/1, WL threshold: 4096, image sequence number: 891983656 [ 1.929687] UBI: available PEBs: 0, total reserved PEBs: 1964, PEBs reserved for bad PEB handling: 40 [ 1.937500] UBI: background thread "ubi_bgt0d" started, PID 355 [ 1.953125] UBIFS: background thread "ubifs_bgt0_0" started, PID 357 [ 1.992187] UBIFS: mounted UBI device 0, volume 0, name "rootfs" [ 2.000000] UBIFS: LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes [ 2.007812] UBIFS: FS size: 63614976 bytes (60 MiB, 501 LEBs), journal size 8634368 bytes (8 MiB, 68 LEBs) [ 2.015625] UBIFS: reserved for root: 0 bytes (0 KiB) [ 2.023437] UBIFS: media format: w4/r0 (latest is w4/r0), UUID 47FE5308-55FD-4F1C-BD13-C23AED232326, small LPT model [ 2.031250] VFS: Mounted root (ubifs filesystem) on device 0:11. [ 2.039062] devtmpfs: mounted [ 2.046875] Freeing unused kernel memory: 112K (c0335000 - c0351000) [ 2.390625] UBI error: ubi_update_fastmap: could not find any anchor PEB [ 2.398437] UBI warning: ubi_update_fastmap: Unable to write new fastmap, err=-28 Best regards, Richard.

2 5

[U-Boot] [PATCH] drivers/net/designware - fix alignment of buffer descriptors
by Alexey Brodkin 25 Sep '13

25 Sep '13

It's important that buffer descriptors are aligned in accordance to GMAC data bus width (32/64/128-bit). It's safe to align to 128-bit (16-bytes) for every bus width type. If buffer descriptor is improperly aligned GMAC discards lower bits of provided address and as a result reads from improper location that doesn't match expected fields. Any other members of structure "dw_eth_dev" (and structure itself) don't need any specific alignment. Moreover commit ef76025a99247cdb8f927a2c9f15400678dfb599 "net: Multiple updates/enhancements to designware.c" introduced another structure member "link_printed" right before buffer descriptors while "padding" member was left untouched. This together with alignment of structure itself to 8-byte boundary forces buffer descriptoprs always to be 4-byte aligned that causes driver complete disfunction if GMAC bus width is 64 or 128-bit. Proposed change makes sure all buffer descriptors are 128-bit aligned. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> --- drivers/net/designware.c | 6 +----- drivers/net/designware.h | 7 +++---- 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index f11cb0b..c8e3fc8 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -534,11 +534,7 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) if (!dev) return -ENOMEM; - /* - * Since the priv structure contains the descriptors which need a strict - * buswidth alignment, memalign is used to allocate memory - */ - priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev)); + priv = (struct dw_eth_dev *) malloc(sizeof(struct dw_eth_dev)); if (!priv) { free(dev); return -ENOMEM; diff --git a/drivers/net/designware.h b/drivers/net/designware.h index d668f8f..137acb0 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -128,7 +128,7 @@ struct dmamacdescr { u32 dmamac_cntl; void *dmamac_addr; struct dmamacdescr *dmamac_next; -}; +} __aligned(16); /* * txrx_status definitions @@ -240,8 +240,7 @@ struct dw_eth_dev { u32 tx_currdescnum; u32 rx_currdescnum; u32 phy_configured; - int link_printed; - u32 padding; + u32 link_printed; struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; @@ -253,7 +252,7 @@ struct dw_eth_dev { struct eth_dma_regs *dma_regs_p; struct eth_device *dev; -} __attribute__ ((aligned(8))); +}; /* Speed specific definitions */ #define SPEED_10M 1 -- 1.8.1.2

1 0

[U-Boot] [PATCH 3/3][v2] board/c29xpcie: Add support of 8K page size NAND flash
by Prabhakar Kushwaha 25 Sep '13

25 Sep '13

Defines constants required to support 8K page size NAND flash. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Changes for v2:Sending as it is include/configs/C29XPCIE.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 83779ef..6a1e145 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -189,13 +189,14 @@ | CSPR_MSEL_NAND \ | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2k */ \ - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ + | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ + | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ FTIM0_NAND_TWP(0x0c) | \ FTIM0_NAND_TWCHT(0x08) | \ @@ -222,6 +223,7 @@ #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -- 1.7.9.5

1 0

[U-Boot] [PATCH 2/3][v2] mtd/ifc: Add support of 8K page size NAND flash
by Prabhakar Kushwaha 25 Sep '13

25 Sep '13

Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Changes for v2: sending as it is arch/powerpc/cpu/mpc8xxx/fsl_ifc.c | 24 +++++++++++ arch/powerpc/include/asm/fsl_ifc.h | 2 + drivers/mtd/nand/fsl_ifc_nand.c | 78 ++++++++++++++++++++++++++++++++++++ drivers/mtd/nand/fsl_ifc_spl.c | 4 ++ 4 files changed, 108 insertions(+) diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c index 2d0fb43..64a5225 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c @@ -34,6 +34,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR0_EXT set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT); #endif +#ifdef CONFIG_SYS_CSOR0_EXT + set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT); +#endif set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); @@ -43,6 +46,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR1_EXT set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT); #endif +#ifdef CONFIG_SYS_CSOR1_EXT + set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT); +#endif #if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); @@ -57,6 +63,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR2_EXT set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT); #endif +#ifdef CONFIG_SYS_CSOR2_EXT + set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT); +#endif #if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); @@ -71,6 +80,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR3_EXT set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT); #endif +#ifdef CONFIG_SYS_CSOR3_EXT + set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT); +#endif #if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); @@ -85,6 +97,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR4_EXT set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); #endif +#ifdef CONFIG_SYS_CSOR4_EXT + set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT); +#endif #if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0); set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1); @@ -99,6 +114,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR5_EXT set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT); #endif +#ifdef CONFIG_SYS_CSOR5_EXT + set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT); +#endif #if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5) set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0); set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1); @@ -113,6 +131,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR6_EXT set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); #endif +#ifdef CONFIG_SYS_CSOR6_EXT + set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT); +#endif #if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0); set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1); @@ -127,6 +148,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR7_EXT set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); #endif +#ifdef CONFIG_SYS_CSOR7_EXT + set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT); +#endif #if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0); set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1); diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h index a945e4b..182b1a6 100644 --- a/arch/powerpc/include/asm/fsl_ifc.h +++ b/arch/powerpc/include/asm/fsl_ifc.h @@ -77,6 +77,7 @@ #define CSOR_NAND_PGS_512 0x00000000 #define CSOR_NAND_PGS_2K 0x00080000 #define CSOR_NAND_PGS_4K 0x00100000 +#define CSOR_NAND_PGS_8K 0x00180000 /* Spare region Size */ #define CSOR_NAND_SPRZ_MASK 0x0000E000 #define CSOR_NAND_SPRZ_SHIFT 13 @@ -86,6 +87,7 @@ #define CSOR_NAND_SPRZ_210 0x00006000 #define CSOR_NAND_SPRZ_218 0x00008000 #define CSOR_NAND_SPRZ_224 0x0000A000 +#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 /* Pages Per Block */ #define CSOR_NAND_PB_MASK 0x00000700 #define CSOR_NAND_PB_SHIFT 8 diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 98a09c0..cfed549 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -125,6 +125,69 @@ static struct nand_ecclayout oob_4096_ecc8 = { .oobfree = { {2, 6}, {136, 82} }, }; +/* 8192-byte page size with 4-bit ECC */ +static struct nand_ecclayout oob_8192_ecc4 = { + .eccbytes = 128, + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, + 128, 129, 130, 131, 132, 133, 134, 135, + }, + .oobfree = { {2, 6}, {136, 208} }, +}; + +/* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */ +static struct nand_ecclayout oob_8192_ecc8 = { + .eccbytes = 256, + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, + 128, 129, 130, 131, 132, 133, 134, 135, + 136, 137, 138, 139, 140, 141, 142, 143, + 144, 145, 146, 147, 148, 149, 150, 151, + 152, 153, 154, 155, 156, 157, 158, 159, + 160, 161, 162, 163, 164, 165, 166, 167, + 168, 169, 170, 171, 172, 173, 174, 175, + 176, 177, 178, 179, 180, 181, 182, 183, + 184, 185, 186, 187, 188, 189, 190, 191, + 192, 193, 194, 195, 196, 197, 198, 199, + 200, 201, 202, 203, 204, 205, 206, 207, + 208, 209, 210, 211, 212, 213, 214, 215, + 216, 217, 218, 219, 220, 221, 222, 223, + 224, 225, 226, 227, 228, 229, 230, 231, + 232, 233, 234, 235, 236, 237, 238, 239, + 240, 241, 242, 243, 244, 245, 246, 247, + 248, 249, 250, 251, 252, 253, 254, 255, + 256, 257, 258, 259, 260, 261, 262, 263, + }, + .oobfree = { {2, 6}, {264, 80} }, +}; /* * Generic flash bbt descriptors @@ -902,6 +965,21 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) priv->bufnum_mask = 1; break; + case CSOR_NAND_PGS_8K: + if ((csor & CSOR_NAND_ECC_MODE_MASK) == + CSOR_NAND_ECC_MODE_4) { + layout = &oob_8192_ecc4; + nand->ecc.strength = 4; + } else { + layout = &oob_8192_ecc8; + nand->ecc.strength = 8; + nand->ecc.bytes = 16; + } + + priv->bufnum_mask = 0; + break; + + default: printf("ifc nand: bad csor %#x: bad page size\n", csor); return -ENODEV; diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index d462265..b6d3335 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -112,6 +112,10 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8; + if (csor & CSOR_NAND_PGS_8K) { + page_size = 8192; + bufnum_mask = 0x0; + } if (csor & CSOR_NAND_PGS_4K) { page_size = 4096; bufnum_mask = 0x1; -- 1.7.9.5

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