July 2013 - U-Boot

[U-Boot] [PATCH v3 0/3] arm: add support for LaCie CloudBox
by Frédéric Leroy 08 Sep '13

08 Sep '13

This series adds support for the LaCie Cloudbox v2 device. Changes in v3: - prepare other LaCie boards for led patch - fix Machine ID - use one commit for adding device Changes in v2: - sort unsorted #ifdef list in lacie_kw.h - add entry to MAINTAINERS - remove unused GPIO definitions - remove empty misc_init_r() - add Machine ID - Use #define values for ethernet phy init - checkpatch compliant Frédéric Leroy (3): lacie_kw: sort #ifdef lists by CONFIG_ identifiers LaCie/common: Uses #defines for ethernet phy leds setup arm: add support for LaCie CloudBox MAINTAINERS | 4 + board/LaCie/cloudbox/Makefile | 46 +++++++++++ board/LaCie/cloudbox/cloudbox.c | 94 +++++++++++++++++++++ board/LaCie/cloudbox/cloudbox.h | 36 ++++++++ board/LaCie/cloudbox/kwbimage.cfg | 167 ++++++++++++++++++++++++++++++++++++++ board/LaCie/common/common.c | 13 ++- boards.cfg | 1 + include/configs/lacie_kw.h | 45 ++++++---- 8 files changed, 388 insertions(+), 18 deletions(-) create mode 100644 board/LaCie/cloudbox/Makefile create mode 100644 board/LaCie/cloudbox/cloudbox.c create mode 100644 board/LaCie/cloudbox/cloudbox.h create mode 100644 board/LaCie/cloudbox/kwbimage.cfg -- 1.8.1.2

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[U-Boot] [PATCH] fs: fat: don't call disk_write with zero sector num
by Josh Wu 06 Sep '13

06 Sep '13

In the set_cluster() function, it will convert the buffer size to sector numbers. Then call disk_write() to write by sector. For remaining buffer, the size is less than a sector, call disk_write() again to write them in one sector. But if the total buffer size is less then one sector, the original code will call disk_write() with zero sector number. It is unnecessary. So this patch fix this. Now it will not call disk_write() if total buffer size is less than one sector. Signed-off-by: Josh Wu <josh.wu(a)atmel.com> --- fs/fat/fat_write.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index fd07240..a05327c 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -568,9 +568,11 @@ set_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, debug("clustnum: %d, startsect: %d\n", clustnum, startsect); - if (disk_write(startsect, size / mydata->sect_size, buffer) < 0) { - debug("Error writing data\n"); - return -1; + if ((size / mydata->sect_size) > 0) { + if (disk_write(startsect, size / mydata->sect_size, buffer) < 0) { + debug("Error writing data\n"); + return -1; + } } if (size % mydata->sect_size) { -- 1.7.9.5

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[U-Boot] [PATCH] mmc/dw_mmc: Fix DMA descriptor corruption
by Mischa Jonker 06 Sep '13

06 Sep '13

In dwmci_prepare_data, the descriptors are allocated for DMA transfer. These are allocated using the ALLOC_CACHE_ALIGN_BUFFER. This macro uses the stack to allocate these descriptors. This becomes a problem if the DMA transfer continues after the processor leaves the function in which the descriptors were allocated. Therefore, I have moved the allocated of the buffers up one level, to dwmci_send_cmd(). The DMA transfer should be complete when leaving this function. Signed-off-by: Mischa Jonker <mjonker(a)synopsys.com> Cc: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Andy Fleming <afleming(a)gmail.com> --- drivers/mmc/dw_mmc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index a82ee17..796a811 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -41,12 +41,11 @@ static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, } static void dwmci_prepare_data(struct dwmci_host *host, - struct mmc_data *data) + struct mmc_data *data, struct dwmci_idmac *cur_idmac) { unsigned long ctrl; unsigned int i = 0, flags, cnt, blk_cnt; ulong data_start, data_end, start_addr; - ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, data->blocks); blk_cnt = data->blocks; @@ -111,6 +110,8 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { struct dwmci_host *host = (struct dwmci_host *)mmc->priv; + ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, + data ? data->blocks : 0); int flags = 0, i; unsigned int timeout = 100000; u32 retry = 10000; @@ -127,7 +128,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); if (data) - dwmci_prepare_data(host, data); + dwmci_prepare_data(host, data, cur_idmac); dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); -- 1.7.9.5

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[U-Boot] [PATCH] arm: lds: Remove libgcc eabi exception handling tables
by Michal Simek 06 Sep '13

06 Sep '13

Remove ARM eabi exception handling tables (for frame unwinding). AFAICT, u-boot stubs away the frame unwiding routines, so the tables will more or less just consume space. It should be OK to remove them. Signed-off-by: Edgar E. Iglesias <edgar.iglesias(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- This patch was sent to ML as RFC (May 9) Here is the origin response in connection to this patch. Ok, so Michal and I just did some fiddling with zynq builds and *exidx* sections. By default the *exidx* sections are between rodata and data, so removing them causes many apparent changes at the binary level. However, builds of zynq based on ARM master with the patch above vs master with a patch mapping *exidx* sections after BSS gives identical binaries. Thus the RFC has no functional effect. Also, ARM EHABI states that [exception] Tables are not required for ABI compliance at the C/Assembler level but are required for C++. http://infocenter.arm.com/help/topic/com.arm.doc.ihi0038a/IHI0038A_ehabi.pdf So as long as we don't put any C++ code in U-Boot (a prospect that I don't see happening any time soon), this RFC is safe and either is a no-op or removes useless bytes from the binary. --- arch/arm/cpu/u-boot.lds | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 3037885..8894c8a 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -113,4 +113,6 @@ SECTIONS /DISCARD/ : { *(.plt*) } /DISCARD/ : { *(.interp*) } /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.ARM.exidx*) } + /DISCARD/ : { *(.gnu.linkonce.armexidx.*) } } -- 1.8.2.3

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[U-Boot] [PATCH] mmc: sdhci: use the SDHCI_QUIRK_USE_WIDE8 for samsung SoC
by Jaehoon Chung 05 Sep '13

05 Sep '13

Samsung SoC is supported the WIDE8, even if Controller version is v2.0. So add the SDHCI_QUIRK_USE_WIDE8 for Samsung-SoC. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- drivers/mmc/s5p_sdhci.c | 4 +++- drivers/mmc/sdhci.c | 13 +++++++------ include/sdhci.h | 3 +++ 3 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index e50ff92..97e153e 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -84,7 +84,7 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width) host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR | - SDHCI_QUIRK_WAIT_SEND_CMD; + SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8; host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; host->version = sdhci_readw(host, SDHCI_HOST_VERSION); @@ -93,6 +93,8 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width) host->index = index; host->host_caps = MMC_MODE_HC; + if (bus_width == 8) + host->host_caps |= MMC_MODE_8BIT; return add_sdhci(host, 52000000, 400000); } diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index c5631bf..9bf3052 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -270,7 +270,7 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) if (clock == 0) return 0; - if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) { + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { /* Version 3.00 divisors must be a multiple of 2. */ if (mmc->f_max <= clock) div = 1; @@ -363,10 +363,11 @@ void sdhci_set_ios(struct mmc *mmc) ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); if (mmc->bus_width == 8) { ctrl &= ~SDHCI_CTRL_4BITBUS; - if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) + if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || + (host->quirks & SDHCI_QUIRK_USE_WIDE8)) ctrl |= SDHCI_CTRL_8BITBUS; } else { - if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ctrl &= ~SDHCI_CTRL_8BITBUS; if (mmc->bus_width == 4) ctrl |= SDHCI_CTRL_4BITBUS; @@ -453,7 +454,7 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) if (max_clk) mmc->f_max = max_clk; else { - if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; else @@ -468,7 +469,7 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) if (min_clk) mmc->f_min = min_clk; else { - if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300; else mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200; @@ -486,7 +487,7 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) mmc->voltages |= host->voltages; mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; - if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) { + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { if (caps & SDHCI_CAN_DO_8BIT) mmc->host_caps |= MMC_MODE_8BIT; } diff --git a/include/sdhci.h b/include/sdhci.h index cffbe53..f3f8219 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -208,6 +208,8 @@ #define SDHCI_SPEC_200 1 #define SDHCI_SPEC_300 2 +#define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK) + /* * End of controller registers. */ @@ -226,6 +228,7 @@ #define SDHCI_QUIRK_NO_CD (1 << 5) #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6) #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 7) +#define SDHCI_QUIRK_USE_WIDE8 (1 << 8) /* to make gcc happy */ struct sdhci_host; -- 1.7.9.5

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[U-Boot] [RFC PATCH] armv7:omap4-common: Correct check of the SPL image size
by Oleg Kosheliev 02 Sep '13

02 Sep '13

From: Oleg_Kosheliev <oleg.kosheliev(a)ti.com> The u-boot-spl image must be stored in SRAM at addresses from 0x40300000 till 0x4030bfff. Higher than that area is located the ROM code stack. Thus we should check that the highest address of the SPL image is not in the stack area or higher. In this patch CONFIG_SPL_MAX_SIZE is corrected based on the max allowed for SPL image address. Signed-off-by: Oleg Kosheliev <oleg.kosheliev(a)ti.com> --- include/configs/omap4_common.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 2fa4382..aeeef6c 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -266,7 +266,14 @@ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x40304350 -#define CONFIG_SPL_MAX_SIZE (38 * 1024) +/* + * The allowed space in SRAM for SPL is from 0x40300000 till 0x4030bfff. + * The space above 0x4030c000 is used by ROM code stack + * and this area must not be rewritten by the SPL + */ +#define CONFIG_SPL_MAX_ADDR 0x4030bfff +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_MAX_ADDR - \ + CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SPL_DISPLAY_PRINT -- 1.7.9.5

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[U-Boot] [PATCH] config.mk: Delete unnecessary code
by Masahiro Yamada 01 Sep '13

01 Sep '13

Currently no makefiles set the following variables: CONFIG_SPL_TEXT_BASE CONFIG_UBOOT_PAD_TO CONFIG_RESET_VECTOR_ADDRESS For all targets which use above macros they are set in header files (include/configs/*.h), so we do not need to set them as CPPFLAGS. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- config.mk | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/config.mk b/config.mk index b16fad8..240b6df 100644 --- a/config.mk +++ b/config.mk @@ -206,18 +206,10 @@ ifneq ($(CONFIG_SYS_TEXT_BASE),) CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) endif -ifneq ($(CONFIG_SPL_TEXT_BASE),) -CPPFLAGS += -DCONFIG_SPL_TEXT_BASE=$(CONFIG_SPL_TEXT_BASE) -endif - ifneq ($(CONFIG_SPL_PAD_TO),) CPPFLAGS += -DCONFIG_SPL_PAD_TO=$(CONFIG_SPL_PAD_TO) endif -ifneq ($(CONFIG_UBOOT_PAD_TO),) -CPPFLAGS += -DCONFIG_UBOOT_PAD_TO=$(CONFIG_UBOOT_PAD_TO) -endif - ifeq ($(CONFIG_SPL_BUILD),y) CPPFLAGS += -DCONFIG_SPL_BUILD endif @@ -230,10 +222,6 @@ Please undefined CONFIG_SYS_GENERIC_BOARD in your board config file) endif endif -ifneq ($(RESET_VECTOR_ADDRESS),) -CPPFLAGS += -DRESET_VECTOR_ADDRESS=$(RESET_VECTOR_ADDRESS) -endif - ifneq ($(OBJTREE),$(SRCTREE)) CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include endif -- 1.8.1.2

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[U-Boot] [PATCH] ARM: mxs: rename function that sets AUTO_RESTART flag
by Hector Palacios 31 Aug '13

31 Aug '13

The AUTO_RESTART flag of HW_RTC_PERSISTENT0 register will power up the chip automatically 180ms after power down. This bit must be enabled by the boot loader to ensure the target can start upon hardware reset or watchdog reset even when powered from a battery. Currently the function named 'mxs_power_clear_auto_restart()' is setting this flag although the 'clear' in its name suggest the opposite. This patch renames the function to 'mxs_power_set_auto_restart()' and removes the comment about EVK revision A which was confusing because the function indeed was setting the flag. Signed-off-by: Hector Palacios <hector.palacios(a)digi.com> --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 5ee2d88..285ac79 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -52,7 +52,7 @@ static void mxs_power_clock2pll(void) CLKCTRL_CLKSEQ_BYPASS_CPU); } -static void mxs_power_clear_auto_restart(void) +static void mxs_power_set_auto_restart(void) { struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE; @@ -65,10 +65,7 @@ static void mxs_power_clear_auto_restart(void) while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE) ; - /* - * Due to the hardware design bug of mx28 EVK-A - * we need to set the AUTO_RESTART bit. - */ + /* Do nothing if flag already set */ if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART) return; @@ -903,7 +900,7 @@ void mxs_power_init(void) (struct mxs_power_regs *)MXS_POWER_BASE; mxs_power_clock2xtal(); - mxs_power_clear_auto_restart(); + mxs_power_set_auto_restart(); mxs_power_set_linreg(); mxs_power_setup_5v_detect();

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[U-Boot] [PATCH] fsl: Fix compiler warnings from gcc-4.4 in sys_eeprom code
by Kumar Gala 30 Aug '13

30 Aug '13

sys_eeprom.c: In function 'do_mac': sys_eeprom.c:323: warning: dereferencing type-punned pointer will break strict-aliasing rules sys_eeprom.c: In function 'mac_read_from_eeprom': sys_eeprom.c:395: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- board/freescale/common/sys_eeprom.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index ae5304a..3e1e332 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -78,12 +78,14 @@ static int has_been_read = 0; #ifdef CONFIG_SYS_I2C_EEPROM_NXID /* Is this a valid NXID EEPROM? */ -#define is_valid (*((u32 *)e.id) == (('N' << 24) | ('X' << 16) | ('I' << 8) | 'D')) +#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \ + (e.id[2] == 'I') || (e.id[3] == 'D')) #endif #ifdef CONFIG_SYS_I2C_EEPROM_CCID /* Is this a valid CCID EEPROM? */ -#define is_valid (*((u32 *)e.id) == (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D')) +#define is_valid ((e.id[0] == 'C') || (e.id[1] == 'C') || \ + (e.id[2] == 'I') || (e.id[3] == 'D')) #endif /** -- 1.6.0.6

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[U-Boot] [PATCH] Origen: Set FIMD as the default display path
by Tushar Behera 30 Aug '13

30 Aug '13

On EXYNOS4210, there are three paths for display data to be processed, namely MIE, MDNIE and FIMD. On Origen board, FIMD display controller is used. Signed-off-by: Tushar Behera <tushar.behera(a)linaro.org> --- This patch is rebased on master branch of u-boot-samsung tree. board/samsung/origen/lowlevel_init.S | 13 +++++++++++++ board/samsung/origen/origen_setup.h | 7 +++++++ 2 files changed, 20 insertions(+) diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S index be9d418..a7ea680 100644 --- a/board/samsung/origen/lowlevel_init.S +++ b/board/samsung/origen/lowlevel_init.S @@ -89,6 +89,7 @@ lowlevel_init: bl uart_asm_init bl arch_cpu_init bl tzpc_init + bl display_init pop {pc} wakeup_reset: @@ -96,6 +97,7 @@ wakeup_reset: bl mem_ctrl_asm_init bl arch_cpu_init bl tzpc_init + bl display_init exit_wakeup: /* Load return address and jump to kernel */ @@ -355,3 +357,14 @@ uart_asm_init: nop nop +/* Setting default display path to FIMD */ +display_init: + push {lr} + ldr r0, =EXYNOS4_SYSREG_BASE + + /* DISPLAY_CONTROL */ + ldr r1, =DISPLAY_CONTROL_VAL + ldr r2, =DISPLAY_CONTROL_OFFSET + str r1, [r0, r2] + + pop {pc} diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h index 926a4cc..b0e1bc2 100644 --- a/board/samsung/origen/origen_setup.h +++ b/board/samsung/origen/origen_setup.h @@ -83,6 +83,8 @@ #define VPLL_CON0_OFFSET 0xC120 #define VPLL_CON1_OFFSET 0xC124 +#define DISPLAY_CONTROL_OFFSET 0x210 + /* DMC: DRAM Controllor Register offsets */ #define DMC_CONCONTROL 0x00 #define DMC_MEMCONTROL 0x04 @@ -485,6 +487,11 @@ | (VPLL_MRR << 24) \ | (VPLL_MFR << 16) \ | (VPLL_K << 0)) + +/* DISPLAY_CONTROL */ +#define FIMDBYPASS_LBLK0 0x1 +#define DISPLAY_CONTROL_VAL (FIMDBYPASS_LBLK0 << 1) + /* * UART GPIO_A0/GPIO_A1 Control Register Value * 0x2: UART Function -- 1.7.9.5

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