June 2013 - U-Boot

[U-Boot] [PATCH] mx6slevk: Allow booting a device tree kernel
by Fabio Estevam 03 Jun '13

03 Jun '13

From: Fabio Estevam <fabio.estevam(a)freescale.com> When the mx6slevk board support was added in U-boot there was no device tree support for mx6sl, so only a FSL 3.0.35 was tested at that time. Now that mx6slevk support is available we can boot a device tree kernel, by adjusting CONFIG_LOADADDR into a proper location, so that a non-dt and a dt kernels can be booted. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- include/configs/mx6slevk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 8a94efd..19dcdd6 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -59,7 +59,7 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_LOADADDR 0x80800000 +#define CONFIG_LOADADDR 0x82000000 #define CONFIG_SYS_TEXT_BASE 0x87800000 #define CONFIG_EXTRA_ENV_SETTINGS \ -- 1.8.1.2

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[U-Boot] [PATCH] arm: mxs: Fix vectoring table crafting
by Marek Vasut 03 Jun '13

03 Jun '13

The vectoring table has to be placed at 0x0, but U-Boot on MX23/MX28 starts from RAM, so the vectoring table at 0x0 is not present. Craft code that will be placed at 0x0 and will redirect interrupt vectoring to proper location of the U-Boot in RAM. Signed-off-by: Marek Vasut <marex(a)denx.de> CC: Stefano Babic <sbabic(a)denx.de> CC: Fabio Estevam <fabio.estevam(a)freescale.com> --- arch/arm/cpu/arm926ejs/mxs/mxs.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index e2b4196..600e2a8 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -139,13 +139,32 @@ int mxs_reset_block(struct mxs_register_32 *reg) return 0; } +/* + * This function will craft a jumptable at 0x0 which will redirect interrupt + * vectoring to proper location of U-Boot in RAM. + * + * The structure of the jumptable will be as follows: + * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times + * <destination address> ... for each previous ldr, thus also repeated 8 times + * + * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at + * offset 0x18 from current value of PC register. Note that PC is already + * incremented by 4 when computing the offset, so the effective offset is + * actually 0x20, this the associated <destination address>. Loading the PC + * register with an address performs a jump to that address. + */ void mx28_fixup_vt(uint32_t start_addr) { - uint32_t *vt = (uint32_t *)0x20; + /* ldr pc, [pc, #0x18] */ + const uint32_t ldr_pc = 0xe59ff018; + /* Jumptable location is 0x0 */ + uint32_t *vt = (uint32_t *)0x0; int i; - for (i = 0; i < 8; i++) - vt[i] = start_addr + (4 * i); + for (i = 0; i < 8; i++) { + vt[i] = ldr_pc; + vt[i + 8] = start_addr + (4 * i); + } } #ifdef CONFIG_ARCH_MISC_INIT -- 1.7.10.4

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[U-Boot] [PATCH v4 0/7] arm: vf610: Add Freescale Vybrid VF610 CPU and VF610TWR board support
by Alison Wang 03 Jun '13

03 Jun '13

This series contain the support for Freescale Vybrid VF610 CPU and VF610TWR board. Vybird devices are built on an asymmetrical-multiprocessing architecture using ARM cores. The families in the Vybrid portfolio span entry-level, single core Cortex-A class SoCs all the way to dual heterogeneous core SoCs with multiple communication and connectivity options. Part of the Vybrid platform, VF610 is a dual-core eMPU combining the ARM Cortex A5 and Cortex M4 cores. VF610 shares some IPs with i.MX family, such as FEC,ESDHC,WATCHDOG,I2C,ASRC and ESAI. VF610 also shares some IPs with ColdFire family, such as eDMA and DSPI. VF610 still has its own IPs, such as PIT,SAI,UART,QSPI and DCU. More documents for this soc can be found at: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=VF6xx&fsrch=… http://www.freescale.com/webapp/sps/site/homepage.jsp?code=VYBRID To align with the description in the above documents, "VF610" is used as the SoC name instead of "MVF600". The u-boot runs on Cortex A5 core. Changes in v4: - Rename "MVF600" to "VF610" - Define PAD_CTL_PUS_47K_UP and PAD_CTL_PUS_100K_UP with PAD_CTL_PUE enabled - Reorganize the definitions - Correct the spaces and tabs - Rename mvf_pins.h to iomux-vf610.h - Add README.vf610 about fuse assignments for MAC addresses - Rename directory name 'mvf600' to 'vf610' - Rename directory 'arch-mvf600' to 'arch-vf610' - Add Vybrid VF610 to mxc_ocotp document - Rename directory name 'mvf600twr' to 'vf610twr' - Rename mvf600twr.h to vf610twr.h - Use NEW_PAD_CTRL instead of MUX_PAD_CTRL - Remove CONFIG_ETHPRIME option - Add CONFIG_CMD_MEMSET option Changes in v3: - Rename the common functions and enums - Move the structure definitions to imx-regs.h - Define PAD_CTL_PUE with PKE enabled - Remove the changes for FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII / FEC_RCNTRL_MII_MODE bits, as they are already set in fec_reg_setup() - Replace BOOT_FROM by BOOT_OFFSET - Enable CONFIG_OF_LIBFDT option - Add useful define instead of raw number - Use clrsetbits_le32 to set the single bits - Move setup_iomux_enet() to board_early_init_f and remove board_eth_init() - Remove redundant define - Move CONFIG_IOMUX_SHARE_CONF_REG to imx-regs.h Changes in v2: - Remove vybrid-common directory - Rename directory name 'vybrid' to 'mvf600' - Add generic.c file - Rewrite get_reset_cause() to make it readable - Remove reset_cpu(), and use the function in imx_watchdog.c - Rewrite timer.c file - Use vybrid_get_clock(VYBRID_UART_CLK) instead of vybrid_get_uartclk() - Remove lowlevel_init.S, and add clock_init() in board_early_init_f() - Remove useless CONFIG_SYS_ defines - Move CONFIG_MACH_TYPE to board configuration file - Define C structures and access C structures to set/read registers - Remove useless errata - Remove useless macros - Rename directory 'arch-vybrid' to 'arch-mvf600' - Use common iomux-v3 code - Use common FEC driver fec_mxc.c - Add watchdog support - Add an entry to MAINTAINERS file - Rename directory name 'vybird' to 'mvf600twr' - Use standard method to set gd->ram_size - Rewrite board_mmc_getcd() function - Remove useless undef - Remove hardcoded IP addresses and MAC addresses - Move CONFIG_MACH_TYPE to board configuration file ---------------------------------------------------------------- Alison Wang (7): arm: vf610: Add IOMUX support for Vybrid VF610 arm: vf610: Add Vybrid VF610 CPU support net: fec_mxc: Add support for Vybrid VF610 arm: vf610: Add watchdog support for Vybrid VF610 arm: vf610: Add uart support for Vybrid VF610 arm: vf610: Add Vybrid VF610 to mxc_ocotp document arm: vf610: Add basic support for Vybrid VF610TWR board MAINTAINERS | 4 + Makefile | 2 +- arch/arm/cpu/armv7/vf610/Makefile | 42 +++++++++++ arch/arm/cpu/armv7/vf610/generic.c | 324 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/vf610/timer.c | 103 ++++++++++++++++++++++++++ arch/arm/imx-common/Makefile | 2 +- arch/arm/imx-common/iomux-v3.c | 6 ++ arch/arm/include/asm/arch-vf610/clock.h | 39 ++++++++++ arch/arm/include/asm/arch-vf610/crm_regs.h | 225 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-vf610/imx-regs.h | 419 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-vf610/iomux-vf610.h | 101 +++++++++++++++++++++++++ arch/arm/include/asm/imx-common/iomux-v3.h | 18 +++++ board/freescale/vf610twr/Makefile | 39 ++++++++++ board/freescale/vf610twr/imximage.cfg | 33 +++++++++ board/freescale/vf610twr/vf610twr.c | 410 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + doc/README.mxc_ocotp | 1 + doc/README.vf610 | 10 +++ drivers/net/fec_mxc.c | 4 +- drivers/serial/Makefile | 1 + drivers/serial/serial_lpuart.c | 132 +++++++++++++++++++++++++++++++++ drivers/watchdog/Makefile | 2 +- include/configs/vf610twr.h | 140 +++++++++++++++++++++++++++++++++++ 23 files changed, 2052 insertions(+), 6 deletions(-) create mode 100644 arch/arm/cpu/armv7/vf610/Makefile create mode 100644 arch/arm/cpu/armv7/vf610/generic.c create mode 100644 arch/arm/cpu/armv7/vf610/timer.c create mode 100644 arch/arm/include/asm/arch-vf610/clock.h create mode 100644 arch/arm/include/asm/arch-vf610/crm_regs.h create mode 100644 arch/arm/include/asm/arch-vf610/imx-regs.h create mode 100644 arch/arm/include/asm/arch-vf610/iomux-vf610.h create mode 100644 board/freescale/vf610twr/Makefile create mode 100644 board/freescale/vf610twr/imximage.cfg create mode 100644 board/freescale/vf610twr/vf610twr.c create mode 100644 doc/README.vf610 create mode 100644 drivers/serial/serial_lpuart.c create mode 100644 include/configs/vf610twr.h

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[U-Boot] [PATCH V2 0/5] ARM: OMAP: Cleanup save_boot_params function
by Sricharan R 03 Jun '13

03 Jun '13

The save_boot_params function does not store the data in a always writable area. So the code is broken for a 'XIP' boot. This series corrects this by storing it in 'gd' and also adds a 'C' equivalent function for the same. The essential cleanups for the same are added in this. Tested this on omap5 uevm board with SD/EMMC boot. omap4/5 boards does not have a XIP flash. So yet to test XIP with this series. Also verfied a MAKEALL for armv7. Sricharan R (5): ARM: OMAP: Make omap_boot_parameters common across socs ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines common ARM: OMAP: Correct save_boot_params and replace with 'C' function ARM: OMAP: Cleanup boot parameters usage ARM: OMAP: Add arch_cpu_init function arch/arm/cpu/armv7/lowlevel_init.S | 8 +++- arch/arm/cpu/armv7/omap-common/boot-common.c | 20 ++------ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 61 +++++++++++++++++++++--- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 50 +------------------ arch/arm/cpu/armv7/omap4/emif.c | 4 +- arch/arm/cpu/armv7/omap4/hw_data.c | 2 +- arch/arm/cpu/armv7/omap4/hwinit.c | 3 +- arch/arm/cpu/armv7/omap5/emif.c | 4 +- arch/arm/cpu/armv7/omap5/hw_data.c | 2 +- arch/arm/cpu/armv7/omap5/hwinit.c | 3 +- arch/arm/include/asm/arch-am33xx/omap.h | 25 ---------- arch/arm/include/asm/arch-omap4/omap.h | 36 -------------- arch/arm/include/asm/arch-omap4/sys_proto.h | 11 ++--- arch/arm/include/asm/arch-omap5/omap.h | 36 -------------- arch/arm/include/asm/arch-omap5/sys_proto.h | 12 ++--- arch/arm/include/asm/global_data.h | 8 ++++ arch/arm/include/asm/omap_boot.h | 50 +++++++++++++++++++ arch/arm/include/asm/omap_common.h | 19 ++++++++ common/spl/spl.c | 12 +++-- include/configs/am335x_evm.h | 4 ++ include/configs/omap4_common.h | 4 ++ include/configs/omap5_common.h | 3 ++ include/configs/pcm051.h | 4 ++ include/configs/ti814x_evm.h | 4 ++ include/spl.h | 1 - 25 files changed, 187 insertions(+), 199 deletions(-) create mode 100644 arch/arm/include/asm/omap_boot.h -- 1.7.9.5

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[U-Boot] [PATCH 1/3] omap-common/hwinit-common.c: Mark omap_rev_string as static
by Tom Rini 03 Jun '13

03 Jun '13

Only called in this file, mark as static. Signed-off-by: Tom Rini <trini(a)ti.com> --- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 1645120..e614641 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -84,7 +84,7 @@ u32 cortex_rev(void) return rev; } -void omap_rev_string(void) +static void omap_rev_string(void) { u32 omap_rev = omap_revision(); u32 soc_variant = (omap_rev & 0xF0000000) >> 28; -- 1.7.9.5

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[U-Boot] [RFC PATCH] arm: lds: Remove libgcc eabi exception handling tables
by Michal Simek 03 Jun '13

03 Jun '13

Remove ARM eabi exception handling tables (for frame unwinding). AFAICT, u-boot stubs away the frame unwiding routines, so the tables will more or less just consume space. It should be OK to remove them. Signed-off-by: Edgar E. Iglesias <edgar.iglesias(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Other options could be to complete u-boot/arch/arm/lib/* so that libgcc routines with exception handling dont get pulled in. Or to avoid user code (like the mentioned patch) which causes external libgcc functions to get pulled in... --- arch/arm/cpu/u-boot.lds | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index d9bbee3..e139b90 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -106,4 +106,6 @@ SECTIONS /DISCARD/ : { *(.plt*) } /DISCARD/ : { *(.interp*) } /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.ARM.exidx*) } + /DISCARD/ : { *(.gnu.linkonce.armexidx.*) } } -- 1.8.2.1

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[U-Boot] [PATCH v2 2/8] sf: spansion: Add support for S25FL128S_64K
by Jagannadha Sutradharudu Teki 02 Jun '13

02 Jun '13

This commit is based on the patch from Xie Xiaobo <X.Xie(a)freescale.com> with commit head title as "sf: spansion: Add support for S25FL128S". pulled the same code changes into current u-boot tree with little update on the name field. http://patchwork.ozlabs.org/patch/218145/ SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash memory have the same device ID and Memory architecture. So they can use the same config parameters. Signed-off-by: Xie Xiaobo <X.Xie(a)freescale.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- Changes for v2: - none drivers/mtd/spi/spansion.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c index 2218e2f..dad4fbb 100644 --- a/drivers/mtd/spi/spansion.c +++ b/drivers/mtd/spi/spansion.c @@ -101,7 +101,7 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { .idcode2 = 0x4d01, .pages_per_sector = 256, .nr_sectors = 256, - .name = "S25FL129P_64K", + .name = "S25FL129P_64K/S25FL128S_64K", }, { .idcode1 = 0x0219, -- 1.8.3

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[U-Boot] [PATCH v3] spi/arm-pl022: Add support for ARM PL022 spi controller
by Vipin Kumar 02 Jun '13

02 Jun '13

From: Armando Visconti <armando.visconti(a)st.com> This patch adds the support for the ARM PL022 SPI controller for the standard variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO. Signed-off-by: Armando Visconti <armando.visconti(a)st.com> Signed-off-by: Vipin Kumar <vipin.kumar(a)st.com> --- Changes in v3 Added void to spi_init arguments Used readl/writel in place of u16 accessors Fix: Provided address of register in place of value to readl/writel IO accessors Tested with spear1340-evb Stefan, I have not added your Acked-by because the patch has changed after you acked it. drivers/spi/Makefile | 1 + drivers/spi/pl022_spi.c | 310 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 311 insertions(+) create mode 100644 drivers/spi/pl022_spi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 824d357..3a4e4b0 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -42,6 +42,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o +COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c new file mode 100644 index 0000000..86d65ae --- /dev/null +++ b/drivers/spi/pl022_spi.c @@ -0,0 +1,310 @@ +/* + * (C) Copyright 2012 + * Armando Visconti, ST Microelectronics, armando.visconti(a)st.com. + * + * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c + * by Atmel Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +/* SSP registers mapping */ +struct pl022 { + u32 ssp_cr0; /* 0x000 */ + u32 ssp_cr1; /* 0x004 */ + u32 ssp_dr; /* 0x008 */ + u32 ssp_sr; /* 0x00c */ + u32 ssp_cpsr; /* 0x010 */ + u32 ssp_imsc; /* 0x014 */ + u32 ssp_ris; /* 0x018 */ + u32 ssp_mis; /* 0x01c */ + u32 ssp_icr; /* 0x020 */ + u32 ssp_dmacr; /* 0x024 */ + u8 reserved_1[0x080 - 0x028]; + u32 ssp_itcr; /* 0x080 */ + u32 ssp_itip; /* 0x084 */ + u32 ssp_itop; /* 0x088 */ + u32 ssp_tdr; /* 0x08c */ + u8 reserved_2[0xFE0 - 0x090]; + u32 ssp_pid0; /* 0xfe0 */ + u32 ssp_pid1; /* 0xfe4 */ + u32 ssp_pid2; /* 0xfe8 */ + u32 ssp_pid3; /* 0xfec */ + u32 ssp_cid0; /* 0xff0 */ + u32 ssp_cid1; /* 0xff4 */ + u32 ssp_cid2; /* 0xff8 */ + u32 ssp_cid3; /* 0xffc */ +}; + +/* SSP Control Register 0 - SSP_CR0 */ +#define SSP_CR0_SPO (0x1 << 6) +#define SSP_CR0_SPH (0x1 << 7) +#define SSP_CR0_8BIT_MODE (0x07) +#define SSP_SCR_MAX (0xFF) +#define SSP_SCR_SHFT 8 + +/* SSP Control Register 0 - SSP_CR1 */ +#define SSP_CR1_MASK_SSE (0x1 << 1) + +#define SSP_CPSR_MAX (0xFE) + +/* SSP Status Register - SSP_SR */ +#define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty */ +#define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not full */ +#define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not empty */ +#define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full */ +#define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */ + +struct pl022_spi_slave { + struct spi_slave slave; + void *regs; + unsigned int freq; +}; + +static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave) +{ + return container_of(slave, struct pl022_spi_slave, slave); +} + +/* + * Following three functions should be provided by the + * board support package. + */ +int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void __weak spi_cs_activate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void __weak spi_cs_deactivate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void spi_init(void) +{ + /* do nothing */ +} + +/* + * ARM PL022 exists in different 'flavors'. + * This drivers currently support the standard variant (0x00041022), that has a + * 16bit wide and 8 locations deep TX/RX FIFO. + */ +static int pl022_is_supported(struct pl022_spi_slave *ps) +{ + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* PL022 version is 0x00041022 */ + if ((readl(&pl022->ssp_pid0) == 0x22) && + (readl(&pl022->ssp_pid1) == 0x10) && + ((readl(&pl022->ssp_pid2) & 0xf) == 0x04) && + (readl(&pl022->ssp_pid3) == 0x00)) + return 1; + + return 0; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct pl022_spi_slave *ps; + struct pl022 *pl022; + u16 scr = 1, prescaler, cr0 = 0, cpsr = 0; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ps = malloc(sizeof(*ps)); + if (!ps) + return NULL; + + ps->slave.bus = bus; + ps->slave.cs = cs; + ps->freq = max_hz; + + switch (bus) { + case 0: + ps->regs = (void *)CONFIG_SYS_SPI_BASE; + break; +#ifdef CONFIG_SYS_SPI_BASE1 + case 1: + ps->regs = (void *)CONFIG_SYS_SPI_BASE1; + break; +#endif +#ifdef CONFIG_SYS_SPI_BASE2 + case 2: + ps->regs = (void *)CONFIG_SYS_SPI_BASE2; + break; +#endif +#ifdef CONFIG_SYS_SPI_BASE3 + case 3: + ps->regs = (void *)CONFIG_SYS_SPI_BASE3; + break; +#endif + default: + free(ps); + return NULL; + } + + pl022 = (struct pl022 *)ps->regs; + + /* Check the PL022 version */ + if (!pl022_is_supported(ps)) { + free(ps); + return NULL; + } + + /* Set requested polarity and 8bit mode */ + cr0 = SSP_CR0_8BIT_MODE; + cr0 |= (mode & SPI_CPHA) ? SSP_CR0_SPH : 0; + cr0 |= (mode & SPI_CPOL) ? SSP_CR0_SPO : 0; + + writel(cr0, &pl022->ssp_cr0); + + /* Program the SSPClk frequency */ + prescaler = CONFIG_SYS_SPI_CLK / ps->freq; + + if (prescaler <= 0xFF) + cpsr = prescaler; + else { + for (scr = 1; scr <= SSP_SCR_MAX; scr++) { + if (!(prescaler % scr)) { + cpsr = prescaler / scr; + if (cpsr <= SSP_CPSR_MAX) + break; + } + } + + if (scr > SSP_SCR_MAX) { + scr = SSP_SCR_MAX; + cpsr = prescaler / scr; + cpsr &= SSP_CPSR_MAX; + } + } + + if (cpsr & 0x1) + cpsr++; + + writel(cpsr, &pl022->ssp_cpsr); + cr0 = readl(&pl022->ssp_cr0); + writel(cr0 | (scr - 1) << SSP_SCR_SHFT, &pl022->ssp_cr0); + + return &ps->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + + free(ps); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* Enable the SPI hardware */ + setbits_le32(&pl022->ssp_cr1, SSP_CR1_MASK_SSE); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* Disable the SPI hardware */ + writel(0x0, &pl022->ssp_cr1); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + u32 len_tx = 0, len_rx = 0, len; + u32 ret = 0; + const u8 *txp = dout; + u8 *rxp = din, value; + + if (bitlen == 0) + /* Finish any previously submitted transfers */ + goto out; + + /* + * TODO: The controller can do non-multiple-of-8 bit + * transfers, but this driver currently doesn't support it. + * + * It's also not clear how such transfers are supposed to be + * represented as a stream of bytes...this is a limitation of + * the current SPI interface. + */ + if (bitlen % 8) { + ret = -1; + + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + while (len_tx < len) { + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_TNF) { + value = (txp != NULL) ? *txp++ : 0; + writel(value, &pl022->ssp_dr); + len_tx++; + } + + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_RNE) { + value = readl(&pl022->ssp_dr); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + + while (len_rx < len_tx) { + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_RNE) { + value = readl(&pl022->ssp_dr); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + +out: + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return ret; +} -- 1.8.0

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[U-Boot] [U-BOOT PATCH] sf: Fix sf read for memory-mapped SPI flashes
by Jagannadha Sutradharudu Teki 02 Jun '13

02 Jun '13

Missing return after memcpy is done for memory-mapped SPI flashes, hence added retun 0 after memcpy done. The return is missing in below patch "sf: Enable FDT-based configuration and memory mapping" (sha1: bb8215f437a7c948eec82a6abe754c226978bd6d) Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- drivers/mtd/spi/spi_flash.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index aeb1ccb..1d45e3b 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -148,8 +148,10 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, u8 cmd[5]; /* Handle memory-mapped SPI */ - if (flash->memory_map) + if (flash->memory_map) { memcpy(data, flash->memory_map + offset, len); + return 0; + } cmd[0] = CMD_READ_ARRAY_FAST; spi_flash_addr(offset, cmd); -- 1.7.4

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[U-Boot] [PATCH v3 1/2] cmd_sf: Add print mesg for 'sf erase' command
by Jagannadha Sutradharudu Teki 02 Jun '13

02 Jun '13

This patch adds a print messages while using 'sf erase' command to make sure that how many bytes erased in flash device. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- common/cmd_sf.c | 8 +++----- drivers/mtd/spi/spi_flash.c | 7 ++----- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/common/cmd_sf.c b/common/cmd_sf.c index 1daff70..12d1aca 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -305,12 +305,10 @@ static int do_spi_flash_erase(int argc, char * const argv[]) } ret = spi_flash_erase(flash, offset, len); - if (ret) { - printf("SPI flash %s failed\n", argv[0]); - return 1; - } + printf("SF: %zu bytes @ %#x Erased: %s\n", (size_t)len, (u32)offset, + ret ? "ERROR" : "OK"); - return 0; + return ret == 0 ? 0 : 1; } #ifdef CONFIG_CMD_SF_TEST diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index d2bee3a..77938d3 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -206,7 +206,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len) { - u32 start, end, erase_size; + u32 end, erase_size; int ret; u8 cmd[4]; @@ -226,8 +226,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len) cmd[0] = CMD_ERASE_4K; else cmd[0] = CMD_ERASE_64K; - start = offset; - end = start + len; + end = offset + len; while (offset < end) { spi_flash_addr(offset, cmd); @@ -251,8 +250,6 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len) goto out; } - debug("SF: Successfully erased %zu bytes @ %#x\n", len, start); - out: spi_release_bus(flash->spi); return ret; -- 1.7.4

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