June 2013 - U-Boot

[U-Boot] [PATCH] powerpc/B4860: enable PBL tool for B4860
by Shaohui Xie 04 Jun '13

04 Jun '13

Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a pbl boot image. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- board/freescale/b4860qds/b4_pbi.cfg | 27 +++++++++++++++++++++++++++ board/freescale/b4860qds/b4_rcw.cfg | 7 +++++++ include/configs/B4860QDS.h | 2 ++ 3 files changed, 36 insertions(+) create mode 100644 board/freescale/b4860qds/b4_pbi.cfg create mode 100644 board/freescale/b4860qds/b4_rcw.cfg diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg new file mode 100644 index 0000000..57b726e --- /dev/null +++ b/board/freescale/b4860qds/b4_pbi.cfg @@ -0,0 +1,27 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/b4860qds/b4_rcw.cfg b/board/freescale/b4860qds/b4_rcw.cfg new file mode 100644 index 0000000..7bf0066 --- /dev/null +++ b/board/freescale/b4860qds/b4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x2A_0x98 +140e0018 0f001218 00000000 00000000 +54980000 9000a000 e8904000 a9000000 +01000000 00000000 00000000 0001f1f8 +00000000 14000020 00000000 00000011 diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 1c9d08e..f8ab478 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -32,6 +32,8 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg +#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg #endif /* High Level Configuration Options */ -- 1.8.0

1 0

[U-Boot] [PATCH] buildman: Allow make flags to be specified for each board
by Simon Glass 04 Jun '13

04 Jun '13

There are a few make options such as BUILD_TAG which can be provided when building U-Boot. Provide a way for buildman to pass these flags to make also. The flags should be in a [make-flags] section and arranged by target name (the 'target' column in boards.cfg. See the README for more details. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- tools/buildman/README | 22 +++++++++++++ tools/buildman/bsettings.py | 3 -- tools/buildman/builder.py | 1 + tools/buildman/buildman.py | 13 ++++++++ tools/buildman/toolchain.py | 79 +++++++++++++++++++++++++++++++++++++++++++-- 5 files changed, 113 insertions(+), 5 deletions(-) diff --git a/tools/buildman/README b/tools/buildman/README index 7221007..281bdbe 100644 --- a/tools/buildman/README +++ b/tools/buildman/README @@ -645,6 +645,28 @@ It is common when refactoring code for the rodata to decrease as the text size increases, and vice versa. +Providing 'make' flags +====================== + +U-Boot's build system supports a few flags (such as BUILD_TAG) which affect +the build product. These flags can be specified in the buildman settings +file. They can also be useful when building U-Boot against other open source +software. + +[make-flags] +at91-boards=ENABLE_AT91_TEST=1 +snapper9260=${at91-boards} BUILD_TAG=442 +snapper9g45=${at91-boards} BUILD_TAG=443 + +This will use 'make ENABLE_AT91_TEST=1 BUILD_TAG=442' for snapper9260 +and 'make ENABLE_AT91_TEST=1 BUILD_TAG=442' for snapper9g45. A special +variable ${target} is available to access the target name (snapper9260 and +snapper9g20 in this case). Variables are resolved recursively. + +It is expected that any variables added are dealt with in U-Boot's +config.mk file and documented in the README. + + Other options ============= diff --git a/tools/buildman/bsettings.py b/tools/buildman/bsettings.py index 7e66c63..6ca7b1e 100644 --- a/tools/buildman/bsettings.py +++ b/tools/buildman/bsettings.py @@ -52,9 +52,6 @@ def GetItems(section): return settings.items(section) except ConfigParser.NoSectionError as e: print e - print ("Warning: No tool chains - please add a [toolchain] section " - "to your buildman config file %s. See README for details" % - config_fname) return [] except: raise diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index e426442..b1a4d5a 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -269,6 +269,7 @@ class BuilderThread(threading.Thread): args.extend(['-j', str(self.builder.num_jobs)]) config_args = ['%s_config' % brd.target] config_out = '' + args.extend(self.builder.toolchains.GetMakeArguments(brd)) # If we need to reconfigure, do that now if do_config: diff --git a/tools/buildman/buildman.py b/tools/buildman/buildman.py index 7b05d0f..1e80c8a 100755 --- a/tools/buildman/buildman.py +++ b/tools/buildman/buildman.py @@ -48,6 +48,19 @@ import toolchain def RunTests(): import test + import doctest + + result = unittest.TestResult() + for module in ['toolchain']: + suite = doctest.DocTestSuite(module) + suite.run(result) + + # TODO: Surely we can just 'print' result? + print result + for test, err in result.errors: + print err + for test, err in result.failures: + print err sys.argv = [sys.argv[0]] suite = unittest.TestLoader().loadTestsFromTestCase(test.TestBuild) diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index e0a6970..9804dfc 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -19,6 +19,7 @@ # MA 02111-1307 USA # +import re import glob import os @@ -113,12 +114,18 @@ class Toolchains: def __init__(self): self.toolchains = {} self.paths = [] - for name, value in bsettings.GetItems('toolchain'): + toolchains = bsettings.GetItems('toolchain') + if not toolchains: + print ("Warning: No tool chains - please add a [toolchain] section" + " to your buildman config file %s. See README for details" % + config_fname) + + for name, value in toolchains: if '*' in value: self.paths += glob.glob(value) else: self.paths.append(value) - + self._make_flags = dict(bsettings.GetItems('make-flags')) def Add(self, fname, test=True, verbose=False): """Add a toolchain to our list @@ -183,3 +190,71 @@ class Toolchains: if not arch in self.toolchains: raise ValueError, ("No tool chain found for arch '%s'" % arch) return self.toolchains[arch] + + def ResolveReferences(self, var_dict, args): + """Resolve variable references in a string + + This converts ${blah} within the string to the value of blah. + This function works recursively. + + Args: + var_dict: Dictionary containing variables and their values + args: String containing make arguments + Returns: + Resolved string + + >>> tc = Toolchain('fred', False) + >>> var_dict = {'oblique' : 'OBLIQUE', 'first' : 'fi${second}rst', \ + 'second' : '2nd'} + >>> tc.ResolveReferences(var_dict, 'this=${oblique}_set') + 'this=OBLIQUE_set' + >>> tc.ResolveReferences(var_dict, 'this=${oblique}_set${first}nd') + 'this=OBLIQUE_setfi2ndrstnd' + """ + re_var = re.compile('(\$\{[a-z0-9A-Z]{1,}\})') + + while True: + m = re_var.search(args) + if not m: + break + lookup = m.group(0)[2:-1] + value = var_dict.get(lookup, '') + args = args[:m.start(0)] + value + args[m.end(0):] + return args + + def GetMakeArguments(self, board): + """Returns 'make' arguments for a given board + + The flags are in a section called 'make-flags'. Flags are named + after the target they represent, for example snapper9260=TESTING=1 + will pass TESTING=1 to make when building the snapper9260 board. + + References to other boards can be added in the string also. For + example: + + [make-flags] + at91-boards=ENABLE_AT91_TEST=1 + snapper9260=${at91-boards} BUILD_TAG=442 + snapper9g45=${at91-boards} BUILD_TAG=443 + + This will return 'ENABLE_AT91_TEST=1 BUILD_TAG=442' for snapper9260 + and 'ENABLE_AT91_TEST=1 BUILD_TAG=443' for snapper9g45. + + A special 'target' variable is set to the board target. + + Args: + board: Board object for the board to check. + Returns: + 'make' flags for that board, or '' if none + """ + self._make_flags['target'] = board.target + arg_str = self.ResolveReferences(self._make_flags, + self._make_flags.get(board.target, '')) + args = arg_str.split(' ') + i = 0 + while i < len(args): + if not args[i]: + del args[i] + else: + i += 1 + return args -- 1.8.2.1

1 1

[U-Boot] U-Boot fit_image_load() refactor patches
by Simon Glass 04 Jun '13

04 Jun '13

Hi Tom, I am not sure that anyone has reviewed these patches, but they are the next stage on cleaning up the image code. Here is a pull request: The following changes since commit d6639d10dbfa42dc888f8917012550b632a88959: Merge branch 'master' of git://git.denx.de/u-boot-nand-flash (2013-05-31 18:28:47 -0400) are available in the git repository at: git://git.denx.de/u-boot-x86.git image3 for you to fetch changes up to e4a91c94b31c651856fbd644987c6ac236ccf46a: sandbox: image: Create a test for loading FIT images (2013-06-03 01:41:56 -0700) ---------------------------------------------------------------- Simon Glass (10): bootstage: Introduce sub-IDs for use with image loading mkimage: Add map_sysmem() and IH_ARCH_DEFAULT to simplfy building image: Introduce fit_image_load() to load images from FITs image: Use fit_image_load() to load ramdisk image: Use fit_image_load() to load FDT sandbox: Adjust bootm command to work with sandbox image: Use fit_image_load() to load kernel sandbox: image: Adjust FIT image printing to work with sandbox bootstage: Remove unused entries related to kernel/ramdisk/fdt load sandbox: image: Create a test for loading FIT images common/cmd_bootm.c | 170 +++++------------------------------ common/image-fdt.c | 207 ++++++------------------------------------ common/image-fit.c | 310 +++++++++++++++++++++++++++++++++++++++++++++------------------ common/image.c | 122 ++++--------------------- include/bootstage.h | 51 ++++++----- include/image.h | 105 ++++++++++++++++++++-- test/image/test-fit.py | 422 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ tools/mkimage.h | 12 +++ 8 files changed, 846 insertions(+), 553 deletions(-) create mode 100755 test/image/test-fit.py Regards, Simon

1 1

[U-Boot] [PATCH 1/1] Add support of IB8315 board
by Sergey Gerasimov 03 Jun '13

03 Jun '13

Signed-off-by: Sergey Gerasimov <Sergey.Gerasimov(a)astrosoft-development.com> --- board/ib8315/Makefile | 49 +++ board/ib8315/sdram.c | 123 +++++++ board/ib8315/tqm8315.c | 194 +++++++++++ boards.cfg | 1 + drivers/block/fsl_sata.c | 21 ++ drivers/block/fsl_sata.h | 7 + include/configs/IB8315.h | 839 +++++++++++++++++++++++++++++++++++++++++++++++ include/sata.h | 4 + 8 files changed, 1238 insertions(+) create mode 100644 board/ib8315/Makefile create mode 100644 board/ib8315/sdram.c create mode 100644 board/ib8315/tqm8315.c create mode 100644 include/configs/IB8315.h diff --git a/board/ib8315/Makefile b/board/ib8315/Makefile new file mode 100644 index 0000000..aa74213 --- /dev/null +++ b/board/ib8315/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + + +COBJS := tqm8315.o sdram.o + +COBJS-$(CONFIG_PCIE) += pcie.o + +COBJS-$(CONFIG_PCI) += pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ib8315/sdram.c b/board/ib8315/sdram.c new file mode 100644 index 0000000..734362a --- /dev/null +++ b/board/ib8315/sdram.c @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2009 TQ-Systems GmbH + * + * Author: Thomas Waehner <thomas.waehner(a)tqs.de> + * + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * Authors: Nick.Spence(a)freescale.com + * Wilson.Lo(a)freescale.com + * scottwood(a)freescale.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <mpc83xx.h> +#include <spd_sdram.h> + +#include <asm/bitops.h> +#include <asm/io.h> + +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Fixed sdram init -- doesn't use serial presence detect. + * + * This is useful for faster booting in configs where the RAM is unlikely + * to be changed, or for things like NAND booting where space is tight. + */ +static long fixed_sdram(void) +{ + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2(msize); + volatile u32 law; + int i; + /* configure local access window for SDRAM address range */ + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); + /* + * According to MPC8315ERM Rev. 1 read back last configured local + * access window configuration register, followed by an isync. + */ + law = im->sysconf.ddrlaw[0].ar; + isync(); + + im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; + + + /* + * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], + * or the DDR2 controller may fail to initialize correctly. + */ + for (i = 0; i < 50; i++) + udelay(1000); + + im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + + /* Currently we use only one CS, so disable the other bank. */ + im->ddr.cs_config[1] = 0; + + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + + if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI; + else + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_md_cntl = CONFIG_SYS_DDR_SDRAM_MD_CNTL; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + eieio(); + + /* + * According to Freescale's application note AN2583 Rev. 8 wait 200 us + * after the DLL is locked before enabling the DDR controller. + */ + udelay(200); + + /* enable DDR controller */ + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + eieio(); + + return msize; +} + +phys_size_t initdram(int board_type) +{ + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + u32 msize; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM */ + msize = fixed_sdram(); + + /* return total bus SDRAM size(bytes) -- DDR */ + return msize; +} diff --git a/board/ib8315/tqm8315.c b/board/ib8315/tqm8315.c new file mode 100644 index 0000000..b21940d --- /dev/null +++ b/board/ib8315/tqm8315.c @@ -0,0 +1,194 @@ +/* + * Copyright (C) 2009 TQ-Systems GmbH + * + * Author: Thomas Waehner <thomas.waehner(a)tqs.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <pci.h> +#include <mpc83xx.h> +#include <netdev.h> +#include <sata.h> +#include <asm/io.h> +#include <asm/fsl_mpc83xx_serdes.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_83XX_GENERIC_PCIE) +#if !defined(CONFIG_FSL_SERDES) +#error PCIe operation needs CONFIG_FSL_SERDES +#endif +#endif + +#define PHYCTRLCFG_REFCLK_MASK 0x00000070 +#define PHYCTRLCFG_REFCLK_125MHZ 0x00000070 + +int board_early_init_f(void) +{ +#ifdef CONFIG_FSL_SERDES + /* Setup SERDES for PCIe operation */ + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); +#endif /* CONFIG_FSL_SERDES */ + return 0; +} + +int checkboard(void) +{ + puts("Board: TQM8315\n"); + return 0; +} + +static struct pci_region pci_regions[] = { + { + .bus_start = CONFIG_SYS_PCI_MEM_BASE, + .phys_start = CONFIG_SYS_PCI_MEM_PHYS, + .size = CONFIG_SYS_PCI_MEM_SIZE, + .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + .bus_start = CONFIG_SYS_PCI_MMIO_BASE, + .phys_start = CONFIG_SYS_PCI_MMIO_PHYS, + .size = CONFIG_SYS_PCI_MMIO_SIZE, + .flags = PCI_REGION_MEM + }, + { + .bus_start = CONFIG_SYS_PCI_IO_BASE, + .phys_start = CONFIG_SYS_PCI_IO_PHYS, + .size = CONFIG_SYS_PCI_IO_SIZE, + .flags = PCI_REGION_IO + } +}; + +#ifdef CONFIG_83XX_GENERIC_PCIE +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, + { + .size = 0, + } +}; + +static struct pci_region pcie_regions_1[] = { + { + .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, + .size = CONFIG_SYS_PCIE2_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE2_IO_BASE, + .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, + .size = CONFIG_SYS_PCIE2_IO_SIZE, + .flags = PCI_REGION_IO, + }, + { + .size = 0, + } +}; +#endif + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci_regions }; +#ifdef CONFIG_83XX_GENERIC_PCIE + volatile sysconf83xx_t *sysconf = &immr->sysconf; + volatile law83xx_t *pcie_law = sysconf->pcielaw; + struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; +#endif + + /* Enable all 3 PCI_CLK_OUTPUTs. */ + clk->occr |= 0xe0000000; + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + mpc83xx_pci_init(1, reg); + +#ifdef CONFIG_83XX_GENERIC_PCIE + /* Configure the clock for PCIE controller */ + clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, + SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + out_be32(&sysconf->pecr2, 0xE0008000); + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); + out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(2, pcie_reg); +#endif +} + +#ifdef CONFIG_LAST_STAGE_INIT +int last_stage_init(void) +{ +#ifdef CONFIG_FSL_SATA + /* Init SATA PHY CLK rate which must only be done once at startup */ + init_mpc8315_sata_phy(); +#endif + return 0; +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Initialize TSECs first */ + return pci_eth_init(bis); +} diff --git a/boards.cfg b/boards.cfg index e2a8d42..97ef108 100644 --- a/boards.cfg +++ b/boards.cfg @@ -734,6 +734,7 @@ MVBLM7 powerpc mpc83xx mvblm7 matrix_ SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP TQM834x powerpc mpc83xx tqm834x tqc +IB8315 powerpc mpc83xx ib8315 - suvd3 powerpc mpc83xx km83xx keymile - suvd3:SUVD3 kmvect1 powerpc mpc83xx km83xx keymile - suvd3:KMVECT1 tuge1 powerpc mpc83xx km83xx keymile - tuxx1:TUGE1 diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index 1f9d7b0..dc834a0 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -87,6 +87,27 @@ static int ata_wait_register(unsigned __iomem *addr, u32 mask, return (i < timeout_msec) ? 0 : -1; } +#if defined(CONFIG_MPC8315) +#ifndef CONFIG_SYS_SATA_CLK +#define CONFIG_SYS_SATA_CLK PHYCTRLCFG_REFCLK_75MHZ +#endif +/* If you have a MPC8315 board, you can call this function from last_stage_init + * call to setup the MPC8315 specific PHY clocking parameter */ +void init_mpc8315_sata_phy(void) +{ + u32 val32; + fsl_sata_reg_t *reg; + + reg = (fsl_sata_reg_t *)(CONFIG_SYS_IMMR + 0x18000); + + /* Configure PHY */ + val32 = in_le32(&reg->phyctrlcfg); + val32 &= ~PHYCTRLCFG_REFCLK_MASK; + val32 |= CONFIG_SYS_SATA_CLK; + out_le32(&reg->phyctrlcfg, val32); +} +#endif + int init_sata(int dev) { u32 length, align; diff --git a/drivers/block/fsl_sata.h b/drivers/block/fsl_sata.h index a9c27bc..0572a48 100644 --- a/drivers/block/fsl_sata.h +++ b/drivers/block/fsl_sata.h @@ -172,6 +172,13 @@ typedef struct fsl_sata_reg { #define PHYCTRLCFG_FPRFTI_MASK 0x00000018 #define PHYCTRLCFG_LOOPBACK_MASK 0x0000000e +#define PHYCTRLCFG_REFCLK_MASK 0x00000070 +#define PHYCTRLCFG_REFCLK_50MHZ 0x00000050 +#define PHYCTRLCFG_REFCLK_75MHZ 0x00000000 +#define PHYCTRLCFG_REFCLK_100MHZ 0x00000060 +#define PHYCTRLCFG_REFCLK_125MHZ 0x00000070 +#define PHYCTRLCFG_REFCLK_150MHZ 0x00000020 + /* * Command Header Entry */ diff --git a/include/configs/IB8315.h b/include/configs/IB8315.h new file mode 100644 index 0000000..dc897bd --- /dev/null +++ b/include/configs/IB8315.h @@ -0,0 +1,839 @@ +/* + * Copyright (C) 2009 TQ-Systems GmbH + * + * Author: Thomas Waehner <thomas.waehner(a)tqs.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 + +#ifdef CONFIG_NAND_U_BOOT +#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ +#define CONFIG_SYS_TEXT_BASE_SPL 0x81f00000 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#endif /* CONFIG_NAND_SPL */ +#endif /* CONFIG_NAND_U_BOOT */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x80000000 +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC831x 1 /* MPC831x CPU family */ +#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ +#define CONFIG_TQM8315 1 /* TQM8315 board specific */ + + + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +/* + * Hardware Reset Configuration Word + * if CLKIN is 66.666 MHz, then + * CSB = 133.333 MHz, CORE = 400 MHz, DDR-Contr. inp. = 266.666 MHz + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_SVCOD_DIV_2 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CORE_TO_CSB_3X1) +#define CONFIG_SYS_HRCW_HIGH_BASE (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) + +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_ROM_LOC_NAND_SP_8BIT |\ + HRCWH_RL_EXT_NAND) +#else +#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY) +#endif + + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x00000000 +#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */ + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_LAST_STAGE_INIT /* call last_stage_init for SATA init */ + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Arbiter Setup + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ +#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency prio is highest */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CONFIG_SYS_DDRCDR_VALUE 0x00080001 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_SYS_DDR_SIZE 256 /* MiB */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ODT_WR_ALL \ + | CSCONFIG_BANK_BIT_3 \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) + /* 0x80044102 */ +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (1 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (1 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (1 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (5 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00110105 */ +#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (9 << TIMING_CFG1_REFREC_SHIFT) \ + | (2 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x26259222 */ +#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (3 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x119048c7 */ +#define CONFIG_SYS_DDR_INTERVAL ((520 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x02080100 */ + +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_32 \ + | SDRAM_CFG_HSE) + /* 0x43080008 */ +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_MODE ((0x440e << SDRAM_MODE_ESD_SHIFT) \ + | (0x0232 << SDRAM_MODE_SD_SHIFT)) + /* 0x440e0232 */ +#define CONFIG_SYS_DDR_MODE2 0x8000C000 +#define CONFIG_SYS_DDR_SDRAM_MD_CNTL 0x00000000 +/* + * Memory test + */ +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00200000 + +/* + * The reserved memory + */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) + #define CONFIG_SYS_RAMBOOT +#else + #undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KiB for Mon*/ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xF0000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 +#define CONFIG_SYS_LBC_LBCR 0x00040000 +#define CONFIG_FSL_ELBC 1 + + +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size in MiB */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size */ + +#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ + + /* 0x80001001 */ +/* Flash timing for LBC = 66.666 MHz */ +#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_GPCM_CSNT \ + | OR_GPCM_SCY_3 \ + | OR_GPCM_TRLX_SET) + /* 0xFC000834 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ + (CONFIG_SYS_FLASH_BASE \ + + ((CONFIG_SYS_FLASH_SIZE / 2) << 20))} +#define CONFIG_SYS_MAX_FLASH_SECT 259 + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* + * NAND Flash on the Local Bus + * define CONFIG_NAND to use it + */ +#undef CONFIG_NAND + +#ifdef CONFIG_NAND + #define CONFIG_SYS_NAND_BASE 0xE0600000 + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_MTD_NAND_VERIFY_WRITE 1 + #define CONFIG_NAND_FSL_ELBC 1 + + /* + * Use HW ECC + * Port Size = 8 bit + * MSEL = FCM + */ + #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ + | (2 << BR_DECC_SHIFT) \ + | BR_PS_8 \ + | BR_MS_FCM \ + | BR_V) + #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 /* address mask 32 KiB */ \ + | OR_FCM_PGS \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_RST) + + #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE + #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32 KiB */ +#endif + +/* + * Serial Port + */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_FSL_I2C +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES {0x50} /* Don't probe config eeprom */ + +/* EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ + +/* + * Config on-board RTC + */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* I2C SYSMON (LM75) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_SYS_I2C_DTT_ADDR 0x48 /* Sensor base address */ +/* Use the following define if you only want the TQM8315 on-module sensor */ +#define CONFIG_DTT_SENSORS {0} +/* + * Use the following define if it is on a STK85xxNG + * to read the temp sensors there, too + */ +/* #define CONFIG_DTT_SENSORS {0, 1, 2, 3} */ +#define CONFIG_SYS_DTT_MAX_TEMP 70 +#define CONFIG_SYS_DTT_LOW_TEMP -30 +#define CONFIG_SYS_DTT_HYSTERESIS 3 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_PCI + +#ifdef CONFIG_PCI + #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ + #define CONFIG_83XX_GENERIC_PCIE 1 + #define CONFIG_PCIE +#endif + +#ifdef CONFIG_83XX_GENERIC_PCI + #define CONFIG_SYS_PCI_MEM_BASE 0xC0000000 + #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE + #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256 MiB */ + #define CONFIG_SYS_PCI_MMIO_BASE 0xD0000000 + #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE + #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256 MiB */ + #define CONFIG_SYS_PCI_IO_BASE (CONFIG_SYS_IMMR + 0x03000000) + #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BASE + #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1 MiB */ + + #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE + #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 + #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 + + #define CONFIG_NET_MULTI + #define CONFIG_PCI_PNP /* do pci plug-and-play */ + + #define CONFIG_EEPRO100 /* Intel Pro/100 NIC support */ + #define CONFIG_E1000 /* Intel Pro/1000 NIC support */ + #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + + #ifndef CONFIG_NET_MULTI + #define CONFIG_NET_MULTI 1 +#endif + +#ifdef CONFIG_83XX_GENERIC_PCIE + #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES + + #define CONFIG_SYS_PCIE1_BASE 0x40000000 + #define CONFIG_SYS_PCIE1_CFG_BASE 0x50000000 + #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 + #define CONFIG_SYS_PCIE1_MEM_BASE 0x40000000 + #define CONFIG_SYS_PCIE1_MEM_PHYS 0x40000000 + #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 + #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 + #define CONFIG_SYS_PCIE1_IO_PHYS (CONFIG_SYS_IMMR + 0x03100000) + #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + + #define CONFIG_SYS_PCIE2_BASE 0x60000000 + #define CONFIG_SYS_PCIE2_CFG_BASE 0x70000000 + #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 + #define CONFIG_SYS_PCIE2_MEM_BASE 0x60000000 + #define CONFIG_SYS_PCIE2_MEM_PHYS 0x60000000 + #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 + #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 + #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_IMMR + 0x03180000) + #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 + #endif +#endif + +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_SYS_SCCR_USBDRCM 1 + +#ifdef CONFIG_HAS_FSL_DR_USB + #define CONFIG_USB_EHCI + #define CONFIG_USB_EHCI_FSL + #define CONFIG_EHCI_HCD_INIT_AFTER_RESET + #define CONFIG_DOS_PARTITION + #define CONFIG_USB_STORAGE +#endif + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) + +/* + * TSEC ethernet configuration + */ +#define CONFIG_GMII + +#define CONFIG_PHYLIB 1 +#define CONFIG_PHY_VITESSE 1 + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS (TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +/* Options are: eTSEC[0-1] */ +#define CONFIG_ETHPRIME "eTSEC0" + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +/* SERDES */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 + +/* + * SATA + */ +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA +/* Choose the phy setting for your SATA clock + * The following values are possible for CONFIG_SYS_SATA_CLK: + * PHYCTRLCFG_REFCLK_50MHZ + * PHYCTRLCFG_REFCLK_75MHZ + * PHYCTRLCFG_REFCLK_100MHZ + * PHYCTRLCFG_REFCLK_125MHZ + * PHYCTRLCFG_REFCLK_150MHZ + */ +#define CONFIG_SYS_SATA_CLK PHYCTRLCFG_REFCLK_125MHZ + + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1_OFFSET 0x18000 +#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR \ + + CONFIG_SYS_SATA1_OFFSET) +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2_OFFSET 0x19000 +#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR \ + + CONFIG_SYS_SATA2_OFFSET) +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#ifdef CONFIG_FSL_SATA + #define CONFIG_LBA48 + #define CONFIG_DOS_PARTITION +#endif + +/* + * MTD + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS + +/* + * Environment + */ +#ifndef CONFIG_SYS_RAMBOOT + #define CONFIG_ENV_IS_IN_FLASH 1 + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128 KiB (one sector) per env */ + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ + + CONFIG_SYS_MONITOR_LEN) /* env1 */ + #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR \ + + CONFIG_ENV_SECT_SIZE) /* env2 */ + #define CONFIG_ENV_SIZE 0x2000 +#else + #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_MII +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING + +#ifdef CONFIG_MTD_PARTITIONS + #define CONFIG_CMD_MTDPARTS + #define MTDIDS_DEFAULT "nor0=80000000.flash" + #define MTDPARTS_DEFAULT "mtdparts=80000000.flash:" \ + "512k(uboot)ro," \ + "128k(env1)ro," \ + "128k(env2)ro," \ + "128k(dtb)," \ + "2m(kernel)," \ + "4m(root)," \ + "-(user)" +#endif + +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) + + #define CONFIG_CMD_DATE + #define CONFIG_CMD_DTT + #define CONFIG_CMD_EEPROM + #define CONFIG_CMD_I2C +#endif + +#ifdef CONFIG_HAS_FSL_DR_USB + #define CONFIG_CMD_USB +#endif + +#ifdef CONFIG_NAND + #define CONFIG_CMD_NAND +#endif + +#if defined(CONFIG_SYS_RAMBOOT) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS +#endif + +#ifdef CONFIG_FSL_SATA + #define CONFIG_CMD_SATA +#endif + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_FSL_SATA) + #define CONFIG_CMD_EXT2 + #define CONFIG_CMD_FAT +#endif + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +/* + * Miscellaneous configurable options + */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MiB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_IMMR \ + | BATL_PP_10 \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_IMMR \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE \ + | BATL_PP_10 \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L (CONFIG_SYS_FLASH_BASE \ + | BATL_PP_10 \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ + | BATL_PP_10) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ + | BATU_BL_128K \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* DDR: 512MiB cache cacheable */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_SDRAM_BASE \ + | BATL_PP_10 \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_SDRAM_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ + | BATL_PP_10 \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +#ifdef CONFIG_PCI + /* PCI MEM space: cacheable */ + #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MEM_PHYS \ + | BATL_PP_10 \ + | BATL_MEMCOHERENCE) + #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MEM_PHYS \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) + #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L + #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + + /* PCI MMIO space: cache-inhibit and guarded */ + #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MMIO_PHYS \ + | BATL_PP_10 \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) + #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MMIO_PHYS \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) + #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L + #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + + #define CONFIG_SYS_IBAT7L 0 + #define CONFIG_SYS_IBAT7U 0 + #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L + #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U +#else + #define CONFIG_SYS_IBAT5L 0 + #define CONFIG_SYS_IBAT5U 0 + #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L + #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + #define CONFIG_SYS_IBAT6L 0 + #define CONFIG_SYS_IBAT6U 0 + #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L + #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + #define CONFIG_SYS_IBAT7L 0 + #define CONFIG_SYS_IBAT7U 0 + #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L + #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) + #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ + #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) + #define CONFIG_HAS_ETH0 + #define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define MK_STR(x) #x + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ubootfile=u-boot_tqm8315.bin\0" \ + "ubootaddr_f=" MK_STR(CONFIG_SYS_FLASH_BASE) "\0" \ + "load=tftpboot $loadaddr $ubootfile\0" \ + "update=protect off $ubootaddr_f +$filesize;" \ + "erase $ubootaddr_f +$filesize;" \ + "cp.b $loadaddr $ubootaddr_f $filesize\0" \ + "upd=run load update\0" \ + "fdtaddr_r=400000\0" \ + "fdtaddr_f=800C0000\0" \ + "fdtfile=tqm8315.dtb\0" \ + "updfdt=tftp $loadaddr $fdtfile;" \ + "protect off $fdtaddr_f +$filesize;" \ + "erase $fdtaddr_f +$filesize;" \ + "cp.b $loadaddr $fdtaddr_f $filesize\0" \ + "kerneladdr_f=800E0000\0" \ + "bootfile=uImage_tqm8315\0" \ + "updkrn=tftp $loadaddr $bootfile;" \ + "protect off $kerneladdr_f +$filesize;" \ + "erase $kerneladdr_f +$filesize;" \ + "cp.b $loadaddr $kerneladdr_f $filesize\0" \ + "ramdiskaddr_r=1000000\0" \ + "ramdiskaddr_f=802E0000\0" \ + "ramdiskfile=uRamdisk\0" \ + "updrd=tftp $loadaddr $ramdiskfile;" \ + "protect off $ramdiskaddr_f +$filesize;" \ + "erase $ramdiskaddr_f +$filesize;" \ + "cp.b $loadaddr $ramdiskaddr_f $filesize\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "flashboot=" CONFIG_FLASHBOOTCOMMAND "\0" \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "usb_phy_type=utmi\0" \ + "hostname=TQM8315\0" \ + MTDPARTS_DEFAULT "\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:" \ + "$hostname:$netdev:off " \ + "console=$consoledev,$baudrate " \ + "mtdparts=$mtdparts " \ + "$othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr_r $fdtfile;" \ + "bootm $loadaddr - $fdtaddr_r" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:" \ + "$hostname:$netdev:off " \ + "console=$consoledev,$baudrate " \ + "mtdparts=$mtdparts " \ + "$othbootargs;" \ + "tftp $ramdiskaddr_r $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr_r $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr_r $fdtaddr_r" + +#define CONFIG_FLASHBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:" \ + "$hostname:$netdev:off " \ + "console=$consoledev,$baudrate " \ + "mtdparts=$mtdparts " \ + "$othbootargs;" \ + "bootm $kerneladdr_f $ramdiskaddr_f $fdtaddr_f" + +#define CONFIG_BOOTCOMMAND "run flashboot" + +#endif /* __CONFIG_H */ diff --git a/include/sata.h b/include/sata.h index c95dc56..c20e8dc 100644 --- a/include/sata.h +++ b/include/sata.h @@ -12,4 +12,8 @@ int __sata_initialize(void); extern block_dev_desc_t sata_dev_desc[]; +#if defined(CONFIG_MPC8315) +void init_mpc8315_sata_phy(void); +#endif + #endif -- 1.7.11.7

2 1

[U-Boot] [PATCH 1/1] Add support of IB8315 board
by Sergey Gerasimov 03 Jun '13

03 Jun '13

Signed-off-by: Sergey Gerasimov <Sergey.Gerasimov(a)astrosoft-development.com> --- board/ib8315/Makefile | 49 +++ board/ib8315/ib8315.c | 194 +++++++++++ board/ib8315/sdram.c | 123 +++++++ board/ib8315/tqm8315.c | 194 +++++++++++ boards.cfg | 1 + drivers/block/fsl_sata.c | 21 ++ drivers/block/fsl_sata.h | 7 + include/configs/IB8315.h | 839 +++++++++++++++++++++++++++++++++++++++++++++++ include/sata.h | 4 + 9 files changed, 1432 insertions(+) create mode 100644 board/ib8315/Makefile create mode 100644 board/ib8315/ib8315.c create mode 100644 board/ib8315/sdram.c create mode 100644 board/ib8315/tqm8315.c create mode 100644 include/configs/IB8315.h diff --git a/board/ib8315/Makefile b/board/ib8315/Makefile new file mode 100644 index 0000000..aa74213 --- /dev/null +++ b/board/ib8315/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + + +COBJS := tqm8315.o sdram.o + +COBJS-$(CONFIG_PCIE) += pcie.o + +COBJS-$(CONFIG_PCI) += pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ib8315/ib8315.c b/board/ib8315/ib8315.c new file mode 100644 index 0000000..b21940d --- /dev/null +++ b/board/ib8315/ib8315.c @@ -0,0 +1,194 @@ +/* + * Copyright (C) 2009 TQ-Systems GmbH + * + * Author: Thomas Waehner <thomas.waehner(a)tqs.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <pci.h> +#include <mpc83xx.h> +#include <netdev.h> +#include <sata.h> +#include <asm/io.h> +#include <asm/fsl_mpc83xx_serdes.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_83XX_GENERIC_PCIE) +#if !defined(CONFIG_FSL_SERDES) +#error PCIe operation needs CONFIG_FSL_SERDES +#endif +#endif + +#define PHYCTRLCFG_REFCLK_MASK 0x00000070 +#define PHYCTRLCFG_REFCLK_125MHZ 0x00000070 + +int board_early_init_f(void) +{ +#ifdef CONFIG_FSL_SERDES + /* Setup SERDES for PCIe operation */ + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); +#endif /* CONFIG_FSL_SERDES */ + return 0; +} + +int checkboard(void) +{ + puts("Board: TQM8315\n"); + return 0; +} + +static struct pci_region pci_regions[] = { + { + .bus_start = CONFIG_SYS_PCI_MEM_BASE, + .phys_start = CONFIG_SYS_PCI_MEM_PHYS, + .size = CONFIG_SYS_PCI_MEM_SIZE, + .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + .bus_start = CONFIG_SYS_PCI_MMIO_BASE, + .phys_start = CONFIG_SYS_PCI_MMIO_PHYS, + .size = CONFIG_SYS_PCI_MMIO_SIZE, + .flags = PCI_REGION_MEM + }, + { + .bus_start = CONFIG_SYS_PCI_IO_BASE, + .phys_start = CONFIG_SYS_PCI_IO_PHYS, + .size = CONFIG_SYS_PCI_IO_SIZE, + .flags = PCI_REGION_IO + } +}; + +#ifdef CONFIG_83XX_GENERIC_PCIE +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, + { + .size = 0, + } +}; + +static struct pci_region pcie_regions_1[] = { + { + .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, + .size = CONFIG_SYS_PCIE2_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE2_IO_BASE, + .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, + .size = CONFIG_SYS_PCIE2_IO_SIZE, + .flags = PCI_REGION_IO, + }, + { + .size = 0, + } +}; +#endif + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci_regions }; +#ifdef CONFIG_83XX_GENERIC_PCIE + volatile sysconf83xx_t *sysconf = &immr->sysconf; + volatile law83xx_t *pcie_law = sysconf->pcielaw; + struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; +#endif + + /* Enable all 3 PCI_CLK_OUTPUTs. */ + clk->occr |= 0xe0000000; + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + mpc83xx_pci_init(1, reg); + +#ifdef CONFIG_83XX_GENERIC_PCIE + /* Configure the clock for PCIE controller */ + clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, + SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + out_be32(&sysconf->pecr2, 0xE0008000); + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); + out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(2, pcie_reg); +#endif +} + +#ifdef CONFIG_LAST_STAGE_INIT +int last_stage_init(void) +{ +#ifdef CONFIG_FSL_SATA + /* Init SATA PHY CLK rate which must only be done once at startup */ + init_mpc8315_sata_phy(); +#endif + return 0; +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Initialize TSECs first */ + return pci_eth_init(bis); +} diff --git a/board/ib8315/sdram.c b/board/ib8315/sdram.c new file mode 100644 index 0000000..734362a --- /dev/null +++ b/board/ib8315/sdram.c @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2009 TQ-Systems GmbH + * + * Author: Thomas Waehner <thomas.waehner(a)tqs.de> + * + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * Authors: Nick.Spence(a)freescale.com + * Wilson.Lo(a)freescale.com + * scottwood(a)freescale.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <mpc83xx.h> +#include <spd_sdram.h> + +#include <asm/bitops.h> +#include <asm/io.h> + +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Fixed sdram init -- doesn't use serial presence detect. + * + * This is useful for faster booting in configs where the RAM is unlikely + * to be changed, or for things like NAND booting where space is tight. + */ +static long fixed_sdram(void) +{ + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2(msize); + volatile u32 law; + int i; + /* configure local access window for SDRAM address range */ + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); + /* + * According to MPC8315ERM Rev. 1 read back last configured local + * access window configuration register, followed by an isync. + */ + law = im->sysconf.ddrlaw[0].ar; + isync(); + + im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; + + + /* + * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], + * or the DDR2 controller may fail to initialize correctly. + */ + for (i = 0; i < 50; i++) + udelay(1000); + + im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + + /* Currently we use only one CS, so disable the other bank. */ + im->ddr.cs_config[1] = 0; + + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + + if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI; + else + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_md_cntl = CONFIG_SYS_DDR_SDRAM_MD_CNTL; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + eieio(); + + /* + * According to Freescale's application note AN2583 Rev. 8 wait 200 us + * after the DLL is locked before enabling the DDR controller. + */ + udelay(200); + + /* enable DDR controller */ + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + eieio(); + + return msize; +} + +phys_size_t initdram(int board_type) +{ + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + u32 msize; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM */ + msize = fixed_sdram(); + + /* return total bus SDRAM size(bytes) -- DDR */ + return msize; +} diff --git a/board/ib8315/tqm8315.c b/board/ib8315/tqm8315.c new file mode 100644 index 0000000..b21940d --- /dev/null +++ b/board/ib8315/tqm8315.c @@ -0,0 +1,194 @@ +/* + * Copyright (C) 2009 TQ-Systems GmbH + * + * Author: Thomas Waehner <thomas.waehner(a)tqs.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <pci.h> +#include <mpc83xx.h> +#include <netdev.h> +#include <sata.h> +#include <asm/io.h> +#include <asm/fsl_mpc83xx_serdes.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_83XX_GENERIC_PCIE) +#if !defined(CONFIG_FSL_SERDES) +#error PCIe operation needs CONFIG_FSL_SERDES +#endif +#endif + +#define PHYCTRLCFG_REFCLK_MASK 0x00000070 +#define PHYCTRLCFG_REFCLK_125MHZ 0x00000070 + +int board_early_init_f(void) +{ +#ifdef CONFIG_FSL_SERDES + /* Setup SERDES for PCIe operation */ + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); +#endif /* CONFIG_FSL_SERDES */ + return 0; +} + +int checkboard(void) +{ + puts("Board: TQM8315\n"); + return 0; +} + +static struct pci_region pci_regions[] = { + { + .bus_start = CONFIG_SYS_PCI_MEM_BASE, + .phys_start = CONFIG_SYS_PCI_MEM_PHYS, + .size = CONFIG_SYS_PCI_MEM_SIZE, + .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + .bus_start = CONFIG_SYS_PCI_MMIO_BASE, + .phys_start = CONFIG_SYS_PCI_MMIO_PHYS, + .size = CONFIG_SYS_PCI_MMIO_SIZE, + .flags = PCI_REGION_MEM + }, + { + .bus_start = CONFIG_SYS_PCI_IO_BASE, + .phys_start = CONFIG_SYS_PCI_IO_PHYS, + .size = CONFIG_SYS_PCI_IO_SIZE, + .flags = PCI_REGION_IO + } +}; + +#ifdef CONFIG_83XX_GENERIC_PCIE +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, + { + .size = 0, + } +}; + +static struct pci_region pcie_regions_1[] = { + { + .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, + .size = CONFIG_SYS_PCIE2_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE2_IO_BASE, + .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, + .size = CONFIG_SYS_PCIE2_IO_SIZE, + .flags = PCI_REGION_IO, + }, + { + .size = 0, + } +}; +#endif + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci_regions }; +#ifdef CONFIG_83XX_GENERIC_PCIE + volatile sysconf83xx_t *sysconf = &immr->sysconf; + volatile law83xx_t *pcie_law = sysconf->pcielaw; + struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; +#endif + + /* Enable all 3 PCI_CLK_OUTPUTs. */ + clk->occr |= 0xe0000000; + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + mpc83xx_pci_init(1, reg); + +#ifdef CONFIG_83XX_GENERIC_PCIE + /* Configure the clock for PCIE controller */ + clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, + SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + out_be32(&sysconf->pecr2, 0xE0008000); + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); + out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(2, pcie_reg); +#endif +} + +#ifdef CONFIG_LAST_STAGE_INIT +int last_stage_init(void) +{ +#ifdef CONFIG_FSL_SATA + /* Init SATA PHY CLK rate which must only be done once at startup */ + init_mpc8315_sata_phy(); +#endif + return 0; +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Initialize TSECs first */ + return pci_eth_init(bis); +} diff --git a/boards.cfg b/boards.cfg index e2a8d42..97ef108 100644 --- a/boards.cfg +++ b/boards.cfg @@ -734,6 +734,7 @@ MVBLM7 powerpc mpc83xx mvblm7 matrix_ SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP TQM834x powerpc mpc83xx tqm834x tqc +IB8315 powerpc mpc83xx ib8315 - suvd3 powerpc mpc83xx km83xx keymile - suvd3:SUVD3 kmvect1 powerpc mpc83xx km83xx keymile - suvd3:KMVECT1 tuge1 powerpc mpc83xx km83xx keymile - tuxx1:TUGE1 diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index 1f9d7b0..dc834a0 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -87,6 +87,27 @@ static int ata_wait_register(unsigned __iomem *addr, u32 mask, return (i < timeout_msec) ? 0 : -1; } +#if defined(CONFIG_MPC8315) +#ifndef CONFIG_SYS_SATA_CLK +#define CONFIG_SYS_SATA_CLK PHYCTRLCFG_REFCLK_75MHZ +#endif +/* If you have a MPC8315 board, you can call this function from last_stage_init + * call to setup the MPC8315 specific PHY clocking parameter */ +void init_mpc8315_sata_phy(void) +{ + u32 val32; + fsl_sata_reg_t *reg; + + reg = (fsl_sata_reg_t *)(CONFIG_SYS_IMMR + 0x18000); + + /* Configure PHY */ + val32 = in_le32(&reg->phyctrlcfg); + val32 &= ~PHYCTRLCFG_REFCLK_MASK; + val32 |= CONFIG_SYS_SATA_CLK; + out_le32(&reg->phyctrlcfg, val32); +} +#endif + int init_sata(int dev) { u32 length, align; diff --git a/drivers/block/fsl_sata.h b/drivers/block/fsl_sata.h index a9c27bc..0572a48 100644 --- a/drivers/block/fsl_sata.h +++ b/drivers/block/fsl_sata.h @@ -172,6 +172,13 @@ typedef struct fsl_sata_reg { #define PHYCTRLCFG_FPRFTI_MASK 0x00000018 #define PHYCTRLCFG_LOOPBACK_MASK 0x0000000e +#define PHYCTRLCFG_REFCLK_MASK 0x00000070 +#define PHYCTRLCFG_REFCLK_50MHZ 0x00000050 +#define PHYCTRLCFG_REFCLK_75MHZ 0x00000000 +#define PHYCTRLCFG_REFCLK_100MHZ 0x00000060 +#define PHYCTRLCFG_REFCLK_125MHZ 0x00000070 +#define PHYCTRLCFG_REFCLK_150MHZ 0x00000020 + /* * Command Header Entry */ diff --git a/include/configs/IB8315.h b/include/configs/IB8315.h new file mode 100644 index 0000000..dc897bd --- /dev/null +++ b/include/configs/IB8315.h @@ -0,0 +1,839 @@ +/* + * Copyright (C) 2009 TQ-Systems GmbH + * + * Author: Thomas Waehner <thomas.waehner(a)tqs.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 + +#ifdef CONFIG_NAND_U_BOOT +#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ +#define CONFIG_SYS_TEXT_BASE_SPL 0x81f00000 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#endif /* CONFIG_NAND_SPL */ +#endif /* CONFIG_NAND_U_BOOT */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x80000000 +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC831x 1 /* MPC831x CPU family */ +#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ +#define CONFIG_TQM8315 1 /* TQM8315 board specific */ + + + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +/* + * Hardware Reset Configuration Word + * if CLKIN is 66.666 MHz, then + * CSB = 133.333 MHz, CORE = 400 MHz, DDR-Contr. inp. = 266.666 MHz + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_SVCOD_DIV_2 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CORE_TO_CSB_3X1) +#define CONFIG_SYS_HRCW_HIGH_BASE (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) + +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_ROM_LOC_NAND_SP_8BIT |\ + HRCWH_RL_EXT_NAND) +#else +#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY) +#endif + + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x00000000 +#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */ + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_LAST_STAGE_INIT /* call last_stage_init for SATA init */ + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Arbiter Setup + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ +#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency prio is highest */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CONFIG_SYS_DDRCDR_VALUE 0x00080001 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_SYS_DDR_SIZE 256 /* MiB */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ODT_WR_ALL \ + | CSCONFIG_BANK_BIT_3 \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) + /* 0x80044102 */ +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (1 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (1 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (1 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (5 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00110105 */ +#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (9 << TIMING_CFG1_REFREC_SHIFT) \ + | (2 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x26259222 */ +#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (3 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x119048c7 */ +#define CONFIG_SYS_DDR_INTERVAL ((520 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x02080100 */ + +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_32 \ + | SDRAM_CFG_HSE) + /* 0x43080008 */ +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_MODE ((0x440e << SDRAM_MODE_ESD_SHIFT) \ + | (0x0232 << SDRAM_MODE_SD_SHIFT)) + /* 0x440e0232 */ +#define CONFIG_SYS_DDR_MODE2 0x8000C000 +#define CONFIG_SYS_DDR_SDRAM_MD_CNTL 0x00000000 +/* + * Memory test + */ +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00200000 + +/* + * The reserved memory + */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) + #define CONFIG_SYS_RAMBOOT +#else + #undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KiB for Mon*/ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xF0000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 +#define CONFIG_SYS_LBC_LBCR 0x00040000 +#define CONFIG_FSL_ELBC 1 + + +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size in MiB */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size */ + +#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ + + /* 0x80001001 */ +/* Flash timing for LBC = 66.666 MHz */ +#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_GPCM_CSNT \ + | OR_GPCM_SCY_3 \ + | OR_GPCM_TRLX_SET) + /* 0xFC000834 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ + (CONFIG_SYS_FLASH_BASE \ + + ((CONFIG_SYS_FLASH_SIZE / 2) << 20))} +#define CONFIG_SYS_MAX_FLASH_SECT 259 + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* + * NAND Flash on the Local Bus + * define CONFIG_NAND to use it + */ +#undef CONFIG_NAND + +#ifdef CONFIG_NAND + #define CONFIG_SYS_NAND_BASE 0xE0600000 + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_MTD_NAND_VERIFY_WRITE 1 + #define CONFIG_NAND_FSL_ELBC 1 + + /* + * Use HW ECC + * Port Size = 8 bit + * MSEL = FCM + */ + #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ + | (2 << BR_DECC_SHIFT) \ + | BR_PS_8 \ + | BR_MS_FCM \ + | BR_V) + #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 /* address mask 32 KiB */ \ + | OR_FCM_PGS \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_RST) + + #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE + #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32 KiB */ +#endif + +/* + * Serial Port + */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_FSL_I2C +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES {0x50} /* Don't probe config eeprom */ + +/* EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ + +/* + * Config on-board RTC + */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* I2C SYSMON (LM75) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_SYS_I2C_DTT_ADDR 0x48 /* Sensor base address */ +/* Use the following define if you only want the TQM8315 on-module sensor */ +#define CONFIG_DTT_SENSORS {0} +/* + * Use the following define if it is on a STK85xxNG + * to read the temp sensors there, too + */ +/* #define CONFIG_DTT_SENSORS {0, 1, 2, 3} */ +#define CONFIG_SYS_DTT_MAX_TEMP 70 +#define CONFIG_SYS_DTT_LOW_TEMP -30 +#define CONFIG_SYS_DTT_HYSTERESIS 3 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_PCI + +#ifdef CONFIG_PCI + #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ + #define CONFIG_83XX_GENERIC_PCIE 1 + #define CONFIG_PCIE +#endif + +#ifdef CONFIG_83XX_GENERIC_PCI + #define CONFIG_SYS_PCI_MEM_BASE 0xC0000000 + #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE + #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256 MiB */ + #define CONFIG_SYS_PCI_MMIO_BASE 0xD0000000 + #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE + #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256 MiB */ + #define CONFIG_SYS_PCI_IO_BASE (CONFIG_SYS_IMMR + 0x03000000) + #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BASE + #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1 MiB */ + + #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE + #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 + #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 + + #define CONFIG_NET_MULTI + #define CONFIG_PCI_PNP /* do pci plug-and-play */ + + #define CONFIG_EEPRO100 /* Intel Pro/100 NIC support */ + #define CONFIG_E1000 /* Intel Pro/1000 NIC support */ + #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + + #ifndef CONFIG_NET_MULTI + #define CONFIG_NET_MULTI 1 +#endif + +#ifdef CONFIG_83XX_GENERIC_PCIE + #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES + + #define CONFIG_SYS_PCIE1_BASE 0x40000000 + #define CONFIG_SYS_PCIE1_CFG_BASE 0x50000000 + #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 + #define CONFIG_SYS_PCIE1_MEM_BASE 0x40000000 + #define CONFIG_SYS_PCIE1_MEM_PHYS 0x40000000 + #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 + #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 + #define CONFIG_SYS_PCIE1_IO_PHYS (CONFIG_SYS_IMMR + 0x03100000) + #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + + #define CONFIG_SYS_PCIE2_BASE 0x60000000 + #define CONFIG_SYS_PCIE2_CFG_BASE 0x70000000 + #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 + #define CONFIG_SYS_PCIE2_MEM_BASE 0x60000000 + #define CONFIG_SYS_PCIE2_MEM_PHYS 0x60000000 + #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 + #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 + #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_IMMR + 0x03180000) + #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 + #endif +#endif + +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_SYS_SCCR_USBDRCM 1 + +#ifdef CONFIG_HAS_FSL_DR_USB + #define CONFIG_USB_EHCI + #define CONFIG_USB_EHCI_FSL + #define CONFIG_EHCI_HCD_INIT_AFTER_RESET + #define CONFIG_DOS_PARTITION + #define CONFIG_USB_STORAGE +#endif + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) + +/* + * TSEC ethernet configuration + */ +#define CONFIG_GMII + +#define CONFIG_PHYLIB 1 +#define CONFIG_PHY_VITESSE 1 + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS (TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +/* Options are: eTSEC[0-1] */ +#define CONFIG_ETHPRIME "eTSEC0" + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +/* SERDES */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 + +/* + * SATA + */ +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA +/* Choose the phy setting for your SATA clock + * The following values are possible for CONFIG_SYS_SATA_CLK: + * PHYCTRLCFG_REFCLK_50MHZ + * PHYCTRLCFG_REFCLK_75MHZ + * PHYCTRLCFG_REFCLK_100MHZ + * PHYCTRLCFG_REFCLK_125MHZ + * PHYCTRLCFG_REFCLK_150MHZ + */ +#define CONFIG_SYS_SATA_CLK PHYCTRLCFG_REFCLK_125MHZ + + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1_OFFSET 0x18000 +#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR \ + + CONFIG_SYS_SATA1_OFFSET) +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2_OFFSET 0x19000 +#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR \ + + CONFIG_SYS_SATA2_OFFSET) +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#ifdef CONFIG_FSL_SATA + #define CONFIG_LBA48 + #define CONFIG_DOS_PARTITION +#endif + +/* + * MTD + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS + +/* + * Environment + */ +#ifndef CONFIG_SYS_RAMBOOT + #define CONFIG_ENV_IS_IN_FLASH 1 + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128 KiB (one sector) per env */ + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ + + CONFIG_SYS_MONITOR_LEN) /* env1 */ + #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR \ + + CONFIG_ENV_SECT_SIZE) /* env2 */ + #define CONFIG_ENV_SIZE 0x2000 +#else + #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_MII +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING + +#ifdef CONFIG_MTD_PARTITIONS + #define CONFIG_CMD_MTDPARTS + #define MTDIDS_DEFAULT "nor0=80000000.flash" + #define MTDPARTS_DEFAULT "mtdparts=80000000.flash:" \ + "512k(uboot)ro," \ + "128k(env1)ro," \ + "128k(env2)ro," \ + "128k(dtb)," \ + "2m(kernel)," \ + "4m(root)," \ + "-(user)" +#endif + +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) + + #define CONFIG_CMD_DATE + #define CONFIG_CMD_DTT + #define CONFIG_CMD_EEPROM + #define CONFIG_CMD_I2C +#endif + +#ifdef CONFIG_HAS_FSL_DR_USB + #define CONFIG_CMD_USB +#endif + +#ifdef CONFIG_NAND + #define CONFIG_CMD_NAND +#endif + +#if defined(CONFIG_SYS_RAMBOOT) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS +#endif + +#ifdef CONFIG_FSL_SATA + #define CONFIG_CMD_SATA +#endif + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_FSL_SATA) + #define CONFIG_CMD_EXT2 + #define CONFIG_CMD_FAT +#endif + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +/* + * Miscellaneous configurable options + */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MiB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_IMMR \ + | BATL_PP_10 \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_IMMR \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE \ + | BATL_PP_10 \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L (CONFIG_SYS_FLASH_BASE \ + | BATL_PP_10 \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ + | BATL_PP_10) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ + | BATU_BL_128K \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* DDR: 512MiB cache cacheable */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_SDRAM_BASE \ + | BATL_PP_10 \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_SDRAM_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ + | BATL_PP_10 \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +#ifdef CONFIG_PCI + /* PCI MEM space: cacheable */ + #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MEM_PHYS \ + | BATL_PP_10 \ + | BATL_MEMCOHERENCE) + #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MEM_PHYS \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) + #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L + #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + + /* PCI MMIO space: cache-inhibit and guarded */ + #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MMIO_PHYS \ + | BATL_PP_10 \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) + #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MMIO_PHYS \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) + #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L + #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + + #define CONFIG_SYS_IBAT7L 0 + #define CONFIG_SYS_IBAT7U 0 + #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L + #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U +#else + #define CONFIG_SYS_IBAT5L 0 + #define CONFIG_SYS_IBAT5U 0 + #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L + #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + #define CONFIG_SYS_IBAT6L 0 + #define CONFIG_SYS_IBAT6U 0 + #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L + #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + #define CONFIG_SYS_IBAT7L 0 + #define CONFIG_SYS_IBAT7U 0 + #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L + #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) + #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ + #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) + #define CONFIG_HAS_ETH0 + #define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define MK_STR(x) #x + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ubootfile=u-boot_tqm8315.bin\0" \ + "ubootaddr_f=" MK_STR(CONFIG_SYS_FLASH_BASE) "\0" \ + "load=tftpboot $loadaddr $ubootfile\0" \ + "update=protect off $ubootaddr_f +$filesize;" \ + "erase $ubootaddr_f +$filesize;" \ + "cp.b $loadaddr $ubootaddr_f $filesize\0" \ + "upd=run load update\0" \ + "fdtaddr_r=400000\0" \ + "fdtaddr_f=800C0000\0" \ + "fdtfile=tqm8315.dtb\0" \ + "updfdt=tftp $loadaddr $fdtfile;" \ + "protect off $fdtaddr_f +$filesize;" \ + "erase $fdtaddr_f +$filesize;" \ + "cp.b $loadaddr $fdtaddr_f $filesize\0" \ + "kerneladdr_f=800E0000\0" \ + "bootfile=uImage_tqm8315\0" \ + "updkrn=tftp $loadaddr $bootfile;" \ + "protect off $kerneladdr_f +$filesize;" \ + "erase $kerneladdr_f +$filesize;" \ + "cp.b $loadaddr $kerneladdr_f $filesize\0" \ + "ramdiskaddr_r=1000000\0" \ + "ramdiskaddr_f=802E0000\0" \ + "ramdiskfile=uRamdisk\0" \ + "updrd=tftp $loadaddr $ramdiskfile;" \ + "protect off $ramdiskaddr_f +$filesize;" \ + "erase $ramdiskaddr_f +$filesize;" \ + "cp.b $loadaddr $ramdiskaddr_f $filesize\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "flashboot=" CONFIG_FLASHBOOTCOMMAND "\0" \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "usb_phy_type=utmi\0" \ + "hostname=TQM8315\0" \ + MTDPARTS_DEFAULT "\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:" \ + "$hostname:$netdev:off " \ + "console=$consoledev,$baudrate " \ + "mtdparts=$mtdparts " \ + "$othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr_r $fdtfile;" \ + "bootm $loadaddr - $fdtaddr_r" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:" \ + "$hostname:$netdev:off " \ + "console=$consoledev,$baudrate " \ + "mtdparts=$mtdparts " \ + "$othbootargs;" \ + "tftp $ramdiskaddr_r $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr_r $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr_r $fdtaddr_r" + +#define CONFIG_FLASHBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:" \ + "$hostname:$netdev:off " \ + "console=$consoledev,$baudrate " \ + "mtdparts=$mtdparts " \ + "$othbootargs;" \ + "bootm $kerneladdr_f $ramdiskaddr_f $fdtaddr_f" + +#define CONFIG_BOOTCOMMAND "run flashboot" + +#endif /* __CONFIG_H */ diff --git a/include/sata.h b/include/sata.h index c95dc56..c20e8dc 100644 --- a/include/sata.h +++ b/include/sata.h @@ -12,4 +12,8 @@ int __sata_initialize(void); extern block_dev_desc_t sata_dev_desc[]; +#if defined(CONFIG_MPC8315) +void init_mpc8315_sata_phy(void); +#endif + #endif -- 1.7.11.7

1 0

[U-Boot] [PATCH v3 1/2] build: Use generic boot logo matching
by Otavio Salvador 03 Jun '13

03 Jun '13

The boot logo matching is now done in following way: - use LOGO_BMP if it is set, or - use $(BOARD).bmp if it exists in tools/logos, or - use $(VENDOR).bmp if it exists in tools/logos, or - use denx.bmp otherwise. Signed-off-by: Otavio Salvador <otavio(a)ossystems.com.br> --- Changes in v3: - New patch, which replaces the 1/2 from v1 and v2 Changes in v2: None tools/Makefile | 27 ++++++++++----------------- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/tools/Makefile b/tools/Makefile index 889c897..93f4a84 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -128,28 +128,21 @@ LOGO-$(CONFIG_LCD_LOGO) += $(LOGO_DATA_H) LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_H) LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_DATA_H) +# Generic logo ifeq ($(LOGO_BMP),) LOGO_BMP= logos/denx.bmp + +# Use board logo and fallback to vendor +ifneq ($(wildcard logos/$(BOARD).bmp),) +LOGO_BMP= logos/$(BOARD).bmp +else +ifneq ($(wildcard logos/$(VENDOR).bmp),) +LOGO_BMP= logos/$(VENDOR).bmp endif -ifeq ($(VENDOR),atmel) -LOGO_BMP= logos/atmel.bmp -endif -ifeq ($(VENDOR),esd) -LOGO_BMP= logos/esd.bmp -endif -ifeq ($(VENDOR),freescale) -LOGO_BMP= logos/freescale.bmp -endif -ifeq ($(VENDOR),ronetix) -LOGO_BMP= logos/ronetix.bmp -endif -ifeq ($(VENDOR),syteco) -LOGO_BMP= logos/syteco.bmp -endif -ifeq ($(VENDOR),intercontrol) -LOGO_BMP= logos/intercontrol.bmp endif +endif # !LOGO_BMP + # now $(obj) is defined HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c)) HOSTSRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c)) -- 1.8.1

3 4

[U-Boot] [PATCH 1/2] wandboard: Enable HDMI splashscreen
by Fabio Estevam 03 Jun '13

03 Jun '13

Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/wandboard/wandboard.c | 98 +++++++++++++++++++++++++++++++++++++++++++++ include/configs/wandboard.h | 15 ++++++- 2 files changed, 112 insertions(+), 1 deletion(-) diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index bb98352..5666cbf 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -10,9 +10,11 @@ */ #include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> #include <asm/arch/iomux.h> #include <asm/arch/imx-regs.h> #include <asm/arch/mx6-pins.h> +#include <asm/arch/mxc_hdmi.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> @@ -21,9 +23,11 @@ #include <asm/sizes.h> #include <common.h> #include <fsl_esdhc.h> +#include <ipu_pixfmt.h> #include <mmc.h> #include <miiphy.h> #include <netdev.h> +#include <linux/fb.h> DECLARE_GLOBAL_DATA_PTR; @@ -206,6 +210,88 @@ int board_phy_config(struct phy_device *phydev) return 0; } +#if defined(CONFIG_VIDEO_IPUV3) +static void enable_hdmi(void) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + u8 reg; + reg = readb(&hdmi->phy_conf0); + reg |= HDMI_PHY_CONF0_PDZ_MASK; + writeb(reg, &hdmi->phy_conf0); + + udelay(3000); + reg |= HDMI_PHY_CONF0_ENTMDS_MASK; + writeb(reg, &hdmi->phy_conf0); + udelay(3000); + reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; + writeb(reg, &hdmi->phy_conf0); + writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); +} + +static struct fb_videomode const hdmi = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +}; + +int board_video_skip(void) +{ + int ret; + + ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24); + + if (ret) + printf("HDMI cannot be configured: %d\n", ret); + + enable_hdmi(); + + return ret; +} + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + int reg; + + /* Turn on IPU clock */ + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; + writel(reg, &mxc_ccm->CCGR3); + + /* Turn on HDMI PHY clock */ + reg = readl(&mxc_ccm->CCGR2); + reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK + | MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; + writel(reg, &mxc_ccm->CCGR2); + + /* clear HDMI PHY reset */ + writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); + + reg = readl(&mxc_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK + | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK + | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) + | (CHSCCDR_PODF_DIVIDE_BY_3 + << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + | (CHSCCDR_IPU_PRE_CLK_540M_PFD + << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + int board_eth_init(bd_t *bis) { int ret; @@ -222,9 +308,21 @@ int board_eth_init(bd_t *bis) int board_early_init_f(void) { setup_iomux_uart(); +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif return 0; } +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { /* 4 bit bus width */ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 9d7ec3f..d4ac086 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -29,7 +29,7 @@ #define CONFIG_REVISION_TAG /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT @@ -86,6 +86,19 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_ATHEROS +/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 260000000 + #if defined(CONFIG_MX6DL) #define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb" #elif defined(CONFIG_MX6S) -- 1.8.1.2

5 6

[U-Boot] [PATCH v6] Add support for Congatec Conga-QEVAl board
by SARTRE Leo 03 Jun '13

03 Jun '13

Add minimal support (only boot from mmc device) for the Congatec Conga-QEVAl Evaluation Carrier Board with conga-Qmx6q (i.MX6 Quad processor) module. Signed-off-by: Leo Sartre <lsartre(a)adeneo-embedded.com> --- Changes in v6: cgtqmx6eval.c: remove unnecessary PAD_CTL_PKE | PAD_CTL_PUE mask and unnecessary #ifdef MAINTAINERS | 4 + board/congatec/cgtqmx6eval/Makefile | 42 +++++++ board/congatec/cgtqmx6eval/README | 29 +++++ board/congatec/cgtqmx6eval/cgtqmx6eval.c | 175 +++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/cgtqmx6eval.h | 192 ++++++++++++++++++++++++++++++ 6 files changed, 443 insertions(+) create mode 100644 board/congatec/cgtqmx6eval/Makefile create mode 100644 board/congatec/cgtqmx6eval/README create mode 100644 board/congatec/cgtqmx6eval/cgtqmx6eval.c create mode 100644 include/configs/cgtqmx6eval.h diff --git a/MAINTAINERS b/MAINTAINERS index 643a5ac..715f83d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -889,6 +889,10 @@ Steve Sakoman <sakoman(a)gmail.com> omap3_overo ARM ARMV7 (OMAP3xx SoC) +Leo Sartre <lsartre(a)adeneo-embedded.com> + + cgtqmx6qeval i.MX6Q + Jens Scharsig <esw(a)bus-elektronik.de> eb_cpux9k2 ARM920T (AT91RM9200 SoC) diff --git a/board/congatec/cgtqmx6eval/Makefile b/board/congatec/cgtqmx6eval/Makefile new file mode 100644 index 0000000..ac16c1f --- /dev/null +++ b/board/congatec/cgtqmx6eval/Makefile @@ -0,0 +1,42 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg(a)denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# (C) Copyright 2013 Adeneo Embedded <www.adeneo-embedded.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := cgtqmx6eval.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/congatec/cgtqmx6eval/README b/board/congatec/cgtqmx6eval/README new file mode 100644 index 0000000..bbf0f75 --- /dev/null +++ b/board/congatec/cgtqmx6eval/README @@ -0,0 +1,29 @@ +U-Boot for the Congatec Conga-QEVAl Evaluation Carrier board with +qmx6 quad module. + +This file contains information for the port of U-Boot to the Congatec +Conga-QEVAl Evaluation Carrier board with qmx6 quad module. + +1. Boot source, boot from SD card +--------------------------------- + +This version of u-boot works only on the SD card. By default, the +Congatec board can boot only from the SPI-NOR. +But, with the u-boot version provided with the board you can write boot +registers to force the board to reboot and boot from the SD slot. If +"bmode" command is not available from your pre-installed u-boot, these +instruction will produce the same effect: + +conga-QMX6 U-Boot > mw.l 0x20d8040 0x3850 +conga-QMX6 U-Boot > mw.l 0x020d8044 0x10000000 +conga-QMX6 U-Boot > reset +resetting ... + +The the board will reboot and, if you have written your SD correctly +the board will use u-boot that live into the SD + +To copy the resulting u-boot.imx to the SD card: + + dd if=u-boot.imx of=/dev/xxx bs=512 seek=2 + +Note: Replace xxx with the device representing the SD card in your system. diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c new file mode 100644 index 0000000..d6eb26f --- /dev/null +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Based on mx6qsabrelite.c file + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Leo Sartre, <lsartre(a)adeneo-embedded.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <mmc.h> +#include <fsl_esdhc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[] = { + {USDHC2_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + gpio_direction_input(IMX_GPIO_NR(1, 4)); + ret = !gpio_get_value(IMX_GPIO_NR(1, 4)); + break; + case USDHC4_BASE_ADDR: + gpio_direction_input(IMX_GPIO_NR(2, 6)); + ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); + break; + default: + printf("Bad USDHC interface\n"); + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + + status = fsl_esdhc_initialize(bis, &usdhc_cfg[0]) | + fsl_esdhc_initialize(bis, &usdhc_cfg[1]); + + return status; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + u32 reg; + /*Same init as the sabrelite*/ + writel(0x41736166, SNVS_BASE_ADDR + 0x64);/*set LPPGDR*/ + udelay(10); + reg = readl(SNVS_BASE_ADDR + 0x4c); + reg |= (1 << 3); + writel(reg, SNVS_BASE_ADDR + 0x4c);/*clear LPSR*/ + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: Conga-QEVAL QMX6 Quad\n"); + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)}, + {"mmc1", MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + return 0; +} diff --git a/boards.cfg b/boards.cfg index 5d78064..164d7ce 100644 --- a/boards.cfg +++ b/boards.cfg @@ -259,6 +259,7 @@ mx6qarm2 arm armv7 mx6qarm2 freesca mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +cgtqmx6qeval arm armv7 cgtqmx6eval congatec mx6 cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q eco5pk arm armv7 eco5pk 8dtech omap3 nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 nitrogen6dl2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h new file mode 100644 index 0000000..7ddf9af --- /dev/null +++ b/include/configs/cgtqmx6eval.h @@ -0,0 +1,192 @@ +/* + * + * Congatec Conga-QEVAl board configuration file. + * + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Based on Freescale i.MX6Q Sabre Lite board configuration file. + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Leo Sartre, <lsartre(a)adeneo-embedded.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_CGTQMX6EVAL_H +#define __CONFIG_CGTQMX6EVAL_H + +#define CONFIG_MX6 + +#include "mx6_common.h" + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_MACH_TYPE 4122 + +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* Miscellaneous commands */ +#define CONFIG_CMD_BMODE + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "fdt_file=imx6q-congatec.dtb\0" \ + "boot_dir=/boot\0" \ + "console=ttymxc1\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_addr=0x11000000\0" \ + "boot_fdt=try\0" \ + "mmcdev=1\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p1 rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${boot_dir}/${uimage}\0" \ + "loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${boot_dir}/${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else "\ + "echo ERR: Fail to boot from mmc; " \ + "fi; " \ + "fi; " \ + "else echo ERR: Fail to boot from mmc; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "CGT-QMX6-Quad U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_ENV_IS_IN_MMC + +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_CGTQMX6EVAL_H */ -- 1.7.10.4

3 2

[U-Boot] [PATCH] mx6: mx6qsabrelite/nitrogen6x: Remove incorrect setting of gpio CS signal
by Andrew Gabbasov 03 Jun '13

03 Jun '13

The number of gpio signal is packed inside CONFIG_SF_DEFAULT_CS macro (shifted and or'ed with chip select), so it's incorrect to pass that macro directly as an argument to gpio_direction_output() call. Also, SPI driver sets the direction and initial value of a gpio, used as a chip select signal, before any actual activity happens on the bus. So, it is safe to just remove the gpio_direction_output call, that works incorrectly, thus making no effect, anyway. Signed-off-by: Andrew Gabbasov <andrew_gabbasov(a)mentor.com> --- board/boundary/nitrogen6x/nitrogen6x.c | 1 - board/freescale/mx6qsabrelite/mx6qsabrelite.c | 1 - 2 files changed, 2 deletions(-) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index cc071d6..735fd76 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -342,7 +342,6 @@ iomux_v3_cfg_t const ecspi1_pads[] = { void setup_spi(void) { - gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); } diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 9f9cac8..29815d7 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -312,7 +312,6 @@ iomux_v3_cfg_t const ecspi1_pads[] = { void setup_spi(void) { - gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); } -- 1.7.10.4

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[U-Boot] [PATCH 1/2] mx6qsabreauto: Add i2c to mx6qsabreauto board
by Renato Frias 03 Jun '13

03 Jun '13

Add i2c2 and 3 to mx6qsabreauto board, i2c3 is multiplexed use gpio to set steering. Signed-off-by: Renato Frias <b13784(a)freescale.com> --- board/freescale/mx6qsabreauto/mx6qsabreauto.c | 50 +++++++++++++++++++++++++ include/configs/mx6qsabreauto.h | 6 +++ 2 files changed, 56 insertions(+) diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index bfe4868..d6df750 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -26,12 +26,14 @@ #include <asm/errno.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> #include <asm/imx-common/boot_mode.h> #include <mmc.h> #include <fsl_esdhc.h> #include <miiphy.h> #include <netdev.h> #include <asm/arch/sys_proto.h> +#include <i2c.h> DECLARE_GLOBAL_DATA_PTR; @@ -46,6 +48,12 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -76,6 +84,41 @@ iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; +/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC, + .gp = IMX_GPIO_NR(2, 30) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* + * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor, + * Compass Sensor, Accelerometer, Res Touch + */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 | PC, + .gp = IMX_GPIO_NR(3, 18) + } +}; + +iomux_v3_cfg_t const i2c3_pads[] = { + MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static void setup_iomux_enet(void) { imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); @@ -216,6 +259,13 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */ + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + /* I2C 3 Steer */ + gpio_direction_output(IMX_GPIO_NR(5, 4), 1); + imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads)); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + return 0; } diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 1583c11..947ea60 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -38,4 +38,10 @@ #define CONFIG_SYS_MMC_ENV_PART 1 /* Boot partition 1 */ #endif +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + #endif /* __MX6QSABREAUTO_CONFIG_H */ -- 1.7.9.5

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