April 2013 - U-Boot

Re: [U-Boot] [PATCH] Exynos: uart: s5p: enabling the uart tx/rx fifo
by Akshay Saraswat 01 Apr '13

01 Apr '13

Hi Simon, >Hi Akshay > > >>On Thu, Mar 21, 2013 at 11:33 PM, Akshay Saraswat <akshay.s(a)samsung.com> wrote: >> >>This patch enables the uart tx/rx fifo. Now that fifo is enabled, >>the uart read/write functions are modfied to check the UFSTAT register >>for fifo status instead of UTRSTAT (as required with fifo's enabled). >>Tested by booting linux kernel. Before enabling tx/rx fifo >>"Uncompressing linux" message is garbled and after enabling it is proper. > >Is this because Linux enables the FIFOs? > >Anyway this seems fine to me, but I have a question below. > >>Signed-off-by: Alim Akhtar <alim.akhtar(a)samsung.com> >>Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> >>--- >> drivers/serial/serial_s5p.c | 13 +++++++++---- >> 1 file changed, 9 insertions(+), 4 deletions(-) >> >>diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c >>index 3c41242..e65125c 100644 >>--- a/drivers/serial/serial_s5p.c >>+++ b/drivers/serial/serial_s5p.c >>@@ -30,6 +30,10 @@ >> >> DECLARE_GLOBAL_DATA_PTR; >> >>+#define RX_FIFO_COUNT_MASK 0xff >>+#define RX_FIFO_FULL_MASK (1 << 8) >>+#define TX_FIFO_FULL_MASK (1 << 24) >>+ >> static inline struct s5p_uart *s5p_get_base_uart(int dev_index) >> { >> u32 offset = dev_index * sizeof(struct s5p_uart); >>@@ -87,8 +91,8 @@ int serial_init_dev(const int dev_index) >> { >> struct s5p_uart *const uart = s5p_get_base_uart(dev_index); >> >>- /* reset and enable FIFOs, set triggers to the maximum */ >>- writel(0, &uart->ufcon); >>+ /* enable FIFOs */ >>+ writel(0x1, &uart->ufcon); >> > >It is odd that you seem to be saying that the old code did not enable FIFOs, but this code does? Or should you update your comment? > Actually old comment was inapt because we were resetting FIFO's but not enabling FIFO. As per manual, for enabling FIFO we need to set LSB of UFCON register, which was missing. But now we are setting this bit and it works as expected. This could be verified by noticing that before applying this patch "Uncompressing linux" message printed garbled/not readable on console but after applying this patch characters appear well in place. Please suggest if this comment needs edit. >> writel(0, &uart->umcon); >> /* 8N1 */ >> writel(0x3, &uart->ulcon); >>@@ -130,7 +134,8 @@ int serial_getc_dev(const int dev_index) >> struct s5p_uart *const uart = s5p_get_base_uart(dev_index); >> >> /* wait for character to arrive */ >>- while (!(readl(&uart->utrstat) & 0x1)) { >>+ while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | >>+ RX_FIFO_FULL_MASK))) { >> if (serial_err_check(dev_index, 0)) >> return 0; >> } >>@@ -146,7 +151,7 @@ void serial_putc_dev(const char c, const int dev_index) >> struct s5p_uart *const uart = s5p_get_base_uart(dev_index); >> >> /* wait for room in the tx FIFO */ >>- while (!(readl(&uart->utrstat) & 0x2)) { >>+ while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { >> if (serial_err_check(dev_index, 1)) >> return; >> } >>-- >>1.8.0 >> >> >>Regards, >> >>Simon >> Thanks & Regards, Akshay Saraswat

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[U-Boot] Pull request: u-boot-staging
by Anatolij Gustschin 01 Apr '13

01 Apr '13

Hello Tom, The following changes since commit 009d75ccc11d27b9a083375a88bb93cb746b4800: Merge branch 'u-boot/master' into 'u-boot-arm/master' (2013-03-28 18:50:01 +0100) are available in the git repository at: git://git.denx.de/u-boot-staging.git agust(a)denx.de Anatolij Gustschin (1): menu: export menu_default_choice() function Pali Rohár (3): menu: Add support for user defined item choice function New command bootmenu: ANSI terminal boot menu support RX-51: Add support for bootmenu board/ait/cam_enc_4xx/cam_enc_4xx.c | 3 +- common/Makefile | 1 + common/cmd_bootmenu.c | 517 +++++++++++++++++++++++++++++++++++ common/cmd_pxe.c | 3 +- common/menu.c | 44 +++- doc/README.bootmenu | 115 ++++++++ doc/README.menu | 9 +- include/ansi.h | 42 +++ include/configs/nokia_rx51.h | 40 +++- include/menu.h | 5 +- 10 files changed, 760 insertions(+), 19 deletions(-) create mode 100644 common/cmd_bootmenu.c create mode 100644 doc/README.bootmenu create mode 100644 include/ansi.h Please pull. Thanks! Anatolij

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[U-Boot] [PATCH] OMAP4/5: Add USB EHCI support
by Lubomir Popov 01 Apr '13

01 Apr '13

Prerequisites (apart from proper config): 1. The HSUSBTLL clock has to be enabled along with the other HW_AUTO essentials, that is, cm_l3init_hsusbtll_clkctrl has to reside in the clk_modules_hw_auto_essential[] array and not in clk_modules_explicit_en_essential[]. Please see related patch to hw_data.c. 2. Other functional clocks have to be enabled prior to starting USB (and, possibly, disabled upon stopping). The proper place for this would be the board file, in the ehci_hcd_init() and ehci_hcd_stop() functions. Please see som5_evb.c as example. 3. If we have HSIC devices on some OMAP5 ports, they shall work only if the design employs reset capability via GPIO. This is performed by the ehci-hcd driver upon applying port power, and requires that we have defined CONFIG_OMAP_HSIC_PORTx_RESET_GPIO in the board config header as appropriate. Please see omap5_som5_evb.h as an example. Note that this additional reset is not needed for OMAP4 HSIC (tested on OMAP4460 and 4470). 4. Can somebody explain why arch/arm/include/asm/arch-omap5/ehci.h has disappeared? It is in fact needed for EHCI USB. Adding it. Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- arch/arm/include/asm/arch-omap5/ehci.h | 44 +++++++++++++++++ drivers/usb/host/ehci-hcd.c | 6 +++ drivers/usb/host/ehci-omap.c | 83 +++++++++++++++++++++++++++++--- drivers/usb/host/ehci.h | 9 ++++ 4 files changed, 135 insertions(+), 7 deletions(-) create mode 100644 arch/arm/include/asm/arch-omap5/ehci.h diff --git a/arch/arm/include/asm/arch-omap5/ehci.h b/arch/arm/include/asm/arch-omap5/ehci.h new file mode 100644 index 0000000..49197f2 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/ehci.h @@ -0,0 +1,44 @@ +/* + * OMAP EHCI port support + * Based on LINUX KERNEL + * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com* + * Author: Govindraj R <govindraj.raja(a)ti.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 of + * the License as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _EHCI_H +#define _EHCI_H + +#define OMAP_EHCI_BASE (OMAP54XX_L4_CORE_BASE + 0x64C00) +#define OMAP_UHH_BASE (OMAP54XX_L4_CORE_BASE + 0x64000) +#define OMAP_USBTLL_BASE (OMAP54XX_L4_CORE_BASE + 0x62000) + +/* TLL Register Set */ +#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) +#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) +#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) +#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) +#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 + +#define OMAP_UHH_SYSCONFIG_SOFTRESET 1 +#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2) +#define OMAP_UHH_SYSCONFIG_NOIDLE (1 << 2) +#define OMAP_UHH_SYSCONFIG_NOSTDBY (1 << 4) + +#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \ + OMAP_UHH_SYSCONFIG_NOSTDBY) + +#endif /* _EHCI_H */ diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index c816878..33d954d 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -750,6 +750,12 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) { reg |= EHCI_PS_PP; ehci_writel(status_reg, reg); + /* + * OMAP5: Reset device for 'fail to connect' + * workaround. Compiled only for OMAP5, and + * only if we have ports in HSIC mode. + */ + omap5_ehci_hsic_reset_device(le16_to_cpu(req->index)); } break; case USB_PORT_FEAT_RESET: diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c index 086c697..07f3774 100644 --- a/drivers/usb/host/ehci-omap.c +++ b/drivers/usb/host/ehci-omap.c @@ -92,12 +92,15 @@ static void omap_usbhs_hsic_init(int port) static void omap_ehci_soft_phy_reset(int port) { + /* This requires proper configs: */ +#if defined(CONFIG_USB_ULPI) && defined(CONFIG_USB_ULPI_VIEWPORT_OMAP) struct ulpi_viewport ulpi_vp; ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi; ulpi_vp.port_num = port; ulpi_reset(&ulpi_vp); +#endif } inline int __board_usb_init(void) @@ -107,7 +110,7 @@ inline int __board_usb_init(void) int board_usb_init(void) __attribute__((weak, alias("__board_usb_init"))); #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \ - defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) + defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) /* controls PHY(s) reset signal(s) */ static inline void omap_ehci_phy_reset(int on, int delay) { @@ -136,10 +139,71 @@ static inline void omap_ehci_phy_reset(int on, int delay) #define omap_ehci_phy_reset(on, delay) do {} while (0) #endif +/* Separate HSIC USB devices reset to fix fail to connect on OMAP5. + * Patch needed in ehci-hcd. See driver code. + */ +#if defined(CONFIG_OMAP_HSIC_PORT1_RESET_GPIO) || \ + defined(CONFIG_OMAP_HSIC_PORT2_RESET_GPIO) || \ + defined(CONFIG_OMAP_HSIC_PORT3_RESET_GPIO) +static inline void omap_ehci_hsic_reset(int port, int on, int delay) +{ + /*printf("omap_ehci_hsic_reset: port %d, reset %s, delay %d\n", port, on ? "On" : "Off", delay);*/ + +#ifdef CONFIG_OMAP_HSIC_PORT1_RESET_GPIO + if (1 == port) { + gpio_request(CONFIG_OMAP_HSIC_PORT1_RESET_GPIO, "USB HSIC1 reset"); + gpio_direction_output(CONFIG_OMAP_HSIC_PORT1_RESET_GPIO, !on); + udelay(delay); + } +#endif +#ifdef CONFIG_OMAP_HSIC_PORT2_RESET_GPIO + if (2 == port) { + gpio_request(CONFIG_OMAP_HSIC_PORT2_RESET_GPIO, "USB HSIC2 reset"); + gpio_direction_output(CONFIG_OMAP_HSIC_PORT2_RESET_GPIO, !on); + udelay(delay); + } +#endif +#ifdef CONFIG_OMAP_HSIC_PORT3_RESET_GPIO + if (3 == port) { + gpio_request(CONFIG_OMAP_HSIC_PORT3_RESET_GPIO, "USB HSIC3 reset"); + gpio_direction_output(CONFIG_OMAP_HSIC_PORT3_RESET_GPIO, !on); + udelay(delay); + } +#endif +} +#else +#define omap_ehci_hsic_reset(port, on, delay) do {} while (0) +#endif + +#if defined(CONFIG_OMAP54XX) && \ + (defined(CONFIG_OMAP_HSIC_PORT1_RESET_GPIO) || \ + defined(CONFIG_OMAP_HSIC_PORT2_RESET_GPIO) || \ + defined(CONFIG_OMAP_HSIC_PORT3_RESET_GPIO)) +/* OMAP5: Reset HSIC devices upon applying port power for + * 'fail to connect' workaround. Called by ehci-hcd. + */ +inline void omap5_ehci_hsic_reset_device(int port_index) +{ + omap_ehci_hsic_reset(port_index, 1, 100); + omap_ehci_hsic_reset(port_index, 0, 0); +} +#else +inline void omap5_ehci_hsic_reset_device(int port_index) {} +#endif + /* Reset is needed otherwise the kernel-driver will throw an error. */ int omap_ehci_hcd_stop(void) { debug("Resetting OMAP EHCI\n"); +#ifdef CONFIG_OMAP_HSIC_PORT1_RESET_GPIO + omap_ehci_hsic_reset(1, 1, 0); +#endif +#ifdef CONFIG_OMAP_HSIC_PORT2_RESET_GPIO + omap_ehci_hsic_reset(2, 1, 0); +#endif +#ifdef CONFIG_OMAP_HSIC_PORT3_RESET_GPIO + omap_ehci_hsic_reset(3, 1, 0); +#endif omap_ehci_phy_reset(1, 0); if (omap_uhh_reset() < 0) @@ -168,7 +232,7 @@ int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata, if (ret < 0) return ret; - /* Put the PHY in RESET */ + /* Put the PHYs (if any) in RESET */ omap_ehci_phy_reset(1, 10); ret = omap_uhh_reset(); @@ -209,11 +273,10 @@ int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata, else setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS); } else if (rev == OMAP_USBHS_REV2) { + /* Clear port mode fields for PHY mode */ clrsetbits_le32(&reg, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR), OMAP4_UHH_HOSTCONFIG_APP_START_CLK); - /* Clear port mode fields for PHY mode*/ - if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0])) setbits_le32(&reg, OMAP_P1_MODE_HSIC); @@ -227,10 +290,16 @@ int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata, debug("OMAP UHH_REVISION 0x%x\n", rev); writel(reg, &uhh->hostconfig); - for (i = 0; i < OMAP_HS_USB_PORTS; i++) - if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i])) + /* OMAP5 HSIC devices (if any) shall be reset again by the + * ehci-hcd driver upon applying port power. See driver patch. + */ + for (i = 0; i < OMAP_HS_USB_PORTS; i++) { + if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i])) { omap_usbhs_hsic_init(i); - + omap_ehci_hsic_reset(i + 1, 0, 0); /* Release reset on HSIC port */ + } + } + /* Release ULPI PHY reset and let PLL lock */ omap_ehci_phy_reset(0, 10); /* diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index d090f0a..9e0230b 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -256,4 +256,13 @@ struct QH { int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor); int ehci_hcd_stop(int index); +/* OMAP5: Reset HSIC devices upon applying port power for + * 'fail to connect' workaround (ehci-omap.c) + */ +#ifndef CONFIG_USB_EHCI_OMAP +static inline void omap5_ehci_hsic_reset_device(int port_index) {} +#else +inline void omap5_ehci_hsic_reset_device(int port_index); +#endif + #endif /* USB_EHCI_H */ -- 1.7.9.5

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[U-Boot] Banner -> git co target?
by Michael Cashwell 01 Apr '13

01 Apr '13

Greetings, My u-boot work area got messed up recently when I pulled from master. I'm having trouble figuring out what's wrong. I have this banner "U-Boot SPL 2013.04-rc1-00024-ga268170-dirty (Mar 15 2013 - 10:24:41)" from a recently working state. A corresponding banner that's broken for me is "U-Boot SPL 2013.04-rc1-00292-g417c558-dirty (Apr 01 2013 - 08:10:25)" I'd like to go through and methodically compare these two but I can't figure out what git command would rewind the work area back to a state that corresponds to a known u-boot banner. I assume the key bits are "00024-ga268170" but I expect I need a commit ID or branch name and that doesn't seem to be either. Any pointers? Thanks, -Mike Cashwell

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[U-Boot] [PATCH] OMAP5: Power: Added more functionality to twl6035 driver
by Lubomir Popov 01 Apr '13

01 Apr '13

Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- This patch adds some new functions that were used for the SOM5_EVB bringup, but might be useful for other OMAP5 designs as well. drivers/power/twl6035.c | 140 +++++++++++++++++++++++++++++++++++++++++++---- include/twl6035.h | 83 ++++++++++++++++++++++++++-- 2 files changed, 206 insertions(+), 17 deletions(-) diff --git a/drivers/power/twl6035.c b/drivers/power/twl6035.c index d3de698..5fc517b 100644 --- a/drivers/power/twl6035.c +++ b/drivers/power/twl6035.c @@ -2,6 +2,8 @@ * (C) Copyright 2012 * Texas Instruments, <www.ti.com> * + * 02/2013 Modified by Lubomir Popov <lpopov(a)mm-sol.com> + * * See file CREDITS for list of people who contributed to this * project. * @@ -21,9 +23,12 @@ * MA 02111-1307 USA */ #include <config.h> + +#ifdef CONFIG_TWL6035_POWER + #include <twl6035.h> -/* Functions to read and write from TWL6030 */ +/* Functions to read and write from TWL6035 */ int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg) { return i2c_write(chip_no, reg, 1, &val, 1); @@ -47,28 +52,141 @@ static inline int palmas_read_u8(u8 chip_no, u8 reg, u8 *val) void twl6035_init_settings(void) { - return; +#ifdef CONFIG_TWL6035_SMPS7_FPWM + int err; + /* Set SMPS7 (1.8 V I/O supply) to forced PWM mode */ + u8 val = SMPS_MODE_SLP_FPWM | SMPS_MODE_ACT_FPWM; + if ((err = palmas_write_u8(TWL6035_CHIP_P1, SMPS7_CTRL, val))) + printf("twl6035: Could not force PWM for SMPS7: err = %d\n", err); +#endif +} + +/* On some hardware the SD card socket and LDO9_IN are powered by an + * external 3.3 V regulator. Therefore VDDS_SDCARD should be 3.3 V + * as well for 3 V cards. This requires that LDO9 is set to 'bypass' + * mode for such cases. + * + * NOTE: Switching LDOs between the 0.9 - 2.1 V and 2.15 - 3.3 V ranges + * cannot be done on the fly and requires restart (off - change + * voltage - on). This should be taken care of at a higher level. + */ +int twl6035_mmc1_set_ldo9(u8 vsel) +{ + u8 cval=0, vval=0; /* Off by default */ + int err; + + if (vsel) { + /* Turn on */ + if (vsel > LDO_VOLT_3V3) { + /* Put LDO9 in bypass */ + cval = LDO9_BYP_EN | RSC_MODE_SLEEP | RSC_MODE_ACTIVE; + vval = LDO_VOLT_3V3; + } + else { + cval = RSC_MODE_SLEEP | RSC_MODE_ACTIVE; + vval = vsel & 0x3f; + } + } + if ((err = palmas_write_u8(TWL6035_CHIP_P1, LDO9_VOLTAGE, vval))) { + printf("twl6035: could not set LDO9 %s: err = %d\n", + vsel > LDO_VOLT_3V3 ? "bypass" : "voltage", err); + return err; + } + if ((err = palmas_write_u8(TWL6035_CHIP_P1, LDO9_CTRL, cval))) + printf("twl6035: could not turn on LDO9: err = %d\n", err); + return err; } int twl6035_mmc1_poweron_ldo(void) { u8 val = 0; - /* set LDO9 TWL6035 to 3V */ - val = 0x2b; /* (3 -.9)*28 +1 */ - - if (palmas_write_u8(0x48, LDO9_VOLTAGE, val)) { + /* Set TWL6035 LDO9 to 3.0 V */ + val = LDO_VOLT_3V0; + if (palmas_write_u8(TWL6035_CHIP_P1, LDO9_VOLTAGE, val)) { printf("twl6035: could not set LDO9 voltage.\n"); return 1; } - /* TURN ON LDO9 */ - val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE; - - if (palmas_write_u8(0x48, LDO9_CTRL, val)) { + val = RSC_MODE_SLEEP | RSC_MODE_ACTIVE; + if (palmas_write_u8(TWL6035_CHIP_P1, LDO9_CTRL, val)) { printf("twl6035: could not turn on LDO9.\n"); return 1; } - return 0; } + +int twl6035_usb_poweron_ldo(void) +{ + u8 val = 0; + int err; + + /* Enable external VCC_3v3_AUX supply on the sEVM (SYSEN2) */ + val = RSC_MODE_SLEEP | RSC_MODE_ACTIVE; + if ((err = palmas_write_u8(TWL6035_CHIP_P1, SYSEN2_CTRL, val))) { + printf("twl6035: could not set SYSEN2: err = %d\n", err); + return err; + } + + /* TURN ON LDO's needed */ + + /* Set LDOUSB to 3.3 V */ + val = LDO_VOLT_3V3; + if ((err = palmas_write_u8(TWL6035_CHIP_P1, LDOUSB_VOLTAGE, val))) { + printf("twl6035: could not set LDOUSB voltage: err = %d\n", err); + return err; + } + + /* Enable LDOUSB */ + val = RSC_MODE_SLEEP | RSC_MODE_ACTIVE; + if ((err = palmas_write_u8(TWL6035_CHIP_P1, LDOUSB_CTRL, val))) + printf("twl6035: could not turn on LDOUSB: err = %d\n", err); + return err; +} + +/* Turn audio codec power and 32 kHz clock on/off + */ +int twl6035_audio_power(u8 on) +{ + u8 cval=0, vval=0, c32k=0; + int err; + + if (on) { + vval = SMPS_VOLT_2V1; + cval = SMPS_MODE_SLP_AUTO | SMPS_MODE_ACT_AUTO; + c32k = RSC_MODE_SLEEP | RSC_MODE_ACTIVE; + } + /* Set SMPS9 to 2.1 V (for TWL604x), or to 0 (off) */ + if ((err = palmas_write_u8(TWL6035_CHIP_P1, SMPS9_VOLTAGE, vval))) { + printf("twl6035: could not set SMPS9 voltage: err = %d\n", err); + return err; + } + /* Turn on or off SMPS9 */ + if ((err = palmas_write_u8(TWL6035_CHIP_P1, SMPS9_CTRL, cval))) { + printf("twl6035: could not turn SMPS9 %s: err = %d\n", + cval ? "on" : "off", err); + return err; + } + /* Output 32 kHz clock on or off */ + if ((err = palmas_write_u8(TWL6035_CHIP_P1, CLK32KGAUDIO_CTRL, c32k))) + printf("twl6035: could not turn CLK32KGAUDIO %s: err = %d\n", + c32k ? "on" : "off", err); + return err; +} + +/* Enable/disable back-up battery (or super cap) charging. + * Please use defines. + */ +int twl6035_enable_bb_charge(u8 bb_fields) +{ + u8 val = bb_fields & 0x0f; + int err; + + val |= (VRTC_EN_SLP | VRTC_EN_OFF | VRTC_PWEN); + if ((err = palmas_write_u8(TWL6035_CHIP_P1, BB_VRTC_CTRL, val))) + printf("twl6035: could not set BB_VRTC_CTRL to 0x%02x: err = %d\n", val, err); + return err; +} + +#endif /* CONFIG_TWL6035_POWER */ + diff --git a/include/twl6035.h b/include/twl6035.h index ce74348..50e0b47 100644 --- a/include/twl6035.h +++ b/include/twl6035.h @@ -2,6 +2,8 @@ * (C) Copyright 2012 * Texas Instruments, <www.ti.com> * + * 02/2013 Modified by Lubomir Popov <lpopov(a)mm-sol.com> + * * See file CREDITS for list of people who contributed to this * project. * @@ -25,18 +27,87 @@ #include <i2c.h> /* I2C chip addresses */ -#define TWL6035_CHIP_ADDR 0x48 +#define TWL6035_CHIP_P1 0x48 /* Page 1 */ +#define TWL6035_CHIP_P2 0x49 /* Page 2 */ +#define TWL6035_CHIP_P3 0x4a /* Page 3 */ + +/* Page 1 registers (0x1XY translates to page 1, register address 0xXY): */ -/* 0x1XY translates to page 1, register address 0xXY */ +/* LDO9_CTRL */ #define LDO9_CTRL 0x60 #define LDO9_VOLTAGE 0x61 -/* Bit field definitions for LDOx_CTRL */ -#define LDO_ON (1 << 4) -#define LDO_MODE_SLEEP (1 << 2) -#define LDO_MODE_ACTIVE (1 << 0) +/* Control of 32 kHz audio clock */ +#define CLK32KGAUDIO_CTRL 0xd5 + +/* SYSEN2_CTRL for VCC_3v3_AUX supply on the sEVM */ +#define SYSEN2_CTRL 0xd9 + +/* LDOUSB_CTRL */ +#define LDOUSB_CTRL 0x64 +#define LDOUSB_VOLTAGE 0x65 + +/* Bit field definitions for LDOx_CTRL, SYSENx_CTRL + * and some other xxx_CTRL resources + */ +#define LDO9_BYP_EN (1 << 6) /* LDO9 only! */ +#define RSC_STAT_ON (1 << 4) /* RO bit! */ +#define RSC_MODE_SLEEP (1 << 2) +#define RSC_MODE_ACTIVE (1 << 0) + +/* Some LDO voltage values */ +#define LDO_VOLT_OFF 0 +#define LDO_VOLT_1V8 0x13 +#define LDO_VOLT_3V0 0x2b +#define LDO_VOLT_3V3 0x31 +/* Request bypass, LDO9 only */ +#define LDO9_BYPASS 0x3f + +/* SMPS7_CTRL */ +#define SMPS7_CTRL 0x30 + +/* SMPS9_CTRL */ +#define SMPS9_CTRL 0x38 +#define SMPS9_VOLTAGE 0x3b + +/* Bit field definitions for SMPSx_CTRL */ +#define SMPS_MODE_ACT_AUTO 1 +#define SMPS_MODE_ACT_ECO 2 +#define SMPS_MODE_ACT_FPWM 3 +#define SMPS_MODE_SLP_AUTO (1 << 2) +#define SMPS_MODE_SLP_ECO (2 << 2) +#define SMPS_MODE_SLP_FPWM (3 << 2) + +/* Some popular SMPS voltages, all with RANGE=1; note + * that RANGE cannot be changed on the fly + */ +#define SMPS_VOLT_OFF 0 +#define SMPS_VOLT_1V2 0x90 +#define SMPS_VOLT_1V8 0xae +#define SMPS_VOLT_2V1 0xbd +#define SMPS_VOLT_3V0 0xea +#define SMPS_VOLT_3V3 0xf9 + +/* Backup Battery & VRTC Control */ +#define BB_VRTC_CTRL 0xa8 +/* Bit definitions for BB_VRTC_CTRL */ +#define VRTC_EN_SLP (1 << 6) +#define VRTC_EN_OFF (1 << 5) +#define VRTC_PWEN (1 << 4) +#define BB_LOW_ICHRG (1 << 3) +#define BB_HIGH_ICHRG (0 << 3) +#define BB_VSEL_3V0 (0 << 1) +#define BB_VSEL_2V5 (1 << 1) +#define BB_VSEL_3V15 (2 << 1) +#define BB_VSEL_VBAT (3 << 1) +#define BB_CHRG_EN (1 << 0) int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg); int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg); void twl6035_init_settings(void); int twl6035_mmc1_poweron_ldo(void); +int twl6035_mmc1_set_ldo9(u8 vsel); +int twl6035_usb_poweron_ldo(void); +int twl6035_audio_power(u8 on); +int twl6035_enable_bb_charge(u8 bb_fields); + -- 1.7.9.5

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[U-Boot] [PATCH v4 0/3] i.MX6 SabreSD and SabreAUTO bmode support
by Otavio Salvador 01 Apr '13

01 Apr '13

This adds the bmode support for i.MX6 SabreSD and SabreAUTO boards. This allows user to choose the boot mode at runtime making it easy to boot from USB or other media. Changes in v4: - Fix switch code to proper break (Stefano) Changes in v3: - Drop change in bootdelay; the change where done by me while testing it and I mistakenly included it. Changes in v2: - Rework code to use a 'ret' variable (Fabio) - Improve commit log Otavio Salvador (3): mx6qsabresd: Fix card detection for invalid card id case mx6qsabresd: Document the mapping of USDHC[2-4] mx6qsabre{sd,auto}: Add boot mode select board/freescale/mx6qsabreauto/mx6qsabreauto.c | 17 ++++++++++++ board/freescale/mx6qsabresd/mx6qsabresd.c | 38 ++++++++++++++++++++++++--- include/configs/mx6qsabre_common.h | 2 ++ 3 files changed, 53 insertions(+), 4 deletions(-) -- 1.8.1

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[U-Boot] [PATCH V7 00/10] EXYNOS5: Enable DWMMC, add FDT support for DWMMC and enable EMMC boot
by Amar 01 Apr '13

01 Apr '13

This patch set enables and initialises DWMMC for Exynos5250 on SMDK5250. Adds driver changes required for DWMMC. Adds FDT support for DWMMC. Adds EMMC boot support for SMDK5250. This patch set is based on: "EXYNOS: mmc: support DesignWare Controller for Samsung-SoC", which is merged in u-boot-mmc. "Exynos: clock: support get_mmc_clk for exynos". "Add DT based ethernet driver for SMDK5250". "SMDK5250: Add FDT support" present at the following link http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/149991 Changes from V1: 1)Corrected in response to review comments. 2)Created separate board files for FDT and non-FDT versions. 3)Added binding file for DWMMC device node. 4)Removed the propname 'index' from device node. 5)Prefixed the vendor name 'samsung' before propname in device node. 6)Ensured to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 7)EMMC clock setting has been moved from spl_boot.c to clock_init.c. Changes from V2: 1)Updation of commit message and resubmition of proper patch set. Changes from V3: 1)Updated to use the macro DWMCI_CTRL_SEND_AS_CCSD instead of the hard coded value (1 << 10). 2)In the file exynos_dw_mmc.c, replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the purpose. 3)In the file exynos_dw_mmc.c, computation of FSYS block clock divisor (pre-ratio) value is added. 4)Removed the new function exynos5_mmc_set_clk_div() from clock.c. Changes from V4: 1)Updated the function dwmci_send_cmd() to use get_timer() instead of using mdelay(1). 2)Replaced the function call 'exynos_dwmmc_init(0, 8);' with the function exynos_dwmmc_add_port() in smdk5250.c. 3)The function get_irom_func(int index) has been added to avoid type casting at many places. 4)Used the generic function "mmc_boot_part_access()" instead of two functions "mmc_boot_open()" and "mmc_boot_close()". By doing so user can specify which boot partition to be accessed (opened / closed). Changes from V5: 1)Added the 'removable' flag to mmc device node. 2)Changed the mmc clock value from 50MHz to 52MHz in the function exynos_dwmci_add_port() present in file drivers/mmc/exynos_dw_mmc.c. 3)Enabled CONFIG_LCD only for non-FDT operation. 4)Removed the function call i2c_init() present inside the function board_i2c_init(). Changes from V6: 1)Re-based to the patch "SMDK5250: Add PMIC voltage settings". Amar (10): FDT: Add compatible string for DWMMC EXYNOS5: FDT: Add DWMMC device node data DWMMC: Initialise dwmci and resolve EMMC read write issues EXYNOS5: DWMMC: Added FDT support for DWMMC EXYNOS5: DWMMC: Initialise the local variable to avoid unwanted results. SMDK5250: Initialise and Enable DWMMC, support FDT and non-FDT MMC: APIs to support resize of EMMC boot partition SMDK5250: Enable EMMC booting COMMON: MMC: Command to support EMMC booting and to resize EMMC boot partition EXYNOS5: I2C: Added FDT and non-FDT support for I2C arch/arm/cpu/armv7/exynos/clock.c | 4 +- arch/arm/dts/exynos5250.dtsi | 31 +++ arch/arm/include/asm/arch-exynos/clk.h | 3 + arch/arm/include/asm/arch-exynos/dwmmc.h | 11 +- board/samsung/dts/exynos5250-smdk5250.dts | 24 +++ board/samsung/smdk5250/Makefile | 4 + board/samsung/smdk5250/clock_init.c | 15 ++ board/samsung/smdk5250/clock_init.h | 5 + board/samsung/smdk5250/exynos5-dt.c | 319 ++++++++++++++++++++++++++++++ board/samsung/smdk5250/smdk5250.c | 165 ++++++---------- board/samsung/smdk5250/spl_boot.c | 52 ++++- common/cmd_mmc.c | 98 ++++++++- doc/device-tree-bindings/exynos/dwmmc.txt | 54 +++++ drivers/i2c/s3c24x0_i2c.c | 12 +- drivers/mmc/dw_mmc.c | 25 ++- drivers/mmc/exynos_dw_mmc.c | 127 +++++++++++- drivers/mmc/mmc.c | 132 +++++++++++++ include/configs/exynos5250-dt.h | 8 + include/dwmmc.h | 3 + include/fdtdec.h | 1 + include/mmc.h | 26 +++ lib/fdtdec.c | 1 + 22 files changed, 974 insertions(+), 146 deletions(-) create mode 100644 board/samsung/smdk5250/exynos5-dt.c create mode 100644 doc/device-tree-bindings/exynos/dwmmc.txt -- 1.8.0

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Re: [U-Boot] [PATCH 00/11 v3] Fix and Re-organise PWM Timer
by Akshay Saraswat 01 Apr '13

01 Apr '13

Hi Minkyu, >Dear Akshay, > >On 28/03/13 23:32, Akshay Saraswat wrote: >> This patch set tries to fix few bugs in timer and re-organises PWM >> clock code. >> >> Changes since v2: >> - Patch-1: New patch. >> - Patch-2: None. >> - Patch-3: None. >> - Patch-4: None. >> - Patch-5: Fixed typo paremters in commit message. >> - Patch-6: None. >> - Patch-7: Added "Acked-by: Simon Glass". >> - Patch-8: >> Fixed typo peripherial to peripheral. >> - Made exynos5_get_periph_rate static. >> - Added an empty line. >> - Replaced "enum periph_id" with "int" in function arguments. >> - Removed "#include <asm/arch/periph.h>" from clk.h. >> - Added "Acked-by: Simon Glass". >> - Patch-9: None. >> - Patch-10: >> - Replaced "exynos5_get_pwm_clk" with "clock_get_periph_rate" in get_pwm_clk >> instead of replacing everywhere. >> - Added "Acked-by: Simon Glass". >> - Patch-11: New patch. >> >> Changes since v1: >> - Patch-1: Added "Acked-by: Simon Glass". >> - Patch-2: Added "Acked-by: Simon Glass". >> - Patch-3: Added "Acked-by: Simon Glass". >> - Patch-4: Added "Acked-by: Simon Glass". >> - Patch-5: Added "Acked-by: Simon Glass". >> - Patch-6: None. >> - Patch-7: Fixed few nits. >> - Patch-8: Added "Acked-by: Simon Glass". >> - Patch-9: Restored get_pwm_clk call in case of non-exynos5 cpu. >> >> Akshay Saraswat (11): >> Exynos5: config: enable time command >> Exynos: Change get_timer() to work correctly >> Exynos: Add timer_get_us function >> Exynos: pwm: Fix two bugs in the exynos pwm configuration code >> Exynos: Avoid a divide by zero by specifying a non-zero period >> for pwm 4 >> Exynos: Tidy up the pwm_config function in the exynos pwm driver >> Exynos: Add peripherial id for pwm >> Exynos: clock: Add generic api to get the clk freq >> Exynos: clock: Correct pwm source clk selection >> Exynos: pwm: Use generic api to get pwm clk freq >> Exynos: pwm: Remove dead code of function exynos5_get_pwm_clk >> >> arch/arm/cpu/armv7/exynos/clock.c | 167 ++++++++++++++++++++++++++---- >> arch/arm/cpu/armv7/s5p-common/pwm.c | 42 ++++---- >> arch/arm/cpu/armv7/s5p-common/timer.c | 117 ++++++++++----------- >> arch/arm/include/asm/arch-exynos/clk.h | 15 +++ >> arch/arm/include/asm/arch-exynos/periph.h | 5 + >> board/samsung/smdk5250/setup.h | 2 +- >> include/configs/exynos5250-dt.h | 3 + >> 7 files changed, 244 insertions(+), 107 deletions(-) >> > >The patch-7 seems to did not reached at mailing list. >If not, please let me know a link of patchwork. > >Thanks, >Minkyu Kang. > I am sorry. I don't know how come this patch was left when the whole set was posted. I am posting patch-7 now. Please consider it. Thanks & Regards, Akshay Saraswat

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[U-Boot] [PATCH v1] bf609: add SPI register base address
by Sonic Zhang 01 Apr '13

01 Apr '13

From: Scott Jiang <scott.jiang.linux(a)gmail.com> - BF609 spi driver depend on this. Signed-off-by: Scott Jiang <scott.jiang.linux(a)gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang(a)analog.com> --- arch/blackfin/include/asm/mach-bf609/BF609_def.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_def.h b/arch/blackfin/include/asm/mach-bf609/BF609_def.h index 4d3b003..02b81d3 100644 --- a/arch/blackfin/include/asm/mach-bf609/BF609_def.h +++ b/arch/blackfin/include/asm/mach-bf609/BF609_def.h @@ -128,6 +128,9 @@ #define EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */ #define EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */ +#define SPI0_REGBASE 0xFFC40400 /* SPI0 Base Address */ +#define SPI1_REGBASE 0xFFC40500 /* SPI1 Base Address */ + #define DMA10_DSCPTR_NXT 0xFFC05000 /* DMA10 Pointer to Next Initial Desc */ #define DMA10_ADDRSTART 0xFFC05004 /* DMA10 Start Address of Current Buf */ #define DMA10_CFG 0xFFC05008 /* DMA10 Configuration Register */ -- 1.7.0.4

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[U-Boot] [PATCH 07/11 v3] Exynos: Add peripherial id for pwm
by Akshay Saraswat 01 Apr '13

01 Apr '13

From: Padmavathi Venna <padma.v(a)samsung.com> Add peripherial id for pwm inorder to support generic api to get the clk frequency Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v(a)samsung.com> Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes since v2: - Added "Acked-by: Simon Glass". Changes since v1: - None. arch/arm/include/asm/arch-exynos/periph.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 89bcdfc..e5aed4b 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -61,6 +61,11 @@ enum periph_id { PERIPH_ID_SPI3, PERIPH_ID_SPI4, PERIPH_ID_SDMMC4, + PERIPH_ID_PWM0, + PERIPH_ID_PWM1, + PERIPH_ID_PWM2, + PERIPH_ID_PWM3, + PERIPH_ID_PWM4, PERIPH_ID_COUNT, PERIPH_ID_NONE = -1, -- 1.8.0

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