March 2013 - U-Boot

[U-Boot] [PATCH 4/5][v2] board/bsc9131rdb:Add NAND boot support using new SPL format
by Prabhakar Kushwaha 22 Mar '13

22 Mar '13

- Add NAND boot target - defines contants - Add spl_minimal.c to initialise DDR - update TLB entries as per NAND boot Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot.git branch master Changes for v2: Sending as it is board/freescale/bsc9131rdb/Makefile | 16 ++++ board/freescale/bsc9131rdb/spl_minimal.c | 118 ++++++++++++++++++++++++++++++ board/freescale/bsc9131rdb/tlb.c | 6 +- boards.cfg | 1 + include/configs/BSC9131RDB.h | 49 ++++++++++--- 5 files changed, 176 insertions(+), 14 deletions(-) create mode 100644 board/freescale/bsc9131rdb/spl_minimal.c diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile index 6f4cb26..2e829ad 100644 --- a/board/freescale/bsc9131rdb/Makefile +++ b/board/freescale/bsc9131rdb/Makefile @@ -24,12 +24,28 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL + +COBJS-y += spl_minimal.o tlb.o law.o + +else + COBJS-y += $(BOARD).o COBJS-y += ddr.o COBJS-y += law.o COBJS-y += tlb.o #COBJS-y += bsc9131rdb_mux.o +endif + SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c new file mode 100644 index 0000000..b5b29e0 --- /dev/null +++ b/board/freescale/bsc9131rdb/spl_minimal.c @@ -0,0 +1,118 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ns16550.h> +#include <asm/io.h> +#include <nand.h> +#include <linux/compiler.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +static void sdram_init(void) +{ + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + + __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); + __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); +#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 + __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); + __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); +#endif + __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); + + __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); + + __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); + + __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); + __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); + __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); + __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); + + /* Set, but do not enable the memory */ + __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg); + + asm volatile("sync;isync"); + udelay(500); + + /* Let the controller go */ + out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); + + set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + gd->bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + + /* Initialize the DDR3 */ + sdram_init(); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c index 5b68f4a..e6cb37a 100644 --- a/board/freescale/bsc9131rdb/tlb.c +++ b/board/freescale/bsc9131rdb/tlb.c @@ -43,16 +43,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), + 0, 0, BOOKE_PAGESZ_8K, 1), /* *I*G* - CCSRBAR (PA) */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), -#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_1G, 1), diff --git a/boards.cfg b/boards.cfg index ee68fdd..57930f5 100644 --- a/boards.cfg +++ b/boards.cfg @@ -875,6 +875,7 @@ P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 P5040DS powerpc mpc85xx corenet_ds freescale BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH +BSC9131RDB_NAND powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,NAND BSC9132QDS_NOR_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100 BSC9132QDS_NOR_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133 BSC9132QDS_SDCARD_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100 diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index fd076e0..73fdc84 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -40,10 +40,34 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#ifdef CONFIG_NAND +#define CONFIG_SPL +#define CONFIG_SPL_INIT_MINIMAL +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" + +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFFE000 +#define CONFIG_SPL_MAX_SIZE (8 * 1024) +#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 +#define CONFIG_SPL_RELOC_STACK 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #endif +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + + /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ @@ -214,6 +238,9 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ @@ -295,7 +322,6 @@ extern unsigned long get_sdram_size(void); /* * Environment */ -#if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_BUS 0 @@ -305,15 +331,16 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 #define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif -#else -#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#elif defined(CONFIG_NAND) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) +#elif defined(CONFIG_SYS_RAMBOOT) +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x400 +#define CONFIG_ENV_SIZE 0x2000 #endif #define CONFIG_LOADS_ECHO /* echo on for serial download */ -- 1.7.9.5

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[U-Boot] [PATCH 3/5][v2] board/p1010rdb:Add NAND boot support using new SPL format
by Prabhakar Kushwaha 22 Mar '13

22 Mar '13

- defines contants - Add spl_minimal.c to initialise DDR - update TLB entries as per NAND boot - remove nand_spl support for P1010RDB Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot.git branch master Changes for v2: - Define CONFIG_A003399_NOR_WORKAROUND for NOR boot board/freescale/p1010rdb/Makefile | 16 ++ .../freescale/p1010rdb/spl_minimal.c | 20 +- board/freescale/p1010rdb/tlb.c | 10 +- include/configs/P1010RDB.h | 71 ++--- nand_spl/board/freescale/p1010rdb/Makefile | 142 ---------- nand_spl/nand_boot_fsl_ifc.c | 271 -------------------- 6 files changed, 73 insertions(+), 457 deletions(-) rename nand_spl/board/freescale/p1010rdb/nand_boot.c => board/freescale/p1010rdb/spl_minimal.c (95%) delete mode 100644 nand_spl/board/freescale/p1010rdb/Makefile delete mode 100644 nand_spl/nand_boot_fsl_ifc.c diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile index 4c705b6..e6563be 100644 --- a/board/freescale/p1010rdb/Makefile +++ b/board/freescale/p1010rdb/Makefile @@ -24,11 +24,27 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL + +COBJS-y += spl_minimal.o tlb.o law.o + +else + COBJS-y += $(BOARD).o COBJS-y += ddr.o COBJS-y += law.o COBJS-y += tlb.o +endif + SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/board/freescale/p1010rdb/spl_minimal.c similarity index 95% rename from nand_spl/board/freescale/p1010rdb/nand_boot.c rename to board/freescale/p1010rdb/spl_minimal.c index 3c7bc2b..c909e0e 100644 --- a/nand_spl/board/freescale/p1010rdb/nand_boot.c +++ b/board/freescale/p1010rdb/spl_minimal.c @@ -31,11 +31,18 @@ DECLARE_GLOBAL_DATA_PTR; -unsigned long ddr_freq_mhz; void sdram_init(void) { ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 ddr_ratio; + unsigned long ddr_freq_mhz; + + ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; + ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; + ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000; + /* mask off E bit */ u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR)); @@ -81,6 +88,7 @@ void sdram_init(void) __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds); } + asm volatile("sync;isync"); udelay(500); /* Let the controller go */ @@ -91,7 +99,7 @@ void sdram_init(void) void board_init_f(ulong bootflag) { - u32 plat_ratio, ddr_ratio; + u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; /* initialize selected port with appropriate baud rate */ @@ -99,10 +107,6 @@ void board_init_f(ulong bootflag) plat_ratio >>= 1; gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; - ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; - ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000; - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, gd->bus_clk / 16 / CONFIG_BAUDRATE); @@ -115,8 +119,8 @@ void board_init_f(ulong bootflag) /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. */ - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, - CONFIG_SYS_NAND_U_BOOT_RELOC); + + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); } void board_init_r(gd_t *gd, ulong dest_addr) diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 4256bf4..cf725ee 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -43,16 +43,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), + 0, 0, BOOKE_PAGESZ_8K, 1), /* *I*G* - CCSRBAR */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SDCARD SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, @@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 3, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_PCI +#ifndef CONFIG_PCI /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_1M, 1), #endif -#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_1G, 1) diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 437ee6e..e02564f 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -48,15 +48,25 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif -#ifdef CONFIG_NAND /* NAND Boot */ -#define CONFIG_RAMBOOT_NAND -#define CONFIG_NAND_U_BOOT -#define CONFIG_SYS_TEXT_BASE_SPL 0xff800000 -#ifdef CONFIG_NAND_SPL -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL -#else -#define CONFIG_SYS_TEXT_BASE 0x11001000 -#endif /* CONFIG_NAND_SPL */ +#ifdef CONFIG_NAND +#define CONFIG_SPL +#define CONFIG_SPL_INIT_MINIMAL +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" + +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFFE000 +#define CONFIG_SPL_MAX_SIZE (8 * 1024) +#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 +#define CONFIG_SPL_RELOC_STACK 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #endif @@ -74,8 +84,10 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif /* High Level Configuration Options */ @@ -241,7 +253,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* Don't relocate CCSRBAR while in NAND_SPL */ -#ifdef CONFIG_NAND_SPL +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif @@ -267,6 +279,10 @@ extern unsigned long get_sdram_size(void); * IFC Definitions */ /* NOR Flash on IFC */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_NO_FLASH +#endif + #define CONFIG_SYS_FLASH_BASE 0xee000000 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ @@ -352,7 +368,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NAND_DDR_LAW 11 /* Set up IFC registers for boot location NOR/NAND */ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SECBOOT) +#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR @@ -384,15 +400,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -/* NAND boot: 8K NAND loader config */ -#define CONFIG_SYS_NAND_SPL_SIZE 0x2000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) -#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x10000 -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) - /* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffb00000 @@ -420,14 +427,18 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_CS3_FTIM3 0x0 #endif /* CONFIG_SDCARD */ -#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ - defined(CONFIG_RAMBOOT_NAND) +#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC #else #undef CONFIG_SYS_RAMBOOT #endif +#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\ + && !defined(CONFIG_SECURE_BOOT) +#define CONFIG_A003399_NOR_WORKAROUND +#endif + #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ #define CONFIG_BOARD_EARLY_INIT_R @@ -449,7 +460,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#ifdef CONFIG_NAND_SPL +#ifdef CONFIG_SPL_BUILD #define CONFIG_NS16550_MIN_FUNCTIONS #endif @@ -504,7 +515,7 @@ extern unsigned long get_sdram_size(void); * SPI interface will not be available in case of NAND boot SPI CS0 will be * used for SLIC */ -#if !defined(CONFIG_NAND_U_BOOT) || !defined(CONFIG_NAND_SECBOOT) +#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) /* eSPI - Enhanced SPI */ #define CONFIG_FSL_ESPI #define CONFIG_SPI_FLASH @@ -599,7 +610,6 @@ extern unsigned long get_sdram_size(void); /* * Environment */ -#if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_ENV_IS_IN_MMC #define CONFIG_FSL_FIXED_MMC_LOCATION @@ -614,16 +624,15 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 #define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_NAND_U_BOOT) +#elif defined(CONFIG_NAND) #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_U_BOOT_SIZE +#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) -#else +#elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 -#endif #else #define CONFIG_ENV_IS_IN_FLASH #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile deleted file mode 100644 index f7bdf92..0000000 --- a/nand_spl/board/freescale/p1010rdb/Makefile +++ /dev/null @@ -1,142 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr(a)denx.de. -# -# Copyright 2011 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -NAND_SPL := y -CONFIG_SYS_TEXT_BASE_SPL := 0xff800000 -PAD_TO := 0xff802000 - -include $(TOPDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds -LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o resetvec.o ticks.o -COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl - -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)board/$(BOARDDIR) \ - -ansi -D__ASSEMBLY__ -P - <$< >$@ - -# create symbolic links for common files - -$(obj)cache.c: - @rm -f $(obj)cache.c - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c - -$(obj)cpu_init_early.c: - @rm -f $(obj)cpu_init_early.c - ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c - -$(obj)spl_minimal.c: - @rm -f $(obj)spl_minimal.c - ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c - -$(obj)fsl_law.c: - @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c - -$(obj)law.c: - @rm -f $(obj)law.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c - -$(obj)nand_boot_fsl_ifc.c: - @rm -f $(obj)nand_boot_fsl_ifc.c - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_ifc.c \ - $(obj)nand_boot_fsl_ifc.c - -$(obj)ns16550.c: - @rm -f $(obj)ns16550.c - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c - -$(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S - -$(obj)fixed_ivor.S: - @rm -f $(obj)fixed_ivor.S - ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S - -$(obj)start.S: $(obj)fixed_ivor.S - @rm -f $(obj)start.S - ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S - -$(obj)ticks.S: - @rm -f $(obj)ticks.S - ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S - -$(obj)tlb.c: - @rm -f $(obj)tlb.c - ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c - -$(obj)tlb_table.c: - @rm -f $(obj)tlb_table.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/nand_boot_fsl_ifc.c b/nand_spl/nand_boot_fsl_ifc.c deleted file mode 100644 index 44972c5..0000000 --- a/nand_spl/nand_boot_fsl_ifc.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * NAND boot for FSL Integrated Flash Controller, NAND Flash Control Machine - * - * Copyright 2011 Freescale Semiconductor, Inc. - * Author: Dipen Dudhat <dipen.dudhat(a)freescale.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/fsl_ifc.h> -#include <linux/mtd/nand.h> - -static inline int is_blank(uchar *addr, int page_size) -{ - int i; - - for (i = 0; i < page_size; i++) { - if (__raw_readb(&addr[i]) != 0xff) - return 0; - } - - /* - * For the SPL, don't worry about uncorrectable errors - * where the main area is all FFs but shouldn't be. - */ - return 1; -} - -/* returns nonzero if entire page is blank */ -static inline int check_read_ecc(uchar *buf, u32 *eccstat, - unsigned int bufnum, int page_size) -{ - u32 reg = eccstat[bufnum / 4]; - int errors = (reg >> ((3 - bufnum % 4) * 8)) & 15; - - if (errors == 15) { /* uncorrectable */ - /* Blank pages fail hw ECC checks */ - if (is_blank(buf, page_size)) - return 1; - - puts("ecc error\n"); - for (;;) - ; - } - - return 0; -} - -static inline void nand_wait(uchar *buf, int bufnum, int page_size) -{ - struct fsl_ifc *ifc = IFC_BASE_ADDR; - u32 status; - u32 eccstat[4]; - int bufperpage = page_size / 512; - int bufnum_end, i; - - bufnum *= bufperpage; - bufnum_end = bufnum + bufperpage - 1; - - do { - status = in_be32(&ifc->ifc_nand.nand_evter_stat); - } while (!(status & IFC_NAND_EVTER_STAT_OPC)); - - if (status & IFC_NAND_EVTER_STAT_FTOER) { - puts("flash time out error\n"); - for (;;) - ; - } - - for (i = bufnum / 4; i <= bufnum_end / 4; i++) - eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); - - for (i = bufnum; i <= bufnum_end; i++) { - if (check_read_ecc(buf, eccstat, i, page_size)) - break; - } - - out_be32(&ifc->ifc_nand.nand_evter_stat, status); -} - -static inline int bad_block(uchar *marker, int port_size) -{ - if (port_size == 8) - return __raw_readb(marker) != 0xff; - else - return __raw_readw((u16 *)marker) != 0xffff; -} - -static void nand_load(unsigned int offs, int uboot_size, uchar *dst) -{ - struct fsl_ifc *ifc = IFC_BASE_ADDR; - uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; - int page_size; - int port_size; - int pages_per_blk; - int blk_size; - int bad_marker = 0; - int bufnum_mask, bufnum; - - int csor, cspr; - int pos = 0; - int j = 0; - - int sram_addr; - int pg_no; - - /* Get NAND Flash configuration */ - csor = CONFIG_SYS_NAND_CSOR; - cspr = CONFIG_SYS_NAND_CSPR; - - if (!(csor & CSOR_NAND_ECC_DEC_EN)) { - /* soft ECC in SPL is unimplemented */ - puts("WARNING: soft ECC not checked in SPL\n"); - } else { - u32 hwcsor; - - /* make sure board is configured with ECC on boot */ - hwcsor = in_be32(&ifc->csor_cs[0].csor); - if (!(hwcsor & CSOR_NAND_ECC_DEC_EN)) - puts("WARNING: ECC not checked in SPL, " - "check board cfg\n"); - } - - port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8; - - if (csor & CSOR_NAND_PGS_4K) { - page_size = 4096; - bufnum_mask = 1; - } else if (csor & CSOR_NAND_PGS_2K) { - page_size = 2048; - bufnum_mask = 3; - } else { - page_size = 512; - bufnum_mask = 15; - - if (port_size == 8) - bad_marker = 5; - } - - pages_per_blk = - 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT); - - blk_size = pages_per_blk * page_size; - - /* Open Full SRAM mapping for spare are access */ - out_be32(&ifc->ifc_nand.ncfgr, 0x0); - - /* Clear Boot events */ - out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff); - - /* Program FIR/FCR for Large/Small page */ - if (page_size > 512) { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); - - out_be32(&ifc->ifc_nand.nand_fcr0, - (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); - } else { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); - - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); - } - - /* Program FBCR = 0 for full page read */ - out_be32(&ifc->ifc_nand.nand_fbcr, 0); - - /* Read and copy u-boot on SDRAM from NAND device, In parallel - * check for Bad block if found skip it and read continue to - * next Block - */ - while (pos < uboot_size) { - int i = 0; - do { - pg_no = offs / page_size; - bufnum = pg_no & bufnum_mask; - sram_addr = bufnum * page_size * 2; - - out_be32(&ifc->ifc_nand.row0, pg_no); - out_be32(&ifc->ifc_nand.col0, 0); - /* start read */ - out_be32(&ifc->ifc_nand.nandseq_strt, - IFC_NAND_SEQ_STRT_FIR_STRT); - - /* wait for read to complete */ - nand_wait(&buf[sram_addr], bufnum, page_size); - - /* - * If either of the first two pages are marked bad, - * continue to the next block. - */ - if (i++ < 2 && - bad_block(&buf[sram_addr + page_size + bad_marker], - port_size)) { - puts("skipping\n"); - offs = (offs + blk_size) & ~(blk_size - 1); - pos &= ~(blk_size - 1); - break; - } - - for (j = 0; j < page_size; j++) - dst[pos + j] = __raw_readb(&buf[sram_addr + j]); - - pos += page_size; - offs += page_size; - } while ((offs & (blk_size - 1)) && (pos < uboot_size)); - } -} - -/* - * Main entrypoint for NAND Boot. It's necessary that SDRAM is already - * configured and available since this code loads the main U-boot image - * from NAND into SDRAM and starts from there. - */ -void nand_boot(void) -{ - __attribute__((noreturn)) void (*uboot)(void); - - /* - * Load U-Boot image from NAND into RAM - */ - nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, - (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); - -#ifdef CONFIG_NAND_ENV_DST - nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_NAND_ENV_DST); - -#ifdef CONFIG_ENV_OFFSET_REDUND - nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, - (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); -#endif -#endif - - /* - * Jump to U-Boot image - */ - /* - * Clean d-cache and invalidate i-cache, to - * make sure that no stale data is executed. - */ - flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); - uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; - uboot(); -} -- 1.7.9.5

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[U-Boot] [v2] new SPL support for IFC based Feescale platforms
by Prabhakar Kushwaha 22 Mar '13

22 Mar '13

This patch series ports existing Freescale's IFC based platforms/boards to new SPL based architecture. It is done to support NAND boot. It contains following patches: 1. powerpc/mpc85xx:No NOR boot,do not compile IFC errata A003399 2. powerpc/mpc85xx: new SPL support for IFC NAND 3. board/p1010rdb:Add NAND boot support using new SPL format 4. board/bsc9131rdb:Add NAND boot support using new SPL format 5. board/bsc9132qds:Add NAND boot support using new SPL format

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Re: [U-Boot] [PATCH 1/4 v7] Exynos: Add hardware accelerated SHA256 and SHA1
by Akshay Saraswat 22 Mar '13

22 Mar '13

Hi Kim, >On Thu, 21 Mar 2013 03:12:54 -0400 >Akshay Saraswat <akshay.s(a)samsung.com> wrote: > >> >On Mon, 18 Mar 2013 02:06:15 -0400 >> >Akshay Saraswat <akshay.s(a)samsung.com> wrote: >> > >> >> + while ((readl(&ace_sha_reg->hash_status) & ACE_HASH_MSGDONE_MASK) == >> >> + ACE_HASH_MSGDONE_OFF) { >> >> + /* >> >> + * PRNG error bit goes HIGH if a PRNG request occurs without >> >> + * a complete seed setup. We are using this bit to check h/w >> >> + * because proper setup is not expected in that case. >> >> + */ >> >> + if ((readl(&ace_sha_reg->hash_status) >> >> + & ACE_HASH_PRNGERROR_MASK) == ACE_HASH_PRNGERROR_ON) >> >> + break; >> >> + } >> > >> >so we have: >> > >> >whilst (not_done) >> > if (PRNGERROR_ON) >> > break; >> > >> >...and then success-assuming code flow continues after this. What >> >value is this check for PRNGERROR_ON, if the code isn't going to do >> >anything differently? And what does the status of the RNG have to >> >do with keyless hashing? It sounds like a check for proper >> >initialization (RNG got seeded) is in order here, but only if it's >> >required for the given hash operations (I doubt it, but the h/w >> >might be fussy). >> >> PRNG ERROR means setup was not proper which should be the case >> when h/w is faulty because driver does everything in order. > >The comment above says: > >"PRNG error bit goes HIGH if a PRNG request occurs without >a complete seed setup" > >But a SHA request isn't a PRNG request. The h/w shouldn't need the >PRNG at all to perform a simple SHA. > >If this is a general initialization/"setup" check, then do it then. >If not, can you do it immediately prior to the wait-for-done after >the "setup"? A PRNG error shouldn't be going off in the middle of >the wait-for-done loop for a SHA. > >> Earlier break was happening which was not correct so changing it to >> "return -EBUSY" which means code flow should not be the same as >> the one being successfull. > >-EBUSY? that means the h/w was busy, and carries a "try again" >implication (much like -EAGAIN) - I doubt that's what's intended >here. > >What happened to reverting to s/w, btw? > What has to be done: Step-1: Data input (DMA Mode). Configure the DMA unit to transfer N bytes of data. Step-2: Poll the status register until [6] == 1; OR When MSG_DONE_IRQ is asserted, execute further code. What is being done right now: No support for interrupt handling in u-boot, hence, while loop. To be on the safer side wanted to keep a check for h/w malfunction which must not happen. We used timeout earlier, but as per the discussion timeout has to be related to frequency. The PRNG IP is based on the SHA-1 algorithm for generating the random numbers. Hence, I found it inapt but an alternative to timeout for h/w fault detection. Other than these two ways there is no way for h/w fault detection in while loop. Shall I drop the idea of h/w fault detection ? About s/w fallback: I think the code calling h/w acceleration for sha should do that, because there may be some situations when developers may need not to do encryption at all instead of doing it with s/w. It's just a driver for h/w acceleration, in my opinion, it should do it's job nothing more than that. If we fallback to s/w, then it might mislead developers in few scenarios. Please suggest if this is correct or not and also what needs to be done. Thanks & Regards, Akshay Saraswat

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Re: [U-Boot] [PATCH 1/4 v7] Exynos: Add hardware accelerated SHA256 and SHA1
by Akshay Saraswat 22 Mar '13

22 Mar '13

Hi Kim, >On Mon, 18 Mar 2013 02:06:15 -0400 >Akshay Saraswat <akshay.s(a)samsung.com> wrote: > >> SHA-256 and SHA-1 accelerated using ACE hardware. >> >> Signed-off-by: ARUN MANKUZHI <arun.m(a)samsung.com> >> Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> >> Acked-by: Simon Glass <sjg(a)chromium.org> >> --- >> +++ b/arch/arm/include/asm/arch-exynos/ace_sha.h > >ace_sha.h belongs in drivers/crypto/ > >> +#define ACE_FC_SELBC_AES (0 << 2) /* AES */ >> +#define ACE_FC_SELBC_DES (1 << 2) /* DES */ > >nit: comments seem a bit redundant Few comments look same but they differ. For example: "Feed control - BTDMA control" and "Feed control - BRDMA control" > >> +#define ACE_FC_BRDMACARPROT_OFS (2) >> +#define ACE_FC_BRDMACARCACHE_OFS (5) >> +#define ACE_FC_BTDMACAWPROT_OFS (2) >> +#define ACE_FC_BTDMACAWCACHE_OFS (5) >> +#define ACE_FC_HRDMACARPROT_OFS (2) >> +#define ACE_FC_HRDMACARCACHE_OFS (5) >> +#define ACE_FC_SRAMOFFSET_MASK (0xfff) > >no parens. > >> +/** >> + * Computes hash value of input pbuf using ACE >> + * >> + * @param in_addr A pointer to the input buffer >> + * @param bufleni Byte length of input buffer >> + * @param out_addr A pointer to the output buffer. When complete >> + * 32 bytes are copied to pout[0]...pout[31]. Thus, a user >> + * should allocate at least 32 bytes at pOut in advance. >> + * @param hash_type SHA1 or SHA256 >> + * >> + * @return 0 on Success, -1 on Failure (Timeout) >... >> + /* Check if status changes within given time limit */ > >leftovers from timeout implementation? > >> + while ((readl(&ace_sha_reg->hash_status) & ACE_HASH_MSGDONE_MASK) == >> + ACE_HASH_MSGDONE_OFF) { >> + /* >> + * PRNG error bit goes HIGH if a PRNG request occurs without >> + * a complete seed setup. We are using this bit to check h/w >> + * because proper setup is not expected in that case. >> + */ >> + if ((readl(&ace_sha_reg->hash_status) >> + & ACE_HASH_PRNGERROR_MASK) == ACE_HASH_PRNGERROR_ON) >> + break; >> + } > >so we have: > >whilst (not_done) > if (PRNGERROR_ON) > break; > >...and then success-assuming code flow continues after this. What >value is this check for PRNGERROR_ON, if the code isn't going to do >anything differently? And what does the status of the RNG have to >do with keyless hashing? It sounds like a check for proper >initialization (RNG got seeded) is in order here, but only if it's >required for the given hash operations (I doubt it, but the h/w >might be fussy). > >Kim > PRNG ERROR means setup was not proper which should be the case when h/w is faulty because driver does everything in order. Earlier break was happening which was not correct so changing it to "return -EBUSY" which means code flow should not be the same as the one being successfull. Regards, Akshay Saraswat

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[U-Boot] [PATCH 1/1 v3] console: USB: KBD: Fix incorrect autoboot timeout
by Jim Lin 21 Mar '13

21 Mar '13

Autoboot timeout defined by CONFIG_BOOTDELAY will not be accurate if CONFIG_USB_KEYBOARD and CONFIG_SYS_USB_EVENT_POLL are defined in configuration file and when tstc() function for checking key pressed takes longer time than 10 ms (e.g., 50 ms) to finish. Signed-off-by: Jim Lin <jilin(a)nvidia.com> --- Changes in v2: - use do-while and get_timer to count timeout. Changes in v3: - revert original udelay(10000); for safety. common/main.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/common/main.c b/common/main.c index b145f85..dcd2a42 100644 --- a/common/main.c +++ b/common/main.c @@ -225,6 +225,7 @@ static inline int abortboot(int bootdelay) { int abort = 0; + unsigned long ts; #ifdef CONFIG_MENUPROMPT printf(CONFIG_MENUPROMPT); @@ -248,11 +249,10 @@ int abortboot(int bootdelay) #endif while ((bootdelay > 0) && (!abort)) { - int i; - --bootdelay; - /* delay 100 * 10ms */ - for (i=0; !abort && i<100; ++i) { + /* delay 1000 ms */ + ts = get_timer(0); + do { if (tstc()) { /* we got a key press */ abort = 1; /* don't auto boot */ bootdelay = 0; /* no more delay */ @@ -264,7 +264,7 @@ int abortboot(int bootdelay) break; } udelay(10000); - } + } while (!abort && get_timer(ts) < 1000); printf("\b\b\b%2d ", bootdelay); } -- 1.7.3 ----------------------------------------------------------------------------------- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. -----------------------------------------------------------------------------------

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[U-Boot] [PATCH] Fix bootdelay timeout calculation when SYS_HZ!=1000
by Stephen Warren 21 Mar '13

21 Mar '13

Commit b2f3e0e "console: USB: KBD: Fix incorrect autoboot timeout" re-wrote the bootdelay timeout loop. However, it hard-coded the value that get_delay() was expected to increment in one second, rather than calculating it based on CONFIG_SYS_HZ. On systems where SYS_HZ != 1000, this caused bootdelay timeout to be incorrect. Fix this. Cc: Jim Lin <jilin(a)nvidia.com> Signed-off-by: Stephen Warren <swarren(a)wwwdotorg.org> --- common/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/main.c b/common/main.c index a15f020..4f81ca9 100644 --- a/common/main.c +++ b/common/main.c @@ -264,7 +264,7 @@ int abortboot(int bootdelay) break; } udelay(10000); - } while (!abort && get_timer(ts) < 1000); + } while (!abort && get_timer(ts) < CONFIG_SYS_HZ); printf("\b\b\b%2d ", bootdelay); } -- 1.7.10.4

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[U-Boot] [PATCH v3 1/2] omap_hsmmc: Check wp and cd GPIO for valid GPIO first
by Tom Rini 21 Mar '13

21 Mar '13

When we cannot check write protect or card change via GPIO (and have been passed -1 in omap_mmc_init), only try if gpio_is_valid is true. This prevents invalid GPIO messages from being seen on the console when doing MMC operations Signed-off-by: Tom Rini <trini(a)ti.com> --- Changes in v3: - Style comments from Nikita Kiryanov Changes in v2: - Use gpio_is_valid not just a check for >= 0 (Fabio Estevam) --- drivers/mmc/omap_hsmmc.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 67cfcc2..d599482 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -73,13 +73,21 @@ static int omap_mmc_setup_gpio_in(int gpio, const char *label) static int omap_mmc_getcd(struct mmc *mmc) { int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio; - return gpio_get_value(cd_gpio); + + if (gpio_is_valid(cd_gpio)) + return gpio_get_value(cd_gpio); + + return -1; } static int omap_mmc_getwp(struct mmc *mmc) { int wp_gpio = ((struct omap_hsmmc_data *)mmc->priv)->wp_gpio; - return gpio_get_value(wp_gpio); + + if (gpio_is_valid(wp_gpio)) + return gpio_get_value(wp_gpio); + + return -1; } #else static inline int omap_mmc_setup_gpio_in(int gpio, const char *label) -- 1.7.9.5

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[U-Boot] [[PATCH V2 1/1] console: Improve TFTP booting performance
by Jim Lin 21 Mar '13

21 Mar '13

TFTP booting is observed a little bit slow, especially when a USB keyboard is installed. The fix is to check whether Ctrl-C key is pressed every CONFIG_CTRLC_POLL_S second. Signed-off-by: Jim Lin <jilin(a)nvidia.com> --- Changes in V2: 1. Change configuration name from CONFIG_CTRLC_POLL_MS to CONFIG_CTRLC_POLL_S. 2. New code will be executed only when CONFIG_CTRLC_POLL_S is defined in configuration header file. 3. Add description in README.console. common/console.c | 16 ++++++++++++++++ doc/README.console | 10 ++++++++++ 2 files changed, 26 insertions(+), 0 deletions(-) diff --git a/common/console.c b/common/console.c index bf73178..b09e129 100644 --- a/common/console.c +++ b/common/console.c @@ -521,12 +521,28 @@ int vprintf(const char *fmt, va_list args) return i; } +#ifdef CONFIG_CTRLC_POLL_S +/* + * Process Ctrl-C every CONFIG_CTRLC_POLL_S second(s) to improve performance + * (like TFTP boot) when interlaced with other tasks like USB KB + * polling. + */ +static unsigned long ctrlc_ts = (CONFIG_CTRLC_POLL_S * CONFIG_SYS_HZ); +#endif + /* test if ctrl-c was pressed */ static int ctrlc_disabled = 0; /* see disable_ctrl() */ static int ctrlc_was_pressed = 0; int ctrlc(void) { if (!ctrlc_disabled && gd->have_console) { +#ifdef CONFIG_CTRLC_POLL_S + if (get_timer(ctrlc_ts) < (CONFIG_CTRLC_POLL_S + * CONFIG_SYS_HZ)) + return 0; + else + ctrlc_ts = get_timer(0); +#endif if (tstc()) { switch (getc()) { case 0x03: /* ^C - Control C */ diff --git a/doc/README.console b/doc/README.console index b353f9f..6b38b8c 100644 --- a/doc/README.console +++ b/doc/README.console @@ -116,3 +116,13 @@ CREDITS for other contact informations): - MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio(a)tin.it - GENIETV with AD7177 on a PAL TV (YCbYCr) - arsenio(a)tin.it + +Config Switches: +---------------- +CONFIG_CTRLC_POLL_S define a value to check whether Ctrl-C is pressed + every defined second(s). This is to improve TFTP + booting if USB KB is installed and polling is used. + For example: + Define the following in configuration header file + #define CONFIG_CTRLC_POLL_S 1 + for console to check Ctrl-C every second. -- 1.7.7

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[U-Boot] Booting zImage from UBOOT
by Ritu Sharma 21 Mar '13

21 Mar '13

I've been framing this mail for quite some time trying to sort all issues myself by googling for info. I learnt a lot in the process by doing it and verify it myself, using my openocd jtag and Samsung based mini2440 board. I read that uImage is nothing more than (64byte header + zImage). I've been studying decompression code so it suited me to tweak UBOOT code to boot zImage rather than writing my own bootcode. Just a small modification in do_bootm_linux function did the job: -- theKernel = (void (*)(int, int, uint))ep; ++ theKernel = (void (*)(int, int, uint))0x32000040; Here I load uImage at 0x32000000(through tftp), so zImage starts at 0x32000040. Kernel booted fine(bootm 0x32000000) but, I was bit sceptical whether my understanding that in effect I booted a zImage is correct or not. Reason for my scepticism is that I let UBOOT to decompress the kernel at required entry point, and same thing is done if I directly jump to offset 0x40 in uImage. Best Regards Ritu

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