February 2013 - U-Boot

[U-Boot] [PATCH 0/2] new IGEP board support
by Enric Balletbo i Serra 06 Feb '13

06 Feb '13

From: Enric Balletbo i Serra <eballetbo(a)iseebcn.com> Hi all, In our effort to mainline the IGEP device support here are two patches to add support to the IGEP COM PROTON board. The first patch is only a trivial patch that changes some IGEP boards names. The second is to add the new board. These patches applies on top of u-boot-ti repository as the following patch is required. OMAP3: use a single board file for IGEP devices commit 076be4528851126b56f2c1b84d07834297797f6c From Javier Martinez Canillas Best regards, Enric Balletbo i Serra (2): OMAP3: igep00x0: use official board names. OMAP3: igep00x0: Add new IGEP COM PROTON. MAINTAINERS | 1 + board/isee/igep00x0/igep00x0.c | 3 +++ board/isee/igep00x0/igep00x0.h | 7 +++++-- boards.cfg | 1 + 4 files changed, 10 insertions(+), 2 deletions(-) -- 1.7.10.4

4 6

[U-Boot] [PATCH v3 1/4] nand: mxc: Prepare to add support for i.MX5
by Benoît Thébaudeau 06 Feb '13

06 Feb '13

Add some abstraction to NFC defitnitions so that some parts of the current code can also be used for future i.MX5 code. Clean up a few things by the way. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau(a)advansee.com> --- Changes in v3: - Separate code reformatting from behavioral changes. Changes in v2: - Fix warning for unused tmp variable in board_nand_init() for NFC V1. drivers/mtd/nand/mxc_nand.c | 92 +++++++++++++++++++++--------------------- include/fsl_nfc.h | 72 ++++++++++++--------------------- nand_spl/nand_boot_fsl_nfc.c | 47 +++++++++++---------- 3 files changed, 97 insertions(+), 114 deletions(-) diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index d0ded48..045df49 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -150,7 +150,7 @@ static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size /* * This function polls the NANDFC to wait for the basic operation to - * complete by checking the INT bit of config2 register. + * complete by checking the INT bit. */ static void wait_op_done(struct mxc_nand_host *host, int max_retries, uint16_t param) @@ -158,10 +158,10 @@ static void wait_op_done(struct mxc_nand_host *host, int max_retries, uint32_t tmp; while (max_retries-- > 0) { - if (readw(&host->regs->config2) & NFC_INT) { - tmp = readw(&host->regs->config2); - tmp &= ~NFC_INT; - writew(tmp, &host->regs->config2); + tmp = readnfc(&host->regs->config2); + if (tmp & NFC_V1_V2_CONFIG2_INT) { + tmp &= ~NFC_V1_V2_CONFIG2_INT; + writenfc(tmp, &host->regs->config2); break; } udelay(1); @@ -180,8 +180,8 @@ static void send_cmd(struct mxc_nand_host *host, uint16_t cmd) { MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd); - writew(cmd, &host->regs->flash_cmd); - writew(NFC_CMD, &host->regs->config2); + writenfc(cmd, &host->regs->flash_cmd); + writenfc(NFC_CMD, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, cmd); @@ -196,8 +196,8 @@ static void send_addr(struct mxc_nand_host *host, uint16_t addr) { MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr); - writew(addr, &host->regs->flash_addr); - writew(NFC_ADDR, &host->regs->config2); + writenfc(addr, &host->regs->flash_addr); + writenfc(NFC_ADDR, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, addr); @@ -229,19 +229,19 @@ static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id, } } - writew(buf_id, &host->regs->buf_addr); + writenfc(buf_id, &host->regs->buf_addr); /* Configure spare or page+spare access */ if (!host->pagesize_2k) { - uint16_t config1 = readw(&host->regs->config1); + uint16_t config1 = readnfc(&host->regs->config1); if (spare_only) - config1 |= NFC_SP_EN; + config1 |= NFC_CONFIG1_SP_EN; else - config1 &= ~NFC_SP_EN; - writew(config1, &host->regs->config1); + config1 &= ~NFC_CONFIG1_SP_EN; + writenfc(config1, &host->regs->config1); } - writew(NFC_INPUT, &host->regs->config2); + writenfc(NFC_INPUT, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, spare_only); @@ -256,19 +256,19 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id, { MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only); - writew(buf_id, &host->regs->buf_addr); + writenfc(buf_id, &host->regs->buf_addr); /* Configure spare or page+spare access */ if (!host->pagesize_2k) { - uint32_t config1 = readw(&host->regs->config1); + uint32_t config1 = readnfc(&host->regs->config1); if (spare_only) - config1 |= NFC_SP_EN; + config1 |= NFC_CONFIG1_SP_EN; else - config1 &= ~NFC_SP_EN; - writew(config1, &host->regs->config1); + config1 &= ~NFC_CONFIG1_SP_EN; + writenfc(config1, &host->regs->config1); } - writew(NFC_OUTPUT, &host->regs->config2); + writenfc(NFC_OUTPUT, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, spare_only); @@ -296,14 +296,14 @@ static void send_read_id(struct mxc_nand_host *host) uint16_t tmp; /* NANDFC buffer 0 is used for device ID output */ - writew(0x0, &host->regs->buf_addr); + writenfc(0x0, &host->regs->buf_addr); /* Read ID into main buffer */ - tmp = readw(&host->regs->config1); - tmp &= ~NFC_SP_EN; - writew(tmp, &host->regs->config1); + tmp = readnfc(&host->regs->config1); + tmp &= ~NFC_CONFIG1_SP_EN; + writenfc(tmp, &host->regs->config1); - writew(NFC_ID, &host->regs->config2); + writenfc(NFC_ID, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, 0); @@ -323,14 +323,14 @@ static uint16_t get_dev_status(struct mxc_nand_host *host) /* store the main area1 first word, later do recovery */ store = readl(main_buf); /* NANDFC buffer 1 is used for device status */ - writew(1, &host->regs->buf_addr); + writenfc(1, &host->regs->buf_addr); /* Read status into main buffer */ - tmp = readw(&host->regs->config1); - tmp &= ~NFC_SP_EN; - writew(tmp, &host->regs->config1); + tmp = readnfc(&host->regs->config1); + tmp &= ~NFC_CONFIG1_SP_EN; + writenfc(tmp, &host->regs->config1); - writew(NFC_STATUS, &host->regs->config2); + writenfc(NFC_STATUS, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, 0); @@ -359,13 +359,13 @@ static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on) { struct nand_chip *nand_chip = mtd->priv; struct mxc_nand_host *host = nand_chip->priv; - uint16_t tmp = readw(&host->regs->config1); + uint16_t tmp = readnfc(&host->regs->config1); if (on) - tmp |= NFC_ECC_EN; + tmp |= NFC_V1_V2_CONFIG1_ECC_EN; else - tmp &= ~NFC_ECC_EN; - writew(tmp, &host->regs->config1); + tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN; + writenfc(tmp, &host->regs->config1); } #ifdef CONFIG_MXC_NAND_HWECC @@ -698,7 +698,7 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, * additional correction. 2-Bit errors cannot be corrected by * HW ECC, so we need to return failure */ - uint16_t ecc_status = readw(&host->regs->ecc_status_result); + uint16_t ecc_status = readnfc(&host->regs->ecc_status_result); if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { MTDDEBUG(MTD_DEBUG_LEVEL0, @@ -1241,24 +1241,24 @@ int board_nand_init(struct nand_chip *this) #endif #ifdef MXC_NFC_V2_1 - tmp = readw(&host->regs->config1); - tmp |= NFC_ONE_CYCLE; - tmp |= NFC_4_8N_ECC; - writew(tmp, &host->regs->config1); + tmp = readnfc(&host->regs->config1); + tmp |= NFC_V2_CONFIG1_ONE_CYCLE; + tmp |= NFC_V2_CONFIG1_ECC_MODE_4; + writenfc(tmp, &host->regs->config1); if (host->pagesize_2k) - writew(64/2, &host->regs->spare_area_size); + writenfc(64/2, &host->regs->spare_area_size); else - writew(16/2, &host->regs->spare_area_size); + writenfc(16/2, &host->regs->spare_area_size); #endif /* * preset operation * Unlock the internal RAM Buffer */ - writew(0x2, &host->regs->config); + writenfc(0x2, &host->regs->config); /* Blocks to be unlocked */ - writew(0x0, &host->regs->unlockstart_blkaddr); + writenfc(0x0, &host->regs->unlockstart_blkaddr); /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the * unlockend_blkaddr, but the magic 0x4000 does not always work * when writing more than some 32 megabytes (on 2k page nands) @@ -1270,10 +1270,10 @@ int board_nand_init(struct nand_chip *this) * This might be NAND chip specific and the i.MX31 datasheet is * extremely vague about the semantics of this register. */ - writew(0xFFFF, &host->regs->unlockend_blkaddr); + writenfc(0xFFFF, &host->regs->unlockend_blkaddr); /* Unlock Block Command for given address range */ - writew(0x4, &host->regs->wrprot); + writenfc(0x4, &host->regs->wrprot); return 0; } diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h index ff537b4..013e9e2 100644 --- a/include/fsl_nfc.h +++ b/include/fsl_nfc.h @@ -113,58 +113,38 @@ struct fsl_nfc_regs { #endif }; -/* - * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command - * operation - */ -#define NFC_CMD 0x1 +/* Set FCMD to 1, rest to 0 for Command operation */ +#define NFC_CMD 0x1 -/* - * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address - * operation - */ -#define NFC_ADDR 0x2 +/* Set FADD to 1, rest to 0 for Address operation */ +#define NFC_ADDR 0x2 -/* - * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input - * operation - */ -#define NFC_INPUT 0x4 +/* Set FDI to 1, rest to 0 for Input operation */ +#define NFC_INPUT 0x4 -/* - * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data - * Output operation - */ -#define NFC_OUTPUT 0x8 +/* Set FDO to 001, rest to 0 for Data Output operation */ +#define NFC_OUTPUT 0x8 -/* - * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID - * operation - */ -#define NFC_ID 0x10 +/* Set FDO to 010, rest to 0 for Read ID operation */ +#define NFC_ID 0x10 -/* - * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read - * Status operation - */ -#define NFC_STATUS 0x20 +/* Set FDO to 100, rest to 0 for Read Status operation */ +#define NFC_STATUS 0x20 -/* - * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status - * operation - */ -#define NFC_INT 0x8000 +#define NFC_CONFIG1_SP_EN (1 << 2) +#define NFC_CONFIG1_RST (1 << 6) +#define NFC_CONFIG1_CE (1 << 7) +#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) +#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) +#define NFC_V1_V2_CONFIG1_BIG (1 << 5) +#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) +#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) +#define NFC_V2_CONFIG1_FP_INT (1 << 11) -#ifdef MXC_NFC_V2_1 -#define NFC_4_8N_ECC (1 << 0) -#endif -#define NFC_SP_EN (1 << 2) -#define NFC_ECC_EN (1 << 3) -#define NFC_INT_MSK (1 << 4) -#define NFC_BIG (1 << 5) -#define NFC_RST (1 << 6) -#define NFC_CE (1 << 7) -#define NFC_ONE_CYCLE (1 << 8) -#define NFC_FP_INT (1 << 11) +#define NFC_V1_V2_CONFIG2_INT (1 << 15) + +#define operation config2 +#define readnfc readw +#define writenfc writew #endif /* __FSL_NFC_H */ diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c index a40c998..615e820 100644 --- a/nand_spl/nand_boot_fsl_nfc.c +++ b/nand_spl/nand_boot_fsl_nfc.c @@ -36,13 +36,13 @@ static void nfc_wait_ready(void) { uint32_t tmp; - while (!(readw(&nfc->config2) & NFC_INT)) + while (!(readnfc(&nfc->config2) & NFC_V1_V2_CONFIG2_INT)) ; /* Reset interrupt flag */ - tmp = readw(&nfc->config2); - tmp &= ~NFC_INT; - writew(tmp, &nfc->config2); + tmp = readnfc(&nfc->config2); + tmp &= ~NFC_V1_V2_CONFIG2_INT; + writenfc(tmp, &nfc->config2); } static void nfc_nand_init(void) @@ -51,43 +51,45 @@ static void nfc_nand_init(void) int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512; int config1; - writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size); + writenfc(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size); /* unlocking RAM Buff */ - writew(0x2, &nfc->config); + writenfc(0x2, &nfc->config); /* hardware ECC checking and correct */ - config1 = readw(&nfc->config1) | NFC_ECC_EN | NFC_INT_MSK | - NFC_ONE_CYCLE | NFC_FP_INT; + config1 = readnfc(&nfc->config1) | NFC_V1_V2_CONFIG1_ECC_EN | + NFC_V1_V2_CONFIG1_INT_MSK | NFC_V2_CONFIG1_ONE_CYCLE | + NFC_V2_CONFIG1_FP_INT; /* * if spare size is larger that 16 bytes per 512 byte hunk * then use 8 symbol correction instead of 4 */ if (CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16) - config1 &= ~NFC_4_8N_ECC; + config1 &= ~NFC_V2_CONFIG1_ECC_MODE_4; else - config1 |= NFC_4_8N_ECC; - writew(config1, &nfc->config1); + config1 |= NFC_V2_CONFIG1_ECC_MODE_4; + writenfc(config1, &nfc->config1); #elif defined(MXC_NFC_V1) /* unlocking RAM Buff */ - writew(0x2, &nfc->config); + writenfc(0x2, &nfc->config); /* hardware ECC checking and correct */ - writew(NFC_ECC_EN | NFC_INT_MSK, &nfc->config1); + writenfc(NFC_V1_V2_CONFIG1_ECC_EN | NFC_V1_V2_CONFIG1_INT_MSK, + &nfc->config1); #endif } static void nfc_nand_command(unsigned short command) { - writew(command, &nfc->flash_cmd); - writew(NFC_CMD, &nfc->config2); + writenfc(command, &nfc->flash_cmd); + writenfc(NFC_CMD, &nfc->operation); nfc_wait_ready(); } static void nfc_nand_address(unsigned short address) { - writew(address, &nfc->flash_addr); - writew(NFC_ADDR, &nfc->config2); + writenfc(address, &nfc->flash_addr); + writenfc(NFC_ADDR, &nfc->operation); nfc_wait_ready(); } @@ -121,8 +123,8 @@ static void nfc_nand_data_output(void) int i; #endif - writew(0, &nfc->buf_addr); - writew(NFC_OUTPUT, &nfc->config2); + writenfc(0, &nfc->buf_addr); + writenfc(NFC_OUTPUT, &nfc->operation); nfc_wait_ready(); #ifdef NAND_MXC_2K_MULTI_CYCLE /* @@ -130,8 +132,8 @@ static void nfc_nand_data_output(void) * for pages larger than 512 bytes. */ for (i = 1; i < CONFIG_SYS_NAND_PAGE_SIZE / 512; i++) { - writew(i, &nfc->buf_addr); - writew(NFC_OUTPUT, &nfc->config2); + writenfc(i, &nfc->buf_addr); + writenfc(NFC_OUTPUT, &nfc->operation); nfc_wait_ready(); } #endif @@ -160,7 +162,8 @@ static int nfc_nand_check_ecc(void) static void nfc_nand_read_page(unsigned int page_address) { - writew(0, &nfc->buf_addr); /* read in first 0 buffer */ + /* read in first 0 buffer */ + writenfc(0, &nfc->buf_addr); nfc_nand_command(NAND_CMD_READ0); nfc_nand_page_address(page_address); -- 1.7.10.4

2 4

[U-Boot] [PATCH V2 0/5] ARM: OMAP5: Add support for OMAP543x ES2.0 Socs
by R Sricharan 06 Feb '13

06 Feb '13

ES2.0 is the latest silicon revision for OMAP543X socs. The SOC supports enhanced opps for MPU (up to 1.5GHz). This series essentially adds the support for both 5430 and 5432 versions. This is on top of the below U-Boot cleanup series. http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/152834 Lokesh Vutla (2): ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup R Sricharan (3): ARM: OMAP5: Add silicon id support for ES2.0 revision. ARM: OMAP5: clock: Add the prcm register changes required for ES2.0 ARM: OMAP5: clocks: Add OPP settings required for OMAP543X ES2.0 soc arch/arm/cpu/armv7/omap-common/clocks-common.c | 4 + arch/arm/cpu/armv7/omap-common/hwinit-common.c | 6 + arch/arm/cpu/armv7/omap4/hw_data.c | 142 ++++++------ arch/arm/cpu/armv7/omap5/hw_data.c | 261 ++++++++++++++------- arch/arm/cpu/armv7/omap5/hwinit.c | 129 ++++++++++- arch/arm/cpu/armv7/omap5/prcm-regs.c | 286 ++++++++++++++++++++++++ arch/arm/cpu/armv7/omap5/sdram.c | 75 ++++++- arch/arm/include/asm/arch-omap5/clocks.h | 8 + arch/arm/include/asm/arch-omap5/omap.h | 27 +++ arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + arch/arm/include/asm/armv7.h | 1 + arch/arm/include/asm/emif.h | 1 + arch/arm/include/asm/omap_common.h | 14 +- 13 files changed, 794 insertions(+), 161 deletions(-) -- 1.7.9.5

3 18

[U-Boot] [PATCH resend] armv7/ltimer: Add support for local timer on armv7 cpus
by Vipin Kumar 06 Feb '13

06 Feb '13

Certain ARMV7 cpus eg. CortexA9 contains a local and a global timer within the CPU core itself. This patch adds generic support for local timer. Signed-off-by: Vipin Kumar <vipin.kumar(a)st.com> --- arch/arm/cpu/armv7/Makefile | 11 ++- arch/arm/cpu/armv7/ca9_ltimer.c | 152 ++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/ca9_ltimer.h | 40 ++++++++++ 3 files changed, 199 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv7/ca9_ltimer.c create mode 100644 arch/arm/include/asm/ca9_ltimer.h diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 4fdbee4..3ef01f6 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -27,15 +27,18 @@ LIB = $(obj)lib$(CPU).o START := start.o -COBJS += cache_v7.o +COBJS-y += cache_v7.o -COBJS += cpu.o -COBJS += syslib.o +COBJS-y += cpu.o +COBJS-y += syslib.o +COBJS-$(CONFIG_ARMV7_CA9LTIMER) += ca9_ltimer.o ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),) -SOBJS += lowlevel_init.o +SOBJS-y += lowlevel_init.o endif +COBJS := $(sort $(COBJS-y)) +SOBJS := $(sort $(SOBJS-y)) SRCS := $(START:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) START := $(addprefix $(obj),$(START)) diff --git a/arch/arm/cpu/armv7/ca9_ltimer.c b/arch/arm/cpu/armv7/ca9_ltimer.c new file mode 100644 index 0000000..cbf1552 --- /dev/null +++ b/arch/arm/cpu/armv7/ca9_ltimer.c @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2012 + * Vipin Kumar, ST Micoelectronics, vipin.kumar(a)st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/ca9_ltimer.h> +#include <asm/arch/hardware.h> + +#define READ_TIMER() readl(&ca9_timer_p->count) + +static struct ca9_timer_regs *const ca9_timer_p = + (struct ca9_timer_regs *)CONFIG_ARMV7_LTIMER_BASE; + +DECLARE_GLOBAL_DATA_PTR; + +#define timestamp gd->tbl +#define lastdec gd->lastinc +#define tickshz gd->timer_rate_hz +#define ticksper10usec gd->tbu + +int timer_init(void) +{ + u32 prescaler, timertickshz; + /* + * Genrally, CortexA9 MPUs are operating from 500MHz to 1500MHz which + * means that CA9 local timer clock would be in the range of 250 MHz to + * 750MHz. + * Try to find a prescaler which can perfectly divide the local timer + * clock. Take prescaler as 200 if nothing is found + */ + for (prescaler = 255; prescaler > 1; prescaler--) { + if (CONFIG_ARMV7_LTMR_CLK == + (CONFIG_ARMV7_LTMR_CLK / prescaler) * prescaler) + break; + } + + if (prescaler == 1) + prescaler = 200; + timertickshz = CONFIG_ARMV7_LTMR_CLK / prescaler; + ticksper10usec = timertickshz / (100 * 1000); + tickshz = timertickshz / CONFIG_SYS_HZ; + + /* disable timers */ + writel(((prescaler - 1) << 8) | AUTO_RELOAD, &ca9_timer_p->control); + + /* load value for free running */ + writel(FREE_RUNNING, &ca9_timer_p->load); + + /* auto reload, start timer */ + setbits_le32(&ca9_timer_p->control, TIMER_ENABLE); + + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return (get_timer_masked() / tickshz) - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +void __udelay(unsigned long usec) +{ + ulong tmo; + ulong start = get_timer_masked(); + ulong rndoff; + + rndoff = (usec % 10) ? 1 : 0; + tmo = ((usec / 10) + rndoff) * ticksper10usec; + + while ((ulong) (get_timer_masked() - start) < tmo); +} + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER(); + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + ulong now = READ_TIMER(); + + if (now <= lastdec) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + FREE_RUNNING - now; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked(unsigned long usec) +{ + return udelay(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/arch/arm/include/asm/ca9_ltimer.h b/arch/arm/include/asm/ca9_ltimer.h new file mode 100644 index 0000000..8833853 --- /dev/null +++ b/arch/arm/include/asm/ca9_ltimer.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2012 + * Vipin Kumar, ST Micoelectronics, vipin.kumar(a)st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ARCH_ARM_CA9TIMER_H +#define __ARCH_ARM_CA9TIMER_H + +struct ca9_timer_regs { + u32 load; + u32 count; + u32 control; +}; + +/* control related definitions */ +#define AUTO_RELOAD (1 << 1) +#define TIMER_ENABLE (1 << 0) + +/* load related definitions */ +#define FREE_RUNNING (0xFFFFFFFF) + +#endif -- 1.8.0

5 11

[U-Boot] [PATCH 0/3 V2] EXYNOS5: Add GPIO numbering feature
by Rajeshwari Shinde 06 Feb '13

06 Feb '13

This patchset adds GPIO numbering feature where pinmux setting can be done just by sending the pin number which is defined as a enum in asm/gpio.h. Changes in V2: - Enabled CMD_GPIO as suggested by Simon Glass and supported same for EXYNOS5 Rajeshwari Shinde (3): S5P: GPIO: Add generic pin numbering API's EXYNOS5: Add gpio pin numbering feature EXYNOS5: GPIO: Enable GPIO Command for EXYNOS5 arch/arm/cpu/armv7/exynos/pinmux.c | 148 ++++------ arch/arm/include/asm/arch-exynos/gpio.h | 448 ++++++++++++++++++++++++++++++- common/cmd_gpio.c | 6 +- drivers/gpio/s5p_gpio.c | 18 ++ include/configs/exynos5250-dt.h | 1 + 5 files changed, 523 insertions(+), 98 deletions(-) -- 1.7.4.4

3 10

[U-Boot] Please Ignore: email client test
by Gray Remlin 06 Feb '13

06 Feb '13

You will NOT wrap long lines under any circumstances unless I tell you to, no matter what the line length is, because I know my intent better than you. Here are tabs because I want tabs. When I want spaces I will used them, and expect them to be where I put them. Finally, if you encapsulate this as a multipart\mime, I will rip out your bytes and nibble them into little bits, you dumb email client.

2 1

[U-Boot] [PATCH 0/5] Create an API for safely accessing BMP header fields
by Nikita Kiryanov 05 Feb '13

05 Feb '13

When configuring U-Boot to display a splash image, the user is free to designate whatever address they see fit as the in-memory location of BMP file. Unfortunately, this makes it easy to place the BMP header fields in unaligned addresses, which will cause a data abort on architectures which can't handle unaligned memory accesses. What's worse, addresses which are supposed to be issue free (32 bit aligned addresses) actually don't work because of the structure of the BMP header file (the header starts with 2 chars, followed by __u32 fields. The two chars offset the 32 bit fields away from proper alignment). As a result, it is very easy to brick the board that U-Boot runs on with certain architectures. Once a bad address for splash image is selected and the board restarted, U-Boot never reaches command line, and yet the only way to prevent the data aborts from happening is to clear or change the environment variable splashimage. While it is possible to fix the problem by compiling all relevant files with $(PLATFORM_NO_UNALIGNED), it is possible to handle it with finer granularity by creating an API for header accesses, and compiling only that with $(PLATFORM_NO_UNALIGNED). This patchset creates such an API, and makes use of it wherever an in-memory BMP header is probed for data. Further information can be found in this discussion: http://lists.denx.de/pipermail/u-boot/2013-January/144666.html Nikita Kiryanov (5): Add bmp_layout module for accessing BMP header data lcd: use bmp_layout API cmd_bmp: use bmp_layout API video/cfb_console: use bmp_layout API video/bus_vcxk: use bmp_layout API common/Makefile | 8 ++++ common/bmp_layout.c | 96 +++++++++++++++++++++++++++++++++++++++++++ common/cmd_bmp.c | 17 ++++---- common/lcd.c | 21 +++++----- drivers/video/bus_vcxk.c | 14 +++---- drivers/video/cfb_console.c | 22 +++++----- include/bmp_layout.h | 15 +++++++ 7 files changed, 152 insertions(+), 41 deletions(-) create mode 100644 common/bmp_layout.c -- 1.7.10.4

6 31

[U-Boot] [PATCH 0/9 v8] Add TMU support for Exynos5250 based SMDK5250
by Akshay Saraswat 05 Feb '13

05 Feb '13

This patch series adds support for TMU driver using device tree for Exynos5250 based SMDK5250 board. COMPILE=("MAKEALL -a arm") No errors or warnings related to dtt or tmu. TEST=Tested over smdk5250. Changes since v7: - Patch-1: None. - Patch-2: None. - Patch-3: None. - Patch-4: None. - Patch-5: None. - Patch-6: Few changes to avoid compilation errors and warnings. - Patch-7: None. - Patch-8: None. - Patch-9: Added 'Acked-by'. Akshay Saraswat (9): EXYNOS5: TMU: Add driver for Thermal Management Unit EXYNOS5: Implement board_poweroff for Thermal Management Unit EXYNOS5: FDT: Add TMU device node values EXYNOS5: TMU: Add TMU init and status check EXYNOS5: Config: Enable support for Exynos TMU driver TMU: Add TMU support in dtt command EXYNOS5: Config: Enable dtt command for TMU EXYNOS5: TMU: Add hardware tripping EXYNOS5: FDT: Add a H/W-trip member to TMU node arch/arm/cpu/armv7/exynos/power.c | 25 ++ arch/arm/dts/exynos5250.dtsi | 5 + arch/arm/include/asm/arch-exynos/exynos-tmu.h | 58 +++++ arch/arm/include/asm/arch-exynos/power.h | 6 + board/samsung/dts/exynos5250-smdk5250.dts | 13 + board/samsung/smdk5250/smdk5250.c | 35 +++ common/cmd_dtt.c | 63 +++-- doc/device-tree-bindings/exynos/tmu.txt | 49 ++++ drivers/power/Makefile | 1 + drivers/power/exynos-tmu.c | 317 +++++++++++++++++++++++++ include/configs/exynos5250-dt.h | 5 + include/dtt.h | 2 +- include/fdtdec.h | 1 + include/tmu.h | 46 ++++ lib/fdtdec.c | 1 + 15 files changed, 600 insertions(+), 27 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/exynos-tmu.h create mode 100644 doc/device-tree-bindings/exynos/tmu.txt create mode 100644 drivers/power/exynos-tmu.c create mode 100644 include/tmu.h -- 1.7.9.5

2 10

[U-Boot] [PATCH 0/5] am335x_evm: support for booting via USB
by Ilya Yanok 05 Feb '13

05 Feb '13

These series add support for booting via USB on TI AM335X based boards. Tested on BeagleBone. Ilya Yanok (5): spl: support for booting via usbeth am33xx: support for booting via usbeth am335x_evm: enable support for booting via USB spl: add possibility to force boot device am335x_evm: add new config with forced USB booting arch/arm/cpu/armv7/omap-common/boot-common.c | 3 +++ arch/arm/include/asm/arch-am33xx/spl.h | 1 + board/ti/am335x/board.c | 3 ++- boards.cfg | 1 + common/spl/spl.c | 9 +++++++++ include/configs/am335x_evm.h | 8 ++++++++ spl/Makefile | 2 ++ 7 files changed, 26 insertions(+), 1 deletion(-) -- 1.8.0.2

2 12

[U-Boot] "#define"d CONFIG_CMD_* variables that are never used -- short list
by Robert P. J. Day 05 Feb '13

05 Feb '13

self-explanatory -- variables that are explicitly defined but are apparently never used anywhere in the code. amusingly, i had to open up the matching when i noticed the misspelling at the end. if all of these are superfluous, i can submit a single patch to remove it all. i will shut up and go back to work now, but if there's any particular scanning you want, i probably have a script that will do the trick. ===== CONFIG_CMD_CLEAR include/configs/nokia_rx51.h:#define CONFIG_CMD_CLEAR /* ANSI terminal clear screen command */ ===== CONFIG_CMD_DEFAULTENV_VARS include/configs/km/keymile-common.h:#define CONFIG_CMD_DEFAULTENV_VARS ===== CONFIG_CMD_DFL include/configs/armadillo-800eva.h:#define CONFIG_CMD_DFL include/configs/sh7752evb.h:#define CONFIG_CMD_DFL ===== CONFIG_CMD_MEMTEST include/configs/ppmc8260.h:#define CONFIG_CMD_MEMTEST ===== CONFIG_CMD_STORAGE include/configs/cam_enc_4xx.h:#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */ include/configs/da830evm.h:#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */ include/configs/davinci_dvevm.h:#define CONFIG_CMD_STORAGE include/configs/davinci_dm365evm.h:#define CONFIG_CMD_STORAGE /* include support for usb */ include/configs/davinci_dm365evm.h:#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */ ===== CONGIG_CMD_STORAGE include/configs/am3517_evm.h:#define CONGIG_CMD_STORAGE include/configs/am3517_crane.h:#define CONGIG_CMD_STORAGE include/configs/omap3_evm_common.h:#define CONGIG_CMD_STORAGE rday

1 0