February 2013 - U-Boot

[U-Boot] PPC405 with XMD boot
by Frank Lombardo 07 Feb '13

07 Feb '13

Rommel, I am using your recently posted patch to boot my custom Virtex4 board with XMD. Execution gets stuck in the NS16550_init() function. It gets stuck at this line: #if (!defined(CONFIG_SYS_NS16550_BROKEN_TEMT)) while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT)) ; #endif If I define CONFIG_SYS_NS16550_BROKEN_TEMT, it gets stuck in the while loop in NS16550_putc: while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0) ; serial_out(c, &com_port->thr); >From the GDB output, I can see it is using the correct address for the the serial port (0x84000000) (gdb) target remote localhost:1234 Remote debugging using localhost:1234 NS16550_putc (com_port=0x84000000, c=13 '\r') at ns16550.c:91 91 while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0) (gdb) In your opinion, is your patch providing everything that I need to boot with XMD? Can you suggest what I might be doing wrong? Thanks for any insight you may have, Frank

4 5

[U-Boot] [PATCH] arm: fix bug on relocation address
by Luca Ellero 07 Feb '13

07 Feb '13

If (N. SDRAM banks > 1) and they are not contiguous, don't relocate u-boot at (CONFIG_SYS_SDRAM_BASE + gd->ram_size), which is a bug. Instead use the end of 2nd bank (even if there are more than 2 banks) Signed-off-by: Luca Ellero <lroluk(a)gmail.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Heiko Schocher <hs(a)denx.de> --- On ARM architectures there is a bug getting top of SDRAM (where u-boot will be relocated). Top of SDRAM will always be: CONFIG_SYS_SDRAM_BASE + gd->ram_size anyway this can be wrong since SDRAM can be composed by more that one bank in not-contiguous address space. (CONFIG_SYS_SDRAM_BASE + gd->ram_size) can land to not existent SDRAM addresses and can be very dangerous since it can potentially corrupt real SDRAM (in most cases SDRAM is aliased so writing to some not-existent address can write to real address). Some arch use more than 2 banks but implementing all macros checks to PHYS_SDRAM_* leads to very ugly code, so I think using 2nd bank is good and does not generates bloated code arch/arm/lib/board.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 9f861cc..98634ab 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -333,7 +333,19 @@ void board_init_f(ulong bootflag) gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; #endif +#if defined(PHYS_SDRAM_2) && defined(PHYS_SDRAM_2_SIZE) + if (CONFIG_NR_DRAM_BANKS > 1 && + (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) != PHYS_SDRAM_2) + addr = PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE; + else + addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size; +#else addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size; +#endif + + + + #ifdef CONFIG_LOGBUFFER #ifndef CONFIG_ALT_LB_ADDR -- 1.7.0.4

3 6

[U-Boot] am33xx config_ddr api change needed to support mDDR
by Markus Brunner 07 Feb '13

07 Feb '13

Hi, for mDDR to work mddr_sel (bit 28) of ddrctrl->ddrioctrl has to be set. There is no way of telling config_ddr(unsigned int pll, unsigned int ioctrl, ...) my desired value, it won't be set atm. >From the 1.3kB ddr_ctrl struct only 2 registers are defined, which is fine if it's used memory mapped, however it makes it unsuitable for passing values in the SPL. So at first glance I would extend config_ddr() with an additional register value, because guessing the ddr type from the values of the other parameters is, in addition to being hackish, not guaranteed to work with every weired ram configuration. However might it be possible, that the second value of config_ddr() should not hold the value for config_io_ctrl(), but the value of my desired ddrctrl->ddrioctrl? The wiki [1] from TI says that the first should _always_ be 0x18B, whereas the second needs to be set depending on the mem type. We are talking about a set of registers named DDR_*_IOCTRL and a single register called DDR_IO_CTRL, so easy to mix up. Ragards, Markus [1] http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips

2 2

[U-Boot] [PATCH]powerpc/usb: Fix usb device-tree fix-up
by Ramneek Mehresh 07 Feb '13

07 Feb '13

Fix USB device-tree fixup to properly handle device-tree fixup and print appropriate message when wrong/junk "dr_mode" or "phy_type" are mentioned in hwconfig string Signed-off-by: Ramneek Mehresh <ramneek.mehresh(a)freescale.com> --- arch/powerpc/cpu/mpc8xxx/fdt.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 2847094..413e184 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -167,6 +167,12 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) } } + if (mode_idx < 0 || phy_idx < 0) { + printf("WARNING: wrong usb mode/phy" + " defined!!\n"); + return; + } + dr_mode_type = modes[mode_idx]; dr_phy_type = phys[phy_idx]; -- 1.7.11.4

2 1

[U-Boot] [PATCH] helper: Add architecture specific symbol prefix in the uboot list link script.
by Sonic Zhang 07 Feb '13

07 Feb '13

From: Sonic Zhang <sonic.zhang(a)analog.com> Blackfin compiler add prefix '_' to each symbols. All symbols defined in the link script should have this prefix. Add it to the uboot list helper function make_u_boot_list. Signed-off-by: Sonic Zhang <sonic.zhang(a)analog.com> --- helper.mk | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/helper.mk b/helper.mk index 79a1da0..16e4cfd 100644 --- a/helper.mk +++ b/helper.mk @@ -58,7 +58,7 @@ $(1): $(2) -e ':s /^.\+$$$$/ { p;s/^$.*$\.[^\.]*$$$$/\1/;b s }' | \ sed -n -e 'h;s/$$$$/\a/p;g;s/$$$$/@/p;g;s/$$$$/~/p;' | \ LC_COLLATE=C sort -u | \ - sed -n -e '/\a$$$$/ { s/\./_/g;s/\a$$$$/__start = .;/p; }'\ - -e '/~$$$$/ { s/\./_/g;s/~$$$$/__end = .;/p; }'\ + sed -n -e '/\a$$$$/ { s/\./_/g;s/\_u_boot_list/$(SYM_PREFIX)_u_boot_list/g;s/\a$$$$/__start = .;/p; }'\ + -e '/~$$$$/ { s/\./_/g;s/\_u_boot_list/$(SYM_PREFIX)_u_boot_list/g;s/~$$$$/__end = .;/p; }'\ -e '/@$$$$/ { s/$.*$(a)$$$$/*(SORT(\1.*));/p }' > $(1) endef -- 1.7.0.4

3 2

[U-Boot] Booting on seaboard (unaligned access)
by Simon Glass 06 Feb '13

06 Feb '13

Hi Tom, I can't boot mainline on seaboard at present without reverting this commit: c50afc1d Revert "arm: armv7: add compile option -mno-unaligned-access if available Is there supposed to be another way of fixing this, or is my toolchain broken? I may have missed something. Regards, Simon

3 3

[U-Boot] [PATCH v4 1/9] nand: mxc: Prepare to add support for i.MX5
by Benoît Thébaudeau 06 Feb '13

06 Feb '13

Add some abstraction to NFC defitnitions so that some parts of the current code can also be used for future i.MX5 code. Clean up a few things by the way. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau(a)advansee.com> --- Changes in v4: None Changes in v3: - Separate code reformatting from behavioral changes. Changes in v2: - Fix warning for unused tmp variable in board_nand_init() for NFC V1. drivers/mtd/nand/mxc_nand.c | 92 +++++++++++++++++++++--------------------- include/fsl_nfc.h | 72 ++++++++++++--------------------- nand_spl/nand_boot_fsl_nfc.c | 47 +++++++++++---------- 3 files changed, 97 insertions(+), 114 deletions(-) diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index d0ded48..045df49 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -150,7 +150,7 @@ static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size /* * This function polls the NANDFC to wait for the basic operation to - * complete by checking the INT bit of config2 register. + * complete by checking the INT bit. */ static void wait_op_done(struct mxc_nand_host *host, int max_retries, uint16_t param) @@ -158,10 +158,10 @@ static void wait_op_done(struct mxc_nand_host *host, int max_retries, uint32_t tmp; while (max_retries-- > 0) { - if (readw(&host->regs->config2) & NFC_INT) { - tmp = readw(&host->regs->config2); - tmp &= ~NFC_INT; - writew(tmp, &host->regs->config2); + tmp = readnfc(&host->regs->config2); + if (tmp & NFC_V1_V2_CONFIG2_INT) { + tmp &= ~NFC_V1_V2_CONFIG2_INT; + writenfc(tmp, &host->regs->config2); break; } udelay(1); @@ -180,8 +180,8 @@ static void send_cmd(struct mxc_nand_host *host, uint16_t cmd) { MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd); - writew(cmd, &host->regs->flash_cmd); - writew(NFC_CMD, &host->regs->config2); + writenfc(cmd, &host->regs->flash_cmd); + writenfc(NFC_CMD, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, cmd); @@ -196,8 +196,8 @@ static void send_addr(struct mxc_nand_host *host, uint16_t addr) { MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr); - writew(addr, &host->regs->flash_addr); - writew(NFC_ADDR, &host->regs->config2); + writenfc(addr, &host->regs->flash_addr); + writenfc(NFC_ADDR, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, addr); @@ -229,19 +229,19 @@ static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id, } } - writew(buf_id, &host->regs->buf_addr); + writenfc(buf_id, &host->regs->buf_addr); /* Configure spare or page+spare access */ if (!host->pagesize_2k) { - uint16_t config1 = readw(&host->regs->config1); + uint16_t config1 = readnfc(&host->regs->config1); if (spare_only) - config1 |= NFC_SP_EN; + config1 |= NFC_CONFIG1_SP_EN; else - config1 &= ~NFC_SP_EN; - writew(config1, &host->regs->config1); + config1 &= ~NFC_CONFIG1_SP_EN; + writenfc(config1, &host->regs->config1); } - writew(NFC_INPUT, &host->regs->config2); + writenfc(NFC_INPUT, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, spare_only); @@ -256,19 +256,19 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id, { MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only); - writew(buf_id, &host->regs->buf_addr); + writenfc(buf_id, &host->regs->buf_addr); /* Configure spare or page+spare access */ if (!host->pagesize_2k) { - uint32_t config1 = readw(&host->regs->config1); + uint32_t config1 = readnfc(&host->regs->config1); if (spare_only) - config1 |= NFC_SP_EN; + config1 |= NFC_CONFIG1_SP_EN; else - config1 &= ~NFC_SP_EN; - writew(config1, &host->regs->config1); + config1 &= ~NFC_CONFIG1_SP_EN; + writenfc(config1, &host->regs->config1); } - writew(NFC_OUTPUT, &host->regs->config2); + writenfc(NFC_OUTPUT, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, spare_only); @@ -296,14 +296,14 @@ static void send_read_id(struct mxc_nand_host *host) uint16_t tmp; /* NANDFC buffer 0 is used for device ID output */ - writew(0x0, &host->regs->buf_addr); + writenfc(0x0, &host->regs->buf_addr); /* Read ID into main buffer */ - tmp = readw(&host->regs->config1); - tmp &= ~NFC_SP_EN; - writew(tmp, &host->regs->config1); + tmp = readnfc(&host->regs->config1); + tmp &= ~NFC_CONFIG1_SP_EN; + writenfc(tmp, &host->regs->config1); - writew(NFC_ID, &host->regs->config2); + writenfc(NFC_ID, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, 0); @@ -323,14 +323,14 @@ static uint16_t get_dev_status(struct mxc_nand_host *host) /* store the main area1 first word, later do recovery */ store = readl(main_buf); /* NANDFC buffer 1 is used for device status */ - writew(1, &host->regs->buf_addr); + writenfc(1, &host->regs->buf_addr); /* Read status into main buffer */ - tmp = readw(&host->regs->config1); - tmp &= ~NFC_SP_EN; - writew(tmp, &host->regs->config1); + tmp = readnfc(&host->regs->config1); + tmp &= ~NFC_CONFIG1_SP_EN; + writenfc(tmp, &host->regs->config1); - writew(NFC_STATUS, &host->regs->config2); + writenfc(NFC_STATUS, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, 0); @@ -359,13 +359,13 @@ static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on) { struct nand_chip *nand_chip = mtd->priv; struct mxc_nand_host *host = nand_chip->priv; - uint16_t tmp = readw(&host->regs->config1); + uint16_t tmp = readnfc(&host->regs->config1); if (on) - tmp |= NFC_ECC_EN; + tmp |= NFC_V1_V2_CONFIG1_ECC_EN; else - tmp &= ~NFC_ECC_EN; - writew(tmp, &host->regs->config1); + tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN; + writenfc(tmp, &host->regs->config1); } #ifdef CONFIG_MXC_NAND_HWECC @@ -698,7 +698,7 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, * additional correction. 2-Bit errors cannot be corrected by * HW ECC, so we need to return failure */ - uint16_t ecc_status = readw(&host->regs->ecc_status_result); + uint16_t ecc_status = readnfc(&host->regs->ecc_status_result); if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { MTDDEBUG(MTD_DEBUG_LEVEL0, @@ -1241,24 +1241,24 @@ int board_nand_init(struct nand_chip *this) #endif #ifdef MXC_NFC_V2_1 - tmp = readw(&host->regs->config1); - tmp |= NFC_ONE_CYCLE; - tmp |= NFC_4_8N_ECC; - writew(tmp, &host->regs->config1); + tmp = readnfc(&host->regs->config1); + tmp |= NFC_V2_CONFIG1_ONE_CYCLE; + tmp |= NFC_V2_CONFIG1_ECC_MODE_4; + writenfc(tmp, &host->regs->config1); if (host->pagesize_2k) - writew(64/2, &host->regs->spare_area_size); + writenfc(64/2, &host->regs->spare_area_size); else - writew(16/2, &host->regs->spare_area_size); + writenfc(16/2, &host->regs->spare_area_size); #endif /* * preset operation * Unlock the internal RAM Buffer */ - writew(0x2, &host->regs->config); + writenfc(0x2, &host->regs->config); /* Blocks to be unlocked */ - writew(0x0, &host->regs->unlockstart_blkaddr); + writenfc(0x0, &host->regs->unlockstart_blkaddr); /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the * unlockend_blkaddr, but the magic 0x4000 does not always work * when writing more than some 32 megabytes (on 2k page nands) @@ -1270,10 +1270,10 @@ int board_nand_init(struct nand_chip *this) * This might be NAND chip specific and the i.MX31 datasheet is * extremely vague about the semantics of this register. */ - writew(0xFFFF, &host->regs->unlockend_blkaddr); + writenfc(0xFFFF, &host->regs->unlockend_blkaddr); /* Unlock Block Command for given address range */ - writew(0x4, &host->regs->wrprot); + writenfc(0x4, &host->regs->wrprot); return 0; } diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h index ff537b4..013e9e2 100644 --- a/include/fsl_nfc.h +++ b/include/fsl_nfc.h @@ -113,58 +113,38 @@ struct fsl_nfc_regs { #endif }; -/* - * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command - * operation - */ -#define NFC_CMD 0x1 +/* Set FCMD to 1, rest to 0 for Command operation */ +#define NFC_CMD 0x1 -/* - * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address - * operation - */ -#define NFC_ADDR 0x2 +/* Set FADD to 1, rest to 0 for Address operation */ +#define NFC_ADDR 0x2 -/* - * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input - * operation - */ -#define NFC_INPUT 0x4 +/* Set FDI to 1, rest to 0 for Input operation */ +#define NFC_INPUT 0x4 -/* - * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data - * Output operation - */ -#define NFC_OUTPUT 0x8 +/* Set FDO to 001, rest to 0 for Data Output operation */ +#define NFC_OUTPUT 0x8 -/* - * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID - * operation - */ -#define NFC_ID 0x10 +/* Set FDO to 010, rest to 0 for Read ID operation */ +#define NFC_ID 0x10 -/* - * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read - * Status operation - */ -#define NFC_STATUS 0x20 +/* Set FDO to 100, rest to 0 for Read Status operation */ +#define NFC_STATUS 0x20 -/* - * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status - * operation - */ -#define NFC_INT 0x8000 +#define NFC_CONFIG1_SP_EN (1 << 2) +#define NFC_CONFIG1_RST (1 << 6) +#define NFC_CONFIG1_CE (1 << 7) +#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) +#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) +#define NFC_V1_V2_CONFIG1_BIG (1 << 5) +#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) +#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) +#define NFC_V2_CONFIG1_FP_INT (1 << 11) -#ifdef MXC_NFC_V2_1 -#define NFC_4_8N_ECC (1 << 0) -#endif -#define NFC_SP_EN (1 << 2) -#define NFC_ECC_EN (1 << 3) -#define NFC_INT_MSK (1 << 4) -#define NFC_BIG (1 << 5) -#define NFC_RST (1 << 6) -#define NFC_CE (1 << 7) -#define NFC_ONE_CYCLE (1 << 8) -#define NFC_FP_INT (1 << 11) +#define NFC_V1_V2_CONFIG2_INT (1 << 15) + +#define operation config2 +#define readnfc readw +#define writenfc writew #endif /* __FSL_NFC_H */ diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c index a40c998..615e820 100644 --- a/nand_spl/nand_boot_fsl_nfc.c +++ b/nand_spl/nand_boot_fsl_nfc.c @@ -36,13 +36,13 @@ static void nfc_wait_ready(void) { uint32_t tmp; - while (!(readw(&nfc->config2) & NFC_INT)) + while (!(readnfc(&nfc->config2) & NFC_V1_V2_CONFIG2_INT)) ; /* Reset interrupt flag */ - tmp = readw(&nfc->config2); - tmp &= ~NFC_INT; - writew(tmp, &nfc->config2); + tmp = readnfc(&nfc->config2); + tmp &= ~NFC_V1_V2_CONFIG2_INT; + writenfc(tmp, &nfc->config2); } static void nfc_nand_init(void) @@ -51,43 +51,45 @@ static void nfc_nand_init(void) int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512; int config1; - writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size); + writenfc(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size); /* unlocking RAM Buff */ - writew(0x2, &nfc->config); + writenfc(0x2, &nfc->config); /* hardware ECC checking and correct */ - config1 = readw(&nfc->config1) | NFC_ECC_EN | NFC_INT_MSK | - NFC_ONE_CYCLE | NFC_FP_INT; + config1 = readnfc(&nfc->config1) | NFC_V1_V2_CONFIG1_ECC_EN | + NFC_V1_V2_CONFIG1_INT_MSK | NFC_V2_CONFIG1_ONE_CYCLE | + NFC_V2_CONFIG1_FP_INT; /* * if spare size is larger that 16 bytes per 512 byte hunk * then use 8 symbol correction instead of 4 */ if (CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16) - config1 &= ~NFC_4_8N_ECC; + config1 &= ~NFC_V2_CONFIG1_ECC_MODE_4; else - config1 |= NFC_4_8N_ECC; - writew(config1, &nfc->config1); + config1 |= NFC_V2_CONFIG1_ECC_MODE_4; + writenfc(config1, &nfc->config1); #elif defined(MXC_NFC_V1) /* unlocking RAM Buff */ - writew(0x2, &nfc->config); + writenfc(0x2, &nfc->config); /* hardware ECC checking and correct */ - writew(NFC_ECC_EN | NFC_INT_MSK, &nfc->config1); + writenfc(NFC_V1_V2_CONFIG1_ECC_EN | NFC_V1_V2_CONFIG1_INT_MSK, + &nfc->config1); #endif } static void nfc_nand_command(unsigned short command) { - writew(command, &nfc->flash_cmd); - writew(NFC_CMD, &nfc->config2); + writenfc(command, &nfc->flash_cmd); + writenfc(NFC_CMD, &nfc->operation); nfc_wait_ready(); } static void nfc_nand_address(unsigned short address) { - writew(address, &nfc->flash_addr); - writew(NFC_ADDR, &nfc->config2); + writenfc(address, &nfc->flash_addr); + writenfc(NFC_ADDR, &nfc->operation); nfc_wait_ready(); } @@ -121,8 +123,8 @@ static void nfc_nand_data_output(void) int i; #endif - writew(0, &nfc->buf_addr); - writew(NFC_OUTPUT, &nfc->config2); + writenfc(0, &nfc->buf_addr); + writenfc(NFC_OUTPUT, &nfc->operation); nfc_wait_ready(); #ifdef NAND_MXC_2K_MULTI_CYCLE /* @@ -130,8 +132,8 @@ static void nfc_nand_data_output(void) * for pages larger than 512 bytes. */ for (i = 1; i < CONFIG_SYS_NAND_PAGE_SIZE / 512; i++) { - writew(i, &nfc->buf_addr); - writew(NFC_OUTPUT, &nfc->config2); + writenfc(i, &nfc->buf_addr); + writenfc(NFC_OUTPUT, &nfc->operation); nfc_wait_ready(); } #endif @@ -160,7 +162,8 @@ static int nfc_nand_check_ecc(void) static void nfc_nand_read_page(unsigned int page_address) { - writew(0, &nfc->buf_addr); /* read in first 0 buffer */ + /* read in first 0 buffer */ + writenfc(0, &nfc->buf_addr); nfc_nand_command(NAND_CMD_READ0); nfc_nand_page_address(page_address); -- 1.7.10.4

1 9

[U-Boot] [PATCH V2] mvsata_ide.c: Correction of typo in comments
by Gray Remlin 06 Feb '13

06 Feb '13

Signed-off-by: Gray Remlin <gryrmln(a)gmail.com> --- Changes since V1 - None, resend due to mailer mangling. diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index a88d0f7..42c177f 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -56,8 +56,8 @@ struct mvsata_port_registers { * Sanity checks: * - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR. * - for ide_preinit to make sense, we need at least one of - * CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE0_OFFSET; - * - for inde_preinit to be called, we need CONFIG_IDE_PREINIT. + * CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET; + * - for ide_preinit to be called, we need CONFIG_IDE_PREINIT. * Fail with an explanation message if these conditions are not met. * This is particularly important for CONFIG_IDE_PREINIT, because * its lack would not cause a build error. -- 1.8.1

1 0

[U-Boot] Pull request - sf tree
by Michal Simek 06 Feb '13

06 Feb '13

Hi Mike and Tom, please pull these sf changes to your tree. Tom: I have sent private email to Mike but I haven't got any response from him. Also I haven't got reactions on mailing list. That's why I am not sure if Mike still cares about this subsystem. If not, please let me know who is responsible for it or just add these patches to your tree. Thanks, Michal The following changes since commit 6ad77d88e57f6ab815ec7e85c5ac329054318c73: Marek Vasut (1): vfat: Fix mkcksum argument sizes are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git mainline/sf Jagannadha Sutradharudu Teki (7): sf: spansion: Correct the first byte of idcode1 for S25FL256S part sf: winbond: Add W25Q64W sf: stmicro: Add support for N25Q64 sf: stmicro: Add support for N25Q64A sf: stmicro: Add support for N25Q32 sf: stmicro: Add support for N25Q32A sf: stmicro: Add support for N25Q256A drivers/mtd/spi/spansion.c | 2 +- drivers/mtd/spi/stmicro.c | 30 ++++++++++++++++++++++++++++++ drivers/mtd/spi/winbond.c | 5 +++++ 3 files changed, 36 insertions(+), 1 deletions(-) -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian

2 1

[U-Boot] Users of ARM repo please re-fetch if your ARM ToT is 1071e736...
by Albert ARIBAUD 06 Feb '13

06 Feb '13

Hello all, I had mistakenly pushed a merge of v2013.01.01 onto the Git ARM repo. I have just force-pushed the correct head, 5bedf884 (parent of 107...) Sorry for the inconvenience. Amicalement, -- Albert.

1 0