February 2013 - U-Boot

[U-Boot] [PATCH v2 01/16] km/common: remove unneeded ifdefs for I2C
by Holger Brunck 19 Feb '13

19 Feb '13

All boards from this serie use i2c. There is no need to #ifdef the header. Signed-off-by: Holger Brunck <holger.brunck(a)keymile.com> --- Changes for v2: - fix typo in commit message board/keymile/common/common.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 6f407b7..468c755 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -38,9 +38,7 @@ #include "post.h" #endif #include "common.h" -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) #include <i2c.h> -#endif #if !defined(CONFIG_MPC83xx) static void i2c_write_start_seq(void); -- 1.7.1

3 18

[U-Boot] [PATCH v4 0/10] mx23/mxs pending patches
by Otavio Salvador 19 Feb '13

19 Feb '13

This patchset includes the pending patches we have in our tree. It fixes issues for mx23evk and mx23_olinuxino boards. The DRAM control register change has been kept specific to mx23evk as it breaks mx23_olinuxino (as it than reads only 16MB) Changes in v4: - Rework soc_ehci_hcd_{enable,disable}_clock to mxs_ehci_hcd_clock (Fabio / Marek) Changes in v3: - Extend code comment to be more verbose (Marek) - Improve commit log - Move code to enable/disable clock to soc_ehci_hcd_{enable,disable}_clock - Proper use mx23 clock registers Changes in v2: - Extend code comment to explicit say it needs to be there. - Use MUX pin name - Requested by Marek - Avoid wrong clock setting in MX23 - Add changes for allow use of the USB hub - Remove extra newline Otavio Salvador (10): mxs: Rename CONFIG_SPL_MX28_PSWITCH_WAIT to CONFIG_SPL_MXS_PSWITCH_WAIT mx23: Document the tRAS lockout setting in memory initialization mx23evk: Adjust DRAM control register to use full 128MB of RAM led: Use STATUS_LED_ON and STATUS_LED_OFF when calling __led_set mxs: Fix iomux.h to not break build during assembly stage mx23_olinuxino: Add support for status LED usb: mxs: Adapt code for i.MX23 support mx23evk: Enable USB support mx23_olinuxino: Enable USB support mx23_olinuxino: Add ethernet support arch/arm/cpu/arm926ejs/mxs/mxs_init.h | 2 +- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 4 ++ arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 2 +- arch/arm/include/asm/arch-mxs/iomux.h | 5 +++ board/freescale/mx23evk/spl_boot.c | 10 +++++ board/olimex/mx23_olinuxino/mx23_olinuxino.c | 13 ++++++ board/olimex/mx23_olinuxino/spl_boot.c | 8 ++++ common/cmd_led.c | 6 ++- drivers/usb/host/ehci-mxs.c | 58 +++++++++++++++---------- include/configs/mx23_olinuxino.h | 63 ++++++++++++++++++++++++++-- include/configs/mx23evk.h | 10 +++++ 11 files changed, 151 insertions(+), 30 deletions(-) -- 1.8.1

2 11

[U-Boot] [PATCH v2] Exynos5: Pinmux: Add fdt for pinmux
by Akshay Saraswat 18 Feb '13

18 Feb '13

This patch adds fdt nodes for peripherals which require pin muxing and configuration. Device tree bindings for pinctrl are kept same as required for Linux. Existing pinmux code modified to retrieve gpio range and function related info from fdt. Depends-on: [PATCH 0/3 V2] EXYNOS5: Add GPIO numbering feature URL: http://lists.denx.de/pipermail/u-boot/2013-January/144681.html Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> --- Changes since v1: - Device tree bindings changed to linux style. - Added documentation for samsung pinctrl. arch/arm/cpu/armv7/exynos/pinmux.c | 445 +++++++++++++---- arch/arm/dts/exynos5250-pinctrl.dtsi | 675 ++++++++++++++++++++++++++ arch/arm/dts/exynos5250.dtsi | 1 + doc/device-tree-bindings/samsung-pinctrl.txt | 253 ++++++++++ include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 6 files changed, 1280 insertions(+), 96 deletions(-) create mode 100644 arch/arm/dts/exynos5250-pinctrl.dtsi create mode 100644 doc/device-tree-bindings/samsung-pinctrl.txt diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index c79d58e..da59483 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -23,91 +23,302 @@ #include <common.h> #include <fdtdec.h> +#include <linux/ctype.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/sromc.h> -static void exynos5_uart_config(int peripheral) +DECLARE_GLOBAL_DATA_PTR; + +/* Struct for storing pin function and gpio related info */ +struct pin_group { + void *dev_name; + int npins; + int function; + enum exynos5_gpio_pin gpio[]; +}; + +static void get_pins(const struct fdt_property *fprop, struct pin_group *pgrp) +{ + int i; + + pgrp->npins = 0; + + for (i = 0; !(fprop->data[i] == (int)NULL && + fprop->data[i-1] == (int)NULL); i += 7) { + int pin_bank = -1; + + if (strncmp(fprop->data + i, "gpa0", 4) == 0) + pin_bank = GPIO_A00; + else if (strncmp(fprop->data + i, "gpa1", 4) == 0) + pin_bank = GPIO_A10; + else if (strncmp(fprop->data + i, "gpa2", 4) == 0) + pin_bank = GPIO_A20; + else if (strncmp(fprop->data + i, "gpb0", 4) == 0) + pin_bank = GPIO_B00; + else if (strncmp(fprop->data + i, "gpb1", 4) == 0) + pin_bank = GPIO_B10; + else if (strncmp(fprop->data + i, "gpb2", 4) == 0) + pin_bank = GPIO_B20; + else if (strncmp(fprop->data + i, "gpb3", 4) == 0) + pin_bank = GPIO_B30; + else if (strncmp(fprop->data + i, "gpc0", 4) == 0) + pin_bank = GPIO_C00; + else if (strncmp(fprop->data + i, "gpc1", 4) == 0) + pin_bank = GPIO_C10; + else if (strncmp(fprop->data + i, "gpc2", 4) == 0) + pin_bank = GPIO_C20; + else if (strncmp(fprop->data + i, "gpc3", 4) == 0) + pin_bank = GPIO_C30; + else if (strncmp(fprop->data + i, "gpd0", 4) == 0) + pin_bank = GPIO_D00; + else if (strncmp(fprop->data + i, "gpd1", 4) == 0) + pin_bank = GPIO_D10; + else if (strncmp(fprop->data + i, "gpy0", 4) == 0) + pin_bank = GPIO_Y00; + else if (strncmp(fprop->data + i, "gpy1", 4) == 0) + pin_bank = GPIO_Y10; + else if (strncmp(fprop->data + i, "gpy2", 4) == 0) + pin_bank = GPIO_Y20; + else if (strncmp(fprop->data + i, "gpy3", 4) == 0) + pin_bank = GPIO_Y30; + else if (strncmp(fprop->data + i, "gpy4", 4) == 0) + pin_bank = GPIO_Y40; + else if (strncmp(fprop->data + i, "gpy5", 4) == 0) + pin_bank = GPIO_Y50; + else if (strncmp(fprop->data + i, "gpy6", 4) == 0) + pin_bank = GPIO_Y60; + else if (strncmp(fprop->data + i, "gpc4", 4) == 0) + pin_bank = GPIO_C40; + else if (strncmp(fprop->data + i, "gpx0", 4) == 0) + pin_bank = GPIO_X00; + else if (strncmp(fprop->data + i, "gpx1", 4) == 0) + pin_bank = GPIO_X10; + else if (strncmp(fprop->data + i, "gpx2", 4) == 0) + pin_bank = GPIO_X20; + else if (strncmp(fprop->data + i, "gpx3", 4) == 0) + pin_bank = GPIO_X30; + else if (strncmp(fprop->data + i, "gpe0", 4) == 0) + pin_bank = GPIO_E00; + else if (strncmp(fprop->data + i, "gpe1", 4) == 0) + pin_bank = GPIO_E10; + else if (strncmp(fprop->data + i, "gpf0", 4) == 0) + pin_bank = GPIO_F10; + else if (strncmp(fprop->data + i, "gpf1", 4) == 0) + pin_bank = GPIO_F10; + else if (strncmp(fprop->data + i, "gpg0", 4) == 0) + pin_bank = GPIO_G00; + else if (strncmp(fprop->data + i, "gpg1", 4) == 0) + pin_bank = GPIO_G10; + else if (strncmp(fprop->data + i, "gpg2", 4) == 0) + pin_bank = GPIO_G20; + else if (strncmp(fprop->data + i, "gph0", 4) == 0) + pin_bank = GPIO_H00; + else if (strncmp(fprop->data + i, "gph1", 4) == 0) + pin_bank = GPIO_H10; + else if (strncmp(fprop->data + i, "gpv0", 4) == 0) + pin_bank = GPIO_V00; + else if (strncmp(fprop->data + i, "gpv1", 4) == 0) + pin_bank = GPIO_V10; + else if (strncmp(fprop->data + i, "gpv2", 4) == 0) + pin_bank = GPIO_V20; + else if (strncmp(fprop->data + i, "gpv3", 4) == 0) + pin_bank = GPIO_V30; + else if (strncmp(fprop->data + i, "gpv4", 4) == 0) + pin_bank = GPIO_V40; + else if (strncmp(fprop->data + i, "gpz", 4) == 0) + pin_bank = GPIO_Z0; + + if (pin_bank >= 0 && isdigit(fprop->data[i+5])) { + pgrp->gpio[pgrp->npins] = + pin_bank + (fprop->data[i+5] - '0'); + pgrp->npins++; + } + } +} + +static int get_fdt_values(struct pin_group *pgrp) +{ + int i; + int node, subnode; + const struct fdt_property *fprop; + + for (i = 0; i < 4; i++) { + /* Get the node from FDT for pinctrl */ + node = fdtdec_next_compatible(gd->fdt_blob, 0, + COMPAT_SAMSUNG_PINCTRL); + if (node < 0) { + printf("PINCTRL: No node for pinctrl in device tree\n"); + return -1; + } + + subnode = fdt_subnode_offset(gd->fdt_blob, + node, pgrp->dev_name); + if (subnode < 0) + continue; + + fprop = fdt_get_property(gd->fdt_blob, + subnode, "samsung,pins", NULL); + pgrp->function = fdtdec_get_int(gd->fdt_blob, + subnode, "samsung,pin-function", -1); + get_pins(fprop, pgrp); + + return 0; + } + + printf("PINCTRL: No subnode for %s", (char *)pgrp->dev_name); + + return -1; +} + +static int exynos5_uart_config(int peripheral) { - int i, start, count; + int i; + char *data, *fctl = NULL; + struct pin_group pgrp; switch (peripheral) { case PERIPH_ID_UART0: - start = GPIO_A00; - count = 4; + data = "uart0-data"; + fctl = "uart0-fctl"; break; case PERIPH_ID_UART1: - start = GPIO_D00; - count = 4; + data = "uart1-data"; + fctl = "uart1-fctl"; break; case PERIPH_ID_UART2: - start = GPIO_A10; - count = 4; + data = "uart2-data"; + fctl = "uart2-fctl"; break; case PERIPH_ID_UART3: - start = GPIO_A14; - count = 2; + data = "uart3-data"; break; } - for (i = start; i < start + count; i++) { - gpio_set_pull(i, GPIO_PULL_NONE); - gpio_cfg_pin(i, GPIO_FUNC(0x2)); + + pgrp.dev_name = data; + + /* Retrieve gpio pins for this UART's data line */ + if (get_fdt_values(&pgrp)) + return -1; + + /* Apply pin configurations */ + for (i = 0; i < pgrp.npins; i++) { + gpio_set_pull(pgrp.gpio[i], GPIO_PULL_NONE); + gpio_cfg_pin(pgrp.gpio[i], GPIO_FUNC(pgrp.function)); } + + if (peripheral != PERIPH_ID_UART3) { + pgrp.dev_name = fctl; + + /* Retrieve gpio pins for this UART's data line */ + if (get_fdt_values(&pgrp)) + return -1; + + /* Apply pin configurations */ + for (i = 0; i < pgrp.npins; i++) { + gpio_set_pull(pgrp.gpio[i], GPIO_PULL_NONE); + gpio_cfg_pin(pgrp.gpio[i], GPIO_FUNC(pgrp.function)); + } + } + + return 0; } static int exynos5_mmc_config(int peripheral, int flags) { - int i, start, start_ext, gpio_func = 0; + int i; + char *clk, *cmd, *width4, *width8 = NULL; + struct pin_group pgrp; switch (peripheral) { case PERIPH_ID_SDMMC0: - start = GPIO_C00; - start_ext = GPIO_C10; - gpio_func = GPIO_FUNC(0x2); + clk = "sd0-clk"; + cmd = "sd0-cmd"; + width4 = "sd0-bus-width4"; + width8 = "sd0-bus-width8"; break; case PERIPH_ID_SDMMC1: - start = GPIO_C20; - start_ext = 0; + clk = "sd1-clk"; + cmd = "sd1-cmd"; + width4 = "sd1-bus-width4"; break; case PERIPH_ID_SDMMC2: - start = GPIO_C30; - start_ext = GPIO_C43; - gpio_func = GPIO_FUNC(0x3); + clk = "sd2-clk"; + cmd = "sd2-cmd"; + width4 = "sd2-bus-width4"; + width8 = "sd2-bus-width8"; break; case PERIPH_ID_SDMMC3: - start = GPIO_C40; - start_ext = 0; + clk = "sd3-clk"; + cmd = "sd3-cmd"; + width4 = "sd3-bus-width4"; break; } - if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { + + /* Apply pin configurations */ + if ((flags & PINMUX_FLAG_8BIT_MODE) && width8 == NULL) { debug("SDMMC device %d does not support 8bit mode", peripheral); return -1; } + if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = start_ext; i <= (start_ext + 3); i++) { - gpio_cfg_pin(i, gpio_func); - gpio_set_pull(i, GPIO_PULL_UP); - gpio_set_drv(i, GPIO_DRV_4X); + pgrp.dev_name = width8; + + /* Retrieve gpio range and base for this SDMMC */ + if (get_fdt_values(&pgrp)) + return -1; + + for (i = 0; i < pgrp.npins; i++) { + gpio_cfg_pin(pgrp.gpio[i], GPIO_FUNC(pgrp.function)); + gpio_set_pull(pgrp.gpio[i], GPIO_PULL_UP); + gpio_set_drv(pgrp.gpio[i], GPIO_DRV_4X); } } - for (i = 0; i < 2; i++) { - gpio_cfg_pin(start + i, GPIO_FUNC(0x2)); - gpio_set_pull(start + i, GPIO_PULL_NONE); - gpio_set_drv(start + i, GPIO_DRV_4X); + + pgrp.dev_name = clk; + + /* Retrieve gpio range and base for this SDMMC */ + if (get_fdt_values(&pgrp)) + return -1; + + for (i = 0; i < pgrp.npins; i++) { + gpio_cfg_pin(pgrp.gpio[i], GPIO_FUNC(pgrp.function)); + gpio_set_pull(pgrp.gpio[i], GPIO_PULL_NONE); + gpio_set_drv(pgrp.gpio[i], GPIO_DRV_4X); } - for (i = 3; i <= 6; i++) { - gpio_cfg_pin(start + i, GPIO_FUNC(0x2)); - gpio_set_pull(start + i, GPIO_PULL_UP); - gpio_set_drv(start + i, GPIO_DRV_4X); + + pgrp.dev_name = cmd; + + /* Retrieve gpio range and base for this SDMMC */ + if (get_fdt_values(&pgrp)) + return -1; + + for (i = 0; i < pgrp.npins; i++) { + gpio_cfg_pin(pgrp.gpio[i], GPIO_FUNC(pgrp.function)); + gpio_set_pull(pgrp.gpio[i], GPIO_PULL_NONE); + gpio_set_drv(pgrp.gpio[i], GPIO_DRV_4X); + } + + pgrp.dev_name = width4; + + /* Retrieve gpio range and base for this SDMMC */ + if (get_fdt_values(&pgrp)) + return -1; + + for (i = 0; i < pgrp.npins ; i++) { + gpio_cfg_pin(pgrp.gpio[i], GPIO_FUNC(pgrp.function)); + gpio_set_pull(pgrp.gpio[i], GPIO_PULL_UP); + gpio_set_drv(pgrp.gpio[i], GPIO_DRV_4X); } return 0; } -static void exynos5_sromc_config(int flags) +static int exynos5_sromc_config(int flags) { int i; + static struct pin_group pgrp; /* * SROM:CS1 and EBI @@ -124,13 +335,28 @@ static void exynos5_sromc_config(int flags) * GPY1[2] SROM_WAIT(2) * GPY1[3] EBI_DATA_RDn(2) */ - gpio_cfg_pin(GPIO_Y00 + (flags & PINMUX_FLAG_BANK), - GPIO_FUNC(2)); - gpio_cfg_pin(GPIO_Y04, GPIO_FUNC(2)); - gpio_cfg_pin(GPIO_Y05, GPIO_FUNC(2)); + pgrp.dev_name = "srom-cs1"; + + /* Retrieve gpio range and base for SROM CS1 */ + if (get_fdt_values(&pgrp)) + return -1; + + /* Apply pin configurations */ + gpio_cfg_pin(pgrp.gpio[0] + (flags & PINMUX_FLAG_BANK), + GPIO_FUNC(pgrp.function)); + + for (i = 1; i < pgrp.npins; i++) + gpio_cfg_pin(pgrp.gpio[i], GPIO_FUNC(pgrp.function)); - for (i = 0; i < 4; i++) - gpio_cfg_pin(GPIO_Y10 + i, GPIO_FUNC(2)); + pgrp.dev_name = "srom-ebi-enable"; + + /* Retrieve gpio range and base for SROM EBI */ + if (get_fdt_values(&pgrp)) + return -1; + + /* Apply pin configurations */ + for (i = 0; i < pgrp.npins; i++) + gpio_cfg_pin(pgrp.gpio[i], GPIO_FUNC(pgrp.function)); /* * EBI: 8 Addrss Lines @@ -164,97 +390,126 @@ static void exynos5_sromc_config(int flags) * GPY6[6] EBI_DATA[14](2) * GPY6[7] EBI_DATA[15](2) */ - for (i = 0; i < 8; i++) { - gpio_cfg_pin(GPIO_Y30 + i, GPIO_FUNC(2)); - gpio_set_pull(GPIO_Y30 + i, GPIO_PULL_UP); + pgrp.dev_name = "srom-ebi-addr-lines"; - gpio_cfg_pin(GPIO_Y50 + i, GPIO_FUNC(2)); - gpio_set_pull(GPIO_Y50 + i, GPIO_PULL_UP); + /* Retrieve gpio range and base for SROM EBI address lines */ + if (get_fdt_values(&pgrp)) + return -1; - gpio_cfg_pin(GPIO_Y60 + i, GPIO_FUNC(2)); - gpio_set_pull(GPIO_Y60 + i, GPIO_PULL_UP); + /* Apply pin configurations */ + for (i = 0; i < pgrp.npins; i++) { + gpio_cfg_pin(pgrp.gpio[i], GPIO_FUNC(pgrp.function)); + gpio_set_pull(pgrp.gpio[i], GPIO_PULL_UP); } + + pgrp.dev_name = "srom-ebi-data-lines"; + + /* Retrieve gpio range and base for SROM EBI data lines */ + if (get_fdt_values(&pgrp)) + return -1; + + /* Apply pin configurations */ + for (i = 0; i < pgrp.npins; i++) { + gpio_cfg_pin(pgrp.gpio[i], GPIO_FUNC(pgrp.function)); + gpio_set_pull(pgrp.gpio[i], GPIO_PULL_UP); + } + + return 0; } -static void exynos5_i2c_config(int peripheral, int flags) +static int exynos5_i2c_config(int peripheral, int flags) { + int i; + struct pin_group pgrp; switch (peripheral) { case PERIPH_ID_I2C0: - gpio_cfg_pin(GPIO_B30, GPIO_FUNC(0x2)); - gpio_cfg_pin(GPIO_B31, GPIO_FUNC(0x2)); + pgrp.dev_name = "i2c0-bus"; break; case PERIPH_ID_I2C1: - gpio_cfg_pin(GPIO_B32, GPIO_FUNC(0x2)); - gpio_cfg_pin(GPIO_B33, GPIO_FUNC(0x2)); + pgrp.dev_name = "i2c1-bus"; break; case PERIPH_ID_I2C2: - gpio_cfg_pin(GPIO_A06, GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_A07, GPIO_FUNC(0x3)); + pgrp.dev_name = "i2c2-bus"; break; case PERIPH_ID_I2C3: - gpio_cfg_pin(GPIO_A12, GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_A13, GPIO_FUNC(0x3)); + pgrp.dev_name = "i2c3-bus"; break; case PERIPH_ID_I2C4: - gpio_cfg_pin(GPIO_A20, GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_A21, GPIO_FUNC(0x3)); + pgrp.dev_name = "i2c4-bus"; break; case PERIPH_ID_I2C5: - gpio_cfg_pin(GPIO_A22, GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_A23, GPIO_FUNC(0x3)); + pgrp.dev_name = "i2c5-bus"; break; case PERIPH_ID_I2C6: - gpio_cfg_pin(GPIO_B13, GPIO_FUNC(0x4)); - gpio_cfg_pin(GPIO_B14, GPIO_FUNC(0x4)); + pgrp.dev_name = "i2c6-bus"; break; case PERIPH_ID_I2C7: - gpio_cfg_pin(GPIO_B22, GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_B23, GPIO_FUNC(0x3)); + pgrp.dev_name = "i2c7-bus"; break; } + + /* Retrieve gpio range and base for this I2C */ + if (get_fdt_values(&pgrp)) + return -1; + + /* Apply pin configurations */ + for (i = 0; i < pgrp.npins; i++) + gpio_cfg_pin(pgrp.gpio[i], GPIO_FUNC(pgrp.function)); + + return 0; } -static void exynos5_i2s_config(int peripheral) +static int exynos5_i2s_config(int peripheral) { int i; + struct pin_group pgrp; - for (i = 0; i < 5; i++) - gpio_cfg_pin(GPIO_B00+i, GPIO_FUNC(0x02)); + pgrp.dev_name = "i2s"; + + /* Retrieve gpio range and base for I2S */ + if (get_fdt_values(&pgrp)) + return -1; + + /* Apply pin configurations */ + for (i = 0; i < pgrp.npins; i++) + gpio_cfg_pin(pgrp.gpio[i], GPIO_FUNC(pgrp.function)); + + return 0; } -void exynos5_spi_config(int peripheral) +int exynos5_spi_config(int peripheral) { - int cfg = 0, pin = 0, i; + int i; + static struct pin_group pgrp; switch (peripheral) { case PERIPH_ID_SPI0: - cfg = GPIO_FUNC(0x2); - pin = GPIO_A20; + pgrp.dev_name = "spi0-bus"; break; case PERIPH_ID_SPI1: - cfg = GPIO_FUNC(0x2); - pin = GPIO_A24; + pgrp.dev_name = "spi1-bus"; break; case PERIPH_ID_SPI2: - cfg = GPIO_FUNC(0x5); - pin = GPIO_B11; + pgrp.dev_name = "spi2-bus"; break; case PERIPH_ID_SPI3: - cfg = GPIO_FUNC(0x2); - pin = GPIO_F10; + pgrp.dev_name = "spi3-bus"; break; case PERIPH_ID_SPI4: - for (i = 0; i < 2; i++) { - gpio_cfg_pin(GPIO_F02 + i, GPIO_FUNC(0x4)); - gpio_cfg_pin(GPIO_E04 + i, GPIO_FUNC(0x4)); - } + pgrp.dev_name = "spi4-bus"; break; } - if (peripheral != PERIPH_ID_SPI4) { - for (i = pin; i < pin + 4; i++) - gpio_cfg_pin(i, cfg); - } + + /* Retrieve gpio range and base for this SPI */ + if (get_fdt_values(&pgrp)) + return -1; + + /* Apply pin configurations */ + for (i = 0; i < pgrp.npins; i++) + gpio_cfg_pin(pgrp.gpio[i], GPIO_FUNC(pgrp.function)); + + return 0; } static int exynos5_pinmux_config(int peripheral, int flags) @@ -264,7 +519,7 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_UART1: case PERIPH_ID_UART2: case PERIPH_ID_UART3: - exynos5_uart_config(peripheral); + return exynos5_uart_config(peripheral); break; case PERIPH_ID_SDMMC0: case PERIPH_ID_SDMMC1: @@ -272,7 +527,7 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC3: return exynos5_mmc_config(peripheral, flags); case PERIPH_ID_SROMC: - exynos5_sromc_config(flags); + return exynos5_sromc_config(flags); break; case PERIPH_ID_I2C0: case PERIPH_ID_I2C1: @@ -282,24 +537,22 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_I2C5: case PERIPH_ID_I2C6: case PERIPH_ID_I2C7: - exynos5_i2c_config(peripheral, flags); + return exynos5_i2c_config(peripheral, flags); break; case PERIPH_ID_I2S1: - exynos5_i2s_config(peripheral); + return exynos5_i2s_config(peripheral); break; case PERIPH_ID_SPI0: case PERIPH_ID_SPI1: case PERIPH_ID_SPI2: case PERIPH_ID_SPI3: case PERIPH_ID_SPI4: - exynos5_spi_config(peripheral); + return exynos5_spi_config(peripheral); break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; } - - return 0; } static void exynos4_i2c_config(int peripheral, int flags) diff --git a/arch/arm/dts/exynos5250-pinctrl.dtsi b/arch/arm/dts/exynos5250-pinctrl.dtsi new file mode 100644 index 0000000..a250d7b --- /dev/null +++ b/arch/arm/dts/exynos5250-pinctrl.dtsi @@ -0,0 +1,675 @@ +/* + * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. + * + * Note: This file does not include pin-ctrl subnodes for all the controllers in + * Exynos5250 SoC. It can be updated as per need in future. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = <0 46 0>; + + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc4: gpc4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samaung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpd0-0", "gpd0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpd0-2", "gpd0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samaung,pin-drv = <0>; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_fctl: uart2-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samaung,pin-drv = <0>; + }; + + uart3_data: uart3-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpc0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpc0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpc0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpc0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpc2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpc2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpc2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpc2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpc3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpc3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpc3-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpc3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus8: sd2-bus-width8 { + samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd3_clk: sd3-clk { + samsung,pins = "gpc4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd3_cmd: sd3-cmd { + samsung,pins = "gpc4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd3_cd: sd3-cd { + samsung,pins = "gpc4-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd3_bus1: sd3-bus-width1 { + samsung,pins = "gpc4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd3_bus4: sd3-bus-width4 { + samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + srom_cs1: srom-cs1 { + samsung,pins = "gpy0-0", "gpy0-4", "gpy0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + srom_ebi: srom-ebi-enable { + samsung,pins = "gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + srom_ebi_a: srom-ebi-addr-lines { + samsung,pins = "gpy3-0", "gpy3-1", "gpy3-2", "gpy3-3", + "gpy3-4", "gpy3-5", "gpy3-6", "gpy3-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + srom_ebi_d: srom-ebi-data-lines { + samsung,pins = "gpy5-0", "gpy5-1", "gpy5-2", "gpy5-3", + "gpy5-4", "gpy5-5", "gpy5-6", "gpy5-7", + "gpy6-0", "gpy6-1", "gpy6-2", "gpy6-3", + "gpy6-4", "gpy6-5", "gpy6-6", "gpy6-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + i2s: i2s { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpa2-4", "gpa2-5", "gpa2-6", "gpa2-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; + samsung,pin-function = <5>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samaung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samaung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpa2-0", "gpa2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samaung,pin-drv = <0>; + }; + + i2c5_bus: i2c5-bus { + samsung,pins = "gpa2-2", "gpa2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samaung,pin-drv = <0>; + }; + + i2c6_bus: i2c6-bus { + samsung,pins = "gpb1-3", "gpb1-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c7_bus: i2c7-bus { + samsung,pins = "gpb2-2", "gpb2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl_1: pinctrl@13400000 { + compatible = "samsung,pinctrl"; + reg = <0x13400000 0x1000>; + interrupts = <0 45 0>; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph0: gph0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + spi3_bus: spi3-bus { + samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi4_bus: spi4-bus { + samsung,pins = "gpf0-2", "gpf0-3", "gpe0-4", "gpe0-5"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl_2: pinctrl@10d10000 { + compatible = "samsung,pinctrl-exynos5250"; + reg = <0x10d10000 0x1000>; + interrupts = <0 45 0>; + + gpv0: gpv0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv1: gpv1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv2: gpv2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv3: gpv3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv4: gpv4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pinctrl_3: pinctrl@03680000 { + compatible = "samsung,pinctrl-exynos5250"; + reg = <0x03680000 0x1000>; + interrupts = <0 45 0>; + + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi index ed8c8dd..8fcf432 100644 --- a/arch/arm/dts/exynos5250.dtsi +++ b/arch/arm/dts/exynos5250.dtsi @@ -18,6 +18,7 @@ */ /include/ "skeleton.dtsi" +/include/ "exynos5250-pinctrl.dtsi" / { compatible = "samsung,exynos5250"; diff --git a/doc/device-tree-bindings/samsung-pinctrl.txt b/doc/device-tree-bindings/samsung-pinctrl.txt new file mode 100644 index 0000000..708ca45 --- /dev/null +++ b/doc/device-tree-bindings/samsung-pinctrl.txt @@ -0,0 +1,253 @@ +Samsung GPIO and Pin Mux/Config controller + +Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware +controller. It controls the input/output settings on the available pads/pins +and also provides ability to multiplex and configure the output of various +on-chip controllers onto these pads. + +Required Properties: +- compatible: should be one of the following. + - "samsung,pinctrl": for Exynos compatible pin-controller. + +- reg: Base address of the pin controller hardware module and length of + the address space it occupies. + +- Pin banks as child nodes: Pin banks of the controller are represented by child + nodes of the controller node. Bank name is taken from name of the node. Each + bank node must contain following properties: + + - gpio-controller: identifies the node as a gpio controller and pin bank. + - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See generic + GPIO binding documentation for description of particular cells. + +- Pin mux/config groups as child nodes: The pin mux (selecting pin function + mode) and pin config (pull up/down, driver strength) settings are represented + as child nodes of the pin-controller node. There should be atleast one + child node and there is no limit on the count of these child nodes. + + The child node should contain a list of pin(s) on which a particular pin + function selection or pin configuration (or both) have to applied. This + list of pins is specified using the property name "samsung,pins". There + should be atleast one pin specfied for this property and there is no upper + limit on the count of pins that can be specified. The pins are specified + using pin names which are derived from the hardware manual of the SoC. As + an example, the pins in GPA0 bank of the pin controller can be represented + as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case. + The format of the pin names should be (as per the hardware manual) + "[pin bank name]-[pin number within the bank]". + + The pin function selection that should be applied on the pins listed in the + child node is specified using the "samsung,pin-function" property. The value + of this property that should be applied to each of the pins listed in the + "samsung,pins" property should be picked from the hardware manual of the SoC + for the specified pin group. This property is optional in the child node if + no specific function selection is desired for the pins listed in the child + node. The value of this property is used as-is to program the pin-controller + function selector register of the pin-bank. + + The child node can also optionally specify one or more of the pin + configuration that should be applied on all the pins listed in the + "samsung,pins" property of the child node. The following pin configuration + properties are supported. + + - samsung,pin-pud: Pull up/down configuration. + - samsung,pin-drv: Drive strength configuration. + - samsung,pin-pud-pdn: Pull up/down configuration in power down mode. + - samsung,pin-drv-pdn: Drive strength configuration in power down mode. + + The values specified by these config properties should be derived from the + hardware manual and these values are programmed as-is into the pin + pull up/down and driver strength register of the pin-controller. + + Note: A child should include atleast a pin function selection property or + pin configuration property (one or more) or both. + + The client nodes that require a particular pin function selection and/or + pin configuration should use the bindings listed in the "pinctrl-bindings.txt" + file. + +External GPIO and Wakeup Interrupts: + +The controller supports two types of external interrupts over gpio. The first +is the external gpio interrupt and second is the external wakeup interrupts. +The difference between the two is that the external wakeup interrupts can be +used as system wakeup events. + +A. External GPIO Interrupts: For supporting external gpio interrupts, the + following properties should be specified in the pin-controller device node. + + - interrupt-parent: phandle of the interrupt parent to which the external + GPIO interrupts are forwarded to. + - interrupts: interrupt specifier for the controller. The format and value of + the interrupt specifier depends on the interrupt parent for the controller. + + In addition, following properties must be present in node of every bank + of pins supporting GPIO interrupts: + + - interrupt-controller: identifies the controller node as interrupt-parent. + - #interrupt-cells: the value of this property should be 2. + - First Cell: represents the external gpio interrupt number local to the + external gpio interrupt space of the controller. + - Second Cell: flags to identify the type of the interrupt + - 1 = rising edge triggered + - 2 = falling edge triggered + - 3 = rising and falling edge triggered + - 4 = high level triggered + - 8 = low level triggered + +B. External Wakeup Interrupts: For supporting external wakeup interrupts, a + child node representing the external wakeup interrupt controller should be + included in the pin-controller device node. This child node should include + the following properties. + + - compatible: identifies the type of the external wakeup interrupt controller + The possible values are: + - samsung,wakeup-eint: represents wakeup interrupt controller + found on Samsung Exynos SoC. + - interrupt-parent: phandle of the interrupt parent to which the external + wakeup interrupts are forwarded to. + - interrupts: interrupt used by multiplexed wakeup interrupts. + + In addition, following properties must be present in node of every bank + of pins supporting wake-up interrupts: + + - interrupt-controller: identifies the node as interrupt-parent. + - #interrupt-cells: the value of this property should be 2 + - First Cell: represents the external wakeup interrupt number local to + the external wakeup interrupt space of the controller. + - Second Cell: flags to identify the type of the interrupt + - 1 = rising edge triggered + - 2 = falling edge triggered + - 3 = rising and falling edge triggered + - 4 = high level triggered + - 8 = low level triggered + + Node of every bank of pins supporting direct wake-up interrupts (without + multiplexing) must contain following properties: + + - interrupt-parent: phandle of the interrupt parent to which the external + wakeup interrupts are forwarded to. + - interrupts: interrupts of the interrupt parent which are used for external + wakeup interrupts from pins of the bank, must contain interrupts for all + pins of the bank. + +Aliases: + +All the pin controller nodes should be represented in the aliases node using +the following format 'pinctrl{n}' where n is a unique number for the alias. + +Example: A pin-controller node with pin banks: + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,pinctrl; + reg = <0x11400000 0x1000>; + interrupts = <0 47 0>; + + /* ... */ + + /* Pin bank without external interrupts */ + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + /* ... */ + + /* Pin bank with external GPIO or muxed wake-up interrupts */ + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ... */ + + /* Pin bank with external direct wake-up interrupts */ + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; + #interrupt-cells = <2>; + }; + + /* ... */ + }; + +Example 1: A pin-controller node with pin groups. + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = <0 47 0>; + + /* ... */ + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + }; + +Example 2: A pin-controller node with external wakeup interrupt controller node. + + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = <0 46 0> + + /* ... */ + + wakeup-interrupt-controller { + compatible = "samsung,wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; + }; + +Example 3: A uart client node that supports 'default' and 'flow-control' states. + + uart@13800000 { + compatible = "samsung,uart"; + reg = <0x13800000 0x100>; + interrupts = <0 52 0>; + pinctrl-names = "default", "flow-control; + pinctrl-0 = <&uart0_data>; + pinctrl-1 = <&uart0_data &uart0_fctl>; + }; diff --git a/include/fdtdec.h b/include/fdtdec.h index 77f244f..9c1bd82 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -81,6 +81,7 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS_EHCI, /* Exynos EHCI controller */ COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */ COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */ + COMPAT_SAMSUNG_PINCTRL, /* PINCTRL */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 3ae348d..16dbdcd 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -56,6 +56,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SAMSUNG_EXYNOS_EHCI, "samsung,exynos-ehci"), COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"), COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"), + COMPAT(SAMSUNG_PINCTRL, "samsung,pinctrl"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- 1.7.9.5

1 0

[U-Boot] [PATCH] powerpc/p1022ds: Add support for NAND and NAND boot using SPL
by Matthew McClintock 18 Feb '13

18 Feb '13

Add defines needed to access NAND, remove second flash bank that is actually connected to NAND. Add nand booting support for P1022DS with hardcoded DDR config using SPL framework from 2011 Signed-off-by: Matthew McClintock <msm(a)freescale.com> Signed-off-by: Jerry Huang <Chang-Ming.Huang(a)freescale.com> Signed-off-by: Jiang Yutang <b14898(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- board/freescale/common/Makefile | 6 ++ board/freescale/p1022ds/Makefile | 14 ++++ board/freescale/p1022ds/law.c | 1 + board/freescale/p1022ds/spl_minimal.c | 133 +++++++++++++++++++++++++++++++ board/freescale/p1022ds/tlb.c | 20 +++-- boards.cfg | 2 + drivers/video/Makefile | 2 + include/configs/P1022DS.h | 138 +++++++++++++++++++++++++++++---- 8 files changed, 296 insertions(+), 20 deletions(-) create mode 100644 board/freescale/p1022ds/spl_minimal.c diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 75725b4..72bb56c 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -33,10 +33,14 @@ COBJS-$(CONFIG_FSL_CADMUS) += cadmus.o COBJS-$(CONFIG_FSL_VIA) += cds_via.o COBJS-$(CONFIG_FMAN_ENET) += fman.o COBJS-$(CONFIG_FSL_PIXIS) += pixis.o +ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o +endif COBJS-$(CONFIG_FSL_QIXIS) += qixis.o COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o +ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o +endif COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o ifndef CONFIG_RAMBOOT_PBL COBJS-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o @@ -48,7 +52,9 @@ COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o +ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_P1022DS) += ics307_clk.o +endif COBJS-$(CONFIG_P2020DS) += ics307_clk.o COBJS-$(CONFIG_P3041DS) += ics307_clk.o COBJS-$(CONFIG_P4080DS) += ics307_clk.o diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile index c6d3418..0eeef05 100644 --- a/board/freescale/p1022ds/Makefile +++ b/board/freescale/p1022ds/Makefile @@ -11,12 +11,26 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL + +COBJS-y += spl_minimal.o tlb.o law.o + +else COBJS-y += $(BOARD).o COBJS-y += ddr.o COBJS-y += law.o COBJS-y += tlb.o COBJS-$(CONFIG_FSL_DIU_FB) += diu.o +endif SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/p1022ds/law.c b/board/freescale/p1022ds/law.c index b23b8f9..feee799 100644 --- a/board/freescale/p1022ds/law.c +++ b/board/freescale/p1022ds/law.c @@ -16,6 +16,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_8K, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c new file mode 100644 index 0000000..7dfc22c --- /dev/null +++ b/board/freescale/p1022ds/spl_minimal.c @@ -0,0 +1,133 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ns16550.h> +#include <asm/io.h> +#include <nand.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> + + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +void sdram_init(void) +{ + volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + + __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); + __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); +#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 + __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); + __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); +#endif + __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); + + __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); + + __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); + + __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); + __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); + __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl); + + /* Set, but do not enable the memory */ + __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, + &ddr->sdram_cfg); + + in_be32(&ddr->sdram_cfg); + udelay(500); + + /* Let the controller go */ + out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); + in_be32(&ddr->sdram_cfg); + + set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1); +} + +const static u32 sysclk_tbl[] = { + 66666000, 7499900, 83332500, 8999900, + 99999000, 11111000, 12499800, 13333200 +}; + +void board_init_f(ulong bootflag) +{ + int px_spd; + u32 plat_ratio, sys_clk, bus_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + +#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) + /* for FPGA */ + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); +#else +#error CONFIG_SYS_BR2_PRELIM, CONFIG_SYS_OR2_PRELIM must be defined +#endif + + /* initialize selected port with appropriate baud rate */ + px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); + sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK]; + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + bus_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + + /* Initialize the DDR3 */ + sdram_init(); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, + CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c index 71e71f7..3acc449 100644 --- a/board/freescale/p1022ds/tlb.c +++ b/board/freescale/p1022ds/tlb.c @@ -41,6 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), +#ifndef CONFIG_SPL_BUILD /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, @@ -67,24 +68,31 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), +#endif SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SYS_RAMBOOT - /* *I*G - eSDHC/eSPI/NAND boot */ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) + /* **** - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_1G, 1), - - /* map the second 1G */ + /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_1G, 1), #endif -# + +#ifdef CONFIG_SYS_NAND_BASE + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16K, 1), +#endif + }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 98f7a14..010e2d6 100644 --- a/boards.cfg +++ b/boards.cfg @@ -785,6 +785,8 @@ P1021RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freesca P1021RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SDCARD P1021RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SPIFLASH P1022DS powerpc mpc85xx p1022ds freescale +P1022DS_NAND powerpc mpc85xx p1022ds freescale - P1022DS:NAND +P1022DS_36BIT_NAND powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,NAND P1022DS_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:SPIFLASH P1022DS_36BIT_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SPIFLASH P1022DS_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:SDCARD diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 170a358..a1c7895 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -34,7 +34,9 @@ COBJS-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o COBJS-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \ exynos_mipi_dsi_lowlevel.o COBJS-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o +ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o +endif COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o COBJS-$(CONFIG_S6E63D6) += s6e63d6.o COBJS-$(CONFIG_LD9040) += ld9040.o diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 14d597a..c2623fc 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -34,6 +34,29 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif +#define CONFIG_NAND_FSL_ELBC + +#ifdef CONFIG_NAND +#define CONFIG_SPL +#define CONFIG_SPL_INIT_MINIMAL +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" + +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xfffff000 +#define CONFIG_SPL_MAX_SIZE (4 * 1024) +#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 +#define CONFIG_SPL_RELOC_STACK 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ @@ -84,6 +107,13 @@ #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k + SPL code*/ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif + + /* DDR Setup */ #define CONFIG_DDR_SPD #define CONFIG_VERY_BIG_RAM @@ -105,6 +135,30 @@ #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ +/* These are used when DDR doesn't use SPD. */ +#define CONFIG_SYS_SDRAM_SIZE 2048 +#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 +#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 +#define CONFIG_SYS_DDR_TIMING_3 0x00010000 +#define CONFIG_SYS_DDR_TIMING_0 0x40110104 +#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 +#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca +#define CONFIG_SYS_DDR_MODE_1 0x00441221 +#define CONFIG_SYS_DDR_MODE_2 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL 0x0a280100 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 +#define CONFIG_SYS_DDR_CONTROL 0xc7000008 +#define CONFIG_SYS_DDR_CONTROL_2 0x24401041 +#define CONFIG_SYS_DDR_TIMING_4 0x00220001 +#define CONFIG_SYS_DDR_TIMING_5 0x02401400 +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 + + /* * Memory map * @@ -118,6 +172,7 @@ * Localbus non-cacheable * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable + * 0xff80_0000 0xff80_1fff NAND 8K non-cacheable * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable @@ -126,38 +181,90 @@ /* * Local Bus Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull #else #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif #define CONFIG_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) +#ifdef CONFIG_NAND +#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#else #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#endif -#define CONFIG_SYS_BR1_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM - -#define CONFIG_SYS_FLASH_BANKS_LIST \ - {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 1024 +#ifndef CONFIG_SYS_MONITOR_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif +#endif #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO +/* Nand Flash */ +#if defined(CONFIG_NAND_FSL_ELBC) && !defined(CONFIG_FSL_DIU_FB) +#define CONFIG_SYS_NAND_BASE 0xff800000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) +#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE + +/* NAND flash config */ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ + | OR_FCM_PGS /* Large Page*/ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) +#ifdef CONFIG_NAND +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#else +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#endif + +#endif /* CONFIG_NAND_FSL_ELBC */ + +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_BR1_PRELIM \ + (BR_PHYS_ADDR(0xe0000000) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | 0xff7) +#endif + #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R @@ -177,6 +284,8 @@ #define PIXIS_LBMAP_SWITCH 7 #define PIXIS_LBMAP_MASK 0xF0 #define PIXIS_LBMAP_ALTBANK 0x20 +#define PIXIS_SPD 0x07 +#define PIXIS_SPD_SYSCLK_MASK 0x07 #define PIXIS_ELBC_SPI_MASK 0xc0 #define PIXIS_SPI 0x80 @@ -199,6 +308,9 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} @@ -419,7 +531,6 @@ /* * Environment */ -#ifdef CONFIG_SYS_RAMBOOT #ifdef CONFIG_RAMBOOT_SPIFLASH #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_BUS 0 @@ -433,16 +544,15 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 -#elif defined(CONFIG_NAND_U_BOOT) +#elif defined(CONFIG_NAND) #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) -#else +#elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 -#endif #else #define CONFIG_ENV_IS_IN_FLASH #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -- 1.7.9.7

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[U-Boot] trying to understand u-boot-nand.ais file for AM1808 exp kit
by Robert P. J. Day 18 Feb '13

18 Feb '13

i hope someone here can clear up what should be a simple question -- i'm trying to figure out what exactly is going on when building and flashing a u-boot image for my new AM1808 experimenter kit or, more accurately, someone else's modified version where the 8M of NOR flash has been replaced with 2G of NAND flash. i've downloaded the DaVinci PSP SDK (v03.22.00.02) and i'm trying to figure out what the prebuilt u-boot images mean, and what it means to flash them. the earlier PSP SDK used separate "ubl" and "u-boot" images, so i've seen examples of using the supplied windows-based sfh_OMAP-L138.exe utility to flash the board, in that it had to reference both binary files since, with that earlier PSP SDK, they were separate objects. with this current SDK, the build now creates a combination image, as explained in the User's Guide: "U-Boot included in this release will replace the UBL which was being used to copy U-Boot to external RAM." the contents of the ready-to-flash images directory in this PSP SDK is: u-boot-mmcsd.ais u-boot-mmcsd.bin u-boot-nand.ais u-boot-nor.bin u-boot-spi.ais so my questions are: 1) when one "flashes" these images to the board, where exactly are they being placed? in some SPI flash of some kind totally separate from the main NOR (or, in this case, NAND) flash? 2) given that the standard NOR flash has been replaced with NAND, which (now single) u-boot image file should i be flashing? i *think*, from the user guide, it would be u-boot-nand.ais, as the command for flashing to NAND flash is given as: > ..\sfh_OMAP-L138.exe -flash_noubl -flashType NAND <u-boot AIS file> it's just not clear what command i'd use for this situation, and where that single u-boot image would end up. rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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[U-Boot] [PATCH 0/1] Davinci: Make MAC address offset in EEPROM configurable
by Kim Bøndergaard 18 Feb '13

18 Feb '13

Like subjects say, offset of MAC adress in EEPROM changed from hardcoded value to a per board configurable value The following changes since commit 79af5f82d78b8bbc5fe81302b8a4b7fb5d880f25: Davinci: Fix, console output confusing while setting MAC address (2013-02-01 07:04:12 +0000) are available in the git repository at: git://gitorious.org/~kibo/u-boot-shr/kibos-u-boot kibo-master http://gitorious.org/~kibo/u-boot-shr/kibos-u-boot/commits/kibo-master Kim Bøndergaard (1): Davinci: Make MAC address offset in EEPROM configurable CONFIG_SYS_I2C_EEPROM_MAC_OFFSET arch/arm/cpu/arm926ejs/davinci/misc.c | 2 +- include/configs/da830evm.h | 1 + include/configs/davinci_dm365evm.h | 1 + include/configs/davinci_dm6467evm.h | 1 + include/configs/davinci_dvevm.h | 1 + include/configs/davinci_sffsdr.h | 1 + include/configs/davinci_sonata.h | 1 + 7 files changed, 7 insertions(+), 1 deletion(-) -- 1.8.0.3

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[U-Boot] [GIT PULL] Please pull u-boot-nds32/master into your branch
by Macpaul Lin 18 Feb '13

18 Feb '13

Hi Tom, Please pull a bug fix for the missing of including header which cause broken on NDS32 (board adp-ag102). Thanks, Macpaul Lin The following changes since commit ea6bd08b7717bf0d3f69ad9f016bf3b03b3eaf16: nds32: Add a basic errno.h (2013-02-18 15:29:07 +0800) are available in the git repository at: git://git.denx.de/u-boot-nds32.git master for you to fetch changes up to ea6bd08b7717bf0d3f69ad9f016bf3b03b3eaf16: nds32: Add a basic errno.h (2013-02-18 15:29:07 +0800) -- Best regards, Macpaul Lin

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[U-Boot] i.MX6: updates to support boards with multiple CPU options
by Eric Nelson 18 Feb '13

18 Feb '13

This set of patches simplifies the code for i.MX6 boards that support multiple processor options as discussed in this RFC: http://lists.denx.de/pipermail/u-boot/2013-January/#145562 Patch 1 is a simple whitespace change so that patch 2 passes checkpatch (ignoring long lines).

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[U-Boot] Notes from the U-Boot BOF Meeting in Geneva 2012/07/12
by Detlev Zundel 18 Feb '13

18 Feb '13

Hi, as promised, here are my expanded notes from the BoF meeting at LSM2012 last week. It was a pleasure to get some core developers into one room at the same time and discuss controversial topics without the health of any one attendant being in jeopardy at any time, so thanks again to everybody for making this meeting as successful as it was! [Note that this text expresses my understanding of the topics and thus may sometimes be slightly imprecise or bluntly wrong, so feel free to correct me where due :) ] * Tips on how to use JTAG to debug custom hardware that does not boot Some experiences on how to recover bricked hardware with the help of JTAG debuggers were exchanged. Some recurring problems one should be aware of in this area are: - Breakpoints on unintialized RAM - How to cope with relocation (e.g. reload symbols in gdb with an offset to the ELF symbol table as described in the Wiki) - Different system architectures, with different responsibilities to setup RAM - What is BootROM doing before U-Boot is running? Analyze the system at hand with respect to its expected boot sequence before hooking into it with a debugger. General rules seem to be hard to find for details as the early phases of booting vary greatly over the range of supported hardware in U-Boot. * U-Boot History visualized The history of the U-Boot repository was shown visualized with the help of the gource tool: http://code.google.com/p/gource/ Unfortunately the movie shown was 2.4GiB in size and found to be unsuitable for putting up on our webspace. We will look into producing a smaller version to publish. It is visually clear from the short movie, that the U-Boot community and the amount of interaction has grown substantially over time. The sheer amount of source files also grew in relation to that ;) * Patman As Simon Glass, the author of the 'patman' tool, was physically present, he agreed to give a short introduction to this tool recently added to the U-Boot repository: http://git.denx.de/?p=u-boot.git;a=tree;f=tools/patman In short, this tool allows to elegantly manage entire patch series over multiple iterations and easily send them to the mailing list. Controlled through meta-data included (but stripped from submission) in the git commit messages, it helps formally verifying patch series with checkpatch, tracking inter-submission changes and addressing the relevant mail recipients. It was agreed that the help to be gained from the tool was substantial and that it should get more exhibition in the documentation and among contributors. * Conflict resolution: setting up a moderator procedure for unhappy submitters A recent occurence on the mailing list where contributers were sent through multiple rounds of patch submissions for non-obvious reasons was used as a ground for discussing non-technical aspects of patch submissions. It was especially discussed that the privilege of being a custodian in U-Boot also brings obligations that should be defined more clearly. Essentially we would like to see somewhat "enforceable" rights for the "motor" of the project, i.e. for patch submitters. For this we should extend our documentation to clearly cover responsibility of custodiands. Require making constructive (testable) suggestions on how to get patch accepted when nak-ing patches for example. This can also be enforced by patch submitters by waiting for clear and precise suggestions for re-work. It was also found to be a good idea to document people willing to act as "moderators" for unhappy contributers, i.e. who can look into problems and try to moderate. (I would volunteer to be such a moderator). Currently the lack of any reaction whatsoever was identified to be a very discouraging sign for contributors. One thing we could do is to declare a "soft" time-limit (two weeks) that patches need to be looked at. After this time-limit, one could declare "backup-custodians" to push patches to or merge patches into some "-staging" branch. (What to do with that branch then?) For this to work, custodians would need to announce "off-times" which currently is not general consensus. * Patchwork pros / cons While talking about the patch submission process it became clear that the handling through patchwork still has some unsolved problems, the most obvious being the large backlog of patches in the archieve. It was agreed that automatic marking of changes as accepted when changes hit mainline would be a good thing. There is some info on our wiki available, although it is not clear who uses them: http://www.denx.de/wiki/view/U-Boot/Patches#pwclient and http://www.mail-archive.com/patchwork@lists.ozlabs.org/msg00057.html A tool to automatically mark patches as superceded on newer versions was also suggested to be very valuable. Unanswered questions: - What can patman do automatically? - Can gerrit help the workflow? During the discussion it showed that many people believe that patches outside the "regular" merge window are handled in-efficiently ending up as large piles in patchwork. It was agreed that rather then being a "accept / don't accept" division, it should be a "accept into mainline / accept into -next branches" split hopefully keeping the flow of incoming patches more uninterrupted. For this to work, every custodian would open his own "-next" branch and start merging patches from the mailing list resulting in patchwork becoming cleaner during "bug fix" phases. It was discussed whether to do some "automatic" merging of these per-custodian trees into a central next, but majority of people believed that the patch handling process should remain as unchanged as possible in sync with the "principle of least surprise". * Continuous integration Discussing such automatic merges, the need for continous integration became apparant. As mid- to longterm goals we would like to see automatic builds shifting the requirement to "do MAKEALL" from individual posters to (cheap) machine time. One obstacle on this way is the complexity of automatic builds for different architectures, i.e. which toolchain to use and how to use them correctly. It was agreed to be a good thing to collect Mike's cross-toolchains on denx.de and ease running MAKEALL. Especially add more switches to MAKEALL for toolchain selection, log-, build- directories. Turn interpretation of environment variables into switches to be more in line with "good unix practice". Simon Glass mentioned that he is working on "buildman" which he will present on the mailing list in due time. (Probably I forgot to mention the eldk-switch tool explicitely that also has a "database" to setup the ELDK environment for known targets: http://git.denx.de/?p=eldk-switch.git;a=summary Maybe it should be extended to cover other tool-chains also?) * Sandbox For people not being aware of the "user-space U-Boot", i.e. the sandbox configuration, Simon Glass described actual use cases for it in his work. He used it as an excellent test bed for generic code and tests not easy to setup on real hardware. During the discussion it became obvious that it may be a very good enabling tool for the "driver model" changes to come. It was also found to be a worthwhile aim to integrate it into the DUTS framework. (I will look into that when time allows). * U-Boot driver model Having some more time on our hands, Marek Vasut was asked to interactively present some aspects of his and his teams work for a driver model. Additional to the key concepts shown in his presentation on thursday, it became clear that it would be extremely helpful if the Linux and U-Boot driver model would be as close as possible to ease porting _and_ maintenance of drivers from the former to the latter. It appears that the Linux driver model lacks the late initialization needed by the U-Boot "initialize hardware only when needed" design goal. Achieving it was one motivation to not simply "clone" the Linux driver model. Although this and other details were discussed very intensly, it was more than obvious that a lot of current problems and limits of scalability of our code base can be alleviated with a solid driver model. All participants agreed to more closely review the documents available in Mareks git Repo: git://git.denx.de/u-boot-marex.git (dm branch, doc/driver-model/) Discussion of the driver model currently is hosted at a separate mailing list: http://lists.denx.de/mailman/listinfo/u-boot-dm Maybe the discussion should be moved completely to the "regular" users mailing list. * Followup Meetings Most participants expressed interest into further meetings of the U-Boot developers in the future, probably once a year. We will actively look for occassions more closely tied to the embedded community for this. Ok, this was actually agreed on after the first couple of beers, but still I believe it fits in here nicely ;) * Organizational info Attendants (in alphebetical order of first names) Anatolij Gustschin Detlev Zundel Fabio Estevam François Revol (Haiku project) Marek Vasut Mike Frysinger Simon Glass Stefan Roese Stefano Babic Tom Rini Wolfgang Grandegger I'm sorry that I missed the name of one other participant who uses U-Boot on a re-implemented Atari ST (Hatari?) project and gave some interesting "user" feedback on several topics. Cheers Detlev -- A language that doesn't affect the way you think about programming, is not worth knowing. -- Alan Perlis, Epigrams on Programming -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu(a)denx.de

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[U-Boot] How to generate an interrupt from u-boot
by VISWANADHULA BALAJI 18 Feb '13

18 Feb '13

Hi, Iam working on the samsung smdkv310 based soc. I want to generate an interrupt from the timer. Is it possible to service an interrupts at u-boot level. Smdkv310 board is having the GIC controller. Is there any patches to initialise the GIC(Generic interrupt controller). Please do needful. Thanks balaji

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