February 2013 - U-Boot

[U-Boot] [PATCH 1/4] sf: Add extended address register writing support
by Jagannadha Sutradharudu Teki 23 Feb '13

23 Feb '13

This patch provides support to program a flash extended address register. extended/bank address register contains an information to access the 4th byte addressing in 3-byte address mode. Currently added an extended/bank address register writing support for spansion flashes. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- drivers/mtd/spi/spi_flash.c | 41 ++++++++++++++++++++++++++++++++++ drivers/mtd/spi/spi_flash_internal.h | 6 +++++ 2 files changed, 47 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 00aece9..232ccc0 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -269,6 +269,47 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) return 0; } +int spi_flash_cmd_extaddr_write(struct spi_flash *flash, u8 ear) +{ + u8 cmd; + u8 idcode0; + int ret; + + ret = spi_flash_cmd(flash->spi, CMD_READ_ID, &idcode0, 1); + if (ret) { + debug("SF: fail to read read id\n"); + return ret; + } + + if (idcode0 == 0x01) + cmd = CMD_EXT_BRWR; + else { + printf("SF: unable to support extaddr reg write" + " for %s flash\n", flash->name); + return -1; + } + + ret = spi_flash_cmd_write_enable(flash); + if (ret < 0) { + debug("SF: enabling write failed\n"); + return ret; + } + + ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &ear, 1); + if (ret) { + debug("SF: fail to write ext addr register\n"); + return ret; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret < 0) { + debug("SF: write config register timed out\n"); + return ret; + } + + return 0; +} + /* * The following table holds all device probe functions * diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index 141cfa8..dbceb81 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -28,6 +28,9 @@ #define CMD_ERASE_64K 0xd8 #define CMD_ERASE_CHIP 0xc7 +/* Extended addr acess commands */ +#define CMD_EXT_BRWR 0x17 + /* Common status */ #define STATUS_WIP 0x01 @@ -77,6 +80,9 @@ static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) /* Program the status register. */ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr); +/* Program the extended address register */ +int spi_flash_cmd_extaddr_write(struct spi_flash *flash, u8 ear); + /* * Same as spi_flash_cmd_read() except it also claims/releases the SPI * bus. Used as common part of the ->read() operation. -- 1.7.4

1 0

[U-Boot] [PATCH] USB: drop unneeded header in ehci-mx6
by Stefano Babic 23 Feb '13

23 Feb '13

Including header for pads is not needed and breaks board after renaming pin definitions. Signed-off-by: Stefano Babic <sbabic(a)denx.de> --- drivers/usb/host/ehci-mx6.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 1b20e41..c1ae3d9 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -21,7 +21,6 @@ #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> -#include <asm/arch/mx6x_pins.h> #include <asm/imx-common/iomux-v3.h> #include "ehci.h" -- 1.7.9.5

1 0

[U-Boot] [PATCH] common: cmd_sata: Fix usage text for 'sata init'
by Fabio Estevam 23 Feb '13

23 Feb '13

From: Fabio Estevam <fabio.estevam(a)freescale.com> Currently sata usage text prints a double 'sata' for the init command. MX53LOCO U-Boot > sata sata - SATA sub system Usage: sata sata init - init SATA sub system sata info - show available SATA devices sata device [dev] - show or set current device sata part [dev] - print partition table sata read addr blk# cnt sata write addr blk# cnt Remove the extra 'sata' from the 'sata init' line. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- common/cmd_sata.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cmd_sata.c b/common/cmd_sata.c index b401bd1..8d57285 100644 --- a/common/cmd_sata.c +++ b/common/cmd_sata.c @@ -196,7 +196,7 @@ static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( sata, 5, 1, do_sata, "SATA sub system", - "sata init - init SATA sub system\n" + "init - init SATA sub system\n" "sata info - show available SATA devices\n" "sata device [dev] - show or set current device\n" "sata part [dev] - print partition table\n" -- 1.7.9.5

2 1

[U-Boot] [PATCH] mtd: nand: Check if NAND is locked tight before lock cmds
by Joe Hershberger 23 Feb '13

23 Feb '13

If the NAND is locked tight, commands such as lock and unlock will not work, but the NAND chip may not report an error. Check the lock tight status before attempting such operations so that an error status can be reported if we know the operation will not succeed. Signed-off-by: Joe Hershberger <joe.hershberger(a)ni.com> --- drivers/mtd/nand/nand_util.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 2ba0c5e..ff2d348 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -237,6 +237,14 @@ int nand_lock(struct mtd_info *mtd, int tight) /* select the NAND device */ chip->select_chip(mtd, 0); + /* check the Lock Tight Status */ + chip->cmdfunc(mtd, NAND_CMD_LOCK_STATUS, -1, 0); + if (chip->read_byte(mtd) & NAND_LOCK_STATUS_TIGHT) { + printf("nand_lock: Device is locked tight!\n"); + ret = -1; + goto out; + } + chip->cmdfunc(mtd, (tight ? NAND_CMD_LOCK_TIGHT : NAND_CMD_LOCK), -1, -1); @@ -249,6 +257,7 @@ int nand_lock(struct mtd_info *mtd, int tight) ret = -1; } + out: /* de-select the NAND device */ chip->select_chip(mtd, -1); return ret; @@ -337,6 +346,15 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length, goto out; } + /* check the Lock Tight Status */ + page = (int)(start >> chip->page_shift); + chip->cmdfunc(mtd, NAND_CMD_LOCK_STATUS, -1, page & chip->pagemask); + if (chip->read_byte(mtd) & NAND_LOCK_STATUS_TIGHT) { + printf("nand_unlock: Device is locked tight!\n"); + ret = -1; + goto out; + } + if ((start & (mtd->erasesize - 1)) != 0) { printf("nand_unlock: Start address must be beginning of " "nand block!\n"); @@ -358,7 +376,6 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length, length -= mtd->erasesize; /* submit address of first page to unlock */ - page = (int)(start >> chip->page_shift); chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); /* submit ADDRESS of LAST page to unlock */ -- 1.7.11.5

2 1

[U-Boot] [PATCH] nand: fix nand read.option parsing
by Harvey Chapman 23 Feb '13

23 Feb '13

"nand read.part addr off size" would be treated as "nand read.raw addr off 1" It now fails as intended stating "Unknown nand command suffix '.part'" Signed-off-by: Harvey Chapman <hchapman(a)3gfp.com> --- common/cmd_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 1568594..495610c 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -608,7 +608,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) size_t rwsize; ulong pagecount = 1; int read; - int raw; + int raw = 0; if (argc < 4) goto usage; -- 1.7.10.4

2 1

[U-Boot] [PATCH v4] imls: Add support to list images in NAND device
by Vipin Kumar 22 Feb '13

22 Feb '13

This patch adds support to list images in NAND flash through imls Signed-off-by: Vipin Kumar <vipin.kumar(a)st.com> --- Changes in v4 - Keep stdout dumps in one line - Continue even after read errors for all the blocks README | 3 +- common/cmd_bootm.c | 167 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 166 insertions(+), 4 deletions(-) diff --git a/README b/README index 2077c3b..46fd21d 100644 --- a/README +++ b/README @@ -831,7 +831,8 @@ The following options need to be configured: CONFIG_CMD_I2C * I2C serial bus support CONFIG_CMD_IDE * IDE harddisk support CONFIG_CMD_IMI iminfo - CONFIG_CMD_IMLS List all found images + CONFIG_CMD_IMLS List all images found in NOR flash + CONFIG_CMD_IMLS_NAND List all images found in NAND flash CONFIG_CMD_IMMAP * IMMR dump support CONFIG_CMD_IMPORTENV * import an environment CONFIG_CMD_INI * import data from an ini file into the env diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index d256ddf..938e500 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -80,9 +80,15 @@ static int image_info(unsigned long addr); #include <flash.h> #include <mtd/cfi_flash.h> extern flash_info_t flash_info[]; /* info for FLASH chips */ +#endif + +#if defined(CONFIG_CMD_IMLS) || defined(CONFIG_CMD_IMLS_NAND) static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); #endif +#include <linux/err.h> +#include <nand.h> + #ifdef CONFIG_SILENT_CONSOLE static void fixup_silent_linux(void); #endif @@ -1175,7 +1181,7 @@ U_BOOT_CMD( /* imls - list all images found in flash */ /*******************************************************************/ #if defined(CONFIG_CMD_IMLS) -static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_imls_nor(void) { flash_info_t *info; int i, j; @@ -1224,6 +1230,161 @@ next_sector: ; } next_bank: ; } + return 0; +} +#endif + +#if defined(CONFIG_CMD_IMLS_NAND) +static int nand_imls_legacyimage(nand_info_t *nand, int nand_dev, loff_t off, + size_t len) +{ + void *imgdata; + int ret; + + imgdata = malloc(len); + if (!imgdata) { + printf("May be a Legacy Image at NAND device %d offset %08llX:\n", + nand_dev, off); + printf(" Low memory(cannot allocate memory for image)\n"); + return -ENOMEM; + } + + ret = nand_read_skip_bad(nand, off, &len, + imgdata); + if (ret < 0 && ret != -EUCLEAN) { + free(imgdata); + return ret; + } + + if (!image_check_hcrc(imgdata)) { + free(imgdata); + return 0; + } + + printf("Legacy Image at NAND device %d offset %08llX:\n", + nand_dev, off); + image_print_contents(imgdata); + + puts(" Verifying Checksum ... "); + if (!image_check_dcrc(imgdata)) + puts("Bad Data CRC\n"); + else + puts("OK\n"); + + free(imgdata); + + return 0; +} + +static int nand_imls_fitimage(nand_info_t *nand, int nand_dev, loff_t off, + size_t len) +{ + void *imgdata; + int ret; + + imgdata = malloc(len); + if (!imgdata) { + printf("May be a FIT Image at NAND device %d offset %08llX:\n", + nand_dev, off); + printf(" Low memory(cannot allocate memory for image)\n"); + return -ENOMEM; + } + + ret = nand_read_skip_bad(nand, off, &len, + imgdata); + if (ret < 0 && ret != -EUCLEAN) { + free(imgdata); + return ret; + } + + if (!fit_check_format(imgdata)) { + free(imgdata); + return 0; + } + + printf("FIT Image at NAND device %d offset %08llX:\n", nand_dev, off); + + fit_print_contents(imgdata); + free(imgdata); + + return 0; +} + +static int do_imls_nand(void) +{ + nand_info_t *nand; + int nand_dev = nand_curr_device; + size_t len; + loff_t off; + u32 buffer[16]; + + if (nand_dev < 0 || nand_dev >= CONFIG_SYS_MAX_NAND_DEVICE) { + puts("\nNo NAND devices available\n"); + return -ENODEV; + } + + printf("\n"); + + for (nand_dev = 0; nand_dev < CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) { + nand = &nand_info[nand_dev]; + if (!nand->name || !nand->size) + continue; + + for (off = 0; off < nand->size; off += nand->erasesize) { + const image_header_t *header; + int ret; + + if (nand_block_isbad(nand, off)) + continue; + + len = sizeof(buffer); + + ret = nand_read(nand, off, &len, (u8 *)buffer); + if (ret < 0 && ret != -EUCLEAN) { + printf("NAND read error %d at offset %08llX\n", + ret, off); + continue; + } + + switch (genimg_get_format(buffer)) { + case IMAGE_FORMAT_LEGACY: + header = (const image_header_t *)buffer; + + len = image_get_image_size(header); + nand_imls_legacyimage(nand, nand_dev, off, len); + break; +#if defined(CONFIG_FIT) + case IMAGE_FORMAT_FIT: + len = fit_get_size(buffer); + nand_imls_fitimage(nand, nand_dev, off, len); + break; +#endif + } + } + } + + return 0; +} +#endif + +#if defined(CONFIG_CMD_IMLS) || defined(CONFIG_CMD_IMLS_NAND) +static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int ret_nor = 0, ret_nand = 0; + +#if defined(CONFIG_CMD_IMLS) + ret_nor = do_imls_nor(); +#endif + +#if defined(CONFIG_CMD_IMLS_NAND) + ret_nand = do_imls_nand(); +#endif + + if (ret_nor) + return ret_nor; + + if (ret_nand) + return ret_nand; return (0); } @@ -1232,8 +1393,8 @@ U_BOOT_CMD( imls, 1, 1, do_imls, "list all images found in flash", "\n" - " - Prints information about all images found at sector\n" - " boundaries in flash." + " - Prints information about all images found at sector/block\n" + " boundaries in nor/nand flash." ); #endif -- 1.8.0

2 4

[U-Boot] [PATCH] mxs: timrot: Add support to i.MX23
by Fadil Berisha 22 Feb '13

22 Feb '13

From: Fadil Berisha <f.koliqi(a)gmail.com> This patch add timer support to i.MX23 and complete bit fields and values on regs-timrot.h. Testet on imx23-olinuxino board. Signed-off-by: Fadil Berisha <f.koliqi(a)gmail.com> --- arch/arm/cpu/arm926ejs/mxs/timer.c | 19 +++++- arch/arm/include/asm/arch-mxs/regs-timrot.h | 91 +++++++++++++++++++++++++++ 2 files changed, 108 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c index 4ed75e6..a99b122 100644 --- a/arch/arm/cpu/arm926ejs/mxs/timer.c +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c @@ -32,7 +32,11 @@ #include <asm/arch/sys_proto.h> /* Maximum fixed count */ -#define TIMER_LOAD_VAL 0xffffffff +#if defined(CONFIG_MX23) +#define TIMER_LOAD_VAL 0xffff +#elif defined(CONFIG_MX28) +#define TIMER_LOAD_VAL 0xffffffff +#endif DECLARE_GLOBAL_DATA_PTR; @@ -77,7 +81,11 @@ int timer_init(void) &timrot_regs->hw_timrot_timctrl0); /* Set fixed_count to maximal value */ +#if defined(CONFIG_MX23) + writel(TIMER_LOAD_VAL-1, HW_TIMROT_TIMCOUNT0); +#elif defined(CONFIG_MX28) writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); +#endif return 0; } @@ -86,9 +94,16 @@ unsigned long long get_ticks(void) { struct mxs_timrot_regs *timrot_regs = (struct mxs_timrot_regs *)MXS_TIMROT_BASE; + uint32_t now; /* Current tick value */ - uint32_t now = readl(&timrot_regs->hw_timrot_running_count0); +#if defined(CONFIG_MX23) + /* upper bits are the valid */ + now = (readl(HW_TIMROT_TIMCOUNT0) >> + TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET); +#elif defined(CONFIG_MX28) + now = readl(&timrot_regs->hw_timrot_running_count0); +#endif if (lastdec >= now) { /* diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h index 529a3bc..400259a 100644 --- a/arch/arm/include/asm/arch-mxs/regs-timrot.h +++ b/arch/arm/include/asm/arch-mxs/regs-timrot.h @@ -71,7 +71,11 @@ struct mxs_timrot_regs { #define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) #define TIMROT_ROTCTRL_POLARITY_B (1 << 9) #define TIMROT_ROTCTRL_POLARITY_A (1 << 8) +#if defined(CONFIG_MX23) +#define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4) +#elif defined(CONFIG_MX28) #define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4) +#endif #define TIMROT_ROTCTRL_SELECT_B_OFFSET 4 #define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4) @@ -79,12 +83,21 @@ struct mxs_timrot_regs { #define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4) +#if defined(CONFIG_MX23) +#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x6 << 4) +#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0x7 << 4) +#elif defined(CONFIG_MX28) #define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4) #define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4) #define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4) +#endif +#if defined(CONFIG_MX23) +#define TIMROT_ROTCTRL_SELECT_A_MASK 0x7 +#elif defined(CONFIG_MX28) #define TIMROT_ROTCTRL_SELECT_A_MASK 0xf +#endif #define TIMROT_ROTCTRL_SELECT_A_OFFSET 0 #define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0 #define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1 @@ -92,18 +105,25 @@ struct mxs_timrot_regs { #define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3 #define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4 #define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5 +#if defined(CONFIG_MX23) +#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x6 +#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0x7 +#elif defined(CONFIG_MX28) #define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6 #define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7 #define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8 #define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9 #define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa +#endif #define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff #define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0 #define TIMROT_TIMCTRLn_IRQ (1 << 15) #define TIMROT_TIMCTRLn_IRQ_EN (1 << 14) +#if defined(CONFIG_MX28) #define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11) +#endif #define TIMROT_TIMCTRLn_POLARITY (1 << 8) #define TIMROT_TIMCTRLn_UPDATE (1 << 7) #define TIMROT_TIMCTRLn_RELOAD (1 << 6) @@ -121,6 +141,15 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRLn_SELECT_PWM2 0x3 #define TIMROT_TIMCTRLn_SELECT_PWM3 0x4 #define TIMROT_TIMCTRLn_SELECT_PWM4 0x5 +#if defined(CONFIG_MX23) +#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x6 +#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0x7 +#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0x8 +#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0x9 +#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xa +#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xb +#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xc +#elif defined(CONFIG_MX28) #define TIMROT_TIMCTRLn_SELECT_PWM5 0x6 #define TIMROT_TIMCTRLn_SELECT_PWM6 0x7 #define TIMROT_TIMCTRLn_SELECT_PWM7 0x8 @@ -131,15 +160,29 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd #define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe #define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf +#endif +#if defined(CONFIG_MX23) +#define HW_TIMROT_TIMCOUNT0 0x80068030 +#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16) +#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16 +#elif defined(CONFIG_MX28) #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0 +#endif +#if defined(CONFIG_MX23) +#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffff +#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 +#elif defined(CONFIG_MX28) #define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff #define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 +#endif +#if defined(CONFIG_MX28) #define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff #define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0 +#endif #define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16 @@ -149,6 +192,15 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16) +#if defined(CONFIG_MX23) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0x9 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16) +#elif defined(CONFIG_MX28) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16) @@ -159,7 +211,46 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) +#endif +#if defined(CONFIG_MX23) +#define TIMROT_TIMCTRL3_IRQ (1 << 15) +#define TIMROT_TIMCTRL3_IRQ_EN (1 << 14) +#define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10) +#endif #define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) +#if defined(CONFIG_MX23) +#define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8) +#define TIMROT_TIMCTRL3_POLARITY_OFFSET 8 +#define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8) +#define TIMROT_TIMCTRL3_POLARITY_NEGATIVE (0x1 << 8) +#define TIMROT_TIMCTRL3_UPDATE (1 << 7) +#define TIMROT_TIMCTRL3_RELOAD (1 << 6) +#define TIMROT_TIMCTRL3_PRESCALE_MASK (0x3 << 4) +#define TIMROT_TIMCTRL3_PRESCALE_OFFSET 4 +#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1 (0x0 << 4) +#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2 (0x1 << 4) +#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4 (0x2 << 4) +#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8 (0x3 << 4) +#define TIMROT_TIMCTRL3_SELECT_MASK 0xf +#define TIMROT_TIMCTRL3_SELECT_OFFSET 0 +#define TIMROT_TIMCTRL3_SELECT_NEVER_TICK 0x0 +#define TIMROT_TIMCTRL3_SELECT_PWM0 0x1 +#define TIMROT_TIMCTRL3_SELECT_PWM1 0x2 +#define TIMROT_TIMCTRL3_SELECT_PWM2 0x3 +#define TIMROT_TIMCTRL3_SELECT_PWM3 0x4 +#define TIMROT_TIMCTRL3_SELECT_PWM4 0x5 +#define TIMROT_TIMCTRL3_SELECT_ROTARYA 0x6 +#define TIMROT_TIMCTRL3_SELECT_ROTARYB 0x7 +#define TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL 0x8 +#define TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL 0x9 +#define TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL 0xa +#define TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL 0xb +#define TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS 0xc +#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK (0xffff << 16) +#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET 16 +#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK 0xffff +#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET 0 +#endif #define TIMROT_VERSION_MAJOR_MASK (0xff << 24) #define TIMROT_VERSION_MAJOR_OFFSET 24 -- 1.7.10

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[U-Boot] fw_setenv on protected flash
by Eibach, Dirk 22 Feb '13

22 Feb '13

Some of your recent cfi flash driver enhancements have made flash protect/unprotect work on our NOR based platforms (S29GL512). Good news so far, but as a consequence fw_setenv is woking no more: MTD erase error on /dev/mtd5: Input/output error Error: can't write fw_env to flash Also flash_unlock from mtd_utils is not doing the trick: Could not unlock MTD device: /dev/mtd5 Unprotecting flash in u-boot before booting linux makes this work, but this is probably no good idea. So what is the recommended workflow for fw_setenv on protected flash? Cheers Dirk ------------------------------------------------------------------------------------------------ Messe-Highlights 2013. Wir freuen uns auf Ihren Besuch. Broadcast Video Expo 2013 London - 26.02. bis 28.02.2013 - Stand B22 CeBIT 2013 In Hannover - 05.03. bis 09.03.2012 - Halle 11, Stand D31 ATC Global 2013 Amsterdam - 12.03. bis 14.03.2012 - Halle 10, Stand D202 ------------------------------------------------------------------------------------------------ Besuchen Sie unseren Blog auf http://blog.gdsys.de oder folgen Sie uns auf: twitter: http://twitter.com/#!/gdsys facebook: http://www.facebook.com/pages/Guntermann-Drunck-GmbH/318396891518396 Google+ : https://plus.google.com/100228872787564309232/ YouTube: http://www.youtube.com/user/GuntermannDrunck ------------------------------------------------------------------------------------------------ Guntermann & Drunck GmbH Systementwicklung Dortmunder Str. 4a D-57234 Wilnsdorf - Germany Tel: +49 (0) 27 39 / 89 01 - 100 Fax: +49 (0) 27 39 / 89 01 - 120 E-Mail: sales(a)gdsys.de - Web: www.gdsys.de ------------------------------------------------------------------------------------------------ Geschaftsfuhrer: Udo Guntermann - Martin Drunck - Reiner Ruelmann HRB 2884, Amtsgericht Siegen - WEEE-Reg.-Nr. DE30763240 USt.-Id.-Nr. DE 126575222 - Steuer-Nr. 342 / 5835 / 1041 ------------------------------------------------------------------------------------------------ DQS-zertifiziert nach ISO 9001:2008 ------------------------------------------------------------------------------------------------

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[U-Boot] Problems around fatwrite command from uboot
by Jean Louis 22 Feb '13

22 Feb '13

Hi, I use the last uboot from your git and boot with it on AM3517 EVM from SD card without NAND. I use this option in uboot config : #define CONFIG_FAT_WRITE 1 I use intensively fatload / fatwrite commands at the boot before kernel loading. Sometimes, in about 2% of cases of boot, the FAT becomes inconsistent and I have systematically these messages at boot when I use fatwrite command : U-Boot 2013.01-gd3b9a66-dirty (Feb 21 2013 - 11:02:33) ... writing MODIFYME.001 mmc_send_cmd: timedout waiting on cmd inhibit to clear mmc_send_cmd: timedout waiting on cmd inhibit to clear mmc_send_cmd: timedout waiting on cmd inhibit to clear mmc_send_cmd: timedout waiting on cmd inhibit to clear mmc_send_cmd: timedout waiting on cmd inhibit to clear mmc_send_cmd: timedout waiting on cmd inhibit to clear mmc_send_cmd: timedout waiting on cmd inhibit to clear mmc_send_cmd: timedout waiting on cmd inhibit to clear mmc_send_cmd: timedout waiting on cmd inhibit to clear mmc_send_cmd: timedout waiting on cmd inhibit to clear mmc_send_cmd: timedout waiting on cmd inhibit to clear 42428 bytes written ... unlike that is said at the last line, the file is not written. If I run a 'fatls' command before this fatwrite, I see the same file 'modifyme.001' twice : AM3517_EVM # fatls mmc 0:1 42428 mlo 261332 u-boot.bin 2 modifyme.001 2 modifyme.001 2644996 uimage ... After the board boot on linux, I run this command to repair FAT part: umount /dev/mmcblk0p1 ; fsck.vfat -a -w -v /dev/mmcblk0p1 dosfsck 2.11 (12 Mar 2005) dosfsck 2.11, 12 Mar 2005, FAT32, LFN Checking we can access the last sector of the filesystem Boot sector contents: System ID "MSDOS5.0" Media byte 0xf8 (hard disk) 512 bytes per logical sector 4096 bytes per cluster 34 reserved sectors First FAT starts at byte 17408 (sector 34) 2 FATs, 32 bit entries 321024 bytes per FAT (= 627 sectors) Root directory start at cluster 2 (arbitrary size) Data area starts at byte 659456 (sector 1288) 80156 data clusters (328318976 bytes) 63 sectors/track, 255 heads 63 hidden sectors 642537 sectors total Wrong checksum for long file name "modifyme.001". (Short name MODIFYME.001 may have changed without updating the long name) Not auto-correcting this. /modifyme.001 Contains a free cluster (3081). Assuming EOF. /modifyme.001 File size is 2 bytes, cluster chain length is 0 bytes. Truncating file to 0 bytes. Reclaiming unconnected clusters. Checking free cluster summary. Performing changes. /dev/mmcblk0p1: 24 files, 3487/80156 clusters As you can see in this return, the error 'Wrong checksum for long file name "modifyme.001"' often appears after use of fatwrite command at the boot. After the part is repaired, I reboot the board and uboot run as infinite loop after the fatwrite command : writing MODIFYME.001 error: overflow occurs error: overflow occurs error: overflow occurs error: overflow occurs error: overflow occurs ... ( seems to be error in source code at disk_write() /* Write FAT buf */ in flush_fat_buffer() ) I do an electrical off / on of my board during this infinite loop and the next boot seems okay but the file is once again corrupted, we can see that the count is incorrect (4096 and not 42428) : ... 42428 bytes read in 6 ms (6.7 MiB/s) writing MODIFYME.001 4096 bytes written ... A fatload at the next boot says 'Invalid FAT Entry' : ... reading MODIFYME.001 Invalid FAT entry ... If I try to fatwrite an another file in this situation, I fall in the first case ( mmc_send_cmd: timedout waiting on cmd inhibit to clear ) I think that the fatwrite command is potentially incomplete maybe around : - free cluster summary - second FAT entry - short/long filenames - deleted files entries any help appreciated Best regards, Jean Louis. (France)

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[U-Boot] [PATCH] Tegra30: fdt: Sync DT nodes with kernel DT files (I2C, SPI, GPIO, clock)
by Tom Warren 22 Feb '13

22 Feb '13

Minor edits to clock, apbdma and SPI, make I2C match kernel DT, and add gpio Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- arch/arm/dts/tegra30.dtsi | 90 ++++++++++++++++++++++------------- board/nvidia/dts/tegra30-cardhu.dts | 5 ++ 2 files changed, 61 insertions(+), 34 deletions(-) diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index 561c617..9483e80 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -3,8 +3,8 @@ / { compatible = "nvidia,tegra30"; - tegra_car: clock@60006000 { - compatible = "nvidia,tegra30-car", "nvidia,tegra20-car"; + tegra_car: clock { + compatible = "nvidia,tegra30-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; }; @@ -44,51 +44,79 @@ 0 141 0x04 0 142 0x04 0 143 0x04>; + clocks = <&tegra_car 34>; + }; + + gpio: gpio { + compatible = "nvidia,tegra30-gpio"; + reg = <0x6000d000 0x1000>; + interrupts = <0 32 0x04 + 0 33 0x04 + 0 34 0x04 + 0 35 0x04 + 0 55 0x04 + 0 87 0x04 + 0 89 0x04 + 0 125 0x04>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; }; i2c@7000c000 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c000 0x100>; + interrupts = <0 38 0x04>; #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000C000 0x100>; - /* PERIPH_ID_I2C1, CLK_M */ - clocks = <&tegra_car 12>; + clocks = <&tegra_car 12>, <&tegra_car 182>; + clock-names = "div-clk", "fast-clk"; + status = "disabled"; }; i2c@7000c400 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c400 0x100>; + interrupts = <0 84 0x04>; #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000C400 0x100>; - /* PERIPH_ID_I2C2, CLK_M */ - clocks = <&tegra_car 54>; + clocks = <&tegra_car 54>, <&tegra_car 182>; + clock-names = "div-clk", "fast-clk"; + status = "disabled"; }; i2c@7000c500 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c500 0x100>; + interrupts = <0 92 0x04>; #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000C500 0x100>; - /* PERIPH_ID_I2C3, CLK_M */ - clocks = <&tegra_car 67>; + clocks = <&tegra_car 67>, <&tegra_car 182>; + clock-names = "div-clk", "fast-clk"; + status = "disabled"; }; i2c@7000c700 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c700 0x100>; + interrupts = <0 120 0x04>; #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000C700 0x100>; - /* PERIPH_ID_I2C4, CLK_M */ - clocks = <&tegra_car 103>; + clocks = <&tegra_car 103>, <&tegra_car 182>; + clock-names = "div-clk", "fast-clk"; + status = "disabled"; }; i2c@7000d000 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000d000 0x100>; + interrupts = <0 53 0x04>; #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000D000 0x100>; - /* PERIPH_ID_I2C_DVC, CLK_M */ - clocks = <&tegra_car 47>; + clocks = <&tegra_car 47>, <&tegra_car 182>; + clock-names = "div-clk", "fast-clk"; + status = "disabled"; }; spi@7000d400 { @@ -98,9 +126,8 @@ nvidia,dma-request-selector = <&apbdma 15>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; - /* PERIPH_ID_SBC1, PLLP_OUT0 */ clocks = <&tegra_car 41>; + status = "disabled"; }; spi@7000d600 { @@ -110,9 +137,8 @@ nvidia,dma-request-selector = <&apbdma 16>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; - /* PERIPH_ID_SBC2, PLLP_OUT0 */ clocks = <&tegra_car 44>; + status = "disabled"; }; spi@7000d800 { @@ -122,9 +148,8 @@ nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; - /* PERIPH_ID_SBC3, PLLP_OUT0 */ clocks = <&tegra_car 46>; + status = "disabled"; }; spi@7000da00 { @@ -134,9 +159,8 @@ nvidia,dma-request-selector = <&apbdma 18>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; - /* PERIPH_ID_SBC4, PLLP_OUT0 */ clocks = <&tegra_car 68>; + status = "disabled"; }; spi@7000dc00 { @@ -146,9 +170,8 @@ nvidia,dma-request-selector = <&apbdma 27>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; - /* PERIPH_ID_SBC5, PLLP_OUT0 */ clocks = <&tegra_car 104>; + status = "disabled"; }; spi@7000de00 { @@ -158,8 +181,7 @@ nvidia,dma-request-selector = <&apbdma 28>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; - /* PERIPH_ID_SBC6, PLLP_OUT0 */ clocks = <&tegra_car 105>; + status = "disabled"; }; }; diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts index 778e513..48039c9 100644 --- a/board/nvidia/dts/tegra30-cardhu.dts +++ b/board/nvidia/dts/tegra30-cardhu.dts @@ -20,22 +20,27 @@ }; i2c@7000c000 { + status = "okay"; clock-frequency = <100000>; }; i2c@7000c400 { + status = "okay"; clock-frequency = <100000>; }; i2c@7000c500 { + status = "okay"; clock-frequency = <100000>; }; i2c@7000c700 { + status = "okay"; clock-frequency = <100000>; }; i2c@7000d000 { + status = "okay"; clock-frequency = <100000>; }; -- 1.7.0.4

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