December 2013 - U-Boot

[U-Boot] [PATCH] common, env: optimize boottime
by Heiko Schocher 14 Jan '14

14 Jan '14

when creating the hashtable, for each environmentvariable getenv(ENV_CALLBACK_VAR) and getenv(ENV_FLAGS_VAR) is called, which costs at this point a lot of time. So call this two getenv() calls only once. Boottime on the ids8313 board without this patch: 2013-12-19 13:38:22,894: NAND: 128 MiB 2013-12-19 13:38:27,659: In: serial (~4.8 sec) Bootime with this patch on the ids8313 board: 2013-12-19 13:40:25,332: NAND: 128 MiB 2013-12-19 13:40:25,546: In: serial (~0.2 sec) Signed-off-by: Heiko Schocher <hs(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Wolfgang Denk <wd(a)denx.de> --- common/env_callback.c | 9 ++++++++- common/env_flags.c | 8 +++++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/common/env_callback.c b/common/env_callback.c index 34bb58e..d03fa03 100644 --- a/common/env_callback.c +++ b/common/env_callback.c @@ -35,6 +35,9 @@ static struct env_clbk_tbl *find_env_callback(const char *name) return NULL; } +static int first_call = 1; +static const char *callback_list; + /* * Look for a possible callback for a newly added variable * This is called specifically when the variable did not exist in the hash @@ -43,11 +46,15 @@ static struct env_clbk_tbl *find_env_callback(const char *name) void env_callback_init(ENTRY *var_entry) { const char *var_name = var_entry->key; - const char *callback_list = getenv(ENV_CALLBACK_VAR); char callback_name[256] = ""; struct env_clbk_tbl *clbkp; int ret = 1; + if (first_call) { + callback_list = getenv(ENV_CALLBACK_VAR); + first_call = 0; + } + /* look in the ".callbacks" var for a reference to this variable */ if (callback_list != NULL) ret = env_attr_lookup(callback_list, var_name, callback_name); diff --git a/common/env_flags.c b/common/env_flags.c index e9b72e6..985f92e 100644 --- a/common/env_flags.c +++ b/common/env_flags.c @@ -395,6 +395,9 @@ static int env_parse_flags_to_bin(const char *flags) return binflags; } +static int first_call = 1; +static const char *flags_list; + /* * Look for possible flags for a newly added variable * This is called specifically when the variable did not exist in the hash @@ -403,10 +406,13 @@ static int env_parse_flags_to_bin(const char *flags) void env_flags_init(ENTRY *var_entry) { const char *var_name = var_entry->key; - const char *flags_list = getenv(ENV_FLAGS_VAR); char flags[ENV_FLAGS_ATTR_MAX_LEN + 1] = ""; int ret = 1; + if (first_call) { + flags_list = getenv(ENV_FLAGS_VAR); + first_call = 0; + } /* look in the ".flags" and static for a reference to this variable */ ret = env_flags_lookup(flags_list, var_name, flags); -- 1.8.3.1

2 1

[U-Boot] BCH8 support when we do not have ELM h/w engine.
by Enric Balletbo Serra 14 Jan '14

14 Jan '14

Dear Pekon, I'm trying to enable the support for BCH8 for platforms that do not have ELM hardware engine. Maybe I'm missing something but my first and quick attempt was applying the following patch: http://pastebin.com/VUjuGChR With this patch I'm able to switch to OMAP_ECC_BCH8_CODE_HW_DETECTION_SW with the nandecc hw bch8 command. Then I tried to flash a ubi rootfs into the nand, but the kernel can't mount the filesystem, I see messages like that: [ 3.703582] ecc unrecoverable error [ 3.707244] UBI warning: ubi_io_read: error -74 (ECC error) while reading 64 bytes from PEB 2:0, read only 64 bytes, retry OTOH, if I flash the rootfs from the kernel (my board sets the ecc to bch8) I don't have any problem, I can mount without problems. I saw that the OOB layout is not the same when I flash the rootfs from the u-boot or from the kernel. For example: If the rootfs is flashed from the kernel the OOB data is like that: U-Boot # nand dump.oob 0x680000 Page 00680000 dump: OOB: ff ff 79 43 68 64 3b 80 b2 46 49 4d 58 2a 6d ff 52 3f 7d 2a 7f a2 98 70 57 32 30 35 c7 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff If the rootfs is flashed for the u-boot the OOB data is like data: Page 00680000 dump: OOB: ff ff 79 43 68 64 3b 80 b2 46 49 4d 58 2a 6d 52 3f 7d 2a 7f a2 98 70 57 32 30 35 c7 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff Note that look the same except after byte number 16. In the first case is ff 52 3f 7d 2a 7f a2 98 70 and in the second case is 52 3f 7d 2a 7f a2 98 70 It's possible that something is wrong writting the OOB data ? Any clue ? I'm in the right direction or completely wrong ? Thanks in advance, Enric

2 6

[U-Boot] [PATCH] arm: use canonical sub mnemonic
by Andreas Bießmann 14 Jan '14

14 Jan '14

Building some arm boards with older binutils may produce errors like this: ---8<--- crt0.S: Assembler messages: crt0.S:70: Error: register expected, not '#(184)' -- `sub sp,#(184)' --->8--- Use canonical version of the subtract mnemonic to avoid those issues. Reported-by: Alexey Smishlayev <alexey(a)xtech2.lv> Signed-off-by: Andreas Bießmann <andreas.devel(a)googlemail.com> --- arch/arm/cpu/armv7/lowlevel_init.S | 2 +- arch/arm/lib/crt0.S | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index 69e3053..f1aea05 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -24,7 +24,7 @@ ENTRY(lowlevel_init) #ifdef CONFIG_SPL_BUILD ldr r9, =gdata #else - sub sp, #GD_SIZE + sub sp, sp, #GD_SIZE bic sp, sp, #7 mov r9, sp #endif diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index ac54b93..dfc2de9 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -67,7 +67,7 @@ ENTRY(_main) ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) #endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - sub sp, #GD_SIZE /* allocate one GD above SP */ + sub sp, sp, #GD_SIZE /* allocate one GD above SP */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ mov r9, sp /* GD is above SP */ mov r0, #0 -- 1.7.10.4

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[U-Boot] [PATCH] arm: put .hash, .got.plt and .machine_param back in binaries
by Albert ARIBAUD 14 Jan '14

14 Jan '14

Some targets will build fine but not boot if sections .hash and .got.plt are not present in the binary. Add them back. Also, Exynos machines require .machine_param section in SPL. Add it. Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- This patch was prepared with the help of Rajeshwari Birge. Please test, especially if you own an Exynos-based board. arch/arm/config.mk | 2 +- arch/arm/cpu/armv7/exynos/config.mk | 7 +++++++ arch/arm/cpu/u-boot.lds | 3 +-- spl/Makefile | 3 ++- 4 files changed, 11 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv7/exynos/config.mk diff --git a/arch/arm/config.mk b/arch/arm/config.mk index fd3e5fb..5d39d39 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -105,4 +105,4 @@ PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations) endif # limit ourselves to the sections we want in the .bin. -OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rel.dyn +OBJCFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn diff --git a/arch/arm/cpu/armv7/exynos/config.mk b/arch/arm/cpu/armv7/exynos/config.mk new file mode 100644 index 0000000..ee0d2da --- /dev/null +++ b/arch/arm/cpu/armv7/exynos/config.mk @@ -0,0 +1,7 @@ +# +# Copyright (C) Albert ARIBAUD <albert.u.boot(a)aribaud.net> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +SPL_OBJCFLAGS += -j .machine_param diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 9463a33..4da5d24 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -92,8 +92,6 @@ SECTIONS } .dynsym _end : { *(.dynsym) } - .hash : { *(.hash) } - .got.plt : { *(.got.plt) } .dynbss : { *(.dynbss) } .dynstr : { *(.dynstr*) } .dynamic : { *(.dynamic*) } @@ -101,4 +99,5 @@ SECTIONS .interp : { *(.interp*) } .gnu : { *(.gnu*) } .ARM.exidx : { *(.ARM.exidx*) } + .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) } } diff --git a/spl/Makefile b/spl/Makefile index 2a787af..b95582b 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -171,7 +171,8 @@ $(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin endif $(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN) - $(OBJCOPY) $(OBJCFLAGS) -O binary $< $@ + $(OBJCOPY) $(OBJCFLAGS) $(SPL_OBJCFLAGS) -O srec $< $(obj)$(SPL_BIN).srec + $(OBJCOPY) $(OBJCFLAGS) $(SPL_OBJCFLAGS) -O binary $< $@ GEN_UBOOT = \ cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $(__START) \ -- 1.8.3.2

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[U-Boot] [PATCH 1/2] socfpga: Adding Scan Manager driver
by Chin Liang See 13 Jan '14

13 Jan '14

Scan Manager driver will be called to configure the IOCSR scan chain. This configuration will setup the IO buffer settings Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Wolfgang Denk <wd(a)denx.de> CC: Pavel Machek <pavel(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> --- arch/arm/cpu/armv7/socfpga/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/scan_manager.c | 231 ++++++++++++++++++++ arch/arm/cpu/armv7/socfpga/spl.c | 4 + arch/arm/include/asm/arch-socfpga/scan_manager.h | 97 ++++++++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 1 + include/configs/socfpga_cyclone5.h | 1 + 6 files changed, 335 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 3e84a0c..4edc5d4 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -9,4 +9,4 @@ obj-y := lowlevel_init.o obj-y += misc.o timer.o reset_manager.o system_manager.o -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o +obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c b/arch/arm/cpu/armv7/socfpga/scan_manager.c new file mode 100644 index 0000000..30cbb8b --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/freeze_controller.h> +#include <asm/arch/scan_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_scan_manager *scan_manager_base = + (void *)(SOCFPGA_SCANMGR_ADDRESS); +static const struct socfpga_freeze_controller *freeze_controller_base = + (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS); + +/* + * Function to check IO scan chain engine status and wait if the engine is + * is active. Poll the IO scan chain engine till maximum iteration reached. + */ +static inline uint32_t scan_mgr_io_scan_chain_engine_is_idle(uint32_t max_iter) +{ + uint32_t scanmgr_status; + + scanmgr_status = readl(&scan_manager_base->stat); + + /* Poll the engine until the scan engine is inactive */ + while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) + || (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) { + + max_iter--; + + if (max_iter > 0) + scanmgr_status = readl(&scan_manager_base->stat); + else + return SCAN_MGR_IO_SCAN_ENGINE_STATUS_ACTIVE; + } + return SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE; +} + + + +/* Program HPS IO Scan Chain */ +uint32_t scan_mgr_io_scan_chain_prg( + uint32_t io_scan_chain_id, + uint32_t io_scan_chain_len_in_bits, + const uint32_t *iocsr_scan_chain) +{ + + uint16_t tdi_tdo_header; + uint32_t io_program_iter; + uint32_t io_scan_chain_data_residual; + uint32_t residual; + uint32_t i; + uint32_t index = 0; + + /* De-assert reinit if the IO scan chain is intended for HIO */ + if (3 == io_scan_chain_id) + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK); + + /* + * Check if the scan chain engine is inactive and the + * WFIFO is empty before enabling the IO scan chain + */ + if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE + != scan_mgr_io_scan_chain_engine_is_idle( + MAX_WAITING_DELAY_IO_SCAN_ENGINE)) { + return 1; + } + + /* + * Enable IO Scan chain based on scan chain id + * Note: only one chain can be enabled at a time + */ + setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id); + + /* + * Calculate number of iteration needed for full 128-bit (4 x32-bits) + * bits shifting. Each TDI_TDO packet can shift in maximum 128-bits + */ + io_program_iter = io_scan_chain_len_in_bits >> + IO_SCAN_CHAIN_128BIT_SHIFT; + io_scan_chain_data_residual = io_scan_chain_len_in_bits & + IO_SCAN_CHAIN_128BIT_MASK; + + /* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */ + tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | (TDI_TDO_MAX_PAYLOAD << + TDI_TDO_HEADER_SECOND_BYTE_SHIFT); + + /* Program IO scan chain in 128-bit iteration */ + for (i = 0; i < io_program_iter; i++) { + + /* write TDI_TDO packet header to scan manager */ + writel(tdi_tdo_header, &scan_manager_base->fifodoublebyte); + + /* calculate array index */ + index = i * 4; + + /* write 4 successive 32-bit IO scan chain data into WFIFO */ + writel(iocsr_scan_chain[index], + &scan_manager_base->fifoquadbyte); + writel(iocsr_scan_chain[index + 1], + &scan_manager_base->fifoquadbyte); + writel(iocsr_scan_chain[index + 2], + &scan_manager_base->fifoquadbyte); + writel(iocsr_scan_chain[index + 3], + &scan_manager_base->fifoquadbyte); + + /* + * Check if the scan chain engine has completed the + * IO scan chain data shifting + */ + if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE + != scan_mgr_io_scan_chain_engine_is_idle( + MAX_WAITING_DELAY_IO_SCAN_ENGINE)) { + /* Disable IO Scan chain when error detected */ + clrbits_le32(&scan_manager_base->en, + 1 << io_scan_chain_id); + return 1; + } + } + + /* Calculate array index for final TDI_TDO packet */ + index = io_program_iter * 4; + + /* Final TDI_TDO packet if any */ + if (0 != io_scan_chain_data_residual) { + + /* + * Calculate number of quad bytes FIFO write + * needed for the final TDI_TDO packet + */ + io_program_iter = io_scan_chain_data_residual >> + IO_SCAN_CHAIN_32BIT_SHIFT; + + /* + * Construct TDI_TDO packet for remaining IO + * scan chain (2 bytes) + */ + tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE | + ((io_scan_chain_data_residual - 1) + << TDI_TDO_HEADER_SECOND_BYTE_SHIFT); + + /* + * Program the last part of IO scan chain write TDI_TDO packet + * header (2 bytes) to scan manager + */ + writel(tdi_tdo_header, &scan_manager_base->fifodoublebyte); + + for (i = 0; i < io_program_iter; i++) { + /* + * write remaining scan chain data into scan + * manager WFIFO with 4 bytes write + */ + writel(iocsr_scan_chain[index + i], + &scan_manager_base->fifoquadbyte); + } + + index += io_program_iter; + residual = io_scan_chain_data_residual & + IO_SCAN_CHAIN_32BIT_MASK; + + if (IO_SCAN_CHAIN_PAYLOAD_24BIT < residual) { + /* + * write the last 4B scan chain data + * into scan manager WFIFO + */ + writel(iocsr_scan_chain[index], + &scan_manager_base->fifoquadbyte); + + } else { + /* + * write the remaining 1 - 3 bytes scan chain + * data into scan manager WFIFO byte by byte + * to prevent JTAG engine shifting unused data + * from the FIFO and mistaken the data as a + * valid command (even though unused bits are + * set to 0, but just to prevent hardware + * glitch) + */ + for (i = 0; i < residual; i += 8) { + writel(((iocsr_scan_chain[index] >> i) + & IO_SCAN_CHAIN_BYTE_MASK), + &scan_manager_base->fifosinglebyte); + + } + } + + /* + * Check if the scan chain engine has completed the + * IO scan chain data shifting + */ + if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE + != scan_mgr_io_scan_chain_engine_is_idle( + MAX_WAITING_DELAY_IO_SCAN_ENGINE)) { + /* Disable IO Scan chain when error detected */ + clrbits_le32(&scan_manager_base->en, + 1 << io_scan_chain_id); + return 1; + } + } /* if (io_scan_chain_data_residual) */ + + /* Disable IO Scan chain when configuration done*/ + clrbits_le32(&scan_manager_base->en, + 1 << io_scan_chain_id); + + return 0; +} + +int scan_mgr_configure_iocsr(void) +{ + int status = 0; + + /* configure the IOCSR through scan chain */ + status |= scan_mgr_io_scan_chain_prg(0, + CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH, iocsr_scan_chain0_table); + status |= scan_mgr_io_scan_chain_prg(1, + CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH, iocsr_scan_chain1_table); + status |= scan_mgr_io_scan_chain_prg(2, + CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH, iocsr_scan_chain2_table); + status |= scan_mgr_io_scan_chain_prg(3, + CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH, iocsr_scan_chain3_table); + return status; +} + + + diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 36a00c3..8a49a1a 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -32,6 +32,10 @@ void spl_board_init(void) /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); + /* configure the IOCSR / IO buffer settings */ + if (scan_mgr_configure_iocsr()) + hang(); + /* configure the pin muxing through system manager */ sysmgr_pinmux_init(); #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ diff --git a/arch/arm/include/asm/arch-socfpga/scan_manager.h b/arch/arm/include/asm/arch-socfpga/scan_manager.h new file mode 100644 index 0000000..dfbfade --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/scan_manager.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SCAN_MANAGER_H_ +#define _SCAN_MANAGER_H_ + +struct socfpga_scan_manager { + u32 stat; + u32 en; + u32 padding[2]; + u32 fifosinglebyte; + u32 fifodoublebyte; + u32 fifoquadbyte; +}; + +/* + * Shift count to get number of IO scan chain data in granularity + * of 128-bit ( N / 128 ) + */ +#define IO_SCAN_CHAIN_128BIT_SHIFT (7) + +/* + * Mask to get residual IO scan chain data in + * granularity of 128-bit ( N mod 128 ) + */ +#define IO_SCAN_CHAIN_128BIT_MASK (0x7F) + +/* + * Shift count to get number of IO scan chain + * data in granularity of 32-bit ( N / 32 ) + */ +#define IO_SCAN_CHAIN_32BIT_SHIFT (5) + +/* + * Mask to get residual IO scan chain data in + * granularity of 32-bit ( N mod 32 ) + */ +#define IO_SCAN_CHAIN_32BIT_MASK (0x1F) + +/* Byte mask */ +#define IO_SCAN_CHAIN_BYTE_MASK (0xFF) + +/* 24-bits (3 bytes) IO scan chain payload definition */ +#define IO_SCAN_CHAIN_PAYLOAD_24BIT (24) + +/* + * Maximum length of TDI_TDO packet payload is 128 bits, + * represented by (length - 1) in TDI_TDO header + */ +#define TDI_TDO_MAX_PAYLOAD (127) + +/* TDI_TDO packet header for IO scan chain program */ +#define TDI_TDO_HEADER_FIRST_BYTE (0x80) + +/* Position of second command byte for TDI_TDO packet */ +#define TDI_TDO_HEADER_SECOND_BYTE_SHIFT (8) + +/* IO scan chain engine is idle */ +#define SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE (0) + +/* IO scan chain engine is active */ +#define SCAN_MGR_IO_SCAN_ENGINE_STATUS_ACTIVE (1) + +/* + * Maximum polling loop to wait for IO scan chain engine + * becomes idle to prevent infinite loop + */ +#define MAX_WAITING_DELAY_IO_SCAN_ENGINE (100) + +#define SCANMGR_STAT_ACTIVE_GET(x) (((x) & 0x80000000) >> 31) +#define SCANMGR_STAT_WFIFOCNT_GET(x) (((x) & 0x70000000) >> 28) + +/* + * Program HPS IO Scan Chain + * io_scan_chain_id - IO scan chain ID + * io_scan_chain_len_in_bits - IO scan chain length in bits + * iocsr_scan_chain - IO scan chain table + */ +uint32_t scan_mgr_io_scan_chain_prg( + uint32_t io_scan_chain_id, + uint32_t io_scan_chain_len_in_bits, + const uint32_t *iocsr_scan_chain); + + +extern const uint32_t iocsr_scan_chain0_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain1_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain2_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain3_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)]; + +#endif /* _SCAN_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index 50c4ebd..8d329cf 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -13,5 +13,6 @@ #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 #endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 980636c..981a26b 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -8,6 +8,7 @@ #include <asm/arch/socfpga_base_addrs.h> #include "../../board/altera/socfpga/pinmux_config.h" +#include "../../board/altera/socfpga/iocsr_config.h" /* * High level configuration -- 1.7.9.5

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[U-Boot] [PATCH] arm: New stack pointer is already aligned
by Tom Rini 13 Jan '14

13 Jan '14

The code in arch/arm/lib/board.c::board_init_f that sets gd->start_addr_sp has already make sure we're 8-byte aligned, so we don't need to do that again. Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Signed-off-by: Tom Rini <trini(a)ti.com> --- arch/arm/lib/crt0.S | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index ac54b93..6b5ec01 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -82,7 +82,6 @@ ENTRY(_main) */ ldr sp, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ ldr r9, [r9, #GD_BD] /* r9 = gd->bd */ sub r9, r9, #GD_SIZE /* new GD is below bd */ -- 1.7.9.5

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[U-Boot] [PATCH REPOST3 1/2] ARM: rpi_b: power on SDHCI and USB HW modules
by Stephen Warren 13 Jan '14

13 Jan '14

Send RPC commands to the VideoCore to turn on the SDHCI and USB modules. For SDHCI this isn't needed in practice, since the firmware already turned on the power in order to load U-Boot. However, it's best to be explicit. For USB, this is necessary, since the module isn't powered otherwise. This will allow the kernel USB driver to work. Signed-off-by: Stephen Warren <swarren(a)wwwdotorg.org> --- arch/arm/include/asm/arch-bcm2835/mbox.h | 48 ++++++++++++++++++++++++++++++ board/raspberrypi/rpi_b/rpi_b.c | 34 ++++++++++++++++++++- 2 files changed, 81 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h index 6b806ec..38cb42a 100644 --- a/arch/arm/include/asm/arch-bcm2835/mbox.h +++ b/arch/arm/include/asm/arch-bcm2835/mbox.h @@ -133,6 +133,54 @@ struct bcm2835_mbox_tag_get_arm_mem { } body; }; +#define BCM2835_MBOX_POWER_DEVID_SDHCI 0 +#define BCM2835_MBOX_POWER_DEVID_UART0 1 +#define BCM2835_MBOX_POWER_DEVID_UART1 2 +#define BCM2835_MBOX_POWER_DEVID_USB_HCD 3 +#define BCM2835_MBOX_POWER_DEVID_I2C0 4 +#define BCM2835_MBOX_POWER_DEVID_I2C1 5 +#define BCM2835_MBOX_POWER_DEVID_I2C2 6 +#define BCM2835_MBOX_POWER_DEVID_SPI 7 +#define BCM2835_MBOX_POWER_DEVID_CCP2TX 8 + +#define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 1) +/* Device doesn't exist */ +#define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1) + +#define BCM2835_MBOX_TAG_GET_POWER_STATE 0x00020001 + +struct bcm2835_mbox_tag_get_power_state { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + u32 device_id; + } req; + struct { + u32 device_id; + u32 state; + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_SET_POWER_STATE 0x00028001 + +#define BCM2835_MBOX_SET_POWER_STATE_REQ_ON (1 << 0) +#define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT (1 << 1) + +struct bcm2835_mbox_tag_set_power_state { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + u32 device_id; + u32 state; + } req; + struct { + u32 device_id; + u32 state; + } resp; + } body; +}; + #define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002 #define BCM2835_MBOX_CLOCK_ID_EMMC 1 diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi_b/rpi_b.c index 16d442a..f33fae9 100644 --- a/board/raspberrypi/rpi_b/rpi_b.c +++ b/board/raspberrypi/rpi_b/rpi_b.c @@ -29,6 +29,12 @@ struct msg_get_arm_mem { u32 end_tag; }; +struct msg_set_power_state { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_set_power_state set_power_state; + u32 end_tag; +}; + struct msg_get_clock_rate { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_get_clock_rate get_clock_rate; @@ -54,11 +60,35 @@ int dram_init(void) return 0; } +static int power_on_module(u32 module) +{ + ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 16); + int ret; + + BCM2835_MBOX_INIT_HDR(msg_pwr); + BCM2835_MBOX_INIT_TAG(&msg_pwr->set_power_state, + SET_POWER_STATE); + msg_pwr->set_power_state.body.req.device_id = module; + msg_pwr->set_power_state.body.req.state = + BCM2835_MBOX_SET_POWER_STATE_REQ_ON | + BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT; + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, + &msg_pwr->hdr); + if (ret) { + printf("bcm2835: Could not set module %u power state\n", + module); + return -1; + } + + return 0; +} + int board_init(void) { gd->bd->bi_boot_params = 0x100; - return 0; + return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD); } int board_mmc_init(void) @@ -66,6 +96,8 @@ int board_mmc_init(void) ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16); int ret; + power_on_module(BCM2835_MBOX_POWER_DEVID_SDHCI); + BCM2835_MBOX_INIT_HDR(msg_clk); BCM2835_MBOX_INIT_TAG(&msg_clk->get_clock_rate, GET_CLOCK_RATE); msg_clk->get_clock_rate.body.req.clock_id = BCM2835_MBOX_CLOCK_ID_EMMC; -- 1.7.10.4

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[U-Boot] [PATCH 2/2] ARM: versatile: pass console setting to the kernel
by Linus Walleij 13 Jan '14

13 Jan '14

The Versatiles come up with the primary UART set to ttyAMA0 at 38400 baud, and unless we pass this to the kernel it will assume it is set to 9600 baud which will be quite awkward for the terminal, let's try to be helpful and inform the kernel what setting is used. Cc: Stefano Babic <sbabic(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- include/configs/versatile.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/versatile.h b/include/configs/versatile.h index 10738ac24be0..29c32fee5178 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -101,7 +101,8 @@ #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\ - "netdev=25,0,0xf1010000,0xf1010010,eth0" + "netdev=25,0,0xf1010000,0xf1010010,eth0 "\ + "console=ttyAMA0,38400n1" /* * Static configuration when assigning fixed address -- 1.8.3.1

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[U-Boot] [PATCH 1/2] ARM: versatile: pass correct machine type for Versatile AB
by Linus Walleij 13 Jan '14

13 Jan '14

When U-Boot is configured for Versatile AB, it will still pass the machine ID of Versatile PB to the kernel. After this simple fix the system boots correctly. Cc: Stefano Babic <sbabic(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- board/armltd/versatile/versatile.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c index 30a3b904db4c..4e2d3421d8b1 100644 --- a/board/armltd/versatile/versatile.c +++ b/board/armltd/versatile/versatile.c @@ -52,7 +52,11 @@ int board_early_init_f (void) int board_init (void) { /* arch number of Versatile Board */ +#ifdef CONFIG_ARCH_VERSATILE_AB + gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_AB; +#else gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB; +#endif /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; -- 1.8.3.1

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[U-Boot] [PATCH v2 0/2] video: ipu reg: Correct some reserved array sizes
by Liu Ying 12 Jan '14

12 Jan '14

The structures ipu_cm and ipu_idmac contain some reserved arrays as placeholders to make sure the trailing entries may point to the relevant IPU registers. This patch corrects the size of the reserved arrays. Changes in v2: Added Robin Gong's ack. Liu Ying (2): video: ipu reg: Correct reserved1 array size in struct ipu_cm video: ipu reg: Correct reserved array size in struct ipu_idmac drivers/video/ipu_regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 1.7.9.5

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