November 2013 - U-Boot

[U-Boot] [PATCH v1+ 00/18] MIPS Malta board support
by Paul Burton 11 Nov '13

11 Nov '13

This series adds support for booting on a physical MIPS Malta board using a coreFPGA6 core card. The first 6 patches lay some groundwork, then the next 8 genericise the existing qemu-malta board to also function on a physical Malta. In the final patch I stake my claim upon, errm I mean step up to support :), the malta(el) board(s). Since the original posting this series has been rebased atop current master & adapted to the KBuild changes. I also included the RTC support patch I previously posted separately, and a couple of extra patches which fix up issues with booted kernels & add environment support. After this series Gabor Juhos' "malta: define CONFIG_MEMSIZE_IN_BYTES" patch is also required in order for a booted Linux kernel to function correctly. Paul Burton (18): mips32: detect L1 cache sizes if they're not defined pcnet: code style cleanup pcnet: s/le16_to_cpu/cpu_to_le16/ in pcnet_send pcnet: add cache flushing & invalidation pcnet: enable the NOUFLO feature pci.h: allow inclusion in assembly source qemu-malta: rename to just "malta" malta: setup super I/O UARTs malta: support for coreFPGA6 boards malta: display "U-boot" on the LCD screen malta: enable CONFIG_PCNET_79C973, PCNET_HAS_PROM, CONFIG_CMD_DHCP malta: remove cache size definitions malta: disable L2 caches malta: enable RTC support malta: store environment in flash malta: setup PIIX4 interrupt route malta: add script & instructions to flash U-boot malta: add myself to maintainers arch/mips/cpu/mips32/cache.S | 90 +++++++++-- arch/mips/cpu/mips32/cpu.c | 73 ++++++++- arch/mips/cpu/mips32/start.S | 2 +- arch/mips/include/asm/malta.h | 50 +++++- arch/mips/include/asm/mipsregs.h | 6 + arch/mips/lib/bootm.c | 12 +- board/imgtec/malta/Makefile | 10 ++ board/imgtec/malta/flash-malta-boot.tcl | 40 +++++ board/imgtec/malta/lowlevel_init.S | 238 +++++++++++++++++++++++++++ board/imgtec/malta/malta.c | 208 ++++++++++++++++++++++++ board/imgtec/malta/superio.c | 63 ++++++++ board/imgtec/malta/superio.h | 15 ++ board/qemu-malta/Makefile | 9 -- board/qemu-malta/lowlevel_init.S | 69 -------- board/qemu-malta/qemu-malta.c | 47 ------ boards.cfg | 4 +- doc/README.malta | 16 ++ drivers/net/pcnet.c | 279 ++++++++++++++++++-------------- drivers/pci/Makefile | 1 + drivers/pci/pci_msc01.c | 125 ++++++++++++++ drivers/rtc/mc146818.c | 2 +- include/configs/malta.h | 122 ++++++++++++++ include/configs/qemu-malta.h | 113 ------------- include/msc01.h | 135 ++++++++++++++++ include/pci.h | 6 +- include/pci_ids.h | 3 + include/pci_msc01.h | 17 ++ 27 files changed, 1356 insertions(+), 399 deletions(-) create mode 100644 board/imgtec/malta/Makefile create mode 100644 board/imgtec/malta/flash-malta-boot.tcl create mode 100644 board/imgtec/malta/lowlevel_init.S create mode 100644 board/imgtec/malta/malta.c create mode 100644 board/imgtec/malta/superio.c create mode 100644 board/imgtec/malta/superio.h delete mode 100644 board/qemu-malta/Makefile delete mode 100644 board/qemu-malta/lowlevel_init.S delete mode 100644 board/qemu-malta/qemu-malta.c create mode 100644 doc/README.malta create mode 100644 drivers/pci/pci_msc01.c create mode 100644 include/configs/malta.h delete mode 100644 include/configs/qemu-malta.h create mode 100644 include/msc01.h create mode 100644 include/pci_msc01.h -- 1.8.4.1

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[U-Boot] [PATCH v2 0/8] SATA support for omap5_uevm and dra7_evm
by Roger Quadros 11 Nov '13

11 Nov '13

Hi, This series adds SATA support for OMAP5 uevm and DRA7 evm. Patches are also availabe at git@github.com:rogerq/u-boot.git sata v2: - Address review comments in the RFC series - Fix cache align error in the ahci driver - Added dra7 support cheers, -roger Roger Quadros (8): ahci: Error out with message on malloc() failure ahci: Fix cache align error messages ARM: OMAP5: Add Pipe3 PHY driver ARM: OMAP5: Add PRCM and Control information for SATA ARM: OMAP5: Add SATA platform glue ARM: omap5_uevm: Add SATA support ARM: DRA7xx: Add PRCM and Control information for SATA ARM: dra7_evm: Add SATA support arch/arm/cpu/armv7/omap-common/Makefile | 5 + arch/arm/cpu/armv7/omap-common/pipe3-phy.c | 233 +++++++++++++++++++++++++++++ arch/arm/cpu/armv7/omap-common/pipe3-phy.h | 36 +++++ arch/arm/cpu/armv7/omap-common/sata.c | 75 ++++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 7 + arch/arm/include/asm/arch-omap5/clock.h | 3 + arch/arm/include/asm/arch-omap5/omap.h | 3 + arch/arm/include/asm/arch-omap5/sata.h | 48 ++++++ arch/arm/include/asm/omap_common.h | 2 + board/ti/dra7xx/evm.c | 7 + board/ti/omap5_uevm/evm.c | 7 + drivers/block/ahci.c | 18 ++- include/configs/dra7xx_evm.h | 11 ++ include/configs/omap5_uevm.h | 10 ++ 14 files changed, 459 insertions(+), 6 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.c create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.h create mode 100644 arch/arm/cpu/armv7/omap-common/sata.c create mode 100644 arch/arm/include/asm/arch-omap5/sata.h -- 1.8.3.2

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[U-Boot] [RFC][PATCH 0/5] SATA support for OMAP5 uevm
by Roger Quadros 11 Nov '13

11 Nov '13

Hi, This series adds SATA support for OMAP5 uevm board. This is an RFC patchset for review only. Patches are based on v2013.10. cheers, -roger --- Roger Quadros (5): ahci: Error out with message on malloc() failure ARM: OMAP5: Add Pipe3 PHY driver ARM: OMAP5: Add PRCM and Control information for SATA ARM: OMAP5: Add SATA platform glue ARM: omap5_uevm: Add SATA support arch/arm/cpu/armv7/omap-common/Makefile | 7 + arch/arm/cpu/armv7/omap-common/pipe3-phy.c | 233 +++++++++++++++++++++++++++++ arch/arm/cpu/armv7/omap-common/pipe3-phy.h | 36 +++++ arch/arm/cpu/armv7/omap-common/sata.c | 78 ++++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 5 + arch/arm/include/asm/arch-omap5/clock.h | 3 + arch/arm/include/asm/arch-omap5/omap.h | 3 + arch/arm/include/asm/arch-omap5/sata.h | 48 ++++++ arch/arm/include/asm/omap_common.h | 3 + board/ti/omap5_uevm/evm.c | 7 + drivers/block/ahci.c | 16 +- include/configs/omap5_uevm.h | 10 ++ 12 files changed, 447 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.c create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.h create mode 100644 arch/arm/cpu/armv7/omap-common/sata.c create mode 100644 arch/arm/include/asm/arch-omap5/sata.h -- 1.8.3.2

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[U-Boot] [PATCH v2] usb: dfu: make nand upload working
by Bo Shen 11 Nov '13

11 Nov '13

Nowhere pass a value to len, which always 0, make no transfer which cause uploading failed. This patch make nand upload working. However it needs enough malloc buffer to store read data, that means the buffer at least equal to the upload partition size, or else it doesn't work. Signed-off-by: Bo Shen <voice.shen(a)atmel.com> --- Changes in v2: - Move code to nand part, or else it will break mmc drivers/dfu/dfu_nand.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c index 1c2e03b..cf082e2 100644 --- a/drivers/dfu/dfu_nand.c +++ b/drivers/dfu/dfu_nand.c @@ -121,6 +121,7 @@ static int dfu_read_medium_nand(struct dfu_entity *dfu, u64 offset, void *buf, switch (dfu->layout) { case DFU_RAW_ADDR: + *len = dfu->data.nand.size; ret = nand_block_read(dfu, offset, buf, len); break; default: -- 1.7.9.5

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Re: [U-Boot] [RFC][PATCH 0/5] SATA support for OMAP5 uevm
by Roger Quadros 11 Nov '13

11 Nov '13

Aneesh, On 11/07/2013 07:15 PM, V, Aneesh wrote: > Hi Roger, > >> -----Original Message----- >> From: Quadros, Roger >> Sent: Thursday, November 07, 2013 2:45 AM >> To: Enric Balletbo Serra >> Cc: u-boot(a)lists.denx.de; Rini, Tom; Krishnamoorthy, Balaji T; >> rob.herring(a)calxeda.com; V, Aneesh >> Subject: Re: [U-Boot] [RFC][PATCH 0/5] SATA support for OMAP5 uevm >> >> +Aneesh. >> >> Hi Enric, >> >> On 11/07/2013 10:52 AM, Enric Balletbo Serra wrote: >>> Hi Roger, >>> >>> Thanks for the patches! >>> >>> 2013/11/6 Roger Quadros <rogerq(a)ti.com>: >>>> Hi, >>>> >>>> This series adds SATA support for OMAP5 uevm board. >>>> >>>> This is an RFC patchset for review only. Patches are based on >>>> v2013.10. >>>> >>>> cheers, >>>> -roger >>>> >>>> --- >>>> Roger Quadros (5): >>>> ahci: Error out with message on malloc() failure >>>> ARM: OMAP5: Add Pipe3 PHY driver >>>> ARM: OMAP5: Add PRCM and Control information for SATA >>>> ARM: OMAP5: Add SATA platform glue >>>> ARM: omap5_uevm: Add SATA support >>>> >>>> arch/arm/cpu/armv7/omap-common/Makefile | 7 + >>>> arch/arm/cpu/armv7/omap-common/pipe3-phy.c | 233 >>>> +++++++++++++++++++++++++++++ arch/arm/cpu/armv7/omap- >> common/pipe3-phy.h | 36 +++++ >>>> arch/arm/cpu/armv7/omap-common/sata.c | 78 ++++++++++ >>>> arch/arm/cpu/armv7/omap5/prcm-regs.c | 5 + >>>> arch/arm/include/asm/arch-omap5/clock.h | 3 + >>>> arch/arm/include/asm/arch-omap5/omap.h | 3 + >>>> arch/arm/include/asm/arch-omap5/sata.h | 48 ++++++ >>>> arch/arm/include/asm/omap_common.h | 3 + >>>> board/ti/omap5_uevm/evm.c | 7 + >>>> drivers/block/ahci.c | 16 +- >>>> include/configs/omap5_uevm.h | 10 ++ >>>> 12 files changed, 447 insertions(+), 2 deletions(-) create mode >>>> 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.c >>>> create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.h >>>> create mode 100644 arch/arm/cpu/armv7/omap-common/sata.c >>>> create mode 100644 arch/arm/include/asm/arch-omap5/sata.h >>>> >>>> -- >>>> 1.8.3.2 >>>> >>>> _______________________________________________ >>>> U-Boot mailing list >>>> U-Boot(a)lists.denx.de >>>> http://lists.denx.de/mailman/listinfo/u-boot >>> >>> I applied your patches and worked perfectly, however I've two small issues. >>> >>> The first issue is that I see the following error: >>> >>> scanning bus for devices... >>> ERROR: v7_dcache_inval_range - start address is not aligned - 0xfee48618 >>> ERROR: v7_dcache_inval_range - stop address is not aligned - >>> 0xfee48818 >> >> I'm seeing this too. Not sure how to fix it. >> Aneesh, any pointers? > > The issue is that the dcache invalidation is requested for a buffer that is not aligned to cache-line > boundary. The cpu instructions for cache invalidation operate on cache lines, so a cache line can > not be invalidated partially. So in this case the invalidation function will refuse to invalidate the > first and last cache lines. > > The solution is to align your DMA buffer correctly. Take a look at : > > ALLOC_CACHE_ALIGN_BUFFER() and DEFINE_CACHE_ALIGN_BUFFER() in > include/common.h > > Also, doc/README.arm-caches has instructions for handling cached buffers for DMA. Thanks for this tip, it helped. One more thing. While I was looking at arch/arm/cpu/armv7/cache_v7.c I failed to understand how you convert the cache line size from words to byte. e.g. > static void v7_maint_dcache_level_setway(u32 level, u32 operation) > { > u32 ccsidr; > u32 num_sets, num_ways, log2_line_len, log2_num_ways; > u32 way_shift; > > set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED); > > ccsidr = get_ccsidr(); > > log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >> > CCSIDR_LINE_SIZE_OFFSET) + 2; > /* Converting from words to bytes */ > log2_line_len += 2; Shouldn't this be log2_line_len += 1; cheers, -roger

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[U-Boot] [RESEND PATCH v14 00/10] arm64 pat
by fenghua＠phytium.com.cn 11 Nov '13

11 Nov '13

From: David Feng <fenghua(a)phytium.com.cn> The content is same with original v14. 04/05/06 patches is totally provided by scott wood. Them are mistakenly encoded "From: David Feng", so modify its to "From: Scott Wood". Changes for v14: - Merge rela relocation patches from Scott Wood <scottwood(a)freescale.com>. - Remove all CONFIG_NEED_MANUAL_RELOC and other fixups due to manual relocation. With rela relocation patches them are not needed. - Fix the bug of MEMORY_ATTRIBUTES definition due to assembler. That need put brackets around (MT_NORMAL*8). Otherwise the result is wrong.This bug is reported by York Sun <yorksun(a)freescale.com>. - -msoft-float is not supported by aarch64-gcc, make a test though $(call cc-option,-msoft-float). - Adjust the virtual address space to 42 bits. - Filter armv8 boards from LIST_arm in MAKEALL. - remove gpio.h in asm/arch-armv8/ and move mmu.h to asm/armv8/ directory. - remove vexpress64.dts from this patch, it could be accessed from linux kernel. Changes for v13: - fix the bug of board_r.c and arm/lib/board.c due to CONFIG_NEED_MANUAL_RELOC. adjust initr_serial() in board_r.c to the first entry of init_sequence_r[] and relocate serial_initialize() in arm/lib/board.c, routines of serial_device should be relocated firstly by serial_initialize(), so that printf access the correct puts function, otherwise uninitialized serial_current will be selected as the output device. - fix the bug of dcache_enable(). after mmu_setup the sctrl register value should be fetched again because it has been modifed by mmu_seup() function. This bug is reported by York Sun <yorksun(a)freescale.com>. - add macro branch_if_slave to macro.h, it choose processor with all zero affinity value as the master and is used in start.S. Changes for v12: - custom the patches to new format boards.cfg. Changes for v11: - Replace CONFIG_ARMV8 with CONFIG_ARM64. Currently, it's hard to distinguish what is armv8 specific and what is aarch64 specific, so we use CONFIG_ARM64 only, no CONFIG_ARMV8 used. - rename README.armv8 with README.arm64 and make some modification. Changes for v10: - add weak definition to include/linux/linkage.h and make setup_el2/setup_el3/lowlevel_init weak routines, so them can be easily overridden by processor specific code. - modify s-o-f of 0002-board-support-of-vexpress_aemv8a which use wrong mail address of Bhupesh Sharma. Changes for v9: - add Signed-off-by information to patch "board support of vexpress_aemv8a" which SMC91111 support is integrated from Sharma Bhupesh's patch. - adjust pt_regs struct and add exception state preservation in exception.S. Changes for v8: - Integrate SMC91111 patch of sharma bhupesh. - remove v8_outer_cache* which is not need currently. - Change license tag. - Mov crt0.S/relocate.S/interrupts.c to arm/lib and rename them with _64 suffix. - Make el3/el2 initializing process of start.S as two separate routines. It could be easier to be replaced with processor specific codes. - Remove exception stack save and restore routine, it is unnecessary now. - simplify __weak function declaration. Changes for v7: - Check the patches with checkpatch.pl and get rid of almost all warnings. There are a few warnings still, but I think it should be that. - change printf format in cmd_pxe.c, use %zd indtead of %ld to format size_t type variable. - add macro PGTABLE_SIZE to identify tlb table size. Changes for v6: - Make modification to inappropriate licensed file and bugs according to ScottWood's advice. Thanks Scott for his checking to these patches. - Enable u-boot's running at EL1. - Get rid of compiling warnings originated from cmd_pxe.c. Changes for v5: - fix the generic board_f.c, remove zero_global_data from init_sequence_f array and move it to board_init_f() function with CONFIG_X86 switch. The previous fixup is inaccurate. - Replace __ARMEB__ with __AARCH64EB__ in byteorder.h and unaligned.h, gcc for aarch64 use __AARCH64EB__ and __AARCH64EL__ to identify endian. - Some modification to README.armv8 Changes for v4: - merge arm64 to arm architecture. David Feng (10): fdt_support: 64bit initrd start address support cmd_pxe.c: remove compiling warnings add weak entry definition arm64: Add tool to statically apply RELA relocations arm64: Turn u-boot.bin back into an ELF file after relocate-rela arm64: Make checkarmreloc accept arm64 relocations arm64: core support arm64: generic board support arm64: board support of vexpress_aemv8a arm64: MAKEALL, filter armv8 boards from LIST_arm MAKEALL | 13 +- Makefile | 39 +++++- arch/arm/config.mk | 3 +- arch/arm/cpu/armv8/Makefile | 38 +++++ arch/arm/cpu/armv8/cache.S | 130 +++++++++++++++++ arch/arm/cpu/armv8/cache_v8.c | 218 ++++++++++++++++++++++++++++ arch/arm/cpu/armv8/config.mk | 15 ++ arch/arm/cpu/armv8/cpu.c | 67 +++++++++ arch/arm/cpu/armv8/exceptions.S | 112 +++++++++++++++ arch/arm/cpu/armv8/start.S | 234 +++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/timer.c | 80 +++++++++++ arch/arm/cpu/armv8/tlb.S | 30 ++++ arch/arm/cpu/armv8/u-boot.lds | 89 ++++++++++++ arch/arm/include/asm/armv8/mmu.h | 110 +++++++++++++++ arch/arm/include/asm/byteorder.h | 12 ++ arch/arm/include/asm/cache.h | 5 + arch/arm/include/asm/config.h | 6 + arch/arm/include/asm/global_data.h | 6 +- arch/arm/include/asm/io.h | 15 +- arch/arm/include/asm/macro.h | 36 +++++ arch/arm/include/asm/posix_types.h | 10 ++ arch/arm/include/asm/proc-armv/ptrace.h | 21 +++ arch/arm/include/asm/proc-armv/system.h | 59 +++++++- arch/arm/include/asm/system.h | 77 ++++++++++ arch/arm/include/asm/types.h | 4 + arch/arm/include/asm/u-boot.h | 4 + arch/arm/include/asm/unaligned.h | 2 +- arch/arm/lib/Makefile | 14 ++ arch/arm/lib/board.c | 7 +- arch/arm/lib/bootm.c | 16 +++ arch/arm/lib/crt0_64.S | 113 +++++++++++++++ arch/arm/lib/interrupts_64.c | 120 ++++++++++++++++ arch/arm/lib/relocate_64.S | 58 ++++++++ board/armltd/vexpress64/Makefile | 27 ++++ board/armltd/vexpress64/vexpress64.c | 50 +++++++ boards.cfg | 1 + common/board_f.c | 20 ++- common/cmd_pxe.c | 4 +- common/fdt_support.c | 66 ++++----- common/image.c | 1 + doc/README.arm64 | 45 ++++++ examples/standalone/stubs.c | 15 ++ include/configs/vexpress_aemv8a.h | 191 +++++++++++++++++++++++++ include/image.h | 1 + include/linux/linkage.h | 4 + tools/Makefile | 6 + tools/relocate-rela.c | 185 ++++++++++++++++++++++++ 47 files changed, 2321 insertions(+), 58 deletions(-) create mode 100644 arch/arm/cpu/armv8/Makefile create mode 100644 arch/arm/cpu/armv8/cache.S create mode 100644 arch/arm/cpu/armv8/cache_v8.c create mode 100644 arch/arm/cpu/armv8/config.mk create mode 100644 arch/arm/cpu/armv8/cpu.c create mode 100644 arch/arm/cpu/armv8/exceptions.S create mode 100644 arch/arm/cpu/armv8/start.S create mode 100644 arch/arm/cpu/armv8/timer.c create mode 100644 arch/arm/cpu/armv8/tlb.S create mode 100644 arch/arm/cpu/armv8/u-boot.lds create mode 100644 arch/arm/include/asm/armv8/mmu.h create mode 100644 arch/arm/lib/crt0_64.S create mode 100644 arch/arm/lib/interrupts_64.c create mode 100644 arch/arm/lib/relocate_64.S create mode 100644 board/armltd/vexpress64/Makefile create mode 100644 board/armltd/vexpress64/vexpress64.c create mode 100644 doc/README.arm64 create mode 100644 include/configs/vexpress_aemv8a.h create mode 100644 tools/relocate-rela.c -- 1.7.9.5

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[U-Boot] Question about patman
by Masahiro Yamada 11 Nov '13

11 Nov '13

Hello Simon. I'm trying patman, but it looks like it doesn't work on my Ubuntu box. How can I resove the following issue? The subject of HEAD is ARM: align MVBAR on 32 byte boundary and the result of my dry run is: $ python --version Python 2.7.4 $ tools/patman/patman -n -c1 Cleaned 1 patches Traceback (most recent call last): File "tools/patman/patman", line 153, in <module> not options.ignore_bad_tags) File "/home/yamada/workspace/arm-linux-pf/u-boot/tools/patman/series.py", line 225, in MakeCcFile raise_on_error=raise_on_error) File "/home/yamada/workspace/arm-linux-pf/u-boot/tools/patman/gitutil.py", line 308, in BuildEmailList raw += LookupEmail(item, alias, raise_on_error=raise_on_error) File "/home/yamada/workspace/arm-linux-pf/u-boot/tools/patman/gitutil.py", line 472, in LookupEmail raise ValueError, msg ValueError: Alias 'arm' not found Best Regards Masahiro Yamada

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[U-Boot] [U-boot] not support parsing Android's boot.img format ?
by TigerLiu＠viatech.com.cn 11 Nov '13

11 Nov '13

Hi, experts: It seems current uboot does not support parse boot.img which saved in NAND chip. Boot.img contains : kernel.img and ramdisk.img It contains a header struct: struct boot_img_hdr { unsigned char magic[BOOT_MAGIC_SIZE]; unsigned kernel_size; /* size in bytes */ unsigned kernel_addr; /* physical load addr */ unsigned ramdisk_size; /* size in bytes */ unsigned ramdisk_addr; /* physical load addr */ unsigned second_size; /* size in bytes */ unsigned second_addr; /* physical load addr */ unsigned tags_addr; /* physical addr for kernel tags */ unsigned page_size; /* flash page size we assume */ unsigned unused[2]; /* future expansion: should be 0 */ unsigned char name[BOOT_NAME_SIZE]; /* asciiz product name */ unsigned char cmdline[BOOT_ARGS_SIZE]; unsigned id[8]; /* timestamp / checksum / sha1 / etc */ }; Nand boot cmd usually should retrieve kernel.img from boot.img. Best wishes,

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[U-Boot] [PATCH] powerpc/t1040qds: Add DDR Raw Timing support
by Priyanka Jain 11 Nov '13

11 Nov '13

T1040QDS-D3 has dual-rank DDR: Micron, MT18KSF51272AZ-1G6 (4GB, x72, CL=10). Add Raw Timing structure for this DDR. Typically SPD method is used for getting DDR parameter and calculating values for various DDR controller registers. But somentimes it may happen that SPD present on DDR may get accidently erased or is not working properly during initial bring-up. In that circumnstance, DDR raw timing structure can be use as fallback option for getting DDR parameters. Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- Based on u-boot-mpc85xx/next branch. board/freescale/t1040qds/ddr.c | 15 +++++++++++++++ board/freescale/t1040qds/ddr.h | 29 +++++++++++++++++++++++++++++ include/configs/T1040QDS.h | 1 + 3 files changed, 45 insertions(+), 0 deletions(-) diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c index 4fd17da..16ab829 100644 --- a/board/freescale/t1040qds/ddr.c +++ b/board/freescale/t1040qds/ddr.c @@ -15,6 +15,21 @@ DECLARE_GLOBAL_DATA_PTR; +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "RAW timing DDR"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h index 8ee206e..4a4f76a 100644 --- a/board/freescale/t1040qds/ddr.h +++ b/board/freescale/t1040qds/ddr.h @@ -6,6 +6,35 @@ #ifndef __DDR_H__ #define __DDR_H__ +dimm_params_t ddr_raw_timing = { + .n_ranks = 2, + .rank_density = 2147483648u, + .capacity = 4294967296u, + .primary_sdram_width = 64, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 2, /* ECC */ + .burst_lengths_bitmask = 0x0c, + .tckmin_x_ps = 1071, + .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 6000, + .trp_ps = 13125, + .tras_ps = 34000, + .trc_ps = 48125, + .trfc_ps = 260000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 35000, +}; + struct board_specific_parameters { u32 n_ranks; u32 datarate_mhz_high; diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 2738242..a8b32fe 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -168,6 +168,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD +#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_FSL_DDR3 #define CONFIG_FSL_DDR_INTERACTIVE -- 1.7.4.1

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[U-Boot] [PATCH 1/4] serial: sh: Add support R8A7791
by Nobuhiro Iwamatsu 11 Nov '13

11 Nov '13

This adds the preset value to register for R8A7791. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> CC: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- drivers/serial/serial_sh.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index a6558af..556b868 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -224,7 +224,7 @@ struct uart_port { # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* Overrun error bit */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -#elif defined(CONFIG_R8A7790) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) # define SCIF_ORER 0x0001 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ #else @@ -301,7 +301,7 @@ struct uart_port { /* SH7763 SCIF2 support */ # define SCIF2_RFDC_MASK 0x001f # define SCIF2_TXROOM_MAX 16 -#elif defined(CONFIG_R8A7790) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) # define SCIF_RFDC_MASK 0x003f #else @@ -585,7 +585,7 @@ SCIF_FNS(SCSPTR, 0, 0, 0, 0) #else SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) #endif -#if defined(CONFIG_R8A7790) +#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) SCIF_FNS(DL, 0, 0, 0x30, 16) SCIF_FNS(CKS, 0, 0, 0x34, 16) #endif @@ -730,7 +730,7 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk) #define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk) #elif defined(__H8300H__) || defined(__H8300S__) #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) -#elif defined(CONFIG_R8A7790) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) #define SCBRR DL #define SCBRR_VALUE(bps, clk) (clk / bps / 16) #else /* Generic SH */ -- 1.8.4.rc3

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