November 2013 - U-Boot

[U-Boot] [RFC] arm926ejs, at91: add common phy_reset function
by Heiko Schocher 13 Nov '13

13 Nov '13

add common phy reset code into a common function. Signed-off-by: Heiko Schocher <hs(a)denx.de> Cc: Andreas Bießmann <andreas.devel(a)googlemail.com> Cc: Bo Shen <voice.shen(a)atmel.com> Cc: Jens Scharsig <esw(a)bus-elektronik.de> Cc: Sergey Lapin <slapin(a)ossfans.org> Cc: Stelian Pop <stelian(a)popies.net> Cc: Albin Tonnerre <albin.tonnerre(a)free-electrons.com> Cc: Eric Benard <eric(a)eukrea.com> Cc: Markus Hubig <mhubig(a)imko.de> --- Patch based on the spl patchset from Bo Shen (as I want to collect this function in at91-common directory), see: http://lists.denx.de/pipermail/u-boot/2013-November/166272.html (reworked this against newest Kconfig Makefile changes ... @Bo: Do you plan an update for this patchset for the Kconfig changes? Maybe my change in arch/arm/cpu/at91-common/Makefile could be done better... Do we have a common define for all this variants? --- arch/arm/cpu/Makefile | 1 + arch/arm/cpu/at91-common/Makefile | 5 +++ arch/arm/cpu/at91-common/phy.c | 48 +++++++++++++++++++++++++ arch/arm/include/asm/arch-at91/at91_common.h | 1 + board/BuS/vl_ma2sc/vl_ma2sc.c | 18 ++-------- board/afeb9260/afeb9260.c | 18 +--------- board/atmel/at91sam9260ek/at91sam9260ek.c | 19 +--------- board/atmel/at91sam9263ek/at91sam9263ek.c | 19 ++-------- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 19 +--------- board/bluewater/snapper9260/snapper9260.c | 16 +-------- board/calao/sbc35_a9g20/sbc35_a9g20.c | 19 +--------- board/eukrea/cpu9260/cpu9260.c | 18 +--------- board/taskit/stamp9g20/stamp9g20.c | 31 +--------------- spl/Makefile | 4 --- 14 files changed, 66 insertions(+), 170 deletions(-) create mode 100644 arch/arm/cpu/at91-common/phy.c diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile index fd0da53..886347d 100644 --- a/arch/arm/cpu/Makefile +++ b/arch/arm/cpu/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_TEGRA) += $(SOC)-common/ obj-$(CONFIG_TEGRA) += tegra-common/ +obj-$(CONFIG_AT91FAMILY) += at91-common/ diff --git a/arch/arm/cpu/at91-common/Makefile b/arch/arm/cpu/at91-common/Makefile index 040b956..255c7b9 100644 --- a/arch/arm/cpu/at91-common/Makefile +++ b/arch/arm/cpu/at91-common/Makefile @@ -8,5 +8,10 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_AT91SAM9260) += phy.o +obj-$(CONFIG_AT91SAM9G20) += phy.o +obj-$(CONFIG_AT91SAM9263) += phy.o +obj-$(CONFIG_AT91SAM9XE) += phy.o +obj-$(CONFIG_AT91SAM9M10G45) += phy.o obj-$(CONFIG_SPL_BUILD) += mpddrc.o obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/arm/cpu/at91-common/phy.c b/arch/arm/cpu/at91-common/phy.c new file mode 100644 index 0000000..4706635 --- /dev/null +++ b/arch/arm/cpu/at91-common/phy.c @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian(a)popies.net> + * Lead Tech Design <www.leadtechdesign.com> + * + * Copyright (C) 2013 DENX Software Engineering, hs(a)denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/sizes.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <watchdog.h> + +void at91_phy_reset(void) +{ + unsigned long erstl; + unsigned long start = get_timer(0); + unsigned long timeout = 1000; /* 1000ms */ + at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC; + + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; + + /* Need to reset PHY -> 500ms reset */ + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); + + /* Wait for end of hardware reset */ + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) { + /* avoid shutdown by watchdog */ + WATCHDOG_RESET(); + mdelay(10); + + /* timeout for not getting stuck in an endless loop */ + if (get_timer(start) >= timeout) { + puts("*** ERROR: Timeout waiting for PHY reset!\n"); + break; + } + }; + + /* Restore NRST value */ + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); +} diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h index 3ca4d5b..59e2f43 100644 --- a/arch/arm/include/asm/arch-at91/at91_common.h +++ b/arch/arm/include/asm/arch-at91/at91_common.h @@ -26,5 +26,6 @@ void at91_plla_init(u32 pllar); void at91_mck_init(u32 mckr); void at91_pmc_init(void); void mem_init(void); +void at91_phy_reset(void); #endif /* AT91_COMMON_H */ diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c index e2ae6fd..412ff3b 100644 --- a/board/BuS/vl_ma2sc/vl_ma2sc.c +++ b/board/BuS/vl_ma2sc/vl_ma2sc.c @@ -16,7 +16,6 @@ #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pio.h> -#include <asm/arch/at91_rstc.h> #include <asm/arch/at91sam9263.h> #include <asm/arch/gpio.h> #include <asm/arch/at91_common.h> @@ -76,25 +75,12 @@ static void vl_ma2sc_nand_hw_init(void) #ifdef CONFIG_MACB static void vl_ma2sc_macb_hw_init(void) { - unsigned long erstl; at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; + /* Enable clock */ writel(1 << ATMEL_ID_EMAC, &pmc->pcer); - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* Need to reset PHY -> 500ms reset */ - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - /* Wait for end hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) - ; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); + at91_phy_reset(); at91_macb_hw_init(); } diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c index e1b1c10..ea9575d 100644 --- a/board/afeb9260/afeb9260.c +++ b/board/afeb9260/afeb9260.c @@ -13,7 +13,6 @@ #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <asm/io.h> #include <asm/arch/hardware.h> @@ -67,8 +66,6 @@ static void afeb9260_macb_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; - unsigned long erstl; /* Enable EMAC clock */ @@ -94,20 +91,7 @@ static void afeb9260_macb_hw_init(void) pin_to_mask(AT91_PIN_PA28), &pioa->pudr); - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* Need to reset PHY -> 500ms reset */ - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - - /* Wait for end hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) - ; - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, - &rstc->mr); - + at91_phy_reset(); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 263de49..7f14af1 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -12,7 +12,6 @@ #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <atmel_mci.h> @@ -73,8 +72,6 @@ static void at91sam9260ek_macb_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; - unsigned long erstl; /* Enable EMAC clock */ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); @@ -98,21 +95,7 @@ static void at91sam9260ek_macb_hw_init(void) pin_to_mask(AT91_PIN_PA28), &pioa->pudr); - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* Need to reset PHY -> 500ms reset */ - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - - /* Wait for end hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) - ; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, - &rstc->mr); + at91_phy_reset(); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 2e9246f..d42a173 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -12,7 +12,6 @@ #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> #include <asm/arch/at91_matrix.h> #include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> @@ -82,10 +81,9 @@ static void at91sam9263ek_nand_hw_init(void) #ifdef CONFIG_MACB static void at91sam9263ek_macb_hw_init(void) { - unsigned long erstl; at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; + /* Enable clock */ writel(1 << ATMEL_ID_EMAC, &pmc->pcer); @@ -97,23 +95,10 @@ static void at91sam9263ek_macb_hw_init(void) * * PHY has internal pull-down */ - writel(1 << 25, &pio->pioc.pudr); writel((1 << 25) | (1 <<26), &pio->pioe.pudr); - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* Need to reset PHY -> 500ms reset */ - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - /* Wait for end hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) - ; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); + at91_phy_reset(); /* Re-enable pull-up */ writel(1 << 25, &pio->pioc.puer); diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 6a071f6..b7e2efd 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -12,7 +12,6 @@ #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> #include <lcd.h> @@ -88,8 +87,6 @@ static void at91sam9m10g45ek_macb_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; - unsigned long erstl; /* Enable clock */ writel(1 << ATMEL_ID_EMAC, &pmc->pcer); @@ -107,21 +104,7 @@ static void at91sam9m10g45ek_macb_hw_init(void) pin_to_mask(AT91_PIN_PA13), &pioa->pudr); - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* Need to reset PHY -> 500ms reset */ - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - - /* Wait for end hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) - ; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, - &rstc->mr); + at91_phy_reset(); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA15) | diff --git a/board/bluewater/snapper9260/snapper9260.c b/board/bluewater/snapper9260/snapper9260.c index 8a6919d..bfde129 100644 --- a/board/bluewater/snapper9260/snapper9260.c +++ b/board/bluewater/snapper9260/snapper9260.c @@ -14,7 +14,6 @@ #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <net.h> #include <netdev.h> @@ -31,8 +30,6 @@ static void macb_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; - unsigned long erstl; /* Enable clock */ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); @@ -54,18 +51,7 @@ static void macb_hw_init(void) /* Enable ethernet power */ pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0); - /* Need to reset PHY -> 500ms reset */ - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - - /* Wait for end hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) - ; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); + at91_phy_reset(); /* Bring the ethernet out of reset */ pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1); diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c index ecf261c..2074a93 100644 --- a/board/calao/sbc35_a9g20/sbc35_a9g20.c +++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c @@ -15,7 +15,6 @@ #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) @@ -77,8 +76,6 @@ static void sbc35_a9g20_macb_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; - unsigned long erstl; /* Enable EMAC clock */ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); @@ -102,21 +99,7 @@ static void sbc35_a9g20_macb_hw_init(void) pin_to_mask(AT91_PIN_PA28), &pioa->pudr); - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* Need to reset PHY -> 500ms reset */ - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - - /* Wait for end hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) - ; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, - &rstc->mr); + at91_phy_reset(); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c index 5e1524e..274f72d 100644 --- a/board/eukrea/cpu9260/cpu9260.c +++ b/board/eukrea/cpu9260/cpu9260.c @@ -17,7 +17,6 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_matrix.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> #include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> #include <asm/arch/hardware.h> @@ -89,29 +88,14 @@ static void cpu9260_nand_hw_init(void) #ifdef CONFIG_MACB static void cpu9260_macb_hw_init(void) { - unsigned long rstcmr; at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; /* Enable clock */ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1); - rstcmr = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* Need to reset PHY -> 500ms reset */ - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0xD) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - - /* Wait for end hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) - ; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | rstcmr | AT91_RSTC_MR_URSTEN, &rstc->mr); + at91_phy_reset(); at91_macb_hw_init(); } diff --git a/board/taskit/stamp9g20/stamp9g20.c b/board/taskit/stamp9g20/stamp9g20.c index 704a63b..27cdf77 100644 --- a/board/taskit/stamp9g20/stamp9g20.c +++ b/board/taskit/stamp9g20/stamp9g20.c @@ -19,7 +19,6 @@ #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <watchdog.h> @@ -67,8 +66,6 @@ static void stamp9G20_nand_hw_init(void) static void stamp9G20_macb_hw_init(void) { struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; - unsigned long erstl; /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */ at91_set_gpio_output(AT91_PIN_PA26, 0); @@ -91,33 +88,7 @@ static void stamp9G20_macb_hw_init(void) pin_to_mask(AT91_PIN_PA28), &pioa->pudr); - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* Need to reset PHY -> 500ms reset */ - writel(AT91_RSTC_KEY | (AT91_RSTC_MR_ERSTL(13) & - ~AT91_RSTC_MR_URSTEN), &rstc->mr); - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - - /* Wait for end of hardware reset */ - unsigned long start = get_timer(0); - unsigned long timeout = 1000; /* 1000ms */ - - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) { - - /* avoid shutdown by watchdog */ - WATCHDOG_RESET(); - mdelay(10); - - /* timeout for not getting stuck in an endless loop */ - if (get_timer(start) >= timeout) { - puts("*** ERROR: Timeout waiting for PHY reset!\n"); - break; - }; - }; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, - &rstc->mr); + at91_phy_reset(); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | diff --git a/spl/Makefile b/spl/Makefile index 736c6ca..cbd3d27 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -111,10 +111,6 @@ ifneq ($(CONFIG_MX23)$(CONFIG_MX35),) LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o endif -ifeq ($(SOC),at91) -LIBS-y += arch/$(ARCH)/cpu/at91-common/libat91-common.o -endif - # Add GCC lib ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o -- 1.8.3.1

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[U-Boot] [PATCH] i2c, zynq: convert zynq i2c driver to new multibus/multiadapter framework
by Heiko Schocher 13 Nov '13

13 Nov '13

- add zync i2c driver to new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: Heiko Schocher <hs(a)denx.de> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Michal Simek <michal.simek(a)xilinx.com> --- README | 5 +++++ drivers/i2c/Makefile | 2 +- drivers/i2c/zynq_i2c.c | 29 ++++++++++++++++------------- include/configs/zynq.h | 8 ++++---- 4 files changed, 26 insertions(+), 18 deletions(-) diff --git a/README b/README index 19aed51..1b9312f 100644 --- a/README +++ b/README @@ -2064,6 +2064,11 @@ CBFS (Coreboot Filesystem) support - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4 - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4 + - drivers/i2c/zynq_i2c.c + - activate this driver with CONFIG_SYS_I2C_ZYNQ + - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting + - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr + additional defines: CONFIG_SYS_NUM_I2C_BUSES diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 298b17b..9dd9094 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -28,4 +28,4 @@ obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o -obj-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o +obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c index ce2d23f..70a9aea 100644 --- a/drivers/i2c/zynq_i2c.c +++ b/drivers/i2c/zynq_i2c.c @@ -74,7 +74,8 @@ static struct zynq_i2c_registers *zynq_i2c = (struct zynq_i2c_registers *)ZYNQ_I2C_BASE; /* I2C init called by cmd_i2c when doing 'i2c reset'. */ -void i2c_init(int requested_speed, int slaveadd) +static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed, + int slaveadd) { /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */ writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) | @@ -151,7 +152,7 @@ static u32 zynq_i2c_wait(u32 mask) * I2C probe called by cmd_i2c when doing 'i2c probe'. * Begin read, nak data byte, end. */ -int i2c_probe(u8 dev) +static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev) { /* Attempt to read a byte */ setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | @@ -170,7 +171,8 @@ int i2c_probe(u8 dev) * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c * Begin write, send address byte(s), begin read, receive data bytes, end. */ -int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) +static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, + int alen, u8 *data, int length) { u32 status; u32 i = 0; @@ -235,7 +237,8 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c * Begin write, send address byte(s), send data bytes, end. */ -int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) +static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, + int alen, u8 *data, int length) { u8 *cur_data = data; @@ -275,16 +278,16 @@ int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) return 0; } -int i2c_set_bus_num(unsigned int bus) +static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) { - /* Only support bus 0 */ - if (bus > 0) - return -1; - return 0; -} + if (speed != 1000000) + return -EINVAL; -unsigned int i2c_get_bus_num(void) -{ - /* Only support bus 0 */ return 0; } + +U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read, + zynq_i2c_write, zynq_i2c_set_bus_speed, + CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE, + 0) diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 4c6e6e8..82ec826 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -60,10 +60,10 @@ /* I2C */ #if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1) # define CONFIG_CMD_I2C -# define CONFIG_ZYNQ_I2C -# define CONFIG_HARD_I2C -# define CONFIG_SYS_I2C_SPEED 100000 -# define CONFIG_SYS_I2C_SLAVE 1 +# define CONFIG_SYS_I2C +# define CONFIG_SYS_I2C_ZYNQ +# define CONFIG_SYS_I2C_ZYNQ_SPEED 100000 +# define CONFIG_SYS_I2C_ZYNQ_SLAVE 1 #endif #if defined(CONFIG_ZYNQ_DCC) -- 1.8.3.1

2 4

[U-Boot] [PATCH] designware_i2c: remove 10msec delay in i2c_xfer_finish
by Alexey Brodkin 13 Nov '13

13 Nov '13

This delay applies to any data transfer on I2C bus. For example 1kB data read with per-byte access (which happens if environment is stored in I2C EEPROM) takes more than 10 seconds. Moreover data bus driver has to care about bus state and data transfer, but not about internal states of attached devices. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Tom Rini <trini(a)ti.com> cc: Armando Visconti <armando.visconti(a)st.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Cc: Heiko Schocher <hs(a)denx.de> Cc: Vipin KUMAR <vipin.kumar(a)st.com> Cc: Tom Rix <Tom.Rix(a)windriver.com> Cc: Mischa Jonker <mjonker(a)synopsys.com> --- drivers/i2c/designware_i2c.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index c5c6015..cb2ac04 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -249,9 +249,6 @@ static int i2c_xfer_finish(void) i2c_flush_rxfifo(); - /* Wait for read/write operation to complete on actual memory */ - udelay(10000); - return 0; } -- 1.8.4.2

2 1

[U-Boot] [PATCH] designware_i2c: disable i2c controller during target address setup
by Alexey Brodkin 13 Nov '13

13 Nov '13

As it is stated in DesignWare I2C databook: writes to IC_TAR (0x4) register succeed only when IC_ENABLE[0] is set to 0. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Tom Rini <trini(a)ti.com> cc: Armando Visconti <armando.visconti(a)st.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Cc: Heiko Schocher <hs(a)denx.de> Cc: Vipin KUMAR <vipin.kumar(a)st.com> Cc: Tom Rix <Tom.Rix(a)windriver.com> Cc: Mischa Jonker <mjonker(a)synopsys.com> --- drivers/i2c/designware_i2c.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index c2f0662..c5c6015 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -151,7 +151,19 @@ void i2c_init(int speed, int slaveadd) */ static void i2c_setaddress(unsigned int i2c_addr) { + unsigned int enbl; + + /* Disable i2c */ + enbl = readl(&i2c_regs_p->ic_enable); + enbl &= ~IC_ENABLE_0B; + writel(enbl, &i2c_regs_p->ic_enable); + writel(i2c_addr, &i2c_regs_p->ic_tar); + + /* Enable i2c */ + enbl = readl(&i2c_regs_p->ic_enable); + enbl |= IC_ENABLE_0B; + writel(enbl, &i2c_regs_p->ic_enable); } /* -- 1.8.4.2

3 2

[U-Boot] [PATCH] cmd_eeprom: fix i2c_{read|write} usage if env is in I2C EEPROM
by Alexey Brodkin 13 Nov '13

13 Nov '13

Data "offset" is not used directly in case of I2C EEPROM. Istead it is split into "block number" and "offset within mentioned block". Which are "addr[0]" and "addr[1]" respectively. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> cc: Peter Tyser <ptyser(a)xes-inc.com> Cc: Heiko Schocher <hs(a)denx.de> Cc: Wolfgang Denk <wd(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Mischa Jonker <mjonker(a)synopsys.com> --- common/cmd_eeprom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c index ef694d8..02539c4 100644 --- a/common/cmd_eeprom.c +++ b/common/cmd_eeprom.c @@ -161,7 +161,7 @@ int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt #if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) spi_read (addr, alen, buffer, len); #else - if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0) + if (i2c_read (addr[0], addr[1], alen-1, buffer, len) != 0) rcode = 1; #endif buffer += len; @@ -339,7 +339,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn /* Write is enabled ... now write eeprom value. */ #endif - if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0) + if (i2c_write (addr[0], addr[1], alen-1, buffer, len) != 0) rcode = 1; #endif -- 1.8.4.2

2 1

[U-Boot] [PATCH V2] i2c: mxs_i2c: Squash endless loop
by Marek Vasut 13 Nov '13

13 Nov '13

The endless waiting for a bit to be set can cause a hang, add a timeout so we prevent such situation. A testcase for such a hang is below. The testcase assumes a device to be present at address 0x50 and a device to NOT be present at address 0x42 . Also note that the "sleep 1" induced delays are imperative for this bug to manifest . i2c read 0x42 0x0.2 0x10 0x42000000 ; sleep 1 ; \ i2c read 0x50 0x0.2 0x10 0x42000000 ; sleep 1 ; \ i2c read 0x42 0x0.2 0x10 0x42000000 The expected result of the above command is: Error reading the chip. Error reading the chip. While without this patch, we observe a hang in the last read from 0x42 precisely when waiting for this bit to be set. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> Cc: Heiko Schocher <hs(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> --- drivers/i2c/mxs_i2c.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) V2: Replace -EINVAL with -ETIMEDOUT diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c index 46106b7..a298c95 100644 --- a/drivers/i2c/mxs_i2c.c +++ b/drivers/i2c/mxs_i2c.c @@ -150,6 +150,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; uint32_t tmp = 0; + int timeout = MXS_I2C_MAX_TIMEOUT; int ret; int i; @@ -169,9 +170,17 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) for (i = 0; i < len; i++) { if (!(i & 3)) { - while (readl(&i2c_regs->hw_i2c_queuestat) & - I2C_QUEUESTAT_RD_QUEUE_EMPTY) - ; + while (--timeout) { + tmp = readl(&i2c_regs->hw_i2c_queuestat); + if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY)) + break; + } + + if (!timeout) { + debug("MXS I2C: Failed receiving data!\n"); + return -ETIMEDOUT; + } + tmp = readl(&i2c_regs->hw_i2c_queuedata); } buffer[i] = tmp & 0xff; -- 1.8.4.rc3

2 1

[U-Boot] [PATCH v2] i2c: sh_i2c: Update to new CONFIG_SYS_I2C framework
by Nobuhiro Iwamatsu 13 Nov '13

13 Nov '13

This updates to new I2C framwwork on sh_i2c. And this also updates boards(kzm9g and ecovec) that using sh_i2c. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- v2: Squash with patch for kzm9g and ecovec. Remove i2c_init() from kzm9g.c and ecovec.c. README | 18 +++ board/kmc/kzm9g/kzm9g.c | 1 - board/renesas/ecovec/ecovec.c | 3 +- drivers/i2c/Makefile | 2 +- drivers/i2c/sh_i2c.c | 294 +++++++++++++++++++----------------------- include/configs/ecovec.h | 15 +-- include/configs/kzm9g.h | 31 ++--- 7 files changed, 174 insertions(+), 190 deletions(-) diff --git a/README b/README index f0eedbb..d7be66a 100644 --- a/README +++ b/README @@ -2028,6 +2028,24 @@ CBFS (Coreboot Filesystem) support - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3 - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses + - drivers/i2c/sh_i2c.c: + - activate this driver with CONFIG_SYS_I2C_SH + - This driver adds from 2 to 5 i2c buses + + - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0 + - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0 + - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1 + - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1 + - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2 + - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2 + - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3 + - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3 + - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4 + - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4 + - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5 + - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5 + - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses + additional defines: CONFIG_SYS_NUM_I2C_BUSES diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c index b669ffe..ea36fa4 100644 --- a/board/kmc/kzm9g/kzm9g.c +++ b/board/kmc/kzm9g/kzm9g.c @@ -289,7 +289,6 @@ void adjust_core_voltage(void) { u8 data; - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); data = 0x35; i2c_set_bus_num(0); i2c_write(0x40, 3, 1, &data, 1); diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c index e2d365a..fb4acf3 100644 --- a/board/renesas/ecovec/ecovec.c +++ b/board/renesas/ecovec/ecovec.c @@ -57,8 +57,7 @@ int board_late_init(void) outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - i2c_set_bus_num(CONFIG_SYS_I2C_MODULE); /* Use I2C 1 */ + i2c_set_bus_num(1); /* Use I2C 1 */ /* Read MAC address */ i2c_read(0x50, 0x10, 0, mac, 6); diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 84a2754..ff52874 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -22,7 +22,6 @@ COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o -COBJS-$(CONFIG_SH_I2C) += sh_i2c.o COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o COBJS-$(CONFIG_SYS_I2C) += i2c_core.o COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o @@ -30,6 +29,7 @@ COBJS-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o COBJS-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o COBJS-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o COBJS-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o +COBJS-$(CONFIG_SYS_I2C_SH) += sh_i2c.o COBJS-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o COBJS-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o COBJS-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index 808202c..cc19100 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <i2c.h> #include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -22,8 +23,6 @@ struct sh_i2c { }; #undef ureg -static struct sh_i2c *base; - /* ICCR */ #define SH_I2C_ICCR_ICE (1 << 7) #define SH_I2C_ICCR_RACK (1 << 6) @@ -43,202 +42,165 @@ static struct sh_i2c *base; #define SH_I2C_ICIC_ICCHB8 (1 << 6) #endif +static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = { + (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0, +#ifdef CONFIG_SYS_I2C_SH_BASE1 + (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1, +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE2 + (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2, +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE3 + (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3, +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE4 + (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4, +#endif +}; + static u16 iccl, icch; #define IRQ_WAIT 1000 -static void irq_dte(struct sh_i2c *base) +static void sh_irq_dte(struct sh_i2c *dev) { int i; - for (i = 0 ; i < IRQ_WAIT ; i++) { - if (SH_IC_DTE & readb(&base->icsr)) + for (i = 0; i < IRQ_WAIT; i++) { + if (SH_IC_DTE & readb(&dev->icsr)) break; udelay(10); } } -static int irq_dte_with_tack(struct sh_i2c *base) +static int sh_irq_dte_with_tack(struct sh_i2c *dev) { int i; - for (i = 0 ; i < IRQ_WAIT ; i++) { - if (SH_IC_DTE & readb(&base->icsr)) + for (i = 0; i < IRQ_WAIT; i++) { + if (SH_IC_DTE & readb(&dev->icsr)) break; - if (SH_IC_TACK & readb(&base->icsr)) + if (SH_IC_TACK & readb(&dev->icsr)) return -1; udelay(10); } return 0; } -static void irq_busy(struct sh_i2c *base) +static void sh_irq_busy(struct sh_i2c *dev) { int i; - for (i = 0 ; i < IRQ_WAIT ; i++) { - if (!(SH_IC_BUSY & readb(&base->icsr))) + for (i = 0; i < IRQ_WAIT; i++) { + if (!(SH_IC_BUSY & readb(&dev->icsr))) break; udelay(10); } } -static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) +static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop) { u8 icic = SH_IC_TACK; - clrbits_8(&base->iccr, SH_I2C_ICCR_ICE); - setbits_8(&base->iccr, SH_I2C_ICCR_ICE); + debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n", + __func__, chip, addr, iccl, icch); + clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE); + setbits_8(&dev->iccr, SH_I2C_ICCR_ICE); - writeb(iccl & 0xff, &base->iccl); - writeb(icch & 0xff, &base->icch); + writeb(iccl & 0xff, &dev->iccl); + writeb(icch & 0xff, &dev->icch); #ifdef CONFIG_SH_I2C_8BIT if (iccl > 0xff) icic |= SH_I2C_ICIC_ICCLB8; if (icch > 0xff) icic |= SH_I2C_ICIC_ICCHB8; #endif - writeb(icic, &base->icic); + writeb(icic, &dev->icic); - writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); - irq_dte(base); + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr); + sh_irq_dte(dev); - clrbits_8(&base->icsr, SH_IC_TACK); - writeb(id << 1, &base->icdr); - if (irq_dte_with_tack(base) != 0) + clrbits_8(&dev->icsr, SH_IC_TACK); + writeb(chip << 1, &dev->icdr); + if (sh_irq_dte_with_tack(dev) != 0) return -1; - writeb(reg, &base->icdr); + writeb(addr, &dev->icdr); if (stop) - writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr); + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr); - if (irq_dte_with_tack(base) != 0) + if (sh_irq_dte_with_tack(dev) != 0) return -1; return 0; } -static void i2c_finish(struct sh_i2c *base) +static void sh_i2c_finish(struct sh_i2c *dev) { - writeb(0, &base->icsr); - clrbits_8(&base->iccr, SH_I2C_ICCR_ICE); + writeb(0, &dev->icsr); + clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE); } -static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val) +static int +sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val) { int ret = -1; - if (i2c_set_addr(base, id, reg, 0) != 0) + if (sh_i2c_set_addr(dev, chip, addr, 0) != 0) goto exit0; udelay(10); - writeb(val, &base->icdr); - if (irq_dte_with_tack(base) != 0) + writeb(val, &dev->icdr); + if (sh_irq_dte_with_tack(dev) != 0) goto exit0; - writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr); - if (irq_dte_with_tack(base) != 0) + writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr); + if (sh_irq_dte_with_tack(dev) != 0) goto exit0; - irq_busy(base); + sh_irq_busy(dev); ret = 0; + exit0: - i2c_finish(base); + sh_i2c_finish(dev); return ret; } -static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) +static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr) { int ret = -1; #if defined(CONFIG_SH73A0) - if (i2c_set_addr(base, id, reg, 0) != 0) + if (sh_i2c_set_addr(dev, chip, addr, 0) != 0) goto exit0; #else - if (i2c_set_addr(base, id, reg, 1) != 0) + if (sh_i2c_set_addr(dev, chip, addr, 1) != 0) goto exit0; udelay(100); #endif - writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); - irq_dte(base); + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr); + sh_irq_dte(dev); - writeb(id << 1 | 0x01, &base->icdr); - if (irq_dte_with_tack(base) != 0) + writeb(chip << 1 | 0x01, &dev->icdr); + if (sh_irq_dte_with_tack(dev) != 0) goto exit0; - writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr); - if (irq_dte_with_tack(base) != 0) + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr); + if (sh_irq_dte_with_tack(dev) != 0) goto exit0; - ret = readb(&base->icdr) & 0xff; + ret = readb(&dev->icdr) & 0xff; + + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr); + readb(&dev->icdr); /* Dummy read */ + sh_irq_busy(dev); - writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr); - readb(&base->icdr); /* Dummy read */ - irq_busy(base); exit0: - i2c_finish(base); + sh_i2c_finish(dev); return ret; } -#ifdef CONFIG_I2C_MULTI_BUS -static unsigned int current_bus; - -/** - * i2c_set_bus_num - change active I2C bus - * @bus: bus index, zero based - * @returns: 0 on success, non-0 on failure - */ -int i2c_set_bus_num(unsigned int bus) -{ - if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) { - printf("Bad bus: %d\n", bus); - return -1; - } - - switch (bus) { - case 0: - base = (void *)CONFIG_SH_I2C_BASE0; - break; - case 1: - base = (void *)CONFIG_SH_I2C_BASE1; - break; -#ifdef CONFIG_SH_I2C_BASE2 - case 2: - base = (void *)CONFIG_SH_I2C_BASE2; - break; -#endif -#ifdef CONFIG_SH_I2C_BASE3 - case 3: - base = (void *)CONFIG_SH_I2C_BASE3; - break; -#endif -#ifdef CONFIG_SH_I2C_BASE4 - case 4: - base = (void *)CONFIG_SH_I2C_BASE4; - break; -#endif - default: - return -1; - } - current_bus = bus; - - return 0; -} - -/** - * i2c_get_bus_num - returns index of active I2C bus - */ -unsigned int i2c_get_bus_num(void) -{ - return current_bus; -} -#endif - -#define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \ - ((clk / rate) * (t_low / t_low + t_high)) -#define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \ - ((clk / rate) * (t_high / t_low + t_high)) - -void i2c_init(int speed, int slaveaddr) +static void +sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) { int num, denom, tmp; @@ -246,11 +208,6 @@ void i2c_init(int speed, int slaveaddr) if (!(gd->flags & GD_FLG_RELOC)) return; -#ifdef CONFIG_I2C_MULTI_BUS - current_bus = 0; -#endif - base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0; - /* * Calculate the value for iccl. From the data sheet: * iccl = (p-clock / transfer-rate) * (L / (L + H)) @@ -272,67 +229,78 @@ void i2c_init(int speed, int slaveaddr) icch = (u16)((num/denom) + 1); else icch = (u16)(num/denom); + + debug("clock: %d, speed %d, iccl: %x, icch: %x\n", + CONFIG_SH_I2C_CLOCK, speed, iccl, icch); } -/* - * i2c_read: - Read multiple bytes from an i2c device - * - * The higher level routines take into account that this function is only - * called with len < page length of the device (see configuration file) - * - * @chip: address of the chip which is to be read - * @addr: i2c data address within the chip - * @alen: length of the i2c data address (1..2 bytes) - * @buffer: where to write the data - * @len: how much byte do we want to read - * @return: 0 in case of success - */ -int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len) +static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip, + uint addr, int alen, u8 *data, int len) { - int ret; - int i = 0; - for (i = 0 ; i < len ; i++) { - ret = i2c_raw_read(base, chip, addr + i); + int ret, i; + struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr]; + + for (i = 0; i < len; i++) { + ret = sh_i2c_raw_read(dev, chip, addr + i); if (ret < 0) return -1; - buffer[i] = ret & 0xff; + + data[i] = ret & 0xff; + debug("%s: data[%d]: %02x\n", __func__, i, data[i]); } + return 0; } -/* - * i2c_write: - Write multiple bytes to an i2c device - * - * The higher level routines take into account that this function is only - * called with len < page length of the device (see configuration file) - * - * @chip: address of the chip which is to be written - * @addr: i2c data address within the chip - * @alen: length of the i2c data address (1..2 bytes) - * @buffer: where to find the data to be written - * @len: how much byte do we want to read - * @return: 0 in case of success - */ -int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) +static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr, + int alen, u8 *data, int len) { - int i = 0; - for (i = 0; i < len ; i++) - if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0) + struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr]; + int i; + + for (i = 0; i < len; i++) { + debug("%s: data[%d]: %02x\n", __func__, i, data[i]); + if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0) return -1; + } return 0; } -/* - * i2c_probe: - Test if a chip answers for a given i2c address - * - * @chip: address of the chip which is searched for - * @return: 0 if a chip was found, -1 otherwhise - */ -int i2c_probe(u8 chip) +static int +sh_i2c_probe(struct i2c_adapter *adap, u8 dev) { - int ret; + return sh_i2c_read(adap, dev, 0, 0, NULL, 0); +} - ret = i2c_set_addr(base, chip, 0, 1); - i2c_finish(base); - return ret; +static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) +{ + struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr]; + + sh_i2c_finish(dev); + sh_i2c_init(adap, speed, 0); + + return 0; } + +/* + * Register RCAR i2c adapters + */ +U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read, + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0) +#ifdef CONFIG_SYS_I2C_SH_BASE1 +U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read, + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1) +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE2 +U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read, + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2) +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE3 +U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read, + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3) +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE4 +U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read, + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4) +#endif diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h index 2c9594b..e09b283 100644 --- a/include/configs/ecovec.h +++ b/include/configs/ecovec.h @@ -58,18 +58,17 @@ /* I2C */ #define CONFIG_CMD_I2C -#define CONFIG_SH_I2C 1 -#define CONFIG_HARD_I2C 1 -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_SYS_MAX_I2C_BUS 2 -#define CONFIG_SYS_I2C_MODULE 1 -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH #define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2 +#define CONFIG_SYS_I2C_SH_BASE0 0xA4470000 +#define CONFIG_SYS_I2C_SH_SPEED0 100000 +#define CONFIG_SYS_I2C_SH_BASE1 0xA4750000 +#define CONFIG_SYS_I2C_SH_SPEED1 100000 #define CONFIG_SH_I2C_DATA_HIGH 4 #define CONFIG_SH_I2C_DATA_LOW 5 #define CONFIG_SH_I2C_CLOCK 41666666 -#define CONFIG_SH_I2C_BASE0 0xA4470000 -#define CONFIG_SH_I2C_BASE1 0xA4750000 /* Ether */ #define CONFIG_SH_ETHER 1 diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 222725c..81e3aff 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -140,21 +140,22 @@ /* I2C */ #define CONFIG_CMD_I2C -#define CONFIG_SH_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5 +#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000 +#define CONFIG_SYS_I2C_SH_SPEED0 100000 +#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000 +#define CONFIG_SYS_I2C_SH_SPEED1 100000 +#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000 +#define CONFIG_SYS_I2C_SH_SPEED2 100000 +#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000 +#define CONFIG_SYS_I2C_SH_SPEED3 100000 +#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000 +#define CONFIG_SYS_I2C_SH_SPEED4 100000 #define CONFIG_SH_I2C_8BIT -#define CONFIG_HARD_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_MAX_I2C_BUS (5) -#define CONFIG_SYS_I2C_MODULE -#define CONFIG_SYS_I2C_SPEED (100000) /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE (0x7F) -#define CONFIG_SH_I2C_DATA_HIGH (4) -#define CONFIG_SH_I2C_DATA_LOW (5) -#define CONFIG_SH_I2C_CLOCK (104000000) /* 104 MHz */ -#define CONFIG_SH_I2C_BASE0 (0xE6820000) -#define CONFIG_SH_I2C_BASE1 (0xE6822000) -#define CONFIG_SH_I2C_BASE2 (0xE6824000) -#define CONFIG_SH_I2C_BASE3 (0xE6826000) -#define CONFIG_SH_I2C_BASE4 (0xE6828000) +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */ #endif /* __KZM9G_H */ -- 1.8.4.rc3

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[U-Boot] [PATCH v4] i2c, omap24xx: convert driver to new mutlibus/mutliadapter framework
by Heiko Schocher 13 Nov '13

13 Nov '13

- add omap24xx driver to new multibus/multiadpater support - adapted all config files, which uses this driver Tested on the am335x based siemens boards rut, dxr2 and pxm2 posted here: http://patchwork.ozlabs.org/patch/263211/ Signed-off-by: Heiko Schocher <hs(a)denx.de> Tested-by: Tom Rini <trini(a)ti.com> Cc: Lars Poeschel <poeschel(a)lemonage.de> Cc: Steve Sakoman <sakoman(a)gmail.com> Cc: Thomas Weber <weber(a)corscience.de> Cc: Tom Rix <Tom.Rix(a)windriver.com> Cc: Grazvydas Ignotas <notasas(a)gmail.com> Cc: Enric Balletbo i Serra <eballetbo(a)iseebcn.com> Cc: Luca Ceresoli <luca.ceresoli(a)comelit.it> Cc: Igor Grinberg <grinberg(a)compulab.co.il> Cc: Ilya Yanok <yanok(a)emcraft.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Nishanth Menon <nm(a)ti.com> Cc: Pali Rohár <pali.rohar(a)gmail.com> Cc: Peter Barada <peter.barada(a)logicpd.com> Cc: Nagendra T S <nagendra(a)mistralsolutions.com> Cc: Michael Jones <michael.jones(a)matrix-vision.de> Cc: Raphael Assenat <raph(a)8d.com> --- - changes for v2: rebased against u-boot-ti 425faf74cd8189c87919f7e72a0101c684ee3b9f - changes for v3: rebase against: u-boot-it 901ce27c6f018992b7dd6c08d3c98cf217cc4c96 add siemens boards (rut, dxr2 and pxm2) - changes for v4: fix u-boot spl mode --- README | 13 ++ arch/arm/cpu/armv7/omap-common/clocks-common.c | 3 +- arch/arm/cpu/armv7/omap-common/u-boot-spl.lds | 4 + arch/arm/cpu/armv7/omap3/board.c | 2 +- arch/arm/cpu/armv7/omap3/clock.c | 2 +- arch/arm/include/asm/arch-am33xx/i2c.h | 6 +- board/compulab/cm_t35/Makefile | 2 +- board/compulab/cm_t35/cm_t35.c | 2 +- board/compulab/cm_t35/eeprom.h | 2 +- board/logicpd/am3517evm/am3517evm.c | 4 +- board/overo/overo.c | 2 +- board/phytec/pcm051/board.c | 4 +- board/siemens/common/board.c | 4 +- board/ti/am335x/board.c | 2 +- board/ti/am3517crane/am3517crane.c | 4 +- board/ti/evm/evm.c | 4 +- drivers/i2c/Makefile | 4 +- drivers/i2c/omap24xx_i2c.c | 172 ++++++++++++++++--------- include/configs/am335x_evm.h | 1 - include/configs/am3517_crane.h | 8 +- include/configs/am3517_evm.h | 8 +- include/configs/cm_t35.h | 8 +- include/configs/devkit8000.h | 8 +- include/configs/dig297.h | 8 +- include/configs/igep00x0.h | 8 +- include/configs/mcx.h | 8 +- include/configs/nokia_rx51.h | 8 +- include/configs/omap3_beagle.h | 9 +- include/configs/omap3_evm_common.h | 9 +- include/configs/omap3_logic.h | 10 +- include/configs/omap3_mvblx.h | 9 +- include/configs/omap3_overo.h | 9 +- include/configs/omap3_pandora.h | 8 +- include/configs/omap3_sdp3430.h | 8 +- include/configs/omap3_zoom1.h | 8 +- include/configs/omap3_zoom2.h | 8 +- include/configs/omap4_common.h | 9 +- include/configs/pcm051.h | 9 +- include/configs/siemens-am33x-common.h | 9 +- include/configs/tam3517-common.h | 11 +- include/configs/ti_armv7_common.h | 9 +- include/configs/tricorder.h | 8 +- 42 files changed, 242 insertions(+), 192 deletions(-) diff --git a/README b/README index 09662a4..e6e0465 100644 --- a/README +++ b/README @@ -2003,6 +2003,19 @@ CBFS (Coreboot Filesystem) support - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0 - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1 + - drivers/i2c/omap24xx_i2c.c + - activate this driver with CONFIG_SYS_I2C_OMAP24XX + - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0 + - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0 + - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1 + - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1 + - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2 + - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2 + - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3 + - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3 + - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4 + - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4 + additional defines: CONFIG_SYS_NUM_I2C_BUSES diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index ab0c568..98c3630 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -779,7 +779,8 @@ void gpi2c_init(void) static int gpi2c = 1; if (gpi2c) { - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, + CONFIG_SYS_OMAP24_I2C_SLAVE); gpi2c = 0; } } diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds index 5e93b34..989083c 100644 --- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds @@ -33,6 +33,10 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } >.sram + . = ALIGN(4); __image_copy_end = .; _end = .; diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 7d1f8d9..2922816 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -98,7 +98,7 @@ void spl_board_init(void) gpmc_init(); #endif #ifdef CONFIG_SPL_I2C_SUPPORT - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif } #endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 9f989ff..14fc7e8 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -708,7 +708,7 @@ void per_clocks_enable(void) sr32(&prcm_base->iclken_per, 17, 1, 1); #endif -#ifdef CONFIG_DRIVER_OMAP34XX_I2C +#ifdef CONFIG_SYS_I2C_OMAP34XX /* Turn on all 3 I2C clocks */ sr32(&prcm_base->fclken1_core, 15, 3, 0x7); sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */ diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h b/arch/arm/include/asm/arch-am33xx/i2c.h index 8bfa53f..8642c8f 100644 --- a/arch/arm/include/asm/arch-am33xx/i2c.h +++ b/arch/arm/include/asm/arch-am33xx/i2c.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _I2C_H_ -#define _I2C_H_ +#ifndef _I2C_AM33XX_H_ +#define _I2C_AM33XX_H_ #define I2C_BASE1 0x44E0B000 #define I2C_BASE2 0x4802A000 @@ -62,4 +62,4 @@ struct i2c { #define I2C_IP_CLK 48000000 #define I2C_INTERNAL_SAMPLING_CLK 12000000 -#endif /* _I2C_H_ */ +#endif /* _I2C_AM33XX_H_ */ diff --git a/board/compulab/cm_t35/Makefile b/board/compulab/cm_t35/Makefile index 6d07947..9014d2a 100644 --- a/board/compulab/cm_t35/Makefile +++ b/board/compulab/cm_t35/Makefile @@ -11,7 +11,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o +COBJS-$(CONFIG_SYS_I2C_OMAP34XX) += eeprom.o COBJS-$(CONFIG_LCD) += display.o COBJS := cm_t35.o leds.o $(COBJS-y) diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index 3caa5be..1dd3647 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -470,7 +470,7 @@ static void setup_net_chip_gmpc(void) &ctrl_base->gpmc_nadv_ale); } -#ifdef CONFIG_DRIVER_OMAP34XX_I2C +#ifdef CONFIG_SYS_I2C_OMAP34XX /* * Routine: reset_net_chip * Description: reset the Ethernet controller via TPS65930 GPIO diff --git a/board/compulab/cm_t35/eeprom.h b/board/compulab/cm_t35/eeprom.h index 02ffbb1..a07559d 100644 --- a/board/compulab/cm_t35/eeprom.h +++ b/board/compulab/cm_t35/eeprom.h @@ -10,7 +10,7 @@ #ifndef _EEPROM_ #define _EEPROM_ -#ifdef CONFIG_DRIVER_OMAP34XX_I2C +#ifdef CONFIG_SYS_I2C_OMAP34XX int cm_t3x_eeprom_read_mac_addr(uchar *buf); u32 cm_t3x_eeprom_get_board_rev(void); #else diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index b6c68da..1569905 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -98,8 +98,8 @@ static void am3517_evm_musb_init(void) */ int misc_init_r(void) { -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#ifdef CONFIG_SYS_I2C_OMAP34XX + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif dieid_num_r(); diff --git a/board/overo/overo.c b/board/overo/overo.c index aace42a..9ac35d2 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -92,7 +92,7 @@ int get_board_revision(void) { int revision; -#ifdef CONFIG_DRIVER_OMAP34XX_I2C +#ifdef CONFIG_SYS_I2C_OMAP34XX unsigned char data; /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */ diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index dafb1eb..034886a 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -91,7 +91,7 @@ void set_mux_conf_regs(void) { /* Initalize the board header */ enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); enable_board_pin_mux(); } @@ -108,7 +108,7 @@ void sdram_init(void) */ int board_init(void) { - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 6279c32..32d2ee4 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -42,7 +42,7 @@ void set_mux_conf_regs(void) { /* Initalize the board header */ enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_set_bus_num(0); if (read_eeprom() < 0) puts("Could not get board ID.\n"); @@ -67,7 +67,7 @@ int board_init(void) #if defined(CONFIG_HW_WATCHDOG) hw_watchdog_init(); #endif /* defined(CONFIG_HW_WATCHDOG) */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_set_bus_num(0); if (read_eeprom() < 0) puts("Could not get board ID.\n"); diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index c2fc5a6..44a1dea 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -395,7 +395,7 @@ const struct dpll_params *get_dpll_ddr_params(void) struct am335x_baseboard_id header; enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c index 5eb97ff..a649697 100644 --- a/board/ti/am3517crane/am3517crane.c +++ b/board/ti/am3517crane/am3517crane.c @@ -43,8 +43,8 @@ int board_init(void) */ int misc_init_r(void) { -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#ifdef CONFIG_SYS_I2C_OMAP34XX + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif dieid_num_r(); diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index c71c218..81dd081 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -146,8 +146,8 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) int misc_init_r(void) { -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#ifdef CONFIG_SYS_I2C_OMAP34XX + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif #if defined(CONFIG_CMD_NET) diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index df3092e..c2001ea 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -17,8 +17,6 @@ COBJS-$(CONFIG_I2C_MV) += mv_i2c.o COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o COBJS-$(CONFIG_I2C_MXS) += mxs_i2c.o COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o -COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o -COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o @@ -29,6 +27,8 @@ COBJS-$(CONFIG_SYS_I2C) += i2c_core.o COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o COBJS-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o COBJS-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o +COBJS-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o +COBJS-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o COBJS-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o COBJS-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o COBJS-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index ef38d71..3d38c03 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -35,6 +35,7 @@ */ #include <common.h> +#include <i2c.h> #include <asm/arch/i2c.h> #include <asm/io.h> @@ -48,22 +49,14 @@ DECLARE_GLOBAL_DATA_PTR; /* Absolutely safe for status update at 100 kHz I2C: */ #define I2C_WAIT 200 -static int wait_for_bb(void); -static u16 wait_for_event(void); -static void flush_fifo(void); +static int wait_for_bb(struct i2c_adapter *adap); +static struct i2c *omap24_get_base(struct i2c_adapter *adap); +static u16 wait_for_event(struct i2c_adapter *adap); +static void flush_fifo(struct i2c_adapter *adap); -/* - * For SPL boot some boards need i2c before SDRAM is initialised so force - * variables to live in SRAM - */ -static struct i2c __attribute__((section (".data"))) *i2c_base = - (struct i2c *)I2C_DEFAULT_BASE; -static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] = - { [0 ... (I2C_BUS_MAX-1)] = 0 }; -static unsigned int __attribute__((section (".data"))) current_bus = 0; - -void i2c_init(int speed, int slaveadd) +static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) { + struct i2c *i2c_base = omap24_get_base(adap); int psc, fsscll, fssclh; int hsscll = 0, hssclh = 0; u32 scll, sclh; @@ -163,16 +156,15 @@ void i2c_init(int speed, int slaveadd) I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); #endif udelay(1000); - flush_fifo(); + flush_fifo(adap); writew(0xFFFF, &i2c_base->stat); writew(0, &i2c_base->cnt); - - if (gd->flags & GD_FLG_RELOC) - bus_initialized[current_bus] = 1; } -static void flush_fifo(void) -{ u16 stat; +static void flush_fifo(struct i2c_adapter *adap) +{ + struct i2c *i2c_base = omap24_get_base(adap); + u16 stat; /* note: if you try and read data when its not there or ready * you get a bus error @@ -192,8 +184,9 @@ static void flush_fifo(void) * i2c_probe: Use write access. Allows to identify addresses that are * write-only (like the config register of dual-port EEPROMs) */ -int i2c_probe(uchar chip) +static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) { + struct i2c *i2c_base = omap24_get_base(adap); u16 status; int res = 1; /* default = fail */ @@ -201,7 +194,7 @@ int i2c_probe(uchar chip) return res; /* Wait until bus is free */ - if (wait_for_bb()) + if (wait_for_bb(adap)) return res; /* No data transfer, slave addr only */ @@ -212,7 +205,7 @@ int i2c_probe(uchar chip) writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, &i2c_base->con); - status = wait_for_event(); + status = wait_for_event(adap); if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) { /* @@ -223,7 +216,7 @@ int i2c_probe(uchar chip) */ if (status == I2C_STAT_XRDY) printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n", - current_bus, status); + adap->hwadapnr, status); goto pr_exit; } @@ -239,7 +232,7 @@ int i2c_probe(uchar chip) I2C_CON_STP, &i2c_base->con); /* STP */ } pr_exit: - flush_fifo(); + flush_fifo(adap); writew(0xFFFF, &i2c_base->stat); writew(0, &i2c_base->cnt); return res; @@ -258,8 +251,10 @@ pr_exit: * or that do not need a register address at all (such as some clock * distributors). */ -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) { + struct i2c *i2c_base = omap24_get_base(adap); int i2c_error = 0; u16 status; @@ -287,7 +282,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) } /* Wait until bus not busy */ - if (wait_for_bb()) + if (wait_for_bb(adap)) return 1; /* Zero, one or two bytes reg address (offset) */ @@ -308,12 +303,12 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) #endif /* Send register offset */ while (1) { - status = wait_for_event(); + status = wait_for_event(adap); /* Try to identify bus that is not padconf'd for I2C */ if (status == I2C_STAT_XRDY) { i2c_error = 2; printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n", - current_bus, status); + adap->hwadapnr, status); goto rd_exit; } if (status == 0 || status & I2C_STAT_NACK) { @@ -348,7 +343,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) /* Receive data */ while (1) { - status = wait_for_event(); + status = wait_for_event(adap); /* * Try to identify bus that is not padconf'd for I2C. This * state could be left over from previous transactions if @@ -357,7 +352,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) if (status == I2C_STAT_XRDY) { i2c_error = 2; printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n", - current_bus, status); + adap->hwadapnr, status); goto rd_exit; } if (status == 0 || status & I2C_STAT_NACK) { @@ -375,15 +370,17 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) } rd_exit: - flush_fifo(); + flush_fifo(adap); writew(0xFFFF, &i2c_base->stat); writew(0, &i2c_base->cnt); return i2c_error; } /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */ -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) { + struct i2c *i2c_base = omap24_get_base(adap); int i; u16 status; int i2c_error = 0; @@ -415,7 +412,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) } /* Wait until bus not busy */ - if (wait_for_bb()) + if (wait_for_bb(adap)) return 1; /* Start address phase - will write regoffset + len bytes data */ @@ -428,12 +425,12 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) while (alen) { /* Must write reg offset (one or two bytes) */ - status = wait_for_event(); + status = wait_for_event(adap); /* Try to identify bus that is not padconf'd for I2C */ if (status == I2C_STAT_XRDY) { i2c_error = 2; printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n", - current_bus, status); + adap->hwadapnr, status); goto wr_exit; } if (status == 0 || status & I2C_STAT_NACK) { @@ -455,7 +452,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) } /* Address phase is over, now write data */ for (i = 0; i < len; i++) { - status = wait_for_event(); + status = wait_for_event(adap); if (status == 0 || status & I2C_STAT_NACK) { i2c_error = 1; printf("i2c_write: error waiting for data ACK (status=0x%x)\n", @@ -474,7 +471,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) } wr_exit: - flush_fifo(); + flush_fifo(adap); writew(0xFFFF, &i2c_base->stat); writew(0, &i2c_base->cnt); return i2c_error; @@ -484,8 +481,9 @@ wr_exit: * Wait for the bus to be free by checking the Bus Busy (BB) * bit to become clear */ -static int wait_for_bb(void) +static int wait_for_bb(struct i2c_adapter *adap) { + struct i2c *i2c_base = omap24_get_base(adap); int timeout = I2C_TIMEOUT; u16 stat; @@ -514,8 +512,9 @@ static int wait_for_bb(void) * Wait for the I2C controller to complete current action * and update status */ -static u16 wait_for_event(void) +static u16 wait_for_event(struct i2c_adapter *adap) { + struct i2c *i2c_base = omap24_get_base(adap); u16 status; int timeout = I2C_TIMEOUT; @@ -540,7 +539,7 @@ static u16 wait_for_event(void) * not been configured for I2C, and/or pull-ups are missing. */ printf("Check if pads/pull-ups of bus %d are properly configured\n", - current_bus); + adap->hwadapnr); writew(0xFFFF, &i2c_base->stat); status = 0; } @@ -548,48 +547,93 @@ static u16 wait_for_event(void) return status; } -int i2c_set_bus_num(unsigned int bus) +static struct i2c *omap24_get_base(struct i2c_adapter *adap) { - if (bus >= I2C_BUS_MAX) { - printf("Bad bus: %x\n", bus); - return -1; - } - - switch (bus) { - default: - bus = 0; /* Fall through */ + switch (adap->hwadapnr) { case 0: - i2c_base = (struct i2c *)I2C_BASE1; + return (struct i2c *)I2C_BASE1; break; case 1: - i2c_base = (struct i2c *)I2C_BASE2; + return (struct i2c *)I2C_BASE2; break; #if (I2C_BUS_MAX > 2) case 2: - i2c_base = (struct i2c *)I2C_BASE3; + return (struct i2c *)I2C_BASE3; break; #if (I2C_BUS_MAX > 3) case 3: - i2c_base = (struct i2c *)I2C_BASE4; + return (struct i2c *)I2C_BASE4; break; #if (I2C_BUS_MAX > 4) case 4: - i2c_base = (struct i2c *)I2C_BASE5; + return (struct i2c *)I2C_BASE5; break; #endif #endif #endif + default: + printf("wrong hwadapnr: %d\n", adap->hwadapnr); + break; } + return NULL; +} - current_bus = bus; +#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1) +#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED +#endif +#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1) +#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE +#endif - if (!bus_initialized[current_bus]) - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, NULL, + CONFIG_SYS_OMAP24_I2C_SPEED, + CONFIG_SYS_OMAP24_I2C_SLAVE, + 0) +U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, NULL, + CONFIG_SYS_OMAP24_I2C_SPEED1, + CONFIG_SYS_OMAP24_I2C_SLAVE1, + 1) +#if (I2C_BUS_MAX > 2) +#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2) +#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED +#endif +#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2) +#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE +#endif - return 0; -} +U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, NULL, + CONFIG_SYS_OMAP24_I2C_SPEED2, + CONFIG_SYS_OMAP24_I2C_SLAVE2, + 2) +#if (I2C_BUS_MAX > 3) +#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3) +#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED +#endif +#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3) +#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE +#endif -int i2c_get_bus_num(void) -{ - return (int) current_bus; -} +U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, NULL, + CONFIG_SYS_OMAP24_I2C_SPEED3, + CONFIG_SYS_OMAP24_I2C_SLAVE3, + 3) +#if (I2C_BUS_MAX > 4) +#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4) +#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED +#endif +#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4) +#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE +#endif + +U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, NULL, + CONFIG_SYS_OMAP24_I2C_SPEED4, + CONFIG_SYS_OMAP24_I2C_SLAVE4, + 4) +#endif +#endif +#endif diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index c2ba7e3..f35ed6f 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -183,7 +183,6 @@ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ #define CONFIG_BAUDRATE 115200 -/* I2C Configuration */ #define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 1fd2508..73207f9 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -142,10 +142,10 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 6500878..fa44597 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -136,10 +136,10 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index bc5b66c..c301697 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -140,10 +140,10 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_I2C_MULTI_BUS diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index c1e996e..9759106 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -90,10 +90,10 @@ #define CONFIG_DOS_PARTITION 1 /* I2C */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* TWL4030 */ #define CONFIG_TWL4030_POWER 1 diff --git a/include/configs/dig297.h b/include/configs/dig297.h index 08d49fb..2a5574e 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -123,10 +123,10 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index e92bb68..41bf758 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -124,10 +124,10 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 5e27ab2..f197490 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -137,10 +137,10 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* RTC */ #define CONFIG_RTC_DS1337 diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 64db0eb..c307686 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -157,10 +157,10 @@ #undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ #define CONFIG_OMAP3_SPI -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 9fcd50b..3b9225d 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -161,11 +161,10 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX #define CONFIG_VIDEO_OMAP3 /* DSS Support */ /* diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index edf6543..bc7d24e 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -88,11 +88,10 @@ /* * I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_OMAP34XX_I2C - -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * PISMO support diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 42cea01..8e177c0 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -118,12 +118,10 @@ /* * I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_OMAP34XX_I2C - -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 73d5d30..328d8c4 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -128,11 +128,10 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_FPGA -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 -#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 88380a4..8344028 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -98,11 +98,10 @@ #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_DRIVER_OMAP34XX_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index ee448bb..7cfed8e 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -111,10 +111,10 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index fc219fa..42384e6 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -114,10 +114,10 @@ /* * I2C for power management setup */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* OMITTED: single 1 Gbit MT29F1G NAND flash */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index a4a739e..86f8daf 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -118,10 +118,10 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index cb8c7ec..f749740 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -138,10 +138,10 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index e9f2383..97d5a6b 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -73,11 +73,10 @@ #define CONFIG_ARCH_CPU_INIT /* I2C */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 -#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* TWL6030 */ #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 2fff0be..1f04acc 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -173,11 +173,10 @@ /* I2C Configuration */ #define CONFIG_I2C #define CONFIG_CMD_I2C -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_DRIVER_OMAP24XX_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP24XX #define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 5426ee8..03c143d 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -133,11 +133,10 @@ /* I2C Configuration */ #define CONFIG_I2C #define CONFIG_CMD_I2C -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_DRIVER_OMAP24XX_I2C - +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED OMAP_I2C_STANDARD +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP24XX /* Defines for SPL */ #define CONFIG_SPL diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 60dd8ff..9e5fe90 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -117,14 +117,13 @@ #undef CONFIG_CMD_IMLS #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 400000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_DRIVER_OMAP34XX_I2C - /* * Board NAND Info. @@ -370,7 +369,7 @@ struct tam3517_module_info { #define TAM3517_READ_EEPROM(info, ret) \ do { \ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \ + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ (void *)info, sizeof(*info))) \ ret = 1; \ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index e89e874..72a4ec5 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -60,12 +60,11 @@ /* I2C IP block */ #define CONFIG_I2C -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_DRIVER_OMAP24XX_I2C #define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP24XX /* MMC/SD IP block */ #define CONFIG_MMC diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index b102739..da3288a 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -80,10 +80,10 @@ #define CONFIG_DOS_PARTITION /* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* TWL4030 */ #define CONFIG_TWL4030_POWER -- 1.8.3.1

4 8

[U-Boot] [PATCH 22/34] nand: Add zynq nand controller driver support
by Jagannadha Sutradharudu Teki 13 Nov '13

13 Nov '13

Added support for Zynq Nand controller driver. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- arch/arm/include/asm/arch-zynq/hardware.h | 2 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/zynq_nand.c | 1200 +++++++++++++++++++++++++++++ 3 files changed, 1203 insertions(+) create mode 100644 drivers/mtd/nand/zynq_nand.c diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 05870ae..f2c76a6 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -20,6 +20,8 @@ #define ZYNQ_SPI_BASEADDR0 0xE0006000 #define ZYNQ_SPI_BASEADDR1 0xE0007000 #define ZYNQ_QSPI_BASEADDR 0xE000D000 +#define ZYNQ_SMC_BASEADDR 0xE000E000 +#define ZYNQ_NAND_BASEADDR 0xE1000000 #define ZYNQ_DDRC_BASEADDR 0xF8006000 /* Reflect slcr offsets */ diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index eb1eafa..fcd6160 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -60,6 +60,7 @@ obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o obj-$(CONFIG_NAND_PLAT) += nand_plat.o obj-$(CONFIG_NAND_DOCG4) += docg4.o +obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o else # minimal SPL drivers diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c new file mode 100644 index 0000000..3e168fc --- /dev/null +++ b/drivers/mtd/nand/zynq_nand.c @@ -0,0 +1,1200 @@ +/* + * (C) Copyright 2013 Xilinx, Inc. + * + * Xilinx Zynq NAND Flash Controller Driver + * This driver is based on plat_nand.c and mxc_nand.c drivers + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <nand.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/nand_ecc.h> +#include <asm/arch/hardware.h> + +/* The NAND flash driver defines */ +#define ZYNQ_NAND_CMD_PHASE 1 /* End command valid in command phase */ +#define ZYNQ_NAND_DATA_PHASE 2 /* End command valid in data phase */ +#define ZYNQ_NAND_ECC_SIZE 512 /* Size of data for ECC operation */ + +/* Flash memory controller operating parameters */ +#define ZYNQ_NAND_CLR_CONFIG ((0x1 << 1) | /* Disable interrupt */ \ + (0x1 << 4) | /* Clear interrupt */ \ + (0x1 << 6)) /* Disable ECC interrupt */ + +/* Assuming 50MHz clock (20ns cycle time) and 3V operation */ +#define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \ + (0x2 << 17) | /* t_ar from nand_cycles */ \ + (0x1 << 14) | /* t_clr from nand_cycles */ \ + (0x3 << 11) | /* t_wp from nand_cycles */ \ + (0x2 << 8) | /* t_rea from nand_cycles */ \ + (0x5 << 4) | /* t_wc from nand_cycles */ \ + (0x5 << 0)) /* t_rc from nand_cycles */ + +#define ZYNQ_NAND_SET_OPMODE 0x0 + +#define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \ + (0x2 << 21)) /* UpdateRegs operation */ + +#define ZYNQ_NAND_ECC_CONFIG ((0x1 << 2) | /* ECC available on APB */ \ + (0x1 << 4) | /* ECC read at end of page */ \ + (0x0 << 5)) /* No Jumping */ + +#define ZYNQ_NAND_ECC_CMD1 ((0x80) | /* Write command */ \ + (0x00 << 8) | /* Read command */ \ + (0x30 << 16) | /* Read End command */ \ + (0x1 << 24)) /* Read End command calid */ + +#define ZYNQ_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \ + (0x05 << 8) | /* Read col change cmd */ \ + (0xE0 << 16) | /* Read col change end cmd */ \ + (0x1 << 24)) /* Read col change + end cmd valid */ +/* AXI Address definitions */ +#define START_CMD_SHIFT 3 +#define END_CMD_SHIFT 11 +#define END_CMD_VALID_SHIFT 20 +#define ADDR_CYCLES_SHIFT 21 +#define CLEAR_CS_SHIFT 21 +#define ECC_LAST_SHIFT 10 +#define COMMAND_PHASE (0 << 19) +#define DATA_PHASE (1 << 19) + +#define ZYNQ_NAND_ECC_LAST (1 << ECC_LAST_SHIFT) /* Set ECC_Last */ +#define ZYNQ_NAND_CLEAR_CS (1 << CLEAR_CS_SHIFT) /* Clear chip select */ + +/* ECC block registers bit position and bit mask */ +#define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */ +#define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */ + +/* SMC register set */ +struct zynq_nand_smc_regs { + u32 csr; /* 0x00 */ + u32 reserved0[2]; + u32 cfr; /* 0x0C */ + u32 dcr; /* 0x10 */ + u32 scr; /* 0x14 */ + u32 sor; /* 0x18 */ + u32 reserved1[249]; + u32 esr; /* 0x400 */ + u32 emcr; /* 0x404 */ + u32 emcmd1r; /* 0x408 */ + u32 emcmd2r; /* 0x40C */ + u32 reserved2[2]; + u32 eval0r; /* 0x418 */ +}; +#define zynq_nand_smc_base ((struct zynq_nand_smc_regs *)ZYNQ_SMC_BASEADDR) + +/* + * struct zynq_nand_command_format - Defines NAND flash command format + * @start_cmd: First cycle command (Start command) + * @end_cmd: Second cycle command (Last command) + * @addr_cycles: Number of address cycles required to send the address + * @end_cmd_valid: The second cycle command is valid for cmd or data phase + */ +struct zynq_nand_command_format { + int start_cmd; + int end_cmd; + u8 addr_cycles; + u8 end_cmd_valid; +}; + +/* + * struct zynq_nand_info - Defines the NAND flash driver instance + * @parts: Pointer to the mtd_partition structure + * @nand_base: Virtual address of the NAND flash device + * @end_cmd_pending: End command is pending + * @end_cmd: End command + */ +struct zynq_nand_info { +#ifdef CONFIG_MTD_PARTITIONS + struct mtd_partition *parts; +#endif + void __iomem *nand_base; + unsigned long end_cmd_pending; + unsigned long end_cmd; +}; + +#define ONDIE_ECC_FEATURE_ADDR 0x90 + +/* The NAND flash operations command format */ +static const struct zynq_nand_command_format zynq_nand_commands[] = { + {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE}, + {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE}, + {NAND_CMD_READID, NAND_CMD_NONE, 1, NAND_CMD_NONE}, + {NAND_CMD_STATUS, NAND_CMD_NONE, 0, NAND_CMD_NONE}, + {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE}, + {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, NAND_CMD_NONE}, + {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE}, + {NAND_CMD_RESET, NAND_CMD_NONE, 0, NAND_CMD_NONE}, + {NAND_CMD_PARAM, NAND_CMD_NONE, 1, NAND_CMD_NONE}, + {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, NAND_CMD_NONE}, + {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, NAND_CMD_NONE}, + {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0}, + /* Add all the flash commands supported by the flash device and Linux + * The cache program command is not supported by driver because driver + * cant differentiate between page program and cached page program from + * start command, these commands can be differentiated through end + * command, which doesn't fit in to the driver design. The cache program + * command is not supported by NAND subsystem also, look at 1612 line + * number (in nand_write_page function) of nand_base.c file. + * {NAND_CMD_SEQIN, NAND_CMD_CACHEDPROG, 5, ZYNQ_NAND_YES} + */ +}; + +/* Define default oob placement schemes for large and small page devices */ +static struct nand_ecclayout nand_oob_16 = { + .eccbytes = 3, + .eccpos = {13, 14, 15}, + .oobfree = { + { .offset = 0, .length = 12 } + } +}; + +static struct nand_ecclayout nand_oob_64 = { + .eccbytes = 12, + .eccpos = { + 52, 53, 54, 55, 56, 57, + 58, 59, 60, 61, 62, 63}, + .oobfree = { + { .offset = 2, .length = 50 } + } +}; + +static struct nand_ecclayout ondie_nand_oob_64 = { + .eccbytes = 32, + + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 24, 25, 26, 27, 28, 29, 30, 31, + 40, 41, 42, 43, 44, 45, 46, 47, + 56, 57, 58, 59, 60, 61, 62, 63 + }, + + .oobfree = { + { .offset = 4, .length = 4 }, + { .offset = 20, .length = 4 }, + { .offset = 36, .length = 4 }, + { .offset = 52, .length = 4 } + } +}; + +/* Generic flash bbt decriptors */ +static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; +static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 4, + .len = 4, + .veroffs = 20, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 4, + .len = 4, + .veroffs = 20, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +/* + * zynq_nand_waitfor_ecc_completion - Wait for ECC completion + * + * returns: status for command completion, -1 for Timeout + */ +static int zynq_nand_waitfor_ecc_completion(void) +{ + unsigned long timeout; + u32 status; + + /* Wait max 10ms */ + timeout = 10; + status = readl(&zynq_nand_smc_base->esr); + while (status & ZYNQ_NAND_ECC_BUSY) { + status = readl(&zynq_nand_smc_base->esr); + if (timeout == 0) + return -1; + timeout--; + udelay(1); + } + + return status; +} + +/* + * zynq_nand_init_nand_flash - Initialize NAND controller + * @option: Device property flags + * + * This function initializes the NAND flash interface on the NAND controller. + * + * returns: 0 on success or error value on failure + */ +static int zynq_nand_init_nand_flash(int option) +{ + u32 status; + + /* disable interrupts */ + writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr); + /* Initialize the NAND interface by setting cycles and operation mode */ + writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr); + if (option & NAND_BUSWIDTH_16) + writel((ZYNQ_NAND_SET_OPMODE | 0x1), &zynq_nand_smc_base->sor); + else + writel(ZYNQ_NAND_SET_OPMODE, &zynq_nand_smc_base->sor); + + writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr); + + /* Wait till the ECC operation is complete */ + status = zynq_nand_waitfor_ecc_completion(); + if (status < 0) { + printf("%s: Timeout\n", __func__); + return status; + } + + /* Set the command1 and command2 register */ + writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r); + writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r); + + return 0; +} + +/* + * zynq_nand_calculate_hwecc - Calculate Hardware ECC + * @mtd: Pointer to the mtd_info structure + * @data: Pointer to the page data + * @ecc_code: Pointer to the ECC buffer where ECC data needs to be stored + * + * This function retrieves the Hardware ECC data from the controller and returns + * ECC data back to the MTD subsystem. + * + * returns: 0 on success or error value on failure + */ +static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data, + u8 *ecc_code) +{ + u32 ecc_value = 0; + u8 ecc_reg, ecc_byte; + u32 ecc_status; + + /* Wait till the ECC operation is complete */ + ecc_status = zynq_nand_waitfor_ecc_completion(); + if (ecc_status < 0) { + printf("%s: Timeout\n", __func__); + return ecc_status; + } + + for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) { + /* Read ECC value for each block */ + ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg); + ecc_status = (ecc_value >> 24) & 0xFF; + /* ECC value valid */ + if (ecc_status & 0x40) { + for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) { + /* Copy ECC bytes to MTD buffer */ + *ecc_code = ecc_value & 0xFF; + ecc_value = ecc_value >> 8; + ecc_code++; + } + } else { + debug("%s: ecc status failed\n", __func__); + } + } + return 0; +} + +/* + * onehot - onehot function + * @value: value to check for onehot + * + * This function checks whether a value is onehot or not. + * onehot is if and only if onebit is set. + * + */ +static int onehot(unsigned short value) +{ + return ((value & (value-1)) == 0); +} + +/* + * zynq_nand_correct_data - ECC correction function + * @mtd: Pointer to the mtd_info structure + * @buf: Pointer to the page data + * @read_ecc: Pointer to the ECC value read from spare data area + * @calc_ecc: Pointer to the calculated ECC value + * + * This function corrects the ECC single bit errors & detects 2-bit errors. + * + * returns: 0 if no ECC errors found + * 1 if single bit error found and corrected. + * -1 if multiple ECC errors found. + */ +static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf, + unsigned char *read_ecc, unsigned char *calc_ecc) +{ + unsigned char bit_addr; + unsigned int byte_addr; + unsigned short ecc_odd, ecc_even; + unsigned short read_ecc_lower, read_ecc_upper; + unsigned short calc_ecc_lower, calc_ecc_upper; + + read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff; + read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff; + + calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff; + calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff; + + ecc_odd = read_ecc_lower ^ calc_ecc_lower; + ecc_even = read_ecc_upper ^ calc_ecc_upper; + + if ((ecc_odd == 0) && (ecc_even == 0)) + return 0; /* no error */ + else if (ecc_odd == (~ecc_even & 0xfff)) { + /* bits [11:3] of error code is byte offset */ + byte_addr = (ecc_odd >> 3) & 0x1ff; + /* bits [2:0] of error code is bit offset */ + bit_addr = ecc_odd & 0x7; + /* Toggling error bit */ + buf[byte_addr] ^= (1 << bit_addr); + return 1; + } else if (onehot(ecc_odd | ecc_even) == 1) { + return 1; /* one error in parity */ + } else { + return -1; /* Uncorrectable error */ + } +} + +/* + * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @page: page number to read + * @sndcmd: flag whether to issue read command or not + */ +static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + unsigned long data_width = 4; + unsigned long data_phase_addr = 0; + u8 *p; + + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); + + p = chip->oob_poi; + chip->read_buf(mtd, p, (mtd->oobsize - data_width)); + p += (mtd->oobsize - data_width); + + data_phase_addr = (unsigned long)chip->IO_ADDR_R; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + chip->read_buf(mtd, p, data_width); + + return 0; +} + +/* + * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @page: page number to write + */ +static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + int status = 0; + const u8 *buf = chip->oob_poi; + unsigned long data_width = 4; + unsigned long data_phase_addr = 0; + + chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); + + chip->write_buf(mtd, buf, (mtd->oobsize - data_width)); + buf += (mtd->oobsize - data_width); + + data_phase_addr = (unsigned long)chip->IO_ADDR_W; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + data_phase_addr |= (1 << END_CMD_VALID_SHIFT); + chip->IO_ADDR_W = (void __iomem *)data_phase_addr; + chip->write_buf(mtd, buf, data_width); + + /* Send command to program the OOB data */ + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + status = chip->waitfunc(mtd, chip); + + return status & NAND_STATUS_FAIL ? -EIO : 0; +} + +/* + * zynq_nand_read_page_raw - [Intern] read raw page data without ecc + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @oob_required: must write chip->oob_poi to OOB + * @page: page number to read + */ +static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + u8 *buf, int oob_required, int page) +{ + unsigned long data_width = 4; + unsigned long data_phase_addr = 0; + u8 *p; + + chip->read_buf(mtd, buf, mtd->writesize); + + p = chip->oob_poi; + chip->read_buf(mtd, p, (mtd->oobsize - data_width)); + p += (mtd->oobsize - data_width); + + data_phase_addr = (unsigned long)chip->IO_ADDR_R; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + + chip->read_buf(mtd, p, data_width); + return 0; +} + +static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd, + struct nand_chip *chip, u8 *buf, int oob_required, int page) +{ + chip->read_buf(mtd, buf, mtd->writesize); + return 0; +} + +static int zynq_nand_read_subpage_raw(struct mtd_info *mtd, + struct nand_chip *chip, u32 data_offs, + u32 readlen, u8 *buf) +{ + if (data_offs != 0) { + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1); + buf += data_offs; + } + + chip->read_buf(mtd, buf, readlen); + return 0; +} + +/* + * zynq_nand_write_page_raw - [Intern] raw page write function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: data buffer + * @oob_required: must write chip->oob_poi to OOB + */ +static int zynq_nand_write_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, const u8 *buf, int oob_required) +{ + unsigned long data_width = 4; + unsigned long data_phase_addr = 0; + u8 *p; + + chip->write_buf(mtd, buf, mtd->writesize); + + p = chip->oob_poi; + chip->write_buf(mtd, p, (mtd->oobsize - data_width)); + p += (mtd->oobsize - data_width); + + data_phase_addr = (unsigned long)chip->IO_ADDR_W; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + data_phase_addr |= (1 << END_CMD_VALID_SHIFT); + chip->IO_ADDR_W = (void __iomem *)data_phase_addr; + + chip->write_buf(mtd, p, data_width); + + return 0; +} + +/* + * nand_write_page_hwecc - Hardware ECC based page write function + * @mtd: Pointer to the mtd info structure + * @chip: Pointer to the NAND chip info structure + * @buf: Pointer to the data buffer + * @oob_required: must write chip->oob_poi to OOB + * + * This functions writes data and hardware generated ECC values in to the page. + */ +static int zynq_nand_write_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, const u8 *buf, int oob_required) +{ + int i, eccsize = chip->ecc.size; + int eccsteps = chip->ecc.steps; + u8 *ecc_calc = chip->buffers->ecccalc; + const u8 *p = buf; + u32 *eccpos = chip->ecc.layout->eccpos; + unsigned long data_phase_addr = 0; + unsigned long data_width = 4; + u8 *oob_ptr; + + for (; (eccsteps - 1); eccsteps--) { + chip->write_buf(mtd, p, eccsize); + p += eccsize; + } + chip->write_buf(mtd, p, (eccsize - data_width)); + p += (eccsize - data_width); + + /* Set ECC Last bit to 1 */ + data_phase_addr = (unsigned long) chip->IO_ADDR_W; + data_phase_addr |= ZYNQ_NAND_ECC_LAST; + chip->IO_ADDR_W = (void __iomem *)data_phase_addr; + chip->write_buf(mtd, p, data_width); + + /* Wait for ECC to be calculated and read the error values */ + p = buf; + chip->ecc.calculate(mtd, p, &ecc_calc[0]); + + for (i = 0; i < chip->ecc.total; i++) + chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]); + + /* Clear ECC last bit */ + data_phase_addr = (unsigned long)chip->IO_ADDR_W; + data_phase_addr &= ~ZYNQ_NAND_ECC_LAST; + chip->IO_ADDR_W = (void __iomem *)data_phase_addr; + + /* Write the spare area with ECC bytes */ + oob_ptr = chip->oob_poi; + chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width)); + + data_phase_addr = (unsigned long)chip->IO_ADDR_W; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + data_phase_addr |= (1 << END_CMD_VALID_SHIFT); + chip->IO_ADDR_W = (void __iomem *)data_phase_addr; + oob_ptr += (mtd->oobsize - data_width); + chip->write_buf(mtd, oob_ptr, data_width); + + return 0; +} + +/* + * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page + * write function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: data buffer + * @oob_required: must write chip->oob_poi to OOB + */ +static int zynq_nand_write_page_swecc(struct mtd_info *mtd, + struct nand_chip *chip, const u8 *buf, int oob_required) +{ + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + u8 *ecc_calc = chip->buffers->ecccalc; + const u8 *p = buf; + u32 *eccpos = chip->ecc.layout->eccpos; + + /* Software ecc calculation */ + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) + chip->ecc.calculate(mtd, p, &ecc_calc[i]); + + for (i = 0; i < chip->ecc.total; i++) + chip->oob_poi[eccpos[i]] = ecc_calc[i]; + + return chip->ecc.write_page_raw(mtd, chip, buf, 1); +} + +/* + * nand_read_page_hwecc - Hardware ECC based page read function + * @mtd: Pointer to the mtd info structure + * @chip: Pointer to the NAND chip info structure + * @buf: Pointer to the buffer to store read data + * @oob_required: must write chip->oob_poi to OOB + * @page: page number to read + * + * This functions reads data and checks the data integrity by comparing hardware + * generated ECC values and read ECC values from spare area. + * + * returns: 0 always and updates ECC operation status in to MTD structure + */ +static int zynq_nand_read_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, u8 *buf, int oob_required, int page) +{ + int i, stat, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + u8 *p = buf; + u8 *ecc_calc = chip->buffers->ecccalc; + u8 *ecc_code = chip->buffers->ecccode; + u32 *eccpos = chip->ecc.layout->eccpos; + unsigned long data_phase_addr = 0; + unsigned long data_width = 4; + u8 *oob_ptr; + + for (; (eccsteps - 1); eccsteps--) { + chip->read_buf(mtd, p, eccsize); + p += eccsize; + } + chip->read_buf(mtd, p, (eccsize - data_width)); + p += (eccsize - data_width); + + /* Set ECC Last bit to 1 */ + data_phase_addr = (unsigned long)chip->IO_ADDR_R; + data_phase_addr |= ZYNQ_NAND_ECC_LAST; + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + chip->read_buf(mtd, p, data_width); + + /* Read the calculated ECC value */ + p = buf; + chip->ecc.calculate(mtd, p, &ecc_calc[0]); + + /* Clear ECC last bit */ + data_phase_addr = (unsigned long)chip->IO_ADDR_R; + data_phase_addr &= ~ZYNQ_NAND_ECC_LAST; + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + + /* Read the stored ECC value */ + oob_ptr = chip->oob_poi; + chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width)); + + /* de-assert chip select */ + data_phase_addr = (unsigned long)chip->IO_ADDR_R; + data_phase_addr |= ZYNQ_NAND_CLEAR_CS; + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + + oob_ptr += (mtd->oobsize - data_width); + chip->read_buf(mtd, oob_ptr, data_width); + + for (i = 0; i < chip->ecc.total; i++) + ecc_code[i] = ~(chip->oob_poi[eccpos[i]]); + + eccsteps = chip->ecc.steps; + p = buf; + + /* Check ECC error for all blocks and correct if it is correctable */ + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + } + return 0; +} + +/* + * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page + * read function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @page: page number to read + */ +static int zynq_nand_read_page_swecc(struct mtd_info *mtd, + struct nand_chip *chip, u8 *buf, int oob_required, int page) +{ + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + u8 *p = buf; + u8 *ecc_calc = chip->buffers->ecccalc; + u8 *ecc_code = chip->buffers->ecccode; + u32 *eccpos = chip->ecc.layout->eccpos; + + chip->ecc.read_page_raw(mtd, chip, buf, 1, page); + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) + chip->ecc.calculate(mtd, p, &ecc_calc[i]); + + for (i = 0; i < chip->ecc.total; i++) + ecc_code[i] = chip->oob_poi[eccpos[i]]; + + eccsteps = chip->ecc.steps; + p = buf; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + int stat; + + stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + } + return 0; +} + +/* + * zynq_nand_select_chip - Select the flash device + * @mtd: Pointer to the mtd_info structure + * @chip: Chip number to be selected + * + * This function is empty as the NAND controller handles chip select line + * internally based on the chip address passed in command and data phase. + */ +static void zynq_nand_select_chip(struct mtd_info *mtd, int chip) +{ + return; +} + +/* + * zynq_nand_cmd_function - Send command to NAND device + * @mtd: Pointer to the mtd_info structure + * @command: The command to be sent to the flash device + * @column: The column address for this command, -1 if none + * @page_addr: The page address for this command, -1 if none + */ +static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + struct nand_chip *chip = mtd->priv; + const struct zynq_nand_command_format *curr_cmd = NULL; + struct zynq_nand_info *xnand; + void *cmd_addr; + unsigned long cmd_data = 0; + unsigned long cmd_phase_addr = 0; + unsigned long data_phase_addr = 0; + unsigned long end_cmd = 0; + unsigned long end_cmd_valid = 0; + unsigned long i; + + xnand = (struct zynq_nand_info *)chip->priv; + if (xnand->end_cmd_pending) { + /* Check for end command if this command request is same as the + * pending command then return + */ + if (xnand->end_cmd == command) { + xnand->end_cmd = 0; + xnand->end_cmd_pending = 0; + return; + } + } + + /* Emulate NAND_CMD_READOOB for large page device */ + if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) && + (command == NAND_CMD_READOOB)) { + column += mtd->writesize; + command = NAND_CMD_READ0; + } + + /* Get the command format */ + for (i = 0; (zynq_nand_commands[i].start_cmd != NAND_CMD_NONE || + zynq_nand_commands[i].end_cmd != NAND_CMD_NONE); i++) { + if (command == zynq_nand_commands[i].start_cmd) + curr_cmd = &zynq_nand_commands[i]; + } + if (curr_cmd == NULL) + return; + + /* Clear interrupt */ + writel((1 << 4), &zynq_nand_smc_base->cfr); + + /* Get the command phase address */ + if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE) + end_cmd_valid = 1; + + if (curr_cmd->end_cmd == NAND_CMD_NONE) + end_cmd = 0x0; + else + end_cmd = curr_cmd->end_cmd; + + cmd_phase_addr = (unsigned long)xnand->nand_base | + (curr_cmd->addr_cycles << ADDR_CYCLES_SHIFT) | + (end_cmd_valid << END_CMD_VALID_SHIFT) | + (COMMAND_PHASE) | + (end_cmd << END_CMD_SHIFT) | + (curr_cmd->start_cmd << START_CMD_SHIFT); + + cmd_addr = (void __iomem *)cmd_phase_addr; + + /* Get the data phase address */ + end_cmd_valid = 0; + + data_phase_addr = (unsigned long)xnand->nand_base | + (0x0 << CLEAR_CS_SHIFT) | + (end_cmd_valid << END_CMD_VALID_SHIFT) | + (DATA_PHASE) | + (end_cmd << END_CMD_SHIFT) | + (0x0 << ECC_LAST_SHIFT); + + chip->IO_ADDR_R = (void __iomem *)data_phase_addr; + chip->IO_ADDR_W = chip->IO_ADDR_R; + + /* Command phase AXI Read & Write */ + if (column != -1 && page_addr != -1) { + /* Adjust columns for 16 bit bus width */ + if (chip->options & NAND_BUSWIDTH_16) + column >>= 1; + cmd_data = column; + if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) { + cmd_data |= page_addr << 16; + /* Another address cycle for devices > 128MiB */ + if (chip->chipsize > (128 << 20)) { + writel(cmd_data, cmd_addr); + cmd_data = (page_addr >> 16); + } + } else { + cmd_data |= page_addr << 8; + } + } + /* Erase */ + else if (page_addr != -1) + cmd_data = page_addr; + /* Change read/write column, read id etc */ + else if (column != -1) { + /* Adjust columns for 16 bit bus width */ + if ((chip->options & NAND_BUSWIDTH_16) && + ((command == NAND_CMD_READ0) || + (command == NAND_CMD_SEQIN) || + (command == NAND_CMD_RNDOUT) || + (command == NAND_CMD_RNDIN))) + column >>= 1; + cmd_data = column; + } else + ; + + writel(cmd_data, cmd_addr); + + if (curr_cmd->end_cmd_valid) { + xnand->end_cmd = curr_cmd->end_cmd; + xnand->end_cmd_pending = 1; + } + + ndelay(100); + + if ((command == NAND_CMD_READ0) || + (command == NAND_CMD_RESET) || + (command == NAND_CMD_PARAM) || + (command == NAND_CMD_GET_FEATURES)) { + while (!chip->dev_ready(mtd)) + ; + return; + } +} + +/* + * zynq_nand_read_buf - read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + */ +static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + const u32 *nand = chip->IO_ADDR_R; + + /* Make sure that buf is 32 bit aligned */ + if (((int)buf & 0x3) != 0) { + if (((int)buf & 0x1) != 0) { + if (len) { + *buf = readb(nand); + buf += 1; + len--; + } + } + + if (((int)buf & 0x3) != 0) { + if (len >= 2) { + *(u16 *)buf = readw(nand); + buf += 2; + len -= 2; + } + } + } + + /* copy aligned data */ + while (len >= 4) { + *(u32 *)buf = readl(nand); + buf += 4; + len -= 4; + } + + /* mop up any remaining bytes */ + if (len) { + if (len >= 2) { + *(u16 *)buf = readw(nand); + buf += 2; + len -= 2; + } + + if (len) + *buf = readb(nand); + } +} + +/* + * zynq_nand_write_buf - write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + const u32 *nand = chip->IO_ADDR_W; + + /* Make sure that buf is 32 bit aligned */ + if (((int)buf & 0x3) != 0) { + if (((int)buf & 0x1) != 0) { + if (len) { + writeb(*buf, nand); + buf += 1; + len--; + } + } + + if (((int)buf & 0x3) != 0) { + if (len >= 2) { + writew(*(u16 *)buf, nand); + buf += 2; + len -= 2; + } + } + } + + /* copy aligned data */ + while (len >= 4) { + writel(*(u32 *)buf, nand); + buf += 4; + len -= 4; + } + + /* mop up any remaining bytes */ + if (len) { + if (len >= 2) { + writew(*(u16 *)buf, nand); + buf += 2; + len -= 2; + } + + if (len) + writeb(*buf, nand); + } +} + +/* + * zynq_nand_device_ready - Check device ready/busy line + * @mtd: Pointer to the mtd_info structure + * + * returns: 0 on busy or 1 on ready state + */ +static int zynq_nand_device_ready(struct mtd_info *mtd) +{ + /* Check the raw_int_status1 bit */ + if ((readl(&zynq_nand_smc_base->csr)) & 0x40) { + /* Clear the interrupt condition */ + writel((1 << 4), &zynq_nand_smc_base->cfr); + return 1; + } + return 0; +} + +static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) +{ + struct zynq_nand_info *xnand; + struct mtd_info *mtd; + unsigned long ecc_page_size; + int err = -1; + u8 maf_id, dev_id, i; + u8 get_feature[4]; + u8 set_feature[4] = {0x08, 0x00, 0x00, 0x00}; + unsigned long ecc_cfg; + int ondie_ecc_enabled = 0; + + xnand = calloc(1, sizeof(struct zynq_nand_info)); + if (!xnand) { + printf("%s: failed to allocate\n", __func__); + goto free; + } + + xnand->nand_base = (void *)ZYNQ_NAND_BASEADDR; + mtd = &nand_info[0]; + + nand_chip->priv = xnand; + mtd->priv = nand_chip; + + /* Set address of NAND IO lines */ + nand_chip->IO_ADDR_R = xnand->nand_base; + nand_chip->IO_ADDR_W = xnand->nand_base; + + /* Set the driver entry points for MTD */ + nand_chip->cmdfunc = zynq_nand_cmd_function; + nand_chip->dev_ready = zynq_nand_device_ready; + nand_chip->select_chip = zynq_nand_select_chip; + + /* If we don't set this delay driver sets 20us by default */ + nand_chip->chip_delay = 30; + + /* Buffer read/write routines */ + nand_chip->read_buf = zynq_nand_read_buf; + nand_chip->write_buf = zynq_nand_write_buf; + + nand_chip->bbt_options = NAND_BBT_USE_FLASH; + + /* Initialize the NAND flash interface on NAND controller */ + if (zynq_nand_init_nand_flash(nand_chip->options) < 0) { + printf("%s: nand flash init failed\n", __func__); + goto free; + } + + /* first scan to find the device and get the page size */ + if (nand_scan_ident(mtd, 1, NULL)) { + printf("%s: nand_scan_ident failed\n", __func__); + goto fail; + } + + /* Send the command for reading device ID */ + nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + + /* Read manufacturer and device IDs */ + maf_id = nand_chip->read_byte(mtd); + dev_id = nand_chip->read_byte(mtd); + + if ((maf_id == 0x2c) && ((dev_id == 0xf1) || + (dev_id == 0xa1) || (dev_id == 0xb1) || + (dev_id == 0xaa) || (dev_id == 0xba) || + (dev_id == 0xda) || (dev_id == 0xca) || + (dev_id == 0xac) || (dev_id == 0xbc) || + (dev_id == 0xdc) || (dev_id == 0xcc) || + (dev_id == 0xa3) || (dev_id == 0xb3) || + (dev_id == 0xd3) || (dev_id == 0xc3))) { + nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, + ONDIE_ECC_FEATURE_ADDR, -1); + + for (i = 0; i < 4; i++) + writeb(set_feature[i], nand_chip->IO_ADDR_W); + + /* wait for 1us after writing data with SET_FEATURES command */ + ndelay(1000); + + nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, + ONDIE_ECC_FEATURE_ADDR, -1); + nand_chip->read_buf(mtd, get_feature, 4); + + if (get_feature[0] & 0x08) { + debug("%s: OnDie ECC flash\n", __func__); + ondie_ecc_enabled = 1; + } else { + printf("%s: Unable to detect OnDie ECC\n", __func__); + } + } + + if (ondie_ecc_enabled) { + /* bypass the controller ECC block */ + ecc_cfg = readl(&zynq_nand_smc_base->emcr); + ecc_cfg &= ~0xc; + writel(ecc_cfg, &zynq_nand_smc_base->emcr); + + /* The software ECC routines won't work + * with the SMC controller + */ + nand_chip->ecc.mode = NAND_ECC_HW; + nand_chip->ecc.strength = 1; + nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob; + nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw; + nand_chip->ecc.write_page = zynq_nand_write_page_raw; + nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw; + nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw; + nand_chip->ecc.read_oob = zynq_nand_read_oob; + nand_chip->ecc.write_oob = zynq_nand_write_oob; + nand_chip->ecc.size = mtd->writesize; + nand_chip->ecc.bytes = 0; + + /* NAND with on-die ECC supports subpage reads */ + nand_chip->options |= NAND_SUBPAGE_READ; + + /* On-Die ECC spare bytes offset 8 is used for ECC codes */ + if (ondie_ecc_enabled) { + nand_chip->ecc.layout = &ondie_nand_oob_64; + /* Use the BBT pattern descriptors */ + nand_chip->bbt_td = &bbt_main_descr; + nand_chip->bbt_md = &bbt_mirror_descr; + } + } else { + /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */ + nand_chip->ecc.mode = NAND_ECC_HW; + nand_chip->ecc.strength = 1; + nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE; + nand_chip->ecc.bytes = 3; + nand_chip->ecc.calculate = zynq_nand_calculate_hwecc; + nand_chip->ecc.correct = zynq_nand_correct_data; + nand_chip->ecc.hwctl = NULL; + nand_chip->ecc.read_page = zynq_nand_read_page_hwecc; + nand_chip->ecc.write_page = zynq_nand_write_page_hwecc; + nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw; + nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw; + nand_chip->ecc.read_oob = zynq_nand_read_oob; + nand_chip->ecc.write_oob = zynq_nand_write_oob; + + switch (mtd->writesize) { + case 512: + ecc_page_size = 0x1; + /* Set the ECC memory config register */ + writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), + &zynq_nand_smc_base->emcr); + break; + case 1024: + ecc_page_size = 0x2; + /* Set the ECC memory config register */ + writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), + &zynq_nand_smc_base->emcr); + break; + case 2048: + ecc_page_size = 0x3; + /* Set the ECC memory config register */ + writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), + &zynq_nand_smc_base->emcr); + break; + default: + /* The software ECC routines won't work with + * the SMC controller + */ + nand_chip->ecc.mode = NAND_ECC_HW; + nand_chip->ecc.calculate = nand_calculate_ecc; + nand_chip->ecc.correct = nand_correct_data; + nand_chip->ecc.read_page = zynq_nand_read_page_swecc; + /* nand_chip->ecc.read_subpage = nand_read_subpage; */ + nand_chip->ecc.write_page = zynq_nand_write_page_swecc; + nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw; + nand_chip->ecc.write_page_raw = + zynq_nand_write_page_raw; + nand_chip->ecc.read_oob = zynq_nand_read_oob; + nand_chip->ecc.write_oob = zynq_nand_write_oob; + nand_chip->ecc.size = 256; + nand_chip->ecc.bytes = 3; + break; + } + + if (mtd->oobsize == 16) + nand_chip->ecc.layout = &nand_oob_16; + else if (mtd->oobsize == 64) + nand_chip->ecc.layout = &nand_oob_64; + else + ; + } + + /* second phase scan */ + if (nand_scan_tail(mtd)) { + printf("%s: nand_scan_tailfailed\n", __func__); + goto fail; + } + + if (nand_register(devnum)) + goto fail; + + return 0; +fail: + nand_release(mtd); +free: + kfree(xnand); + return err; +} + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; + +void board_nand_init(void) +{ + struct nand_chip *nand = &nand_chip[0]; + + if (zynq_nand_init(nand, 0)) + puts("ZYNQ NAND init failed\n"); +} -- 1.8.3

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[U-Boot] [PATCH 23/34] zynq-common: Define CONFIG_NAND_ZYNQ
by Jagannadha Sutradharudu Teki 13 Nov '13

13 Nov '13

Defined CONFIG_NAND_ZYNQ for enabling zynq nand controller with onfi detection support. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- include/configs/zynq-common.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index ffe1b93..97b49d4 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -102,6 +102,16 @@ # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #endif +/* NAND */ +#ifdef CONFIG_NAND_ZYNQ +# define CONFIG_CMD_NAND +# define CONFIG_CMD_NAND_LOCK_UNLOCK +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_SELF_INIT +# define CONFIG_SYS_NAND_ONFI_DETECTION +# define CONFIG_MTD_DEVICE +#endif + /* MMC */ #if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) # define CONFIG_MMC -- 1.8.3

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