November 2013 - U-Boot

[U-Boot] [PATCH v2] mtd: move & update nand_ecclayout structure (plus tricorder change)
by Scott Wood 16 Nov '13

16 Nov '13

From: Prabhakar Kushwaha <prabhakar(a)freescale.com> nand_ecclayout is present in mtd.h at Linux. Move this structure to mtd.h to comply with Linux. Also, increase the ecc placement locations to 640 to suport device having writesize/oobsize of 8KB/640B. This means that the maximum oobsize has gone up to 640 bytes and consequently the maximum ecc placement locations have also gone up to 640. Changes from Prabhabkar's version (squashed into one patch to preserve bisectability): - Added _LARGE to MTD_MAX_*_ENTRIES This makes the names match current Linux source, and resolves a conflict between http://patchwork.ozlabs.org/patch/280488/ and http://patchwork.ozlabs.org/patch/284513/ The former was posted first and is closer to matching Linux, but unlike Linux it does not add _LARGE to the names. The second adds _LARGE to one of the names, and depends on it in a subsequent patch (http://patchwork.ozlabs.org/patch/284512/). - Made max oobfree/eccpos configurable, and used this on tricorder On tricorder SPL, this saves 2576 bytes (and makes the SPL build again) versus the new default of 640 eccpos and 32 oobfree, and saves 336 bytes versus the old default of 128 eccpos and 8 oobfree. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> CC: Vipin Kumar <vipin.kumar(a)st.com> [scottwood(a)freescale.com: changes as described above] Signed-off-by: Scott Wood <scottwood(a)freescale.com> Cc: Thomas Weber <weber(a)corscience.de> Cc: Tom Rini <trini(a)ti.com> --- doc/README.nand | 10 ++++++++++ drivers/mtd/onenand/onenand_base.c | 15 ++++++++++----- include/configs/tricorder.h | 2 ++ include/linux/mtd/mtd.h | 23 +++++++++++++++++++++++ include/mtd/mtd-abi.h | 12 ------------ 5 files changed, 45 insertions(+), 17 deletions(-) diff --git a/doc/README.nand b/doc/README.nand index 913e9b5..3a507b6 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -104,6 +104,16 @@ Configuration Options: CONFIG_SYS_MAX_NAND_DEVICE The maximum number of NAND devices you want to support. + CONFIG_SYS_NAND_MAX_ECCPOS + If specified, overrides the maximum number of ECC bytes + supported. Useful for reducing image size, especially with SPL. + This must be at least 48 if nand_base.c is used. + + CONFIG_SYS_NAND_MAX_OOBFREE + If specified, overrides the maximum number of free OOB regions + supported. Useful for reducing image size, especially with SPL. + This must be at least 2 if nand_base.c is used. + CONFIG_SYS_NAND_MAX_CHIPS The maximum number of NAND chips per device to be supported. diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 067f8ef..979e4af 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -761,7 +761,8 @@ static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, uint8_t *oob_buf = this->oob_buf; free = this->ecclayout->oobfree; - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length; + i++, free++) { if (readcol >= lastgap) readcol += free->offset - lastgap; if (readend >= lastgap) @@ -770,7 +771,8 @@ static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, } this->read_bufferram(mtd, 0, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize); free = this->ecclayout->oobfree; - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length; + i++, free++) { int free_end = free->offset + free->length; if (free->offset < readend && free_end > readcol) { int st = max_t(int,free->offset,readcol); @@ -1356,7 +1358,8 @@ static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf, unsigned int i; free = this->ecclayout->oobfree; - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length; + i++, free++) { if (writecol >= lastgap) writecol += free->offset - lastgap; if (writeend >= lastgap) @@ -1364,7 +1367,8 @@ static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf, lastgap = free->offset + free->length; } free = this->ecclayout->oobfree; - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length; + i++, free++) { int free_end = free->offset + free->length; if (free->offset < writeend && free_end > writecol) { int st = max_t(int,free->offset,writecol); @@ -2750,7 +2754,8 @@ int onenand_scan(struct mtd_info *mtd, int maxchips) * the out of band area */ this->ecclayout->oobavail = 0; - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && + + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && this->ecclayout->oobfree[i].length; i++) this->ecclayout->oobavail += this->ecclayout->oobfree[i].length; diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index d57394e..590eab7 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -140,6 +140,8 @@ /* devices */ #define CONFIG_NAND_OMAP_BCH8 #define CONFIG_BCH +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 /* commands to include */ #include <config_cmd_default.h> diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 6f44abd..a65b681 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -96,6 +96,29 @@ struct mtd_oob_ops { uint8_t *oobbuf; }; +#ifdef CONFIG_SYS_NAND_MAX_OOBFREE +#define MTD_MAX_OOBFREE_ENTRIES_LARGE CONFIG_SYS_NAND_MAX_OOBFREE +#else +#define MTD_MAX_OOBFREE_ENTRIES_LARGE 32 +#endif + +#ifdef CONFIG_SYS_NAND_MAX_ECCPOS +#define MTD_MAX_ECCPOS_ENTRIES_LARGE CONFIG_SYS_NAND_MAX_ECCPOS +#else +#define MTD_MAX_ECCPOS_ENTRIES_LARGE 640 +#endif + +/* + * ECC layout control structure. Exported to userspace for + * diagnosis and to allow creation of raw images + */ +struct nand_ecclayout { + uint32_t eccbytes; + uint32_t eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE]; + uint32_t oobavail; + struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE]; +}; + struct mtd_info { u_char type; u_int32_t flags; diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h index d51c1ab..ac3c298 100644 --- a/include/mtd/mtd-abi.h +++ b/include/mtd/mtd-abi.h @@ -155,18 +155,6 @@ struct nand_oobfree { uint32_t length; }; -#define MTD_MAX_OOBFREE_ENTRIES 8 -/* - * ECC layout control structure. Exported to userspace for - * diagnosis and to allow creation of raw images - */ -struct nand_ecclayout { - uint32_t eccbytes; - uint32_t eccpos[128]; - uint32_t oobavail; - struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES]; -}; - /** * struct mtd_ecc_stats - error correction stats * -- 1.8.1.2

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[U-Boot] [PATCH v2] malta: use unmapped flash base address
by Gabor Juhos 15 Nov '13

15 Nov '13

The physical base address of the NOR flash is 0x1e000000 on the Malta boards. The hardware also maps the first 4MiB of the flash into the 0x1fc00000-0x1fffffff range. Currently, U-Boot uses the mapped address to access the flash, which does not work in recent qemu versions. Since commit a427338b222b43197c2776cbc996936df0302f51 (mips_malta: correct reading MIPS revision at 0x1fc00010) writing to the mapped address space causes a CPU exception. Due to the exception, U-Boot hangs during boot when it tries to detect the CFI flash chip. Use the correct physical address for the MALTA_FLASH_BASE constant to fix the problem. In order to avoid relocation problems, also update the CONFIG_SYS_{TEXT,MONITOR}_BASE constants. The change makes it possible to start U-Boot on a Malta board emulated with Qemu 1.6.1 and 1.7.0-rc0. It also works on older versions (tested with 1.1.1, 1.2.2, 1.4.2, 1.5.3). Signed-off-by: Gabor Juhos <juhosg(a)openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Cc: Paul Burton <paul.burton(a)imgtec.com> --- Changes since v1: - update CONFIG_SYS_{TEXT,MONITOR}_BASE constants - update commit message --- arch/mips/include/asm/malta.h | 2 +- include/configs/malta.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index 9b1100b..bd9043d 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -44,7 +44,7 @@ #define MALTA_RESET_BASE 0x1f000500 #define GORESET 0x42 -#define MALTA_FLASH_BASE 0x1fc00000 +#define MALTA_FLASH_BASE 0x1e000000 #define MALTA_REVISION 0x1fc00010 #define MALTA_REVISION_CORID_SHF 10 diff --git a/include/configs/malta.h b/include/configs/malta.h index 4098e72..458c33a 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -40,8 +40,8 @@ /* * Memory map */ -#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_TEXT_BASE 0xbe000000 /* Rom version */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ #define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024) -- 1.7.10

2 1

[U-Boot] [PATCH v9 0/4] mtd: nand: omap: optimize and clean-up of OMAP NAND driver
by Pekon Gupta 15 Nov '13

15 Nov '13

*changes in v9* (Important) As this patch series was becoming bulky and had many un-related patches, so it has been split into two parts. Part-1: Current patch series focuses on cleaning up GPMC and ELM drivers maintaining existing functionality. And update ecc-scheme selection mechanism across all platforms. Part-2: Next patch series will focus on optimizing data-paths of GPMC and ELM drivers for better performance and scalability. This Part-1 series has following patches, maintaining earlier feedbacks. [PATCH 1/4] [NEW] mtd: nand: omap: make am33xx/elm.c as common driver - move ELM driver source to drivers/mtd/nand/ to reuse driver on all platforms [PATCH 2/4] [SPLIT] mtd: nand: omap: enable BCH ECC scheme using ELM for ... v8 version of this patch is split into follwing part maintaining earlier feedbacks. - [PATCH 2/4] handles ecc-scheme selection clean-up - [PATCH 3/4] add CONFIG_NAND_OMAP_ECCSCHEME [PATCH 3/4] [NEW] mtd: nand: omap: add CONFIG_NAND_OMAP_ECCSCHEME ... - split from previous patch to introduce new CONFIG_xx for having common method of ecc-scheme selection across all platforms. - updated include/configs/ for SoC platforms (like OMAP3) which use omap_gpmc.c [PATCH 4/4] [NEW] am335x: fix GPMC config for NAND and NOR SPL boot - clean separation of NOR Boot and NAND Boot configurations - configuration of GPMC registers moved to arch/am33xx from board/ti/am335x/board.c, so that its re-usable for other boards also. This patch is tested on beagle-bone (white) with NAND cape, using following (a) Patch to add beaglebone pin-mux support http://lists.denx.de/pipermail/u-boot/2013-September/163881.html (b) Hack in board-file to configure GPMC for x16 device -------------- diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c index 56c9e7d..b166a94 100644 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -64,7 +64,7 @@ void gpmc_init(void) u32 base = CONFIG_SYS_FLASH_BASE; #elif defined(CONFIG_NAND) /* configure GPMC for NAND */ - const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, + const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1 | 0x1000, M_NAND_GPMC_CONFIG2, M_NAND_GPMC_CONFIG3, M_NAND_GPMC_CONFIG4, -------------- *changes in v8* [PATCH] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform - incorporated following feedbacks from Scott Wood <scottwood(a)freescale.com> - using symbolic names (enums) as values of CONFIG_NAND_OMAP_ECCSCHEME - updated omap_select_ecc_scheme(): perform ecc-scheme compatibility checks before updating nand_chip.ecc fields. This avoids corrupting of existing ecc-scheme in case of switching failures. - code clean-up (removed fall-back on omap_select_ecc_scheme() failures) *changes in v7* [PATCH] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform - omap_gpmc.c: fix: free bytes in OOB (ecclayout->oobfree[0].length) - omap_gpmc.c: cleanup: redundant code added in previous patch versions - am335x_evm.h: cleanup: redundant code added in previous patch versions - tricorder.h: fix: CONFIG_NAND_OMAP_ECCSCHEME *changes in v6* [PATCH] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform - incorporated feedbacks from Scott Wood <scottwood(a)freescale.com> - renamed CONFIG_SYS_NAND_ECCSCHEME to CONFIG_NAND_OMAP_ECCSCHEME - updated omap_select_ecc_scheme() to handle error conditions without depending on caller. - renamed OMAP_ECC_HAM1_CODE_HW_ROMCODE to OMAP_ECC_HAM1_CODE_HW to keep it naming compatible to linux kernel - updated doc/README.nand and doc/README.omap3 - moved CONFIG_NAND_OMAP_ECCSCHEME description to README.nand *changes in v5* This version of patch is tested on am335x-evm with x8 NAND device, and boots SPL and u-boot from NAND [PATCH] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform - re-added omap_read_page_bch(): needed proper sequence of while reading DATA and ECC from NAND page, so that calc_ecc generated from GPMC is understood by ELM. - added check to see if NAND OOB can accomodate ECC for entire page *changes in v4* [PATCH] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform - removed omap_read_page_bch(): chip->ecc.read_page uses default API nand_read_page_hwecc() in nand_base.c - updated tricorder.h: added new CONFIGS for ECCSCHEME & ONFI_DETECTION - converted printf("ECC-SCHEME") to debug("ECC-SCHEME") *changes in v3* [PATCH] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform (complete re-work) - ecc-scheme is selection is controller by s/w, not CONFIG_NAND_xx - added omap_select_ecc_scheme(), as common function to handle all ecc-scheme related configurations for both board_nand_init() & omap_nand_switch_ecc(). - removed un-used defines from asm/arch-am33xx/omap_gpmc.h - updated doc/REAME.nand - removed un-used defines from asm/omap_gpmc.h *changes in v2* - added documentation for CONFIG_NAND_OMAP_xx in doc/README.nand - added CONFIG_BCH along with CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW to include software library lib/bch.c - fixed board_nand_init() and omap_enable_hwecc() *original v1* This patch series updates BCH8_ECC schemes in mtd/nand/omap_gpmc.c driver - adds scalability for higher ECC schemes in future. - removes CONFIG_AM335x and it makes it generic for all platforms. - optimizes read_data paths Pekon Gupta (4): mtd: nand: omap: make am33xx/elm.c as common driver for all OMAPx and AMxxxx platforms mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform mtd: nand: omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-scheme am335x: fix GPMC config for NAND and NOR SPL boot arch/arm/cpu/armv7/am33xx/Makefile | 1 - arch/arm/cpu/armv7/am33xx/elm.c | 196 -------------------- arch/arm/cpu/armv7/am33xx/mem.c | 52 +++--- arch/arm/include/asm/arch-am33xx/elm.h | 77 -------- arch/arm/include/asm/arch-am33xx/mem.h | 5 - arch/arm/include/asm/omap_elm.h | 77 ++++++++ arch/arm/include/asm/omap_gpmc.h | 16 ++ board/ti/am335x/board.c | 14 +- doc/README.nand | 53 ++++++ doc/README.omap3 | 3 +- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/omap_elm.c | 196 ++++++++++++++++++++ drivers/mtd/nand/omap_gpmc.c | 323 ++++++++++++++++++++------------- include/configs/am335x_evm.h | 5 +- include/configs/am335x_igep0033.h | 2 + include/configs/am3517_crane.h | 1 + include/configs/am3517_evm.h | 1 + include/configs/devkit8000.h | 1 + include/configs/mcx.h | 2 +- include/configs/omap3_beagle.h | 1 + include/configs/omap3_evm.h | 1 + include/configs/omap3_evm_quick_nand.h | 1 + include/configs/omap3_igep00x0.h | 1 + include/configs/omap3_overo.h | 1 + include/configs/siemens-am33x-common.h | 2 + include/configs/tam3517-common.h | 2 +- include/configs/tricorder.h | 2 +- 27 files changed, 592 insertions(+), 445 deletions(-) delete mode 100644 arch/arm/cpu/armv7/am33xx/elm.c delete mode 100644 arch/arm/include/asm/arch-am33xx/elm.h create mode 100644 arch/arm/include/asm/omap_elm.h create mode 100644 drivers/mtd/nand/omap_elm.c -- 1.8.1

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[U-Boot] [PATCH] TI:omap: Update u-boot-spl.lds for i2c multibus/multiadapter update
by Tom Rini 15 Nov '13

15 Nov '13

In 6789e84 we update u-boot-spl.lds for OMAP to ensure we include adapter information, as we use i2c during SPL. However, the regex used also means we included commands that may have been built. On omap5_uevm this leads to a failure as we include the command from the do_tca642x command, and fail to link. The fix is to restrict our regex to only the i2c list parts. Signed-off-by: Tom Rini <trini(a)ti.com> --- arch/arm/cpu/armv7/omap-common/u-boot-spl.lds | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds index 989083c..02aa129 100644 --- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds @@ -34,8 +34,9 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + KEEP(*(SORT(.u_boot_list*_i2c_*))); } >.sram + . = ALIGN(4); __image_copy_end = .; _end = .; -- 1.7.9.5

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[U-Boot] [PATCH v1 1/4] udoo: Move and optimize platform register setting.
by Giuseppe Pagano 15 Nov '13

15 Nov '13

Previous uDoo configuration adopts register settings for DDR3, clock, muxing, etc. taken from Nitrogen6x. uDoo schematics is rather different from that board, and it needs customized setting for most of the registers. All this changes can be considered atomical since it is part of initial support of the board. Patch changes uDoo configuration files path to a specific one, and adopt optimized value for every configured register. Signed-off-by: Giuseppe Pagano <giuseppe.pagano(a)seco.com> CC: Stefano Babic <sbabic(a)denx.de> CC: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/udoo/1066mhz_4x256mx16.cfg | 56 ++++++++++++++++++++++++ board/udoo/clocks.cfg | 32 ++++++++++++++ board/udoo/ddr-setup.cfg | 87 ++++++++++++++++++++++++++++++++++++++ board/udoo/udoo.cfg | 29 +++++++++++++ boards.cfg | 2 +- 5 files changed, 205 insertions(+), 1 deletion(-) create mode 100644 board/udoo/1066mhz_4x256mx16.cfg create mode 100644 board/udoo/clocks.cfg create mode 100644 board/udoo/ddr-setup.cfg create mode 100644 board/udoo/udoo.cfg diff --git a/board/udoo/1066mhz_4x256mx16.cfg b/board/udoo/1066mhz_4x256mx16.cfg new file mode 100644 index 0000000..539e3f6 --- /dev/null +++ b/board/udoo/1066mhz_4x256mx16.cfg @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 + +DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB + +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 + +DATA 4, MX6_MMDC_P0_MDOR, 0x00591023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 + +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266 + +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45 + +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001 + +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + diff --git a/board/udoo/clocks.cfg b/board/udoo/clocks.cfg new file mode 100644 index 0000000..9cd1af1 --- /dev/null +++ b/board/udoo/clocks.cfg @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF + +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + diff --git a/board/udoo/ddr-setup.cfg b/board/udoo/ddr-setup.cfg new file mode 100644 index 0000000..78cbe17 --- /dev/null +++ b/board/udoo/ddr-setup.cfg @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits x16/x32 + */ +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + diff --git a/board/udoo/udoo.cfg b/board/udoo/udoo.cfg new file mode 100644 index 0000000..8d7ff25 --- /dev/null +++ b/board/udoo/udoo.cfg @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "1066mhz_4x256mx16.cfg" +#include "clocks.cfg" diff --git a/boards.cfg b/boards.cfg index cec154b..1863f2a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -288,7 +288,7 @@ Active arm armv7 mx5 freescale mx53smd Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic <sbabic(a)denx.de> -Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.estevam(a)freescale.com> +Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.este...(a)freescale.com> Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fabio.estevam(a)freescale.com> Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam(a)freescale.com> Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam <fabio.estevam(a)freescale.com> -- 1.7.10.4

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[U-Boot] tr
by Frank Ihle 15 Nov '13

15 Nov '13

Hi everybody I'm writing you since you have been mentioned in the README as help I got this ARM9 SAM9G25, and i try to use it with embedded linux, I already made the images but there's an Error on the target while booting which says "No NandFlash detected !" and afterwards it continues with the system already installed. Since there is a special page from Atmel for this job, i sticked to that content (http://www.at91.com/linux4sam/bin/view/Linux4SAM/SAM9x5Page). I wanted to boot that system from SD Card, therefore i used bootstrap with the at91sam9x5sduboot_defconfig (like the page says) and U-Boot with the at91sam9x5ek_nandflash_config. And i made an image with buildroot (with the patch for that CPU). So in the end I put the boot.bin, u-boot.bin and the uImage-2.6.39-r1-at91sam9x5ek (from buildroot) on the FAT16 SD card and when i try to boot from that Card the error message appears '("no NandFlash detected"), then he ignores the SD-Card device and continues with the already installed system. Unfortunately i have completly no clue whats the problem here, i hope some of you can help me out. But what I know: it trys to read the SD-Card, since there's a little bit of a different startup when booting without the Card. Thank you! and greetings Frank

2 1

[U-Boot] [PATCH 1/3] arm: spl: Fix SPL booting for OMAP3
by Stefan Roese 15 Nov '13

15 Nov '13

SPL already has GD set to the correct location (in s_init), we mustn't move it around now since some data (clocks etc) is already present. This error was detected on the SPL port for the Compulab CM-T35 board (OMAP3530). Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- arch/arm/lib/crt0.S | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index a9657d1..b05f66a 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -85,7 +85,13 @@ ENTRY(_main) bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ sub sp, #GD_SIZE /* allocate one GD above SP */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ +#if !defined(CONFIG_SPL_BUILD) +/* + * SPL already has GD set to the correct location (in s_init), we mustn't + * move it around now since some data (clocks etc) is already present. + */ mov r8, sp /* GD is above SP */ +#endif mov r0, #0 bl board_init_f -- 1.8.2.3

5 32

[U-Boot] [PATCH 00/10 V6] EXYNOS5420: Add SMDK5420 board support
by Rajeshwari S Shinde 15 Nov '13

15 Nov '13

This patch adds basic board support for SMDK5420 board. These patches are tested for booting fine on EVT1 SMDK5420. Changes in V2: - Corrected a compilation issue for SMDK5420. Changes in V3: - Add patch to support variable size SPL support - Add patch to disable SMU for eMMC. Changes in V4: - Added check for MAX77686 pmic compilation. - Added correct calculation of gpio based addresses. - Rebased on the latest u-boot code. - Removed patches for UART and TZPC changes as they were not needed. - Added flag to disable SMU for eMMC. Changes in V5: - Moved functions board_mmc_init and board_eth_init to common/board.c in case of device tree support. Changes in V6: - Rebased on the latest mainline branch. - Moved the definitions for SMU to arch/arm dwmmc.h Rajeshwari S Shinde (10): EXYNOS5: Create a common board file Exynos5420: Add base addresses for 5420 Exynos5420: Add clock initialization for 5420 Exynos5420: Add DDR3 initialization for 5420 Exynos5420: Add support for 5420 in pinmux and gpio Exynos5420: Add base patch for SMDK5420 DTS: Add dts support for SMDK5420 Config: Add initial config for SMDK5420 SPL: EXYNOS: Prepare for variable size SPL support DWMMC: SMDK5420: Disable SMU for eMMC arch/arm/cpu/armv7/exynos/clock.c | 270 ++++++++- arch/arm/cpu/armv7/exynos/clock_init.h | 17 + arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 352 +++++++++++- arch/arm/cpu/armv7/exynos/dmc_common.c | 10 +- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 421 +++++++++++++- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 740 +++++++++++++++++++------ arch/arm/cpu/armv7/exynos/pinmux.c | 241 +++++++- arch/arm/dts/exynos5.dtsi | 211 +++++++ arch/arm/dts/exynos5250.dtsi | 178 +----- arch/arm/dts/exynos5420.dtsi | 74 +++ arch/arm/include/asm/arch-exynos/board.h | 17 + arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/clock.h | 494 +++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 53 +- arch/arm/include/asm/arch-exynos/dmc.h | 121 ++-- arch/arm/include/asm/arch-exynos/dwmmc.h | 13 + arch/arm/include/asm/arch-exynos/gpio.h | 143 ++++- arch/arm/include/asm/arch-exynos/periph.h | 3 + board/samsung/common/Makefile | 4 + board/samsung/common/board.c | 407 ++++++++++++++ board/samsung/dts/exynos5420-smdk5420.dts | 172 ++++++ board/samsung/smdk5250/exynos5-dt.c | 361 +----------- board/samsung/smdk5250/smdk5250.c | 182 +----- board/samsung/smdk5420/Makefile | 34 ++ board/samsung/smdk5420/smdk5420.c | 159 ++++++ board/samsung/smdk5420/smdk5420_spl.c | 52 ++ boards.cfg | 1 + drivers/mmc/dw_mmc.c | 11 + drivers/mmc/exynos_dw_mmc.c | 3 + include/configs/exynos5-dt.h | 302 ++++++++++ include/configs/exynos5250-dt.h | 317 +---------- include/configs/smdk5420.h | 56 ++ include/dwmmc.h | 3 + spl/Makefile | 7 +- tools/Makefile | 2 + tools/mkexynosspl.c | 167 ++++-- 36 files changed, 4271 insertions(+), 1328 deletions(-) create mode 100644 arch/arm/dts/exynos5.dtsi create mode 100644 arch/arm/dts/exynos5420.dtsi create mode 100644 arch/arm/include/asm/arch-exynos/board.h create mode 100644 board/samsung/common/board.c create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts create mode 100644 board/samsung/smdk5420/Makefile create mode 100644 board/samsung/smdk5420/smdk5420.c create mode 100644 board/samsung/smdk5420/smdk5420_spl.c create mode 100644 include/configs/exynos5-dt.h create mode 100644 include/configs/smdk5420.h -- 1.7.12.4

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[U-Boot] [PATCH 1/3][v5] mtd: move & update nand_ecclayout structure
by Prabhakar Kushwaha 15 Nov '13

15 Nov '13

nand_ecclayout is present in mtd.h at Linux. Move this structure to mtd.h to comply with Linux. Also, increase the ecc placement locations to 640 to suport device having writesize/oobsize of 8KB/640B. This means that the maximum oobsize has gone up to 640 bytes and consequently the maximum ecc placement locations have also gone up to 640. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> CC: Vipin Kumar <vipin.kumar(a)st.com> --- Changes for v2: Incorporated Scott's comments - move nand_ecclayout to mtd.h - updated OOBFREE, ECCPOS max entries Changes for v3: Sending as it is Changes for v4: Sending as it is Changes for v5: Sending as it is include/linux/mtd/mtd.h | 14 ++++++++++++++ include/mtd/mtd-abi.h | 12 ------------ 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 6f44abd..3a18f8f 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -96,6 +96,20 @@ struct mtd_oob_ops { uint8_t *oobbuf; }; +#define MTD_MAX_OOBFREE_ENTRIES 32 +#define MTD_MAX_ECCPOS_ENTRIES 640 + +/* + * ECC layout control structure. Exported to userspace for + * diagnosis and to allow creation of raw images + */ +struct nand_ecclayout { + uint32_t eccbytes; + uint32_t eccpos[MTD_MAX_ECCPOS_ENTRIES]; + uint32_t oobavail; + struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES]; +}; + struct mtd_info { u_char type; u_int32_t flags; diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h index d51c1ab..ac3c298 100644 --- a/include/mtd/mtd-abi.h +++ b/include/mtd/mtd-abi.h @@ -155,18 +155,6 @@ struct nand_oobfree { uint32_t length; }; -#define MTD_MAX_OOBFREE_ENTRIES 8 -/* - * ECC layout control structure. Exported to userspace for - * diagnosis and to allow creation of raw images - */ -struct nand_ecclayout { - uint32_t eccbytes; - uint32_t eccpos[128]; - uint32_t oobavail; - struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES]; -}; - /** * struct mtd_ecc_stats - error correction stats * -- 1.7.9.5

2 1

[U-Boot] [PATCHv4] Optimized nand_read_buf for kirkwood
by Phil Sutter 15 Nov '13

15 Nov '13

From: Nico Erfurth <ne(a)erfurth.eu> The basic idea is taken from the linux-kernel, but further optimized. First align the buffer to 8 bytes, then use ldrd/strd to read and store in 8 byte quantities, then do the final bytes. Tested using: 'date ; nand read.raw 0xE00000 0x0 0x10000 ; date'. Without this patch, NAND read of 132MB took 49s (~2.69MB/s). With this patch in place, reading the same amount of data was done in 27s (~4.89MB/s). So read performance is increased by ~80%! Signed-off-by: Nico Erfurth <ne(a)erfurth.eu> Tested-by: Phil Sutter <phil.sutter(a)viprinet.com> Cc: Prafulla Wadaskar <prafulla(a)marvell.com> --- Changed since V3: - fixed author --- drivers/mtd/nand/kirkwood_nand.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c index 0a99a10..85ea5d2 100644 --- a/drivers/mtd/nand/kirkwood_nand.c +++ b/drivers/mtd/nand/kirkwood_nand.c @@ -38,6 +38,37 @@ struct kwnandf_registers { static struct kwnandf_registers *nf_reg = (struct kwnandf_registers *)KW_NANDF_BASE; + +/* + * The basic idea is stolen from the linux kernel, but the inner loop is + * optimized a bit more. + */ +static void kw_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + + while (len && (unsigned long)buf & 7) { + *buf++ = readb(chip->IO_ADDR_R); + len--; + }; + + /* This loop reads and writes 64bit per round. */ + asm volatile ( + "1:\n" + " subs %0, #8\n" + " ldrpld r2, [%2]\n" + " strpld r2, [%1], #8\n" + " bhi 1b\n" + " addne %0, #8\n" + : "+&r" (len), "+&r" (buf) + : "r" (chip->IO_ADDR_R) + : "r2", "r3", "memory", "cc" + ); + + while (len--) + *buf++ = readb(chip->IO_ADDR_R); +} + /* * hardware specific access to control-lines/bits */ @@ -80,6 +111,7 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.mode = NAND_ECC_SOFT; #endif nand->cmd_ctrl = kw_nand_hwcontrol; + nand->read_buf = kw_nand_read_buf; nand->chip_delay = 40; nand->select_chip = kw_nand_select_chip; return 0; -- 1.8.1.5

3 7