October 2013 - U-Boot

[U-Boot] [PATCH V2] buildman: make board selector argument a regex
by Stephen Warren 21 Nov '13

21 Nov '13

From: Stephen Warren <swarren(a)nvidia.com> A common use-case is to build all boards for a particular SoC. This can be achieved by: ./tools/buildman/buildman -b mainline_dev tegra20 However, when the SoC is a member of a family of SoCs, and each SoC has a different name, it would be even more useful to build all boards for every SoC in that family. This currently isn't possible since buildman's board selection command-line arguments are compared to board definitions using pure string equality. To enable this, compare using a regex match instead. This matches MAKEALL's handling of command-line arguments. This enables: (all Tegra) ./tools/buildman/buildman -b mainline_dev tegra (all Tegra) ./tools/buildman/buildman -b mainline_dev '^tegra.*$' (all Tegra20, Tegra30 boards, but not Tegra114) ./tools/buildman/buildman -b mainline_dev 'tegra[23]' Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- v2: Update README to mention new regex matching support. Remove -n from command-line examples in the commit description. --- tools/buildman/README | 14 ++++++++++---- tools/buildman/board.py | 12 +++++++++++- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/tools/buildman/README b/tools/buildman/README index f63f278..8bf907e 100644 --- a/tools/buildman/README +++ b/tools/buildman/README @@ -89,10 +89,16 @@ a few commits or boards, it will be pretty slow. As a tip, if you don't plan to use your machine for anything else, you can use -T to increase the number of threads beyond the default. -Buildman lets you build all boards, or a subset. Specify the subset using -the board name, architecture name, SOC name, or anything else in the -boards.cfg file. So 'at91' will build all AT91 boards (arm), powerpc will -build all PowerPC boards. +Buildman lets you build all boards, or a subset. Specify the subset by passing +command-line arguments that list the desired board name, architecture name, +SOC name, or anything else in the boards.cfg file. Multiple arguments are +allowed. Each argument will be interpreted as a regular expression, so +behaviour is a superset of exact or substring matching. Examples are: + +* 'tegra20' All boards with a Tegra20 SoC +* 'tegra' All boards with any Tegra Soc (Tegra20, Tegra30, Tegra114...) +* '^tegra[23]0$' All boards with either Tegra20 or Tegra30 SoC +* 'powerpc' All PowerPC boards Buildman does not store intermediate object files. It optionally copies the binary output into a directory when a build is successful. Size diff --git a/tools/buildman/board.py b/tools/buildman/board.py index 1d3db20..5172a47 100644 --- a/tools/buildman/board.py +++ b/tools/buildman/board.py @@ -3,6 +3,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +import re + class Board: """A particular board that we can build""" def __init__(self, status, arch, cpu, soc, vendor, board_name, target, options): @@ -135,14 +137,22 @@ class Boards: due to each argument, arranged by argument. """ result = {} + argres = {} for arg in args: result[arg] = 0 + argres[arg] = re.compile(arg) result['all'] = 0 for board in self._boards: if args: for arg in args: - if arg in board.props: + argre = argres[arg] + match = False + for prop in board.props: + match = argre.match(prop) + if match: + break + if match: if not board.build_it: board.build_it = True result[arg] += 1 -- 1.8.1.5

2 2

[U-Boot] [PATCH] mii: dump: parameter choice
by Stephan Bauroth 21 Nov '13

21 Nov '13

Hi all, since no one commented on my prior mail, i just took the liberty to write a little patch that chooses regs 0-5 if none are specified for 'mii dump'. Also fixes some alignment issues, typos and introduces the 'Selector Field' to the register description of PHY regs 4 and 5. On top, 'mii dump' now prints the PHY address in front of a register dump. this is my first patch, if anything is wrong, plese tell me :) diff --git a/common/cmd_mii.c b/common/cmd_mii.c index d3dd6b1..1856c5b 100644 --- a/common/cmd_mii.c +++ b/common/cmd_mii.c @@ -78,9 +78,9 @@ static const MII_field_desc_t reg_3_desc_tbl[] = { static const MII_field_desc_t reg_4_desc_tbl[] = { { 15, 15, 0x01, "next page able" }, - { 14, 14, 0x01, "reserved" }, + { 14, 14, 0x01, "(reserved)" }, { 13, 13, 0x01, "remote fault" }, - { 12, 12, 0x01, "reserved" }, + { 12, 12, 0x01, "(reserved)" }, { 11, 11, 0x01, "asymmetric pause" }, { 10, 10, 0x01, "pause enable" }, { 9, 9, 0x01, "100BASE-T4 able" }, @@ -88,7 +88,7 @@ static const MII_field_desc_t reg_4_desc_tbl[] = { { 7, 7, 0x01, "100BASE-TX able" }, { 6, 6, 0x01, "10BASE-T full duplex able" }, { 5, 5, 0x01, "10BASE-T able" }, - { 4, 0, 0x1f, "xxx to do" }, + { 4, 0, 0x1f, "Selector Field" }, }; static const MII_field_desc_t reg_5_desc_tbl[] = { @@ -103,7 +103,7 @@ static const MII_field_desc_t reg_5_desc_tbl[] = { { 7, 7, 0x01, "100BASE-TX able" }, { 6, 6, 0x01, "10BASE-T full duplex able" }, { 5, 5, 0x01, "10BASE-T able" }, - { 4, 0, 0x1f, "xxx to do" }, + { 4, 0, 0x1f, "Selctor Field" }, }; typedef struct _MII_field_desc_and_len_t { const MII_field_desc_t *pdesc; @@ -130,6 +130,7 @@ static int special_field( ushort regval); static void MII_dump_0_to_5( + unsigned char addr, ushort regvals[6], uchar reglo, uchar reghi) @@ -138,6 +139,7 @@ static void MII_dump_0_to_5( for (i = 0; i < 6; i++) { if ((reglo <= i) && (i <= reghi)) + printf("%02x.", addr); dump_reg(regvals[i], &reg_0_5_desc_tbl[i], &desc_and_len_tbl[i]); } @@ -218,7 +220,7 @@ static int special_field( else if ((regno == MII_ADVERTISE) && (pdesc->lo == 0)) { ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask; - printf("%2u-%2u = %5u selector = %s", + printf("%2u-%2u = %5u Selector Field = %s", pdesc->hi, pdesc->lo, sel_bits, sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3" : @@ -230,7 +232,7 @@ static int special_field( else if ((regno == MII_LPA) && (pdesc->lo == 0)) { ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask; - printf("%2u-%2u = %u selector = %s", + printf("%2u-%2u = %5u Selector Field = %s", pdesc->hi, pdesc->lo, sel_bits, sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3" : @@ -384,6 +386,10 @@ static int do_mii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) "standard MII registers, 0-5.\n"); return 1; } + if (argc < 4){ /* no reg-range given -> dump 0 to 5 */ + reglo = 0; + reghi = 5; + } for (addr = addrlo; addr <= addrhi; addr++) { for (reg = reglo; reg < reghi + 1; reg++) { if (miiphy_read(devname, addr, reg, &regs[reg]) != 0) { @@ -394,8 +400,9 @@ static int do_mii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) rcode = 1; } } - if (ok) - MII_dump_0_to_5(regs, reglo, reghi); + if (ok) { + MII_dump_0_to_5(addr, regs, reglo, reghi); + } printf("\n"); } } else if (strncmp(op, "de", 2) == 0) {

2 1

[U-Boot] [PATCH 0/4] Wandboard support for Future Eletronics 7" WVGA LCD extension board
by Otavio Salvador 21 Nov '13

21 Nov '13

This patchset adds support for the Future Eletronics 7" WVGA LCD extension board and implements its auto-detection using i2c to check for it's touch controller presence. The IOMUXC change is included here as it makes both SoC type MUX settings in line to each other and took a while to figure out why it worked with one and failed with another SoC. Otavio Salvador (4): mx6: Remove PAD_CTL_DSE_120ohm from i.MX6DL's IPU1_DI0_PIN4 pin wandboard: add Future Eletronics 7" WVGA LCD extension board wandboard: Use '0' as bootdelay but interruptable wandboard: Pass 'quiet' bootparam by default arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 2 +- board/wandboard/wandboard.c | 238 ++++++++++++++++++++++++++--- include/configs/wandboard.h | 38 ++++- 3 files changed, 254 insertions(+), 24 deletions(-) -- 1.8.4.rc3

3 8

[U-Boot] [PATCH] Net: FEC: Fix huge memory leak
by Marek Vasut 21 Nov '13

21 Nov '13

The fec_halt() never free'd both RX and TX DMA descriptors that were allocated in fec_init(), nor did it free the RX buffers. Rework the FEC driver so that these descriptors and buffers are allocated only once in fec_probe(). Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> Cc: Stefano Babic <sbabic(a)denx.de> --- drivers/net/fec_mxc.c | 177 ++++++++++++++++++++++++++++---------------------- 1 file changed, 99 insertions(+), 78 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 107cd6e..3b2b995 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -270,49 +270,34 @@ static int fec_tx_task_disable(struct fec_priv *fec) * @param[in] dsize desired size of each receive buffer * @return 0 on success * - * For this task we need additional memory for the data buffers. And each - * data buffer requires some alignment. Thy must be aligned to a specific - * boundary each. + * Init all RX descriptors to default values. */ -static int fec_rbd_init(struct fec_priv *fec, int count, int dsize) +static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) { uint32_t size; + uint8_t *data; int i; /* - * Allocate memory for the buffers. This allocation respects the - * alignment + * Reload the RX descriptors with default values and wipe + * the RX buffers. */ size = roundup(dsize, ARCH_DMA_MINALIGN); for (i = 0; i < count; i++) { - uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); - if (data_ptr == 0) { - uint8_t *data = memalign(ARCH_DMA_MINALIGN, - size); - if (!data) { - printf("%s: error allocating rxbuf %d\n", - __func__, i); - goto err; - } - writel((uint32_t)data, &fec->rbd_base[i].data_pointer); - } /* needs allocation */ - writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status); - writew(0, &fec->rbd_base[i].data_length); + data = (uint8_t *)fec->rbd_base[i].data_pointer; + memset(data, 0, dsize); + flush_dcache_range((uint32_t)data, (uint32_t)data + size); + + fec->rbd_base[i].status = FEC_RBD_EMPTY; + fec->rbd_base[i].data_length = 0; } /* Mark the last RBD to close the ring. */ - writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status); + fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; fec->rbd_index = 0; - return 0; - -err: - for (; i >= 0; i--) { - uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); - free((void *)data_ptr); - } - - return -ENOMEM; + flush_dcache_range((unsigned)fec->rbd_base, + (unsigned)fec->rbd_base + size); } /** @@ -332,10 +317,12 @@ static void fec_tbd_init(struct fec_priv *fec) unsigned addr = (unsigned)fec->tbd_base; unsigned size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); - writew(0x0000, &fec->tbd_base[0].status); - writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); + + memset(fec->tbd_base, 0, size); + fec->tbd_base[0].status = 0; + fec->tbd_base[1].status = FEC_TBD_WRAP; fec->tbd_index = 0; - flush_dcache_range(addr, addr+size); + flush_dcache_range(addr, addr + size); } /** @@ -527,51 +514,18 @@ static int fec_init(struct eth_device *dev, bd_t* bd) { struct fec_priv *fec = (struct fec_priv *)dev->priv; uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; - uint32_t size; - int i, ret; + int i; /* Initialize MAC address */ fec_set_hwaddr(dev); /* - * Allocate transmit descriptors, there are two in total. This - * allocation respects cache alignment. + * Setup transmit descriptors, there are two in total. */ - if (!fec->tbd_base) { - size = roundup(2 * sizeof(struct fec_bd), - ARCH_DMA_MINALIGN); - fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); - if (!fec->tbd_base) { - ret = -ENOMEM; - goto err1; - } - memset(fec->tbd_base, 0, size); - fec_tbd_init(fec); - } + fec_tbd_init(fec); - /* - * Allocate receive descriptors. This allocation respects cache - * alignment. - */ - if (!fec->rbd_base) { - size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), - ARCH_DMA_MINALIGN); - fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); - if (!fec->rbd_base) { - ret = -ENOMEM; - goto err2; - } - memset(fec->rbd_base, 0, size); - /* - * Initialize RxBD ring - */ - if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { - ret = -ENOMEM; - goto err3; - } - flush_dcache_range((unsigned)fec->rbd_base, - (unsigned)fec->rbd_base + size); - } + /* Setup receive descriptors. */ + fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE); fec_reg_setup(fec); @@ -608,13 +562,6 @@ static int fec_init(struct eth_device *dev, bd_t* bd) #endif fec_open(dev); return 0; - -err3: - free(fec->rbd_base); -err2: - free(fec->tbd_base); -err1: - return ret; } /** @@ -907,6 +854,74 @@ static void fec_set_dev_name(char *dest, int dev_id) sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id); } +static int fec_alloc_descs(struct fec_priv *fec) +{ + unsigned int size; + int i; + uint8_t *data; + + /* Allocate TX descriptors. */ + size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); + fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); + if (!fec->tbd_base) + goto err_tx; + + /* Allocate RX descriptors. */ + size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); + fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); + if (!fec->rbd_base) + goto err_rx; + + memset(fec->rbd_base, 0, size); + + /* Allocate RX buffers. */ + + /* Maximum RX buffer size. */ + size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN); + for (i = 0; i < FEC_RBD_NUM; i++) { + data = memalign(ARCH_DMA_MINALIGN, size); + if (!data) { + printf("%s: error allocating rxbuf %d\n", __func__, i); + goto err_ring; + } + + memset(data, 0, size); + + fec->rbd_base[i].data_pointer = (uint32_t)data; + fec->rbd_base[i].status = FEC_RBD_EMPTY; + fec->rbd_base[i].data_length = 0; + /* Flush the buffer to memory. */ + flush_dcache_range((uint32_t)data, (uint32_t)data + size); + } + + /* Mark the last RBD to close the ring. */ + fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; + + fec->rbd_index = 0; + fec->tbd_index = 0; + + return 0; + +err_ring: + for (; i >= 0; i--) + free((void *)fec->rbd_base[i].data_pointer); + free(fec->rbd_base); +err_rx: + free(fec->tbd_base); +err_tx: + return -ENOMEM; +} + +static void fec_free_descs(struct fec_priv *fec) +{ + int i; + + for (i = 0; i < FEC_RBD_NUM; i++) + free((void *)fec->rbd_base[i].data_pointer); + free(fec->rbd_base); + free(fec->tbd_base); +} + #ifdef CONFIG_PHYLIB int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, struct mii_dev *bus, struct phy_device *phydev) @@ -939,6 +954,10 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, memset(edev, 0, sizeof(*edev)); memset(fec, 0, sizeof(*fec)); + ret = fec_alloc_descs(fec); + if (ret) + goto err3; + edev->priv = fec; edev->init = fec_init; edev->send = fec_send; @@ -957,7 +976,7 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { printf("FEC MXC: Timeout reseting chip\n"); - goto err3; + goto err4; } udelay(10); } @@ -984,6 +1003,8 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, eth_setenv_enetaddr("ethaddr", ethaddr); } return ret; +err4: + fec_free_descs(fec); err3: free(fec); err2: -- 1.8.4.rc3

2 1

[U-Boot] [PATCH] spi: Add support SH Quad SPI driver
by Nobuhiro Iwamatsu 21 Nov '13

21 Nov '13

This patch adds a driver for Renesas SoC's Quad SPI bus. This supports with 8 bits per transfer to use with SPI flash. Signed-off-by: Kouei Abe <kouei.abe.cp(a)renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- Changes for v5: - Add print abort when call ctrlc(). - Move source code in spi_xfer() which should be processed by spi_cs_activate(). - Move source code in spi_xfer() which should be processed by spi_cs_deactivate(). - Remove sh_qspi_xfer, move to spi_xfer(). Changes for v4: - Added tabs - Added comments - Added sh_qspi_init() Changes for v3: - Change Queued to Quad. - Remove path of file from file header. - Use read* and write* directly instead of sh_qspi_write* sh_qspi_read*. - Change driver format. Changes for v2: - "SH QSPI" to "SH QSPI (Queued SPI)". - Remove magic number. drivers/spi/Makefile | 1 + drivers/spi/sh_qspi.c | 244 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 245 insertions(+) create mode 100644 drivers/spi/sh_qspi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 91d24ce..c44f851 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o +COBJS-$(CONFIG_SH_QSPI) += sh_qspi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c new file mode 100644 index 0000000..8f53552 --- /dev/null +++ b/drivers/spi/sh_qspi.c @@ -0,0 +1,244 @@ +/* + * SH QSPI (Quad SPI) driver + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> + +/* SH QSPI register bit masks <REG>_<BIT> */ +#define SPCR_MSTR 0x08 +#define SPCR_SPE 0x40 +#define SPSR_SPRFF 0x80 +#define SPSR_SPTEF 0x20 +#define SPPCR_IO3FV 0x04 +#define SPPCR_IO2FV 0x02 +#define SPPCR_IO1FV 0x01 +#define SPBDCR_RXBC0 (1 << 0) +#define SPCMD_SCKDEN (1 << 15) +#define SPCMD_SLNDEN (1 << 14) +#define SPCMD_SPNDEN (1 << 13) +#define SPCMD_SSLKP (1 << 7) +#define SPCMD_BRDV0 (1 << 2) +#define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \ + SPCMD_SPNDEN | SPCMD_SSLKP | \ + SPCMD_BRDV0 +#define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \ + SPCMD_BRDV0 +#define SPBFCR_TXRST (1 << 7) +#define SPBFCR_RXRST (1 << 6) + +/* SH QSPI register set */ +struct sh_qspi_regs { + unsigned char spcr; + unsigned char sslp; + unsigned char sppcr; + unsigned char spsr; + unsigned long spdr; + unsigned char spscr; + unsigned char spssr; + unsigned char spbr; + unsigned char spdcr; + unsigned char spckd; + unsigned char sslnd; + unsigned char spnd; + unsigned char dummy0; + unsigned short spcmd0; + unsigned short spcmd1; + unsigned short spcmd2; + unsigned short spcmd3; + unsigned char spbfcr; + unsigned char dummy1; + unsigned short spbdcr; + unsigned long spbmul0; + unsigned long spbmul1; + unsigned long spbmul2; + unsigned long spbmul3; +}; + +struct sh_qspi_slave { + struct spi_slave slave; + struct sh_qspi_regs *regs; +}; + +static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave) +{ + return container_of(slave, struct sh_qspi_slave, slave); +} + +static void sh_qspi_init(struct sh_qspi_slave *ss) +{ + /* QSPI initialize */ + writeb(SPCR_MSTR, &ss->regs->spcr); + writeb(0x00, &ss->regs->sslp); + writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr); + + /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */ + writeb(0x01, &ss->regs->spbr); + + writeb(0x00, &ss->regs->spdcr); + writeb(0x00, &ss->regs->spckd); + writeb(0x00, &ss->regs->sslnd); + writeb(0x00, &ss->regs->spnd); + writew(SPCMD_INIT1, &ss->regs->spcmd0); + writew(SPCMD_INIT2, &ss->regs->spcmd0); + writeb(SPBFCR_TXRST|SPBFCR_RXRST, &ss->regs->spbfcr); + writeb(0x00, &ss->regs->spbfcr); + writeb(0x00, &ss->regs->spscr); + writeb(SPCR_SPE|SPCR_MSTR, &ss->regs->spcr); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct sh_qspi_slave *ss = to_sh_qspi(slave); + + writeb(SPCR_MSTR, &ss->regs->spcr); + writew(SPCMD_INIT1, &ss->regs->spcmd0); + writeb(SPBFCR_TXRST|SPBFCR_RXRST, &ss->regs->spbfcr); + writeb(0x00, &ss->regs->spbfcr); + writeb(0x00, &ss->regs->spscr); + writeb(SPCR_SPE|SPCR_MSTR, &ss->regs->spcr); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct sh_qspi_slave *ss = to_sh_qspi(slave); + + writeb(SPCR_MSTR, &ss->regs->spcr); +} + +void spi_init(void) +{ + /* nothing to do */ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct sh_qspi_slave *ss; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs); + if (!ss) { + printf("SPI_error: Fail to allocate sh_qspi_slave\n"); + return NULL; + } + + ss->regs = (struct sh_qspi_regs *)CONFIG_SH_QSPI_BASE; + + /* Init SH QSPI */ + sh_qspi_init(ss); + + return &ss->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct sh_qspi_slave *spi = to_sh_qspi(slave); + + free(spi); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct sh_qspi_slave *ss = to_sh_qspi(slave); + unsigned long nbyte; + int ret = 0; + unsigned char dtdata = 0, drdata; + unsigned char *tdata = &dtdata, *rdata = &drdata; + unsigned long *spbmul0 = &ss->regs->spbmul0; + + if (dout == NULL && din == NULL) { + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + return 0; + } + + if (bitlen % 8) { + printf("%s: bitlen is not 8bit alined %d", __func__, bitlen); + return 1; + } + + nbyte = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) { + spi_cs_activate(slave); + + /* Set 1048576 byte */ + writel(0x100000, spbmul0); + } + + if (flags & SPI_XFER_END) + writel(nbyte, spbmul0); + + if (dout != NULL) + tdata = (unsigned char *)dout; + + if (din != NULL) + rdata = din; + + while (nbyte > 0) { + while (!(readb(&ss->regs->spsr) & SPSR_SPTEF)) { + if (ctrlc()) { + puts("abort\n"); + return 1; + } + udelay(10); + } + + writeb(*tdata, (unsigned char *)(&ss->regs->spdr)); + + while ((readw(&ss->regs->spbdcr) != SPBDCR_RXBC0)) { + if (ctrlc()) { + puts("abort\n"); + return 1; + } + udelay(1); + } + + while (!(readb(&ss->regs->spsr) & SPSR_SPRFF)) { + if (ctrlc()) { + puts("abort\n"); + return 1; + } + udelay(10); + } + + *rdata = readb((unsigned char *)(&ss->regs->spdr)); + + if (dout != NULL) + tdata++; + if (din != NULL) + rdata++; + + nbyte--; + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return ret; +} -- 1.8.4.rc3

1 1

[U-Boot] [RESEND PATCH] imx: Easy enabling of SION per-pin using MUX_MODE_SION helper macro
by Otavio Salvador 21 Nov '13

21 Nov '13

The macro allows easy setting in per-pin, as for example: ,---- | imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION); `---- The IOMUX_CONFIG_SION allows for reading PAD value from PSR register. The following quote from the datasheet: ,---- | ... | 28.4.2.2 GPIO Write Mode | The programming sequence for driving output signals should be as follows: | 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need | to read loopback pad value through PSR | 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b). | 3. Write value to data register (GPIO_DR). | ... `---- This fixes the gpio_get_value to properly work when a GPIO is set for output and has no conflicts. Thanks for Benoît Thébaudeau <benoit.thebaudeau(a)advansee.com>, Fabio Estevam <fabio.estevam(a)freescale.com> and Eric Bénard <eric(a)eukrea.com> for helping to properly trace this down. Signed-off-by: Otavio Salvador <otavio(a)ossystems.com.br> --- arch/arm/include/asm/imx-common/iomux-v3.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dc2b3ef..dec11a1 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -63,6 +63,8 @@ typedef u64 iomux_v3_cfg_t; #define MUX_SEL_INPUT_SHIFT 59 #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) +#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \ + MUX_MODE_SHIFT) #define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ -- 1.8.4.rc3

2 1

[U-Boot] [PATCH v2 0/3] mtd: nand: omap: add support for BCH16_ECC
by Pekon Gupta 20 Nov '13

20 Nov '13

*changes in v2* - rebased for http://lists.denx.de/pipermail/u-boot/2013-September/162107.html - minor code cleanup *original v1* This patch series add support of BCH16_ECC scheme. As BCH16_ECC scheme generates 26bytes of ECC syndrome per 512B data, hence this scheme is usable only for NAND devices having 4K or above page-size, as their OOB/spare area has enough space to accomodate ECC. This patch series is applicable over an above following series: http://lists.denx.de/pipermail/u-boot/2013-September/161859.html Pekon Gupta (3): [PATCH 1/3] am33xx: elm: add support for BCH16_ECC - ELM driver updates [PATCH 2/3] mtd: nand: omap: add support for BCH16_ECC - NAND driver updates [PATCH 3/3] am335x: update README for BCH16 arch/arm/cpu/armv7/am33xx/elm.c | 95 ++++++++++++++++++---------- arch/arm/include/asm/arch-am33xx/cpu.h | 15 ++++- arch/arm/include/asm/arch-am33xx/elm.h | 16 ++--- arch/arm/include/asm/arch-am33xx/omap_gpmc.h | 4 +- board/ti/am335x/README | 43 ++++++++++++- drivers/mtd/nand/omap_gpmc.c | 87 ++++++++++++++++++++----- include/mtd/mtd-abi.h | 3 +- 7 files changed, 200 insertions(+), 63 deletions(-) -- 1.8.1

3 8

[U-Boot] [PATCH][v2] powerpc/T1040EMU: Add T1040 emulator support
by Priyanka Jain 19 Nov '13

19 Nov '13

Add emulator support for T1040. Emulator has limited peripherals and interfaces. Difference between T1040QDS and emulator includes: -ECC for DDR is disabled due to procedure to load images -Depends on raw timing for DDR initialization -No board FPGA (Qixis) -No PCI -No SPI -No flash support Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- Changes for v2: Incorporated Wolfgang Denk's review comments Based on u-boot-mpc85xx/next branch. This patch depends upon following patches: 1)[U-Boot] powerpc/t1040qds: Add DDR Raw Timing support http://patchwork.ozlabs.org/patch/286112/ 2)[U-Boot] powerpc/t1040qds: Correct Maintainer name in boards.cfg http://patchwork.ozlabs.org/patch/286113/ board/freescale/t1040qds/Makefile | 3 +- board/freescale/t1040qds/ddr.c | 3 + board/freescale/t1040qds/ddr.h | 13 ++ board/freescale/t1040qds/t1040emu.c | 75 ++++++++ board/freescale/t1040qds/tlb.c | 4 + boards.cfg | 1 + include/configs/T1040EMU.h | 344 +++++++++++++++++++++++++++++++++++ 7 files changed, 442 insertions(+), 1 deletions(-) create mode 100644 board/freescale/t1040qds/t1040emu.c create mode 100644 include/configs/T1040EMU.h diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile index 8f0057b..4bd7103 100644 --- a/board/freescale/t1040qds/Makefile +++ b/board/freescale/t1040qds/Makefile @@ -8,7 +8,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS-y += $(BOARD).o +COBJS-$(CONFIG_T1040QDS) += t1040qds.o +COBJS-$(CONFIG_T1040EMU) += t1040emu.o COBJS-y += ddr.o COBJS-$(CONFIG_PCI) += pci.o COBJS-y += law.o diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c index 16ab829..d46021b 100644 --- a/board/freescale/t1040qds/ddr.c +++ b/board/freescale/t1040qds/ddr.c @@ -123,6 +123,9 @@ phys_size_t initdram(int board_type) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); +#ifdef CONFIG_T1040EMU + dram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +#endif dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h index 4a4f76a..5e0a078 100644 --- a/board/freescale/t1040qds/ddr.h +++ b/board/freescale/t1040qds/ddr.h @@ -54,6 +54,18 @@ struct board_specific_parameters { * for each n_ranks group. */ +#ifdef CONFIG_T1040EMU +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ + {2, 2140, 4, 4, 8, 0x0, 0x0, 0xff, 2, 0}, + {1, 2140, 4, 4, 8, 0x0, 0x0, 0xff, 2, 0}, + {} +}; +#else static const struct board_specific_parameters udimm0[] = { /* * memory controller 0 @@ -72,6 +84,7 @@ static const struct board_specific_parameters udimm0[] = { {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, {} }; +#endif static const struct board_specific_parameters *udimms[] = { udimm0, diff --git a/board/freescale/t1040qds/t1040emu.c b/board/freescale/t1040qds/t1040emu.c new file mode 100644 index 0000000..e9362d6 --- /dev/null +++ b/board/freescale/t1040qds/t1040emu.c @@ -0,0 +1,75 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <netdev.h> +#include <linux/compiler.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> +#include <fm_eth.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + printf("Board: %sEMU\n", cpu->name); + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + return 0; +} + + +int misc_init_r(void) +{ + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + base = getenv_bootm_low(); + size = getenv_bootm_size(); + fdt_fixup_memory(blob, (u64)base, (u64)size); + fdt_fixup_liodn(blob); +} diff --git a/board/freescale/t1040qds/tlb.c b/board/freescale/t1040qds/tlb.c index 412c591..0bc3960 100644 --- a/board/freescale/t1040qds/tlb.c +++ b/board/freescale/t1040qds/tlb.c @@ -53,15 +53,19 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifdef CONFIG_SYS_PCIE1_MEM_PHYS /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), +#endif +#ifdef CONFIG_SYS_PCIE1_IO_PHYS /* *I*G* - PCI I/O */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256K, 1), +#endif /* Bman/Qman */ #ifdef CONFIG_SYS_BMAN_MEM_PHYS diff --git a/boards.cfg b/boards.cfg index dfe1c59..11efdd4 100644 --- a/boards.cfg +++ b/boards.cfg @@ -962,6 +962,7 @@ Active powerpc mpc85xx - freescale t4qds Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale t1040qds T1040EMU T1040EMU:PPC_T1040 Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach(a)gdsys.de> Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach(a)gdsys.de> diff --git a/include/configs/T1040EMU.h b/include/configs/T1040EMU.h new file mode 100644 index 0000000..8c547f2 --- /dev/null +++ b/include/configs/T1040EMU.h @@ -0,0 +1,344 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * T1040 Emulator configuration file + */ +#define CONFIG_T1040EMU +#define CONFIG_PHYS_64BIT + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_MP /* support multiple processors */ +#define CONFIG_SYS_NO_FLASH 1 +#define CONFIG_SYS_FSL_DDR_EMU 1 +#define CONFIG_SYS_FSL_NO_QIXIS 1 +#define CONFIG_SYS_FSL_NO_SERDES 1 + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ + +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_FSL_DDR3 + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x51 + +#define CONFIG_SYS_SDRAM_SIZE 1024 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(0) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ + FTIM0_NOR_TEADC(0x1) | \ + FTIM0_NOR_TEAHC(0x1)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ + FTIM1_NOR_TRAD_NOR(0x1)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ + FTIM2_NOR_TCH(0x0) | \ + FTIM2_NOR_TWP(0x1)) +#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CONFIG_SYS_IFC_CCR 0x01000000 + +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* + * Serial Port + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK 300000000 + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* FIT support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C support */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 25 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 25 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME + +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin"/* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define CONFIG_BAUDRATE 14745600 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ + "bank_intlv=cs0_cs1;\0" \ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t1040emu/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=t1040emu/t1040emu.dtb\0" \ + "bdev=sda3\0" +/* + * For emulation this causes u-boot to jump to the start of the proof point + * app code automatically + */ +#define CONFIG_PROOF_POINTS \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x29000000 - - -;" \ + "cpu 2 release 0x29000000 - - -;" \ + "cpu 3 release 0x29000000 - - -;" \ + "cpu 4 release 0x29000000 - - -;" \ + "cpu 5 release 0x29000000 - - -;" \ + "cpu 6 release 0x29000000 - - -;" \ + "cpu 7 release 0x29000000 - - -;" \ + "go 0x29000000\0" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#endif /* __CONFIG_H */ -- 1.7.4.1

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[U-Boot] [PATCH 1/2 V2] powerpc/esdhc: Map register for eSDHC Host Controller V3.0
by Haijun Zhang 19 Nov '13

19 Nov '13

eSDHC host controller has new register to support SD Spec 3.0. And the according host controller version was Freescale eSDHC Version 3.0. Signed-off-by: Haijun Zhang <haijun.zhang(a)freescale.com> --- changes: - Split from patch [PATCH] powerpc/esdhc: Map register for eSDHC host controller 3.0 drivers/mmc/fsl_esdhc.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 1fba3f7..a3b165e 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -45,9 +45,21 @@ struct fsl_esdhc { uint mixctrl; char reserved1[4]; uint fevt; - char reserved2[168]; + uint admaes; + uint adsaddr; + char reserved2[160]; uint hostver; - char reserved3[780]; + char reserved3[4]; + uint dmaerraddr; + char reserved4[4]; + uint dmaerrattr; + char reserved5[4]; + uint hostcapblt2; + char reserved6[8]; + uint tcr; + char reserved7[28]; + uint sddirctl; + char reserved8[712]; uint scr; }; -- 1.8.4

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[U-Boot] [PATCH 1/3] arm: spl: Fix SPL booting for OMAP3
by Stefan Roese 15 Nov '13

15 Nov '13

SPL already has GD set to the correct location (in s_init), we mustn't move it around now since some data (clocks etc) is already present. This error was detected on the SPL port for the Compulab CM-T35 board (OMAP3530). Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- arch/arm/lib/crt0.S | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index a9657d1..b05f66a 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -85,7 +85,13 @@ ENTRY(_main) bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ sub sp, #GD_SIZE /* allocate one GD above SP */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ +#if !defined(CONFIG_SPL_BUILD) +/* + * SPL already has GD set to the correct location (in s_init), we mustn't + * move it around now since some data (clocks etc) is already present. + */ mov r8, sp /* GD is above SP */ +#endif mov r0, #0 bl board_init_f -- 1.8.2.3

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