October 2013 - U-Boot

[U-Boot] [UBOOT]: Mcspi/qspi conflicting configs leading to build failure.
by Sourav Poddar 03 Oct '13

03 Oct '13

Hi Jagan, If you see the mcspi defconfig(CONFIG_OMAP3_SPI), it is moved to common file "include/configs/ti_armv7_common.h" . But with this, now after adding qspi the build breaks like this.. ti_qspi.o: In function `spi_cs_is_valid': /home/a0131647/clone/u-boot/drivers/spi/ti_qspi.c:108: multiple definition of `spi_cs_is_valid' omap3_spi.o:/home/a0131647/clone/u-boot/drivers/spi/omap3_spi.c:415: first defined here ti_qspi.o: In function `spi_cs_activate': /home/a0131647/clone/u-boot/drivers/spi/ti_qspi.c:114: multiple definition of `spi_cs_activate' omap3_spi.o:/home/a0131647/clone/u-boot/drivers/spi/omap3_spi.c:419: first defined here ti_qspi.o: In function `spi_cs_deactivate': /home/a0131647/clone/u-boot/drivers/spi/ti_qspi.c:120: multiple definition of `spi_cs_deactivate' omap3_spi.o:/home/a0131647/clone/u-boot/drivers/spi/omap3_spi.c:423: first defined here ti_qspi.o: In function `spi_init': /home/a0131647/clone/u-boot/drivers/spi/ti_qspi.c:125: multiple definition of `spi_init' As of now, I am tackling this by doing a undef CONFIG_OMAP3_SPI in my configs. But, we should have a way to use both(spi/qspi) of them simultaneously ?

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[U-Boot] [UBOOT][PATCHv3 0/7] mtd/spi: add quad/memory mapped read support, add ti qspi controller.
by Sourav Poddar 03 Oct '13

03 Oct '13

This patch series add support for TI qspi controller and in the process also add support for quad read and memory mapped read in mtd spi framework. Testing details: Did a boot from qspi mode on DRA7xx. Testing details present in the last patch of the series. Currently, TI qpsi controller supports only 16MB access. Access for higher MB area will be added later. v2->v3: 1. run checkpatch 2. Rearrange the code logically. 3. Remove a page read hack. Matt Porter (3): omap5: add qspi support spi: add TI QSPI driver dra7xx_evm: add SPL API, QSPI, and serial flash support Ravikumar Kattekola (1): drivers: mtd: :spi: Add quad read support Sourav Poddar (3): armv7: hw_data: change clock divider setting. driver: mtd: spi: Add memory mapped read support README: qspi usecase and testing documentation. arch/arm/cpu/armv7/omap5/hw_data.c | 10 +- arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 + arch/arm/include/asm/arch-omap5/omap.h | 3 + arch/arm/include/asm/arch-omap5/spl.h | 1 + arch/arm/include/asm/omap_common.h | 1 + board/ti/dra7xx/mux_data.h | 10 + doc/README.ti_qspi_dra_test | 38 ++++ doc/README.ti_qspi_flash | 47 +++++ drivers/mtd/spi/spansion.c | 1 + drivers/mtd/spi/spi_flash.c | 113 +++++++++++- drivers/mtd/spi/spi_flash_internal.h | 2 + drivers/spi/Makefile | 1 + drivers/spi/ti_qspi.c | 324 ++++++++++++++++++++++++++++++++ include/configs/dra7xx_evm.h | 20 ++ include/spi.h | 5 + 15 files changed, 575 insertions(+), 2 deletions(-) create mode 100644 doc/README.ti_qspi_dra_test create mode 100644 doc/README.ti_qspi_flash create mode 100644 drivers/spi/ti_qspi.c

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[U-Boot] [PATCH] usb: Fix error handling in musb_hcd.c
by Andrew Murray 03 Oct '13

03 Oct '13

The wait_until_[rx|tx]ep_ready functions return a u8 to indicate success containing the value 0, 1 or -1. This patch changes the return type to an int to accommodate the negative return values. These functions are used in the file using calls such as if (!wait_until... Where a -1 is returned it is mishandled and treated as success instead of a CRC error. This patch addresses this. Cc: Marek Vasut <marex(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Signed-off-by: Andrew Murray <amurray(a)embedded-bits.co.uk> --- drivers/usb/musb/musb_hcd.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c index ae39c4a..708fa12 100644 --- a/drivers/usb/musb/musb_hcd.c +++ b/drivers/usb/musb/musb_hcd.c @@ -267,7 +267,7 @@ static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask) /* * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error. */ -static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep) +static int wait_until_txep_ready(struct usb_device *dev, u8 ep) { u16 csr; int timeout = CONFIG_MUSB_TIMEOUT; @@ -299,7 +299,7 @@ static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep) /* * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error. */ -static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep) +static int wait_until_rxep_ready(struct usb_device *dev, u8 ep) { u16 csr; int timeout = CONFIG_MUSB_TIMEOUT; @@ -1018,7 +1018,7 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr); /* Wait until the TxPktRdy bit is cleared */ - if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) { + if (wait_until_txep_ready(dev, MUSB_BULK_EP) != 1) { readw(&musbr->txcsr); usb_settoggle(dev, ep, dir_out, (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); @@ -1053,7 +1053,7 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); /* Wait until the RxPktRdy bit is set */ - if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) { + if (wait_until_rxep_ready(dev, MUSB_BULK_EP) != 1) { csr = readw(&musbr->rxcsr); usb_settoggle(dev, ep, dir_out, (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); @@ -1226,7 +1226,7 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); /* Wait until the RxPktRdy bit is set */ - if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) { + if (wait_until_rxep_ready(dev, MUSB_INTR_EP) != 1) { csr = readw(&musbr->rxcsr); usb_settoggle(dev, ep, dir_out, (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); -- 1.7.9.5

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[U-Boot] [PATCH] sf: spansion: Add support for S25FL512S_256K
by Nobuhiro Iwamatsu 03 Oct '13

03 Oct '13

Add support for Spansion S25FL512S_256K SPI flash. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> --- drivers/mtd/spi/spansion.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c index 47a4897..a7dc096 100644 --- a/drivers/mtd/spi/spansion.c +++ b/drivers/mtd/spi/spansion.c @@ -1,4 +1,5 @@ /* + * Copyright (C) 2013 Renesas Electronics Corporation * Copyright (C) 2009 Freescale Semiconductor, Inc. * * Author: Mingkai Hu (Mingkai.hu(a)freescale.com) @@ -101,6 +102,13 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { .nr_sectors = 1024, .name = "S25FL512S_64K", }, + { + .idcode1 = 0x0220, + .idcode2 = 0x4d00, + .pages_per_sector = 1024, + .nr_sectors = 256, + .name = "S25FL512S_256K", + }, }; struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) -- 1.8.3.2

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[U-Boot] [PATCH v2] sf: probe: Add support for EN25S64
by Jagannadha Sutradharudu Teki 03 Oct '13

03 Oct '13

From: Priyanka Jain <Priyanka.Jain(a)freescale.com> Add support for EON EN25S64 SPI flash. Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- Changes for v2: - Updated as per new probe code drivers/mtd/spi/sf_probe.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 8f56c63..1525636 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -51,6 +51,7 @@ static const struct spi_flash_params spi_flash_params_table[] = { {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0}, {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, SECT_4K}, {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0}, + {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0}, #endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, SECT_4K}, -- 1.8.3

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[U-Boot] [PATCH] imx: Easy enabling of SION per-pin using MUX_MODE_SION helper macro
by Otavio Salvador 03 Oct '13

03 Oct '13

The macro allows easy setting in per-pin, as for example: ,---- | imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION); `---- The IOMUX_CONFIG_SION allows for reading PAD value from PSR register. The following quote from the datasheet: ,---- | ... | 28.4.2.2 GPIO Write Mode | The programming sequence for driving output signals should be as follows: | 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need | to read loopback pad value through PSR | 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b). | 3. Write value to data register (GPIO_DR). | ... `---- This fixes the gpio_get_value to properly work when a GPIO is set for output and has no conflicts. Thanks for Benoît Thébaudeau <benoit.thebaudeau(a)advansee.com>, Fabio Estevam <fabio.estevam(a)freescale.com> and Eric Bénard <eric(a)eukrea.com> for helping to properly trace this down. Signed-off-by: Otavio Salvador <otavio(a)ossystems.com.br> --- arch/arm/include/asm/imx-common/iomux-v3.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dc2b3ef..b7bdaa5 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -57,6 +57,7 @@ typedef u64 iomux_v3_cfg_t; MUX_SEL_INPUT_OFS_SHIFT) #define MUX_MODE_SHIFT 36 +#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << MUX_MODE_SHIFT) #define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) #define MUX_PAD_CTRL_SHIFT 41 #define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT) -- 1.8.4.rc3

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Re: [U-Boot] [PATCH 1/2] Armada100: Adds SD/MMC Register definitions
by Ajay Bhargav 03 Oct '13

03 Oct '13

----- "Pantelis Antoniou" <panto(a)antoniou-consulting.com> wrote: > Hi Ajay, > > On Sep 24, 2013, at 11:02 AM, Ajay Bhargav wrote: > > > This patch add SD/MMC interface register difinitions for Armada100 > > series. > > > > Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> > > --- > > arch/arm/include/asm/arch-armada100/armada100.h | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/arch/arm/include/asm/arch-armada100/armada100.h > b/arch/arm/include/asm/arch-armada100/armada100.h > > index d9feb16..81e4b8a 100644 > > --- a/arch/arm/include/asm/arch-armada100/armada100.h > > +++ b/arch/arm/include/asm/arch-armada100/armada100.h > > @@ -27,6 +27,14 @@ > > #define SSP2_APBCLK 0x01 > > #define SSP2_FNCLK 0x02 > > > > +/* SD Clock/Reset Control Register Bit definition */ > > +#define SD1_SD2_AXI_RESET 0x01 > > +#define SD1_RESET 0x02 > > +#define SD1_SD2_AXICLK_EN 0x08 > > +#define SD1_CLK_EN 0x10 > > +#define SD2_RESET 0x02 > > +#define SD2_CLK_EN 0x10 > > + > > /* USB Clock/reset control bits */ > > #define USB_SPH_AXICLK_EN 0x10 > > #define USB_SPH_AXI_RST 0x02 > > @@ -53,6 +61,8 @@ > > #define ARMD1_UART3_BASE 0xD4026000 > > #define ARMD1_MPMU_BASE 0xD4050000 > > #define ARMD1_USB_HOST_BASE 0xD4209000 > > +#define ARMD1_SD1_BASE 0xD4280000 > > +#define ARMD1_SD2_BASE 0xD4281000 > > #define ARMD1_APMU_BASE 0xD4282800 > > #define ARMD1_CPU_BASE 0xD4282C00 > > > > -- > > 1.8.3.rc3 > > > > Looks fine. > > Acked-by: Pantelis Antoniou <panto(a)antoniou-consulting.com> > > > > Hi Pantelis, May I know, when are you going to update u-boot-mmc custodian? Regards, Ajay Bhargav --------------------------------------------------------------------------------------------- Notice: This message has been scanned by Trend Micro Mail Security scanner and is believed to be clean ---------------------------------------------------------------------------------------------

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[U-Boot] [PATCH] driver/mtd/ifc: Read Status while programming NAND flash
by Prabhakar Kushwaha 03 Oct '13

03 Oct '13

as per controller description, "While programming a NAND flash, status read should never skipped. Because it may happen that a new command is issued to the NAND Flash, even when the device has not yet finished processing the previous request. This may result in unpredictable behaviour." IFC controller never polls for R/B signal after command send. It just return control to software. This behaviour may not occur with NAND flash access. because new commands are sent after polling R/B signal. But it may happen in scenario where GPCM-ASIC and NAND flash device are working simultaneously. Update the controller driver to take care of this requirement Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- drivers/mtd/nand/fsl_ifc_nand.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index cfed549..49b63af 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -491,20 +491,27 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, if (mtd->writesize > 512) { nand_fcr0 = (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT); + (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) | + (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT); out_be32(&ifc->ifc_nand.nand_fir0, (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0); + (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT)); + out_be32(&ifc->ifc_nand.nand_fir1, + (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | + (IFC_FIR_OP_RDSTAT << + IFC_NAND_FIR1_OP6_SHIFT) | + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT)); } else { nand_fcr0 = ((NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT) | (NAND_CMD_SEQIN << - IFC_NAND_FCR0_CMD2_SHIFT)); + IFC_NAND_FCR0_CMD2_SHIFT) | + (NAND_CMD_STATUS << + IFC_NAND_FCR0_CMD3_SHIFT)); out_be32(&ifc->ifc_nand.nand_fir0, (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | @@ -513,7 +520,11 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT)); out_be32(&ifc->ifc_nand.nand_fir1, - (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT)); + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | + (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | + (IFC_FIR_OP_RDSTAT << + IFC_NAND_FIR1_OP7_SHIFT) | + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT)); if (column >= mtd->writesize) nand_fcr0 |= -- 1.7.9.5

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[U-Boot] [PATCH 3/3][v4] board/c29xpcie: Add support of 8K page size NAND flash
by Prabhakar Kushwaha 03 Oct '13

03 Oct '13

Defines constants required to support 8K page size NAND flash. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Changes for v2:Sending as it is Changes for v3:Sending as it is Changes for v4:Sending as it is include/configs/C29XPCIE.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 83779ef..6a1e145 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -189,13 +189,14 @@ | CSPR_MSEL_NAND \ | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2k */ \ - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ + | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ + | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ FTIM0_NAND_TWP(0x0c) | \ FTIM0_NAND_TWCHT(0x08) | \ @@ -222,6 +223,7 @@ #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -- 1.7.9.5

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[U-Boot] [PATCH 2/3][v4] mtd/ifc: Add support of 8K page size NAND flash
by Prabhakar Kushwaha 03 Oct '13

03 Oct '13

Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> CC: Liu Po <po.liu(a)freescale.com> --- Changes for v2: sending as it is Changes for v3: Incorporated Liu Po's commetns - Updated fsl_ifc_spl 8K if conditional check Changes for v4: fix SPL 8K condition check arch/powerpc/cpu/mpc8xxx/fsl_ifc.c | 24 +++++++++++ arch/powerpc/include/asm/fsl_ifc.h | 2 + drivers/mtd/nand/fsl_ifc_nand.c | 78 ++++++++++++++++++++++++++++++++++++ drivers/mtd/nand/fsl_ifc_spl.c | 5 ++- 4 files changed, 108 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c index 2d0fb43..64a5225 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c @@ -34,6 +34,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR0_EXT set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT); #endif +#ifdef CONFIG_SYS_CSOR0_EXT + set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT); +#endif set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); @@ -43,6 +46,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR1_EXT set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT); #endif +#ifdef CONFIG_SYS_CSOR1_EXT + set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT); +#endif #if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); @@ -57,6 +63,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR2_EXT set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT); #endif +#ifdef CONFIG_SYS_CSOR2_EXT + set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT); +#endif #if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); @@ -71,6 +80,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR3_EXT set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT); #endif +#ifdef CONFIG_SYS_CSOR3_EXT + set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT); +#endif #if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); @@ -85,6 +97,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR4_EXT set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); #endif +#ifdef CONFIG_SYS_CSOR4_EXT + set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT); +#endif #if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0); set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1); @@ -99,6 +114,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR5_EXT set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT); #endif +#ifdef CONFIG_SYS_CSOR5_EXT + set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT); +#endif #if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5) set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0); set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1); @@ -113,6 +131,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR6_EXT set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); #endif +#ifdef CONFIG_SYS_CSOR6_EXT + set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT); +#endif #if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0); set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1); @@ -127,6 +148,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR7_EXT set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); #endif +#ifdef CONFIG_SYS_CSOR7_EXT + set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT); +#endif #if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0); set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1); diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h index a945e4b..182b1a6 100644 --- a/arch/powerpc/include/asm/fsl_ifc.h +++ b/arch/powerpc/include/asm/fsl_ifc.h @@ -77,6 +77,7 @@ #define CSOR_NAND_PGS_512 0x00000000 #define CSOR_NAND_PGS_2K 0x00080000 #define CSOR_NAND_PGS_4K 0x00100000 +#define CSOR_NAND_PGS_8K 0x00180000 /* Spare region Size */ #define CSOR_NAND_SPRZ_MASK 0x0000E000 #define CSOR_NAND_SPRZ_SHIFT 13 @@ -86,6 +87,7 @@ #define CSOR_NAND_SPRZ_210 0x00006000 #define CSOR_NAND_SPRZ_218 0x00008000 #define CSOR_NAND_SPRZ_224 0x0000A000 +#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 /* Pages Per Block */ #define CSOR_NAND_PB_MASK 0x00000700 #define CSOR_NAND_PB_SHIFT 8 diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 98a09c0..cfed549 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -125,6 +125,69 @@ static struct nand_ecclayout oob_4096_ecc8 = { .oobfree = { {2, 6}, {136, 82} }, }; +/* 8192-byte page size with 4-bit ECC */ +static struct nand_ecclayout oob_8192_ecc4 = { + .eccbytes = 128, + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, + 128, 129, 130, 131, 132, 133, 134, 135, + }, + .oobfree = { {2, 6}, {136, 208} }, +}; + +/* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */ +static struct nand_ecclayout oob_8192_ecc8 = { + .eccbytes = 256, + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, + 128, 129, 130, 131, 132, 133, 134, 135, + 136, 137, 138, 139, 140, 141, 142, 143, + 144, 145, 146, 147, 148, 149, 150, 151, + 152, 153, 154, 155, 156, 157, 158, 159, + 160, 161, 162, 163, 164, 165, 166, 167, + 168, 169, 170, 171, 172, 173, 174, 175, + 176, 177, 178, 179, 180, 181, 182, 183, + 184, 185, 186, 187, 188, 189, 190, 191, + 192, 193, 194, 195, 196, 197, 198, 199, + 200, 201, 202, 203, 204, 205, 206, 207, + 208, 209, 210, 211, 212, 213, 214, 215, + 216, 217, 218, 219, 220, 221, 222, 223, + 224, 225, 226, 227, 228, 229, 230, 231, + 232, 233, 234, 235, 236, 237, 238, 239, + 240, 241, 242, 243, 244, 245, 246, 247, + 248, 249, 250, 251, 252, 253, 254, 255, + 256, 257, 258, 259, 260, 261, 262, 263, + }, + .oobfree = { {2, 6}, {264, 80} }, +}; /* * Generic flash bbt descriptors @@ -902,6 +965,21 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) priv->bufnum_mask = 1; break; + case CSOR_NAND_PGS_8K: + if ((csor & CSOR_NAND_ECC_MODE_MASK) == + CSOR_NAND_ECC_MODE_4) { + layout = &oob_8192_ecc4; + nand->ecc.strength = 4; + } else { + layout = &oob_8192_ecc8; + nand->ecc.strength = 8; + nand->ecc.bytes = 16; + } + + priv->bufnum_mask = 0; + break; + + default: printf("ifc nand: bad csor %#x: bad page size\n", csor); return -ENODEV; diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index d462265..ccad2a4 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -112,7 +112,10 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8; - if (csor & CSOR_NAND_PGS_4K) { + if (csor & CSOR_NAND_PGS_8K == CSOR_NAND_PGS_8K) { + page_size = 8192; + bufnum_mask = 0x0; + } else if (csor & CSOR_NAND_PGS_4K) { page_size = 4096; bufnum_mask = 0x1; } else if (csor & CSOR_NAND_PGS_2K) { -- 1.7.9.5

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