October 2013 - U-Boot

[U-Boot] [PATCH v5 0/16] Driver model implementation, tests, demo and GPIO
by Simon Glass 06 Nov '13

06 Nov '13

Note: If you are reviewing this code, but don't have a lot of time, please consider starting with the 'demo' driver (patch 'dm: Add a demonstration/example driver') since it clearly shows how devices and uclasses work. Much of this series consists of test code and plumbing, so is of less interest to driver authors. This patch adds a driver model implementation. It is taken from the driver model code developed by: Marek Vasut <marex(a)denx.de> Pavel Herrmann <morpheus.ibis(a)gmail.com> Viktor Křivák <viktor.krivak(a)gmail.com> Tomas Hlavacek <tmshlvck(a)gmail.com> Please see doc/driver-model/README.txt for details of how to run this and what to look for. So far the documentation in doc/driver-model has not been updated. You can find a test version of the code used here in branch dm4 at: http://git.denx.de/u-boot-x86.git (Branch dm contains the original implementation) Changes in v5: - Change to new SPDX license headers - Correct >80col line missed last time - Change to new SPDX license headers - Fix style nit on for() loop - Change to new SPDX license headers - Change to new SPDX license headers - Change to new SPDX license headers - Adjust patch to completely remove old driver model documentation Changes in v4: - Move common/dm to drivers/core - device_chld_unbind() continues on error - Correct 'out.dtb' typo - Change 'dm dump' command to 'dm tree' - Remove duplicated .op line Changes in v3: - Add new patch to build a device tree file for sandbox - Updated README.txt to cover changes since version 2 - Tidy up commenting of functions and structures - Rename per_device_priv_size to per_device_auto_alloc_size, etc. - Add a flag for tracking whether DM allocates/frees platform_data - Add function/struct comments to tests - Fix up demo command help - Update demo driver to use device tree - Update GPIO support to use new struct member names - Tidy up comments/documentation in GPIO module - Update sandbox GPIO header file comments - Add new patch to move driver model documentation Changes in v2: - Removed pointer return values in favour of integer - Use driver_bind() in dm_init() instead of writing new code - Allow driver_bind() to support a NULL parent - Add dm_warn() to warn about impending doom - Standardise variable names (e.g. uclass instead of class) - Remove relocation functions - Add new header file for lists - Add new util file to hold utility functions - Allow a driver to bind to only one uclass - Remove unneeded arguments to uclass_bind(), uclass_unbind() - Rename struct device's 'bus' to 'parent' - Rename data structures to hopefully be clearer - Put platform_data definitions in their own header file - Add U_BOOT_DEVICE to declare platform_data - Add auto-probing feature for platform_data to avoid driver_bind() calls - Add simple unit test functions - Add test infrastructure for driver model - Add integration tests for driver model - Add device tree support in driver model - Add automatic allocation of platform_data for FDT - Add automatic allocation of priv data for devices - Add automatic allocation of device-specific priv data for uclasses - Add GPIO uclass and tests - Add sandbox GPIO driver - Update gpio command to use driver model - Add tests for core code - Add script to run tests - Add a single include/dm.h to bring in driver model code Simon Glass (16): sandbox: Make map_to_sysmem() use a constant pointer sandbox: Correct data sizes and printf() strings in fdtdec.c sandbox: config: Don't use 64-bit physical memory sandbox: Build a device tree file for sandbox Add cmd_process_error() to report and process errors dm: Add README for driver model dm: Add base driver model support sandbox: config: Enable driver model dm: Set up driver model after relocation dm: Add basic tests dm: Add a 'dm' command for testing dm: Add a demonstration/example driver dm: Add GPIO support and tests sandbox: Convert GPIOs to use driver model dm: Enable gpio command to support driver model dm: Remove old driver model documentation Makefile | 4 + arch/sandbox/config.mk | 2 + arch/sandbox/include/asm/gpio.h | 14 +- arch/sandbox/include/asm/io.h | 2 +- arch/sandbox/include/asm/types.h | 4 +- board/sandbox/dts/sandbox.dts | 20 ++ board/sandbox/sandbox/sandbox.c | 7 +- common/Makefile | 1 + common/board_r.c | 33 +++ common/cmd_demo.c | 102 +++++++ common/cmd_gpio.c | 127 ++++++++- common/command.c | 10 + doc/driver-model/README.txt | 321 ++++++++++++++++++++++ doc/driver-model/UDM-block.txt | 278 ------------------- doc/driver-model/UDM-cores.txt | 126 --------- doc/driver-model/UDM-design.txt | 315 ---------------------- doc/driver-model/UDM-fpga.txt | 115 -------- doc/driver-model/UDM-gpio.txt | 106 -------- doc/driver-model/UDM-hwmon.txt | 118 --------- doc/driver-model/UDM-keyboard.txt | 47 ---- doc/driver-model/UDM-mmc.txt | 319 ---------------------- doc/driver-model/UDM-net.txt | 434 ------------------------------ doc/driver-model/UDM-pci.txt | 257 ------------------ doc/driver-model/UDM-pcmcia.txt | 78 ------ doc/driver-model/UDM-power.txt | 88 ------ doc/driver-model/UDM-rtc.txt | 253 ------------------ doc/driver-model/UDM-serial.txt | 175 ------------ doc/driver-model/UDM-spi.txt | 200 -------------- doc/driver-model/UDM-stdio.txt | 191 ------------- doc/driver-model/UDM-tpm.txt | 48 ---- doc/driver-model/UDM-twserial.txt | 47 ---- doc/driver-model/UDM-usb.txt | 94 ------- doc/driver-model/UDM-video.txt | 74 ------ doc/driver-model/UDM-watchdog.txt | 329 ----------------------- drivers/core/Makefile | 27 ++ drivers/core/device.c | 323 ++++++++++++++++++++++ drivers/core/lists.c | 155 +++++++++++ drivers/core/root.c | 102 +++++++ drivers/core/uclass.c | 285 ++++++++++++++++++++ drivers/core/util.c | 37 +++ drivers/demo/Makefile | 31 +++ drivers/demo/demo-pdata.c | 47 ++++ drivers/demo/demo-shape.c | 130 +++++++++ drivers/demo/demo-simple.c | 47 ++++ drivers/demo/demo-uclass.c | 60 +++++ drivers/gpio/Makefile | 2 + drivers/gpio/gpio-uclass.c | 266 +++++++++++++++++++ drivers/gpio/sandbox.c | 210 +++++++++------ include/asm-generic/global_data.h | 8 + include/asm-generic/gpio.h | 104 ++++++++ include/command.h | 9 + include/common.h | 2 +- include/configs/sandbox.h | 10 +- include/dm-demo.h | 36 +++ include/dm.h | 14 + include/dm/device-internal.h | 87 ++++++ include/dm/device.h | 136 ++++++++++ include/dm/lists.h | 39 +++ include/dm/platform_data.h | 22 ++ include/dm/root.h | 53 ++++ include/dm/test.h | 167 ++++++++++++ include/dm/uclass-id.h | 28 ++ include/dm/uclass-internal.h | 85 ++++++ include/dm/uclass.h | 142 ++++++++++ include/dm/ut.h | 95 +++++++ include/dm/util.h | 29 ++ lib/fdtdec.c | 8 +- test/dm/Makefile | 40 +++ test/dm/cmd_dm.c | 133 ++++++++++ test/dm/core.c | 544 ++++++++++++++++++++++++++++++++++++++ test/dm/gpio.c | 111 ++++++++ test/dm/test-driver.c | 146 ++++++++++ test/dm/test-fdt.c | 135 ++++++++++ test/dm/test-main.c | 107 ++++++++ test/dm/test-uclass.c | 104 ++++++++ test/dm/test.dts | 59 +++++ test/dm/ut.c | 33 +++ 77 files changed, 4745 insertions(+), 3802 deletions(-) create mode 100644 board/sandbox/dts/sandbox.dts create mode 100644 common/cmd_demo.c create mode 100644 doc/driver-model/README.txt delete mode 100644 doc/driver-model/UDM-block.txt delete mode 100644 doc/driver-model/UDM-cores.txt delete mode 100644 doc/driver-model/UDM-design.txt delete mode 100644 doc/driver-model/UDM-fpga.txt delete mode 100644 doc/driver-model/UDM-gpio.txt delete mode 100644 doc/driver-model/UDM-hwmon.txt delete mode 100644 doc/driver-model/UDM-keyboard.txt delete mode 100644 doc/driver-model/UDM-mmc.txt delete mode 100644 doc/driver-model/UDM-net.txt delete mode 100644 doc/driver-model/UDM-pci.txt delete mode 100644 doc/driver-model/UDM-pcmcia.txt delete mode 100644 doc/driver-model/UDM-power.txt delete mode 100644 doc/driver-model/UDM-rtc.txt delete mode 100644 doc/driver-model/UDM-serial.txt delete mode 100644 doc/driver-model/UDM-spi.txt delete mode 100644 doc/driver-model/UDM-stdio.txt delete mode 100644 doc/driver-model/UDM-tpm.txt delete mode 100644 doc/driver-model/UDM-twserial.txt delete mode 100644 doc/driver-model/UDM-usb.txt delete mode 100644 doc/driver-model/UDM-video.txt delete mode 100644 doc/driver-model/UDM-watchdog.txt create mode 100644 drivers/core/Makefile create mode 100644 drivers/core/device.c create mode 100644 drivers/core/lists.c create mode 100644 drivers/core/root.c create mode 100644 drivers/core/uclass.c create mode 100644 drivers/core/util.c create mode 100644 drivers/demo/Makefile create mode 100644 drivers/demo/demo-pdata.c create mode 100644 drivers/demo/demo-shape.c create mode 100644 drivers/demo/demo-simple.c create mode 100644 drivers/demo/demo-uclass.c create mode 100644 drivers/gpio/gpio-uclass.c create mode 100644 include/dm-demo.h create mode 100644 include/dm.h create mode 100644 include/dm/device-internal.h create mode 100644 include/dm/device.h create mode 100644 include/dm/lists.h create mode 100644 include/dm/platform_data.h create mode 100644 include/dm/root.h create mode 100644 include/dm/test.h create mode 100644 include/dm/uclass-id.h create mode 100644 include/dm/uclass-internal.h create mode 100644 include/dm/uclass.h create mode 100644 include/dm/ut.h create mode 100644 include/dm/util.h create mode 100644 test/dm/Makefile create mode 100644 test/dm/cmd_dm.c create mode 100644 test/dm/core.c create mode 100644 test/dm/gpio.c create mode 100644 test/dm/test-driver.c create mode 100644 test/dm/test-fdt.c create mode 100644 test/dm/test-main.c create mode 100644 test/dm/test-uclass.c create mode 100644 test/dm/test.dts create mode 100644 test/dm/ut.c -- 1.8.4

3 20

[U-Boot] [PATCH v8 0/5] mtd: nand: omap: optimize and clean-up of OMAP NAND driver
by Pekon Gupta 06 Nov '13

06 Nov '13

*changes in v8* [PATCH 1/5] incorporated following feedbacks from Scott Wood <scottwood(a)freescale.com> - using symbolic names (enums) as values of CONFIG_NAND_OMAP_ECCSCHEME - updated omap_select_ecc_scheme(): perform ecc-scheme compatibility checks before updating nand_chip.ecc fields. This avoids corrupting of existing ecc-scheme in case of switching failures. - code clean-up (removed fall-back on omap_select_ecc_scheme() failures) [PATCH 2/5], [PATCH 3/5], [PATCH 4/5] minor code clean-up [PATCH 5/5] <no update> *changes in v7* [PATCH 1/5] - omap_gpmc.c: fix: free bytes in OOB (ecclayout->oobfree[0].length) - omap_gpmc.c: cleanup: redundant code added in previous patch versions - am335x_evm.h: cleanup: redundant code added in previous patch versions - tricorder.h: fix: CONFIG_NAND_OMAP_ECCSCHEME [PATCH 2/5] removed: re-configuration of gpmc.config1[dev_width] added in previous version of patch [PATCH 3/5] <no update> [PATCH 4/5] <no update> [PATCH 5/5] minor fix: missing '$' in ${loadaddr} *changes in v6* [PATCH 1/5] incorporated feedbacks from Scott Wood <scottwood(a)freescale.com> - renamed CONFIG_SYS_NAND_ECCSCHEME to CONFIG_NAND_OMAP_ECCSCHEME - updated omap_select_ecc_scheme() to handle error conditions without depending on caller. - renamed OMAP_ECC_HAM1_CODE_HW_ROMCODE to OMAP_ECC_HAM1_CODE_HW to keep it naming compatible to linux kernel - updated doc/README.nand and doc/README.omap3 [PATCH 2/5] minor code clean-up [PATCH 3/5] minor code clean-up [PATCH 4/5] <no update> [PATCH 5/5] <moved CONFIG_NAND_OMAP_ECCSCHEME description to README.nand> *changes in v5* This version of patch is tested on am335x-evm with x8 NAND device, and boots SPL and u-boot from NAND [PATCH 1/5] - re-added omap_read_page_bch(): needed proper sequence of while reading DATA and ECC from NAND page, so that calc_ecc generated from GPMC is understood by ELM. - added check to see if NAND OOB can accomodate ECC for entire page [PATCH 2/5] fixed device-width in GPMC_CONFIG1_X to support x16 devices [PATCH 3/5] code clean-up for OMAP_ECC_BCH8_CODE_HW_DETECTION_SW mode [PATCH 4/5] - fixed omap_correct_data_bch() for correcting bit-flips using ELM - code-cleanup + added omap_reverse_list() [PATCH 5/5] incorporated feedbacks from Peter Korsgaard <jacmet(a)sunsite.dk> *changes in v4* [PATCH 1/5] - removed omap_read_page_bch(): chip->ecc.read_page uses default API nand_read_page_hwecc() in nand_base.c - updated tricorder.h: added new CONFIGS for ECCSCHEME & ONFI_DETECTION - converted printf("ECC-SCHEME") to debug("ECC-SCHEME") [PATCH 2/5] minor code clean-up [PATCH 3/5] <no update> [PATCH 4/5] <no update> [PATCH 5/5] updated README as per feedbacks from trini(a)ti.com *changes in v3* [PATCH 1/5] (complete change) - ecc-scheme is selection is controller by s/w, not CONFIG_NAND_xx - added omap_select_ecc_scheme(), as common function to handle all ecc-scheme related configurations for both board_nand_init() & omap_nand_switch_ecc(). - removed un-used defines from asm/arch-am33xx/omap_gpmc.h - updated doc/REAME.nand [PATCH 2/5] removed un-used defines from asm/omap_gpmc.h [PATCH 3/5] removed omap_calculate_ecc_bch_sw() and omap_calculate_ecc() and merged their logic into omap_calculate_ecc_bch() [PATCH 4/5] updated return error-code in-case of invalid conditions [PATCH 5/5] (new) for board/ti/am335x/README *changes in v2* - added documentation for CONFIG_NAND_OMAP_xx in doc/README.nand - added CONFIG_BCH along with CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW to include software library lib/bch.c - fixed board_nand_init() and omap_enable_hwecc() *original v1* This patch series updates BCH8_ECC schemes in mtd/nand/omap_gpmc.c driver - adds scalability for higher ECC schemes in future. - removes CONFIG_AM335x and it makes it generic for all platforms. - optimizes read_data paths Pekon Gupta (5): [PATCH 1/5] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform [PATCH 2/5] mtd: nand: omap: optimize chip->ecc.hwctl() for H/W ECC schemes [PATCH 3/5] mtd: nand: omap: optimize chip->ecc.calculate() for H/W ECC schemes [PATCH 4/5] mtd: nand: omap: optimized chip->ecc.correct() for H/W ECC schemes [PATCH 5/5] board/ti/am335x/README: update for NAND boot arch/arm/include/asm/arch-am33xx/omap_gpmc.h | 52 +- arch/arm/include/asm/omap_gpmc.h | 7 - board/ti/am335x/README | 53 +- doc/README.nand | 38 ++ doc/README.omap3 | 4 +- drivers/mtd/nand/omap_gpmc.c | 843 +++++++++++---------------- include/configs/am335x_evm.h | 11 +- include/configs/tricorder.h | 3 +- 8 files changed, 446 insertions(+), 565 deletions(-) -- 1.8.1

6 14

[U-Boot] [PATCH 6/6][v2] T1040QDS: Add support of 2 stage NAND boot loader
by Prabhakar Kushwaha 06 Nov '13

06 Nov '13

Add support of 2 stage NAND boot loader using SPL framework. here, PBL initialise the internal SRAM(256K) and copy SPL(192K). This further initialise DDR using SPD and environment and copy u-boot(512 kb) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot-mpc85xx.git branch next Changes for v2: sending as it is board/freescale/t1040qds/Makefile | 9 ++- board/freescale/t1040qds/README | 33 ++++++++++ board/freescale/t1040qds/ddr.c | 7 ++- board/freescale/t1040qds/spl.c | 122 +++++++++++++++++++++++++++++++++++++ board/freescale/t1040qds/tlb.c | 8 ++- boards.cfg | 1 + include/configs/T1040QDS.h | 58 +++++++++++++++--- 7 files changed, 227 insertions(+), 11 deletions(-) create mode 100644 board/freescale/t1040qds/spl.c diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile index 8f0057b..8f3d7ef 100644 --- a/board/freescale/t1040qds/Makefile +++ b/board/freescale/t1040qds/Makefile @@ -8,9 +8,16 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +ifdef CONFIG_SPL_BUILD +COBJS-y += spl.o +endif + +ifndef CONFIG_SPL_BUILD COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +endif + COBJS-y += ddr.o -COBJS-$(CONFIG_PCI) += pci.o COBJS-y += law.o COBJS-y += tlb.o diff --git a/board/freescale/t1040qds/README b/board/freescale/t1040qds/README index f8b53b4..0e4d32e 100644 --- a/board/freescale/t1040qds/README +++ b/board/freescale/t1040qds/README @@ -167,3 +167,36 @@ T1042 Personality -------------------- T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit Ethernet switch. Rest of the blocks are same as T1040 + + +2 Stage boot loader +------------------- +PBL initialise the internal SRAM and copy SPL(192K) in SRAM. +SPL further initialise DDR using SPD and environment variables and copy +u-boot(512 KB) from flash to DDR. +Finally SPL transer control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - Actual SPL size 96K + padding till 192K for extra code + - No relocation required + + Run time view of SPL framework :- + ----------------------------------------------- + Area | Address | + ----------------------------------------------- + GD, BD | 0x0xFFFC0000 (4K) | + ----------------------------------------------- + HEAP | 0xFFFC1000 (40K) grow downwards | + ----------------------------------------------- + STACK | 0xFFFD0000 (20K) grow upwards | + ----------------------------------------------- + U-boot SPL | 0xfffD0000 - 0xfffffffc (192K) | + ----------------------------------------------- + +Command to build 2 stage NAND boot loader + - modify RCW at board/freescale/t1040qds/t1040_rcw.cfg for nand boot + -66000002 00000000 fc027000 01000000 + +66000002 00000000 ec106000 01000000 + - make T1040QDS_NAND_config + - make u-boot-with-spl-pbl.bin diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c index 4fd17da..dd2e0cb 100644 --- a/board/freescale/t1040qds/ddr.c +++ b/board/freescale/t1040qds/ddr.c @@ -107,11 +107,14 @@ phys_size_t initdram(int board_type) puts("Initializing....using SPD\n"); +#ifdef CONFIG_SPL_BUILD dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - - puts(" DDR: "); +#else + puts("DDR has been initialised by pre loader\n"); + dram_size = 0x80000000; +#endif return dram_size; } diff --git a/board/freescale/t1040qds/spl.c b/board/freescale/t1040qds/spl.c new file mode 100644 index 0000000..5f39466 --- /dev/null +++ b/board/freescale/t1040qds/spl.c @@ -0,0 +1,122 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <ns16550.h> +#include <asm/spl.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> +#include <malloc.h> +#include <nand.h> +#include <i2c.h> +#include "../common/qixis.h" +#include "t1040qds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +ulong get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; + u32 stack = CONFIG_SPL_RELOC_STACK; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + /* clear BSS segment */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* Set STACK pointer */ + asm volatile ("lwz 1, %0" : : "m"(stack)); + + board_init_r(NULL, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_SPL_GD_ADDR; + bd_t *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + env_init(); + + /* relocate environment function pointers etc. */ + env_relocate(); + + i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE); + + gd->ram_size = initdram(0); + puts("Second program loader running in sram...\n"); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_boot(); +#endif +} diff --git a/board/freescale/t1040qds/tlb.c b/board/freescale/t1040qds/tlb.c index 412c591..c733040 100644 --- a/board/freescale/t1040qds/tlb.c +++ b/board/freescale/t1040qds/tlb.c @@ -52,7 +52,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), - +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -82,6 +82,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -103,6 +104,11 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 11, BOOKE_PAGESZ_4K, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 17, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 5e10125..295d952 100644 --- a/boards.cfg +++ b/boards.cfg @@ -963,6 +963,7 @@ Active powerpc mpc85xx - freescale t4qds Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Naveen Burmi <NaveenBurmi(a)freescale.com> +Active powerpc mpc85xx - freescale t1040qds T1040QDS_NAND T1040QDS:PPC_T1040,RAMBOOT_PBL,NAND Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach(a)gdsys.de> Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach(a)gdsys.de> Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach(a)gdsys.de> diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 7c6bec8..6269ce5 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -30,10 +30,40 @@ #define CONFIG_PHYS_64BIT #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SKIP_RELOCATE_SPL +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD0000 +#define CONFIG_SPL_PAD_TO 0x80000 +#define CONFIG_SPL_MAX_SIZE 0x30000 +#define RESET_VECTOR_OFFSET 0x2FFFC +#define BOOT_PAGE_OFFSET 0x20000 +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (512 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif +#define CONFIG_RAMBOOT_TEXT_BASE 0xFFFC0000 #endif /* High Level Configuration Options */ @@ -97,8 +127,8 @@ #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) @@ -144,7 +174,13 @@ unsigned long get_board_ddr_clk(void); /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_L3_SIZE 256 << 10 +#define CONFIG_SPL_GD_ADDR CONFIG_SYS_INIT_L3_ADDR +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L3_ADDR + 4 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (40 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L3_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (20 << 10) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -171,7 +207,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DDR_SPD #define CONFIG_FSL_DDR3 +#ifndef CONFIG_SPL_BUILD #define CONFIG_FSL_DDR_INTERACTIVE +#endif #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 @@ -347,7 +385,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif #if defined(CONFIG_RAMBOOT_PBL) #define CONFIG_SYS_RAMBOOT @@ -395,7 +437,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ +#endif /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER @@ -589,7 +633,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (9 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 -- 1.7.9.5

2 1

[U-Boot] [PATCH 5/6][v2] SPL:Defines function required to env read for IFC & env_nand
by Prabhakar Kushwaha 06 Nov '13

06 Nov '13

fsl_ifs_spl.c reads data from NAND and store at a memory location in raw mode. It does not used MTD layer. To read env variable from NAND MTD layer read/write required. Hence, add mtd_block_isbad & nand_read_skip_bad function required during env variable read. Also, avoid nand_info during env read for SPL Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot-mpc85xx.git branch next Changes for v2: Sending as it is common/env_nand.c | 4 ++++ drivers/mtd/nand/fsl_ifc_spl.c | 22 ++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/common/env_nand.c b/common/env_nand.c index 695a9ee..77ba003 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -245,7 +245,11 @@ int readenv(size_t offset, u_char *buf) size_t blocksize, len; u_char *char_ptr; +#ifdef CONFIG_SPL_BUILD + blocksize = CONFIG_ENV_SIZE;; +#else blocksize = nand_info[0].erasesize; +#endif if (!blocksize) return 1; diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index d462265..0db7142 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -11,6 +11,28 @@ #include <asm/io.h> #include <asm/fsl_ifc.h> #include <linux/mtd/nand.h> +#ifndef CONFIG_SPL_INIT_MINIMAL +#include <linux/mtd/mtd.h> +#endif + +static void nand_load(unsigned int offs, int uboot_size, uchar *dst); + +#ifdef CONFIG_ENV_IS_IN_NAND +struct mtd_info nand_info[CONFIG_SYS_MAX_NAND_DEVICE]; + +int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs) +{ + return 0; +} + +int nand_read_skip_bad(struct mtd_info *nand, loff_t offset, size_t *length, + size_t *actual, loff_t lim, u_char *buffer) +{ + nand_load(offset, *length, buffer); + return 0; +} +#endif + static inline int is_blank(uchar *addr, int page_size) { -- 1.7.9.5

2 1

[U-Boot] [PATCH 4/6][v2] Makefile:Add u-boot-with-spl-pbl.bin target for SPL
by Prabhakar Kushwaha 06 Nov '13

06 Nov '13

This image combines the pbl format of SPL with and U-Boot. This is a convenient way of having a single image to program on indirect boot source. Corenet platforms like T4240, P4080 etc have PBL hardware which read data in PBL format and copy to internal SRAM for further execution. This image configures DDR, copy u-boot to DDR and transfer the control. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot-mpc85xx.git branch next Changes for v2: Sending as it is Makefile | 7 +++++++ spl/Makefile | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/Makefile b/Makefile index 2d18d27..565aa7a 100644 --- a/Makefile +++ b/Makefile @@ -497,6 +497,9 @@ endif $(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(SPL_PAYLOAD) $(call SPL_PAD_APPEND,$<,$(SPL_PAYLOAD),spl/u-boot-spl-pad.bin,$(CONFIG_SPL_PAD_TO)) +$(obj)u-boot-with-spl-pbl.bin: $(obj)spl/u-boot-spl.pbl $(SPL_PAYLOAD) + $(call SPL_PAD_APPEND,$<,$(SPL_PAYLOAD),spl/u-boot-spl-pad.bin,$(CONFIG_SPL_PAD_TO)) + $(obj)tpl/u-boot-with-tpl.bin: $(obj)tpl/u-boot-tpl.bin $(obj)u-boot.bin $(call SPL_PAD_APPEND,$<,$(obj)u-boot.bin,tpl/u-boot-tpl-pad.bin,$(CONFIG_TPL_PAD_TO)) @@ -624,6 +627,9 @@ $(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend $(MAKE) -C spl all +$(obj)spl/u-boot-spl.pbl: $(SUBDIR_TOOLS) depend + $(MAKE) -C spl all + $(obj)tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend $(MAKE) -C spl all CONFIG_TPL_BUILD=y @@ -918,6 +924,7 @@ clobber: tidy @rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map} @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map} @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map} + @rm -f $(obj)spl/u-boot-spl.pbl @rm -f $(obj)spl/u-boot-spl.lds @rm -f $(obj)tpl/{u-boot-tpl,u-boot-tpl.bin,u-boot-tpl.map} @rm -f $(obj)tpl/u-boot-spl.lds diff --git a/spl/Makefile b/spl/Makefile index b366ac2..6d1ec47 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -181,6 +181,10 @@ ifdef CONFIG_SAMSUNG ALL-y += $(obj)$(BOARD)-spl.bin endif +ifdef CONFIG_PBLPBI_CONFIG +ALL-y += $(obj)$(SPL_BIN).pbl +endif + all: $(ALL-y) ifdef CONFIG_SAMSUNG @@ -192,6 +196,11 @@ endif $(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN) $(OBJCOPY) $(OBJCFLAGS) -O binary $< $@ +$(obj)$(SPL_BIN).pbl: $(obj)$(SPL_BIN).bin + $(obj)../tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \ + -R $(CONFIG_PBLPBI_CONFIG) -T pblimage \ + -d $< $@ + GEN_UBOOT = \ cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $(__START) \ --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ -- 1.7.9.5

2 1

[U-Boot] [PATCH 3/6][v2] common/env: Point default envirenoment for GD
by Prabhakar Kushwaha 06 Nov '13

06 Nov '13

GD(Global Data) structure has pointer to envirenoment variable array. but, it is not being assigned for SPL framwork. So update GD pointer with env variable array. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot-mpc85xx.git branch next Changes for v2: Incorporated York's comments - fix compile warning common/env_common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/common/env_common.c b/common/env_common.c index c0bfc2f..ce95c1a 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -162,6 +162,9 @@ int env_import(const char *buf, int check) if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0, 0, NULL)) { gd->flags |= GD_FLG_ENV_READY; +#ifdef CONFIG_SPL_BUILD + gd->env_addr = (u32)ep->data; +#endif return 1; } -- 1.7.9.5

2 1

[U-Boot] [PATCH 2/6][v2] powerpc/SPL:Allow Parsing of LAW table in both SPL & non SPL
by Prabhakar Kushwaha 06 Nov '13

06 Nov '13

SPL does not relocates the CCSRBAR hence it is using CCSRBAR at 0xfe00_0000. U-boot relocates CCSRBAR to 0xf_fe00_0000. So law talbe needs to be updated again. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot-mpc85xx.git branch next Changes for v2: Sending as it is arch/powerpc/cpu/mpc8xxx/law.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index a401083..d76ba22 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -244,15 +244,6 @@ void init_laws(void) gd->arch.used_laws |= (1 << i); } -#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) - /* - * in SPL boot we've already parsed the law_table and setup those LAWs - * so don't do it again. - */ - return; -#endif - for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, -- 1.7.9.5

2 1

[U-Boot] [PATCH 1/6][v2] powerpc:Add support of SPL non-relocation
by Prabhakar Kushwaha 06 Nov '13

06 Nov '13

Current SPL code base has BSS section placed after reset_vector. This means they have to relocate to use the global variables. This put an implicit requirement of having SPL size = Memory/2. To avoid relocation, move bss_section within SPL range. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot-mpc85xx.git branch next Changes for v2: Sending as it is arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index bc13267..ffc6ad3 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -57,13 +57,34 @@ SECTIONS . = ALIGN(8); __init_begin = .; __init_end = .; +#ifdef CONFIG_SKIP_RELOCATE_SPL + /* + * Make sure that the bss segment isn't linked at 0x0, otherwise its + * address won't be updated during relocation fixups. + */ + . |= 0x10; + + . = ALIGN(4); + __bss_start = .; + .bss : { + *(.sbss*) + *(.bss*) + } + . = ALIGN(4); + __bss_end = .; +#endif /* FIXME for non-NAND SPL */ #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ - .bootpg ADDR(.text) + 0x1000 : +#ifndef BOOT_PAGE_OFFSET +#define BOOT_PAGE_OFFSET 0x1000 +#endif + .bootpg ADDR(.text) + BOOT_PAGE_OFFSET : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) } +#ifndef RESET_VECTOR_OFFSET #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ +#endif #elif defined(CONFIG_FSL_ELBC) #define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ #else @@ -80,6 +101,7 @@ SECTIONS } = 0xffff #endif +#ifndef CONFIG_SKIP_RELOCATE_SPL /* * Make sure that the bss segment isn't linked at 0x0, otherwise its * address won't be updated during relocation fixups. @@ -94,4 +116,5 @@ SECTIONS } . = ALIGN(4); __bss_end = .; +#endif } -- 1.7.9.5

2 1

[U-Boot] [PATCH 1/1] [RFC] DM: early_malloc for DM added.
by Tomas Hlavacek 05 Nov '13

05 Nov '13

Modular early_malloc for DM with support for more heaps and lightweight first heap on stack. (RFC. Not intended for merging!) Signed-off-by: Tomas Hlavacek <tmshlvck(a)gmail.com> --- arch/arm/include/asm/global_data.h | 1 + arch/arm/lib/board.c | 5 ++ arch/avr32/include/asm/global_data.h | 1 + arch/avr32/lib/board.c | 4 ++ arch/blackfin/include/asm/global_data.h | 1 + arch/blackfin/lib/board.c | 4 ++ arch/m68k/include/asm/global_data.h | 1 + arch/m68k/lib/board.c | 4 ++ arch/microblaze/include/asm/global_data.h | 1 + arch/microblaze/lib/board.c | 5 ++ arch/mips/include/asm/global_data.h | 1 + arch/mips/lib/board.c | 4 ++ arch/nds32/include/asm/global_data.h | 1 + arch/nds32/lib/board.c | 4 ++ arch/nios2/include/asm/global_data.h | 1 + arch/nios2/lib/board.c | 4 ++ arch/openrisc/include/asm/global_data.h | 1 + arch/openrisc/lib/board.c | 4 ++ arch/powerpc/include/asm/global_data.h | 1 + arch/powerpc/lib/board.c | 4 ++ arch/sandbox/include/asm/global_data.h | 1 + arch/sandbox/lib/board.c | 4 ++ arch/sh/include/asm/global_data.h | 1 + arch/sparc/include/asm/global_data.h | 1 + arch/sparc/lib/board.c | 4 ++ arch/x86/include/asm/global_data.h | 1 + arch/x86/lib/board.c | 4 ++ common/Makefile | 1 + common/earlymalloc.c | 91 +++++++++++++++++++++++++++++ include/earlymalloc.h | 48 +++++++++++++++ 30 files changed, 208 insertions(+) create mode 100644 common/earlymalloc.c create mode 100644 include/earlymalloc.h diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index c3ff789..71ae6dc 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -84,6 +84,7 @@ typedef struct global_data { unsigned long post_log_res; /* success of POST test */ unsigned long post_init_f_time; /* When post_init_f started */ #endif + void *early_heap_first; /* early heap for early_malloc */ } gd_t; /* diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 500e216..ad124c6 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -52,6 +52,7 @@ #include <fdtdec.h> #include <post.h> #include <logbuff.h> +#include <earlymalloc.h> #ifdef CONFIG_BITBANGMII #include <miiphy.h> @@ -273,6 +274,10 @@ void board_init_f(ulong bootflag) memset((void *)gd, 0, sizeof(gd_t)); + /* Initialize early_malloc */ + DECLARE_EARLY_HEAP_ON_STACK; + early_heap_init(gd->early_heap_first, CONFIG_SYS_EARLY_HEAP_SIZE); + gd->mon_len = _bss_end_ofs; #ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ diff --git a/arch/avr32/include/asm/global_data.h b/arch/avr32/include/asm/global_data.h index 5c654bd..5edb1f0 100644 --- a/arch/avr32/include/asm/global_data.h +++ b/arch/avr32/include/asm/global_data.h @@ -50,6 +50,7 @@ typedef struct global_data { #endif void **jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ + void *early_heap_first; /* early heap for early_malloc */ } gd_t; /* diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index 63fe297..8cb56df 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -149,6 +149,10 @@ void board_init_f(ulong board_type) memset(&gd_data, 0, sizeof(gd_data)); gd = &gd_data; + /* Initialize early_malloc */ + DECLARE_EARLY_HEAP_ON_STACK; + early_heap_init(gd->early_heap_first, CONFIG_SYS_EARLY_HEAP_SIZE); + /* Perform initialization sequence */ board_early_init_f(); cpu_init(); diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h index 67aa30f..33d3cec 100644 --- a/arch/blackfin/include/asm/global_data.h +++ b/arch/blackfin/include/asm/global_data.h @@ -59,6 +59,7 @@ typedef struct global_data { void **jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ + void *early_heap_first; /* early heap for early_malloc */ } gd_t; /* diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index e3ee4cd..f8dade6 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -250,6 +250,10 @@ void board_init_f(ulong bootflag) bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + /* Initialize early_malloc */ + DECLARE_EARLY_HEAP_ON_STACK; + early_heap_init(gd->early_heap_first, CONFIG_SYS_EARLY_HEAP_SIZE); + /* Initialize */ serial_early_puts("IRQ init\n"); irq_init(); diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h index 0ba2b43..ddd76f9 100644 --- a/arch/m68k/include/asm/global_data.h +++ b/arch/m68k/include/asm/global_data.h @@ -68,6 +68,7 @@ typedef struct global_data { #endif void **jt; /* Standalone app jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ + void *early_heap_first; /* early heap for early_malloc */ } gd_t; /* diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index 1526967..a420d21 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -227,6 +227,10 @@ board_init_f (ulong bootflag) /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); + /* Initialize early_malloc */ + DECLARE_EARLY_HEAP_ON_STACK; + early_heap_init(gd->early_heap_first, CONFIG_SYS_EARLY_HEAP_SIZE); + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { if ((*init_fnc_ptr)() != 0) { hang (); diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h index 6e8537c..4e340e6 100644 --- a/arch/microblaze/include/asm/global_data.h +++ b/arch/microblaze/include/asm/global_data.h @@ -47,6 +47,7 @@ typedef struct global_data { unsigned long fb_base; /* base address of frame buffer */ void **jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ + void *early_heap_first; /* early heap for early_malloc */ } gd_t; /* diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index 9828b76..302a323 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -101,6 +101,11 @@ void board_init (void) asm ("nop"); /* FIXME gd is not initialize - wait */ memset ((void *)gd, 0, GENERATED_GBL_DATA_SIZE); memset ((void *)bd, 0, GENERATED_BD_INFO_SIZE); + + /* Initialize early_malloc */ + DECLARE_EARLY_HEAP_ON_STACK; + early_heap_init(gd->early_heap_first, CONFIG_SYS_EARLY_HEAP_SIZE); + gd->bd = bd; gd->baudrate = CONFIG_BAUDRATE; bd->bi_baudrate = CONFIG_BAUDRATE; diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h index f6cf9fe..9656fd6 100644 --- a/arch/mips/include/asm/global_data.h +++ b/arch/mips/include/asm/global_data.h @@ -61,6 +61,7 @@ typedef struct global_data { unsigned long env_valid; /* Checksum of Environment valid? */ void **jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ + void *early_heap_first; /* early heap for early_malloc */ } gd_t; /* diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c index d998f0e..f40258c 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c @@ -160,6 +160,10 @@ void board_init_f(ulong bootflag) memset((void *)gd, 0, sizeof(gd_t)); + /* Initialize early_malloc */ + DECLARE_EARLY_HEAP_ON_STACK; + early_heap_init(gd->early_heap_first, CONFIG_SYS_EARLY_HEAP_SIZE); + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { if ((*init_fnc_ptr)() != 0) hang(); diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h index de20a0a..313fecb 100644 --- a/arch/nds32/include/asm/global_data.h +++ b/arch/nds32/include/asm/global_data.h @@ -65,6 +65,7 @@ typedef struct global_data { void **jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ + void *early_heap_first; /* early heap for early_malloc */ } gd_t; /* diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c index 074aabf..34fff30 100644 --- a/arch/nds32/lib/board.c +++ b/arch/nds32/lib/board.c @@ -190,6 +190,10 @@ void board_init_f(ulong bootflag) memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE); + /* Initialize early_malloc */ + DECLARE_EARLY_HEAP_ON_STACK; + early_heap_init(gd->early_heap_first, CONFIG_SYS_EARLY_HEAP_SIZE); + gd->mon_len = (unsigned int)(&__bss_end__) - (unsigned int)(&_start); for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h index 4b86fbd..02f93d3 100644 --- a/arch/nios2/include/asm/global_data.h +++ b/arch/nios2/include/asm/global_data.h @@ -42,6 +42,7 @@ typedef struct global_data { #endif void **jt; /* Standalone app jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ + void *early_heap_first; /* early heap for early_malloc */ } gd_t; /* flags */ diff --git a/arch/nios2/lib/board.c b/arch/nios2/lib/board.c index 65de26e..87e0559 100644 --- a/arch/nios2/lib/board.c +++ b/arch/nios2/lib/board.c @@ -97,6 +97,10 @@ void board_init (void) memset( gd, 0, GENERATED_GBL_DATA_SIZE ); + /* Initialize early_malloc */ + DECLARE_EARLY_HEAP_ON_STACK; + early_heap_init(gd->early_heap_first, CONFIG_SYS_EARLY_HEAP_SIZE); + gd->bd = (bd_t *)(gd+1); /* At end of global data */ gd->baudrate = CONFIG_BAUDRATE; gd->cpu_clk = CONFIG_SYS_CLK_FREQ; diff --git a/arch/openrisc/include/asm/global_data.h b/arch/openrisc/include/asm/global_data.h index 36de9d0..032b6b2 100644 --- a/arch/openrisc/include/asm/global_data.h +++ b/arch/openrisc/include/asm/global_data.h @@ -46,6 +46,7 @@ typedef struct global_data { unsigned long fb_base; /* base address of frame buffer */ void **jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ + void *early_heap_first; /* early heap for early_malloc */ } gd_t; /* diff --git a/arch/openrisc/lib/board.c b/arch/openrisc/lib/board.c index 85aa189..2a92899 100644 --- a/arch/openrisc/lib/board.c +++ b/arch/openrisc/lib/board.c @@ -86,6 +86,10 @@ void board_init(void) memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE); + /* Initialize early_malloc */ + DECLARE_EARLY_HEAP_ON_STACK; + early_heap_init(gd->early_heap_first, CONFIG_SYS_EARLY_HEAP_SIZE); + gd->bd = (bd_t *)(gd+1); /* At end of global data */ gd->baudrate = CONFIG_BAUDRATE; gd->cpu_clk = CONFIG_SYS_CLK_FREQ; diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 01f1d4a..0839d03 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -184,6 +184,7 @@ typedef struct global_data { #endif void **jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ + void *early_heap_first; /* early heap for early_malloc */ } gd_t; /* diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 3f9af1d..ac88ae2 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -389,6 +389,10 @@ void board_init_f(ulong bootflag) memset((void *) gd, 0, sizeof(gd_t)); #endif + /* Initialize early_malloc */ + DECLARE_EARLY_HEAP_ON_STACK; + early_heap_init(gd->early_heap_first, CONFIG_SYS_EARLY_HEAP_SIZE); + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) if ((*init_fnc_ptr) () != 0) hang(); diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h index 8d47191..54342c0 100644 --- a/arch/sandbox/include/asm/global_data.h +++ b/arch/sandbox/include/asm/global_data.h @@ -47,6 +47,7 @@ typedef struct global_data { phys_size_t ram_size; /* RAM size */ void **jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ + void *early_heap_first; /* early heap for early_malloc */ } gd_t; /* diff --git a/arch/sandbox/lib/board.c b/arch/sandbox/lib/board.c index b7997e9..3d06cfc 100644 --- a/arch/sandbox/lib/board.c +++ b/arch/sandbox/lib/board.c @@ -156,6 +156,10 @@ void board_init_f(ulong bootflag) memset((void *)gd, 0, sizeof(gd_t)); + /* Initialize early_malloc */ + DECLARE_EARLY_HEAP_ON_STACK; + early_heap_init(gd->early_heap_first, CONFIG_SYS_EARLY_HEAP_SIZE); + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { if ((*init_fnc_ptr)() != 0) hang(); diff --git a/arch/sh/include/asm/global_data.h b/arch/sh/include/asm/global_data.h index 1b782fc..180f56e 100644 --- a/arch/sh/include/asm/global_data.h +++ b/arch/sh/include/asm/global_data.h @@ -42,6 +42,7 @@ typedef struct global_data unsigned long env_valid; /* Checksum of Environment valid */ void **jt; /* Standalone app jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ + void *early_heap_first; /* early heap for early_malloc */ } gd_t; #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ diff --git a/arch/sparc/include/asm/global_data.h b/arch/sparc/include/asm/global_data.h index 613e2d8..82ed56f 100644 --- a/arch/sparc/include/asm/global_data.h +++ b/arch/sparc/include/asm/global_data.h @@ -76,6 +76,7 @@ typedef struct global_data { #endif void **jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ + void *early_heap_first; /* early heap for early_malloc */ } gd_t; /* diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c index 519a4fb..86ee8db 100644 --- a/arch/sparc/lib/board.c +++ b/arch/sparc/lib/board.c @@ -179,6 +179,10 @@ void board_init_f(ulong bootflag) /* Clear initial global data */ memset((void *)gd, 0, sizeof(gd_t)); + /* Initialize early_malloc */ + DECLARE_EARLY_HEAP_ON_STACK; + early_heap_init(gd->early_heap_first, CONFIG_SYS_EARLY_HEAP_SIZE); + gd->bd = (bd_t *) (gd + 1); /* At end of global data */ gd->baudrate = CONFIG_BAUDRATE; gd->cpu_clk = CONFIG_SYS_CLK_FREQ; diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 908a02c..171f85b 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -59,6 +59,7 @@ typedef struct global_data { unsigned long reset_status; /* reset status register at boot */ void **jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ + void *early_heap_first; /* early heap for early_malloc */ } gd_t; static inline gd_t *get_fs_gd_ptr(void) diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c index 5f0b62c..5ff4f42 100644 --- a/arch/x86/lib/board.c +++ b/arch/x86/lib/board.c @@ -220,6 +220,10 @@ void board_init_f(ulong boot_flags) { gd->flags = boot_flags; + /* Initialize early_malloc */ + DECLARE_EARLY_HEAP_ON_STACK; + early_heap_init(gd->early_heap_first, CONFIG_SYS_EARLY_HEAP_SIZE); + do_init_loop(init_sequence_f); /* diff --git a/common/Makefile b/common/Makefile index 2a31c62..744beb8 100644 --- a/common/Makefile +++ b/common/Makefile @@ -188,6 +188,7 @@ COBJS-y += console.o COBJS-y += dlmalloc.o COBJS-y += memsize.o COBJS-y += stdio.o +COBJS-y += earlymalloc.o COBJS := $(sort $(COBJS-y)) diff --git a/common/earlymalloc.c b/common/earlymalloc.c new file mode 100644 index 0000000..6ba4df6 --- /dev/null +++ b/common/earlymalloc.c @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2012 + * Tomas Hlavacek (tmshlvck(a)gmail.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> /* for ROUND_UP */ +#include <asm/u-boot.h> +#include <asm/global_data.h> /* for gd_t and gd */ +#include <asm/types.h> /* for phys_addr_t and size_addt_t */ + +#include <earlymalloc.h> + +DECLARE_GLOBAL_DATA_PTR; + + +void early_heap_init(void *heap, size_t size) +{ + struct early_heap_header *h = heap; + + h->free_space_pointer = (void *)(roundup((phys_addr_t)heap + + sizeof(struct early_heap_header), + sizeof(phys_addr_t))); + h->free_bytes = size - roundup(sizeof(struct early_heap_header), + sizeof(phys_addr_t)); + h->next_early_heap = NULL; +} + +void *early_malloc(size_t size) +{ + phys_addr_t addr; + struct early_heap_header *h; + + /* Align size. */ + size = roundup(size, sizeof(phys_addr_t)); + + /* Choose early_heap with enough space. */ + h = gd->early_heap_first; + while ((h->free_bytes < size)&&(h->next_early_heap != NULL)) + h = h->next_early_heap; + + if(h->free_bytes < size) { + debug("Early heap overflow. Heap %08lX, free %d, required %d.", + h, h->free_bytes, size); + return NULL; + } + + /* Choose block beginning address and mark next free space. */ + addr = h->free_space_pointer; + + h->free_space_pointer += size; + h->free_bytes -= size; + + return (void *)addr; +} + + +int early_malloc_isaddress(void *addr) +{ + if ((phys_addr_t)addr < (phys_addr_t)gd->early_heap_first) + return 0; + + if ((phys_addr_t)addr >= (phys_addr_t)gd->early_heap_first + + CONFIG_SYS_EARLY_HEAP_SIZE) + return 0; + + return 1; +} + +int early_malloc_finished(void) +{ + return gd->flags & GD_FLG_RELOC; +} + diff --git a/include/earlymalloc.h b/include/earlymalloc.h new file mode 100644 index 0000000..345bdef --- /dev/null +++ b/include/earlymalloc.h @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2012 + * Tomas Hlavacek (tmshlvck(a)gmail.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __INCLUDE_EARLYMALLOC_H +#define __INCLUDE_EARLYMALLOC_H + +#include <linux/stddef.h> /* for size_t */ + +struct early_heap_header { + void *free_space_pointer; + size_t free_bytes; + void *next_early_heap; +}; + +void early_heap_init(void *heap, size_t size); +void *early_malloc(size_t size); +int early_malloc_isaddress(void *addr); +int early_malloc_finished(void); + +#ifndef CONFIG_SYS_EARLY_HEAP_SIZE +#define CONFIG_SYS_EARLY_HEAP_SIZE 256 +#endif /* CONFIG_SYS_EARLY_HEAP_SIZE */ + +#define DECLARE_EARLY_HEAP_ON_STACK char __early_heap[CONFIG_SYS_EARLY_HEAP_SIZE]; \ + gd->early_heap_first = (void *)__early_heap + +#endif /* __INCLUDE_EARLYMALLOC_H */ + -- 1.7.10.4

7 47

[U-Boot] [PATCH] Add support for TechNexion edm1-cf-imx6 SoM
by Tapani 05 Nov '13

05 Nov '13

Add support for TechNexion edm-cf-imx6 SoM The edm1-cf-imx6 SoM comes in three variants, one with imx6 solo cpu, one with an imx6 dual lite cpu and one with an imx6 quad cpu. This patch adds basic support for the module that utilizes SPL boot mechanism for detecting imx6 CPU runtime and sets the system accordingly. Signed-off-by: Richard Hu <richard.hu(a)technexion.com> Signed-off-by: Tapani Utriainen <tapani(a)technexion.com> Signed-off-by: Edward Lin <edward.lin(a)technexion.com> --- MAINTAINERS | 4 + arch/arm/include/asm/arch-mx6/spl.h | 19 + board/technexion/edm_cf_imx6/Makefile | 26 + board/technexion/edm_cf_imx6/README | 30 + board/technexion/edm_cf_imx6/clocks.cfg | 44 ++ board/technexion/edm_cf_imx6/edm_cf_imx6.c | 801 ++++++++++++++++++++++++ board/technexion/edm_cf_imx6/edm_cf_imx6_pins.h | 44 ++ board/technexion/edm_cf_imx6/imximage.cfg | 17 + boards.cfg | 1 + include/configs/edm_cf_imx6.h | 140 +++++ 10 files changed, 1126 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx6/spl.h create mode 100644 board/technexion/edm_cf_imx6/Makefile create mode 100644 board/technexion/edm_cf_imx6/README create mode 100644 board/technexion/edm_cf_imx6/clocks.cfg create mode 100644 board/technexion/edm_cf_imx6/edm_cf_imx6.c create mode 100644 board/technexion/edm_cf_imx6/edm_cf_imx6_pins.h create mode 100644 board/technexion/edm_cf_imx6/imximage.cfg create mode 100644 include/configs/edm_cf_imx6.h diff --git a/MAINTAINERS b/MAINTAINERS index 0a900dc..2c0f8b1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1074,6 +1074,10 @@ Eric Nelson <eric.nelson(a)boundarydevices.com> nitrogen6s i.MX6S 512MB nitrogen6s1g i.MX6S 1GB +Tapani Utriainen <tapani(a)technexion.com> + + edm_cf_imx6 i.MX6 several configurations + Alison Wang <b18965(a)freescale.com> vf610twr VF610 diff --git a/arch/arm/include/asm/arch-mx6/spl.h b/arch/arm/include/asm/arch-mx6/spl.h new file mode 100644 index 0000000..dd04088 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/spl.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2013 TechNexion Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __ASM_ARCH_IMX6_SPL_H__ +#define __ASM_ARCH_IMX6_SPL_H__ + +#define BOOT_DEVICE_MMC1 0 +#define BOOT_DEVICE_MMC2 1 +#define BOOT_DEVICE_MMC2_2 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_NONE 4 + +#endif /* __ASM_ARCH_IMX6_SPL_H__ */ diff --git a/board/technexion/edm_cf_imx6/Makefile b/board/technexion/edm_cf_imx6/Makefile new file mode 100644 index 0000000..2e764cb --- /dev/null +++ b/board/technexion/edm_cf_imx6/Makefile @@ -0,0 +1,26 @@ +# +# (C) Copyright 2013 TechNexion Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := edm_cf_imx6.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/technexion/edm_cf_imx6/README b/board/technexion/edm_cf_imx6/README new file mode 100644 index 0000000..aaca361 --- /dev/null +++ b/board/technexion/edm_cf_imx6/README @@ -0,0 +1,30 @@ +U-Boot for edm_cf_imx6 +-------------------- + +The edm_cf_imx6 uses SPL boot for auto configuration of CPU type and memory. +Supported cpus are imx6 duallite, quad and solo. + +For more details of the SoM, please refer to: +http://www.technexion.com + +Building U-boot for edm_cf_imx6 +----------------------------- + +To build U-Boot for i.mx6 solo, dual lite, quad: + +$ make distclean +$ make edm_cf_imx6_config +$ make +$ make u-boot.img + +Flashing U-boot into the SD card +-------------------------------- + +- After the 'make u-boot.img' command completes, the generated 'SPL' and +'u-boot.img' binary must be flashed into the SD card: + +# dd if=SPL of=/dev/$dev bs=1k seek=1 + +# dd if=u-boot.img of=/dev/$dev bs=64k seek=1; sync + +Only raw mmc boot has been verified to work. diff --git a/board/technexion/edm_cf_imx6/clocks.cfg b/board/technexion/edm_cf_imx6/clocks.cfg new file mode 100644 index 0000000..9a182c8 --- /dev/null +++ b/board/technexion/edm_cf_imx6/clocks.cfg @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2013 TechNexion Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) for both imx6sdl and imx6q + * + * Each entry must be well-defined on all applicable cpu variants + * + * Also, each entry must have the format + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + * + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 + +/* Note: this turns off NAND clock */ +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU and set Qos=0xf (bypass) */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/technexion/edm_cf_imx6/edm_cf_imx6.c b/board/technexion/edm_cf_imx6/edm_cf_imx6.c new file mode 100644 index 0000000..1a98168 --- /dev/null +++ b/board/technexion/edm_cf_imx6/edm_cf_imx6.c @@ -0,0 +1,801 @@ +/* + * Copyright (C) 2013 TechNexion Ltd. + * + * Author: Richard Hu (richard.hu(a)technexion.com) + * Tapani Utriainen (tapani(a)technexion.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#ifdef CONFIG_SPL +#include <spl.h> +#endif +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/io.h> +#include <asm/sizes.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <mmc.h> + +#include "edm_cf_imx6_pins.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) +#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) + +enum boot_device { + SD0_BOOT, + SD1_BOOT, + MMC_BOOT, + NAND_BOOT, + WEIM_NOR_BOOT, + ONE_NAND_BOOT, + PATA_BOOT, + SATA_BOOT, + I2C_BOOT, + SPI_NOR_BOOT, + UNKNOWN_BOOT, + BOOT_DEV_NUM = UNKNOWN_BOOT, +}; + + +static enum boot_device boot_dev; +enum boot_device get_boot_device(void); + +static inline void setup_boot_device(void) +{ + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ; + uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3; + uint bt_mem_mmc = (soc_sbmr & 0x00001000) >> 12; + + switch (bt_mem_ctl) { + case 0x0: + if (bt_mem_type) + boot_dev = ONE_NAND_BOOT; + else + boot_dev = WEIM_NOR_BOOT; + break; + case 0x2: + boot_dev = SATA_BOOT; + break; + case 0x3: + if (bt_mem_type) + boot_dev = I2C_BOOT; + else + boot_dev = SPI_NOR_BOOT; + break; + case 0x4: + case 0x5: + if (bt_mem_mmc) + boot_dev = SD0_BOOT; + else + boot_dev = SD1_BOOT; + break; + case 0x6: + case 0x7: + boot_dev = MMC_BOOT; + break; + case 0x8 ... 0xf: + boot_dev = NAND_BOOT; + break; + default: + boot_dev = UNKNOWN_BOOT; + break; + } +} + +enum boot_device get_boot_device(void) { + return boot_dev; +} + + +int dram_init(void) +{ + uint cpurev, imxtype; + u32 sdram_size; + + cpurev = get_cpu_rev(); + imxtype = (cpurev & 0xFF000) >> 12; + + switch (imxtype){ + case MXC_CPU_MX6SOLO: + sdram_size = 512 * 1024 * 1024; + break; + case MXC_CPU_MX6Q: + sdram_size = 2u * 1024 * 1024 * 1024; + break; + case MXC_CPU_MX6DL: + default: + sdram_size = 1u * 1024 * 1024 * 1024;; + break; + } + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, sdram_size); + + return 0; +} + +static iomux_v3_cfg_t const edmdl_uart1_pads[] = { + MX6DL_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6DL_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const edmq_uart1_pads[] = { + MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const edmdl_usdhc1_pads[] = { + MX6DL_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6DL_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6DL_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6DL_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6DL_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6DL_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* Card detect */ + MX6DL_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const edmq_usdhc1_pads[] = { + MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* Card detect */ + MX6Q_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const edmdl_usdhc3_pads[] = { + MX6DL_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6DL_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* Card detect */ + MX6DL_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const edmq_usdhc3_pads[] = { + MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* Card detect */ + MX6Q_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static bool cpu_is_mx6q(void) +{ + u32 cpurev, imxtype; + + cpurev = get_cpu_rev(); + imxtype = (cpurev & 0xFF000) >> 12; + + return (imxtype == MXC_CPU_MX6Q); +} + +static void setup_iomux_uart(void) +{ + const iomux_v3_cfg_t *uart1_pads = NULL; + u32 uart1_pads_cnt; + + if (cpu_is_mx6q()) + { + uart1_pads = edmq_uart1_pads; + uart1_pads_cnt = ARRAY_SIZE(edmq_uart1_pads); + } + else + { + uart1_pads = edmdl_uart1_pads; + uart1_pads_cnt = ARRAY_SIZE(edmdl_uart1_pads); + } + imx_iomux_v3_setup_multiple_pads(uart1_pads, uart1_pads_cnt); +} + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + { USDHC3_BASE_ADDR }, + { USDHC1_BASE_ADDR }, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + const iomux_v3_cfg_t *usdhc3_pads = NULL; + u32 usdhc3_pads_cnt; + const iomux_v3_cfg_t *usdhc1_pads = NULL; + u32 usdhc1_pads_cnt; + /* + * Following map is done: + * (U-boot device node) (Physical Port) + * mmc0 SOM MicroSD + * mmc1 Carrier board MicroSD + */ + switch (get_boot_device()) { + case SD1_BOOT: + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + case SD0_BOOT: + default: + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + } + + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + + if (cpu_is_mx6q()) + { + usdhc3_pads = edmq_usdhc3_pads; + usdhc3_pads_cnt = ARRAY_SIZE(edmq_usdhc3_pads); + } + else + { + usdhc3_pads = edmdl_usdhc3_pads; + usdhc3_pads_cnt = ARRAY_SIZE(edmdl_usdhc3_pads); + } + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, usdhc3_pads_cnt); + + gpio_direction_input(USDHC3_CD_GPIO); + break; + case 1: + if (cpu_is_mx6q()) + { + usdhc1_pads = edmq_usdhc1_pads; + usdhc1_pads_cnt = ARRAY_SIZE(edmq_usdhc1_pads); + } + else + { + usdhc1_pads = edmdl_usdhc1_pads; + usdhc1_pads_cnt = ARRAY_SIZE(edmdl_usdhc1_pads); + } + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, usdhc1_pads_cnt); + gpio_direction_input(USDHC1_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } + return status; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + return 0; +} + +int board_init(void) +{ + setup_boot_device(); + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: edm_cf_imx6\n"); + + return 0; +} + +#if defined(CONFIG_SPL_BUILD) +void board_init_f(ulong dummy) +{ + /* Set the stack pointer. */ + asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* Set global data pointer. */ + gd = &gdata; + + arch_cpu_init(); + board_early_init_f(); + timer_init(); + preloader_console_init(); + + board_init_r(NULL, 0); +} + +static void spl_dram_init_mx6solo_512mb(void) +{ + /* DDR3 initialization based on the MX6Solo Auto Reference Design (ARD) */ + /* DDR IO TYPE */ + writel(0x000c0000, IOMUXC_BASE_ADDR + 0x774); + writel(0x00000000, IOMUXC_BASE_ADDR + 0x754); + /* Clock */ + writel(0x00000030, IOMUXC_BASE_ADDR + 0x4ac); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x4b0); + /* Address */ + writel(0x00000030, IOMUXC_BASE_ADDR + 0x464); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x490); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x74c); + /* Control */ + writel(0x000c0030, IOMUXC_BASE_ADDR + 0x494); + writel(0x00003000, IOMUXC_BASE_ADDR + 0x4a4); + writel(0x00003000, IOMUXC_BASE_ADDR + 0x4a8); + writel(0x00000000, IOMUXC_BASE_ADDR + 0x4a0); + writel(0x00003030, IOMUXC_BASE_ADDR + 0x4b4); + writel(0x00003030, IOMUXC_BASE_ADDR + 0x4b8); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x76c); + /* Strobe */ + writel(0x00020000, IOMUXC_BASE_ADDR + 0x750); + writel(0x00000038, IOMUXC_BASE_ADDR + 0x4bc); + writel(0x00000038, IOMUXC_BASE_ADDR + 0x4c0); + writel(0x00000038, IOMUXC_BASE_ADDR + 0x4c4); + writel(0x00000038, IOMUXC_BASE_ADDR + 0x4c8); + writel(0x00000038, IOMUXC_BASE_ADDR + 0x4cc); + writel(0x00000038, IOMUXC_BASE_ADDR + 0x4d0); + writel(0x00000038, IOMUXC_BASE_ADDR + 0x4d4); + writel(0x00000038, IOMUXC_BASE_ADDR + 0x4d8); + /* Data */ + writel(0x00020000, IOMUXC_BASE_ADDR + 0x760); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x764); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x770); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x778); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x77c); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x780); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x784); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x78c); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x748); + + writel(0x00000030, IOMUXC_BASE_ADDR + 0x470); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x474); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x478); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x47c); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x480); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x484); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x488); + writel(0x000C0030, IOMUXC_BASE_ADDR + 0x48c); + /* ZQ */ + writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800); + writel(0xa1390003, MMDC_P1_BASE_ADDR + 0x800); + /* Write leveling */ + writel(0x0040003c, MMDC_P0_BASE_ADDR + 0x80c); + writel(0x0032003e, MMDC_P0_BASE_ADDR + 0x810); + + writel(0x42350231, MMDC_P0_BASE_ADDR + 0x83c); + writel(0x021a0218, MMDC_P0_BASE_ADDR + 0x840); + writel(0x4b4b4e49, MMDC_P0_BASE_ADDR + 0x848); + writel(0x3f3f3035, MMDC_P0_BASE_ADDR + 0x850); + /* Read data bit delay */ + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c); + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820); + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824); + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828); + /* Complete calibration by forced measurement */ + writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8); + + writel(0x0002002d, MMDC_P0_BASE_ADDR + 0x004); + writel(0x00333030, MMDC_P0_BASE_ADDR + 0x008); + writel(0x696d5323, MMDC_P0_BASE_ADDR + 0x00c); + writel(0xb66e8c63, MMDC_P0_BASE_ADDR + 0x010); + writel(0x01ff00db, MMDC_P0_BASE_ADDR + 0x014); + writel(0x00001740, MMDC_P0_BASE_ADDR + 0x018); + writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x000026d2, MMDC_P0_BASE_ADDR + 0x02c); + writel(0x006d0e21, MMDC_P0_BASE_ADDR + 0x030); + writel(0x00000027, MMDC_P0_BASE_ADDR + 0x040); + writel(0x84190000, MMDC_P0_BASE_ADDR + 0x000); + writel(0x04008032, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x07208030, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x00005800, MMDC_P0_BASE_ADDR + 0x020); + writel(0x00011117, MMDC_P0_BASE_ADDR + 0x818); + writel(0x00011117, MMDC_P1_BASE_ADDR + 0x818); + writel(0x0002556d, MMDC_P0_BASE_ADDR + 0x004); + writel(0x00011006, MMDC_P1_BASE_ADDR + 0x004); + writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c); +} + +static void spl_dram_init_mx6dl_1g(void) +{ + /* DDR3 initialization based on the MX6Solo Auto Reference Design (ARD) */ + /* DDR IO TYPE */ + writel(0x000c0000, IOMUXC_BASE_ADDR + 0x774); + writel(0x00000000, IOMUXC_BASE_ADDR + 0x754); + /* Clock */ + writel(0x00000030, IOMUXC_BASE_ADDR + 0x4ac); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x4b0); + /* Address */ + writel(0x00000030, IOMUXC_BASE_ADDR + 0x464); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x490); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x74c); + /* Control */ + writel(0x00000030, IOMUXC_BASE_ADDR + 0x494); + writel(0x00003000, IOMUXC_BASE_ADDR + 0x4a4); + writel(0x00003000, IOMUXC_BASE_ADDR + 0x4a8); + writel(0x00000000, IOMUXC_BASE_ADDR + 0x4a0); + writel(0x00003030, IOMUXC_BASE_ADDR + 0x4b4); + writel(0x00003030, IOMUXC_BASE_ADDR + 0x4b8); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x76c); + /* Data Strobe */ + writel(0x00020000, IOMUXC_BASE_ADDR + 0x750); + + writel(0x00000030, IOMUXC_BASE_ADDR + 0x4bc); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x4c0); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x4c4); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x4c8); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x4cc); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x4d0); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x4d4); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x4d8); + /* Data */ + writel(0x00020000, IOMUXC_BASE_ADDR + 0x760); + + writel(0x00000030, IOMUXC_BASE_ADDR + 0x764); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x770); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x778); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x77c); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x780); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x784); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x78c); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x748); + + writel(0x00000030, IOMUXC_BASE_ADDR + 0x470); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x474); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x478); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x47c); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x480); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x484); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x488); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x48c); + + /* Calibrations */ + /* ZQ */ + writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800); + writel(0xa1390003, MMDC_P1_BASE_ADDR + 0x800); + /* write leveling */ + writel(0x001F001F, MMDC_P0_BASE_ADDR + 0x80c); + writel(0x001F001F, MMDC_P0_BASE_ADDR + 0x810); + writel(0x001F001F, MMDC_P1_BASE_ADDR + 0x80c); + writel(0x001F001F, MMDC_P1_BASE_ADDR + 0x810); + /* DQS gating, read delay, write delay calibration values */ + /* based on calibration compare of 0x00ffff00 */ + writel(0x420E020E, MMDC_P0_BASE_ADDR + 0x83c); + writel(0x02000200, MMDC_P0_BASE_ADDR + 0x840); + writel(0x42020202, MMDC_P1_BASE_ADDR + 0x83C); + writel(0x01720172, MMDC_P1_BASE_ADDR + 0x840); + writel(0x494C4F4C, MMDC_P0_BASE_ADDR + 0x848); + writel(0x4A4C4C49, MMDC_P1_BASE_ADDR + 0x848); + writel(0x3F3F3133, MMDC_P0_BASE_ADDR + 0x850); + writel(0x39373F2E, MMDC_P1_BASE_ADDR + 0x850); + /* read data bit delay */ + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c); + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820); + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824); + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828); + /* Complete calibration by forced measurment */ + writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8); + writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8); + + writel(0x0002002d, MMDC_P0_BASE_ADDR + 0x004); + writel(0x00333030, MMDC_P0_BASE_ADDR + 0x008); + + writel(0x40445323, MMDC_P0_BASE_ADDR + 0x00c); + writel(0xb66e8c63, MMDC_P0_BASE_ADDR + 0x010); + + writel(0x01ff00db, MMDC_P0_BASE_ADDR + 0x014); + writel(0x00081740, MMDC_P0_BASE_ADDR + 0x018); + writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x000026d2, MMDC_P0_BASE_ADDR + 0x02c); + writel(0x00440e21, MMDC_P0_BASE_ADDR + 0x030); + writel(0x00000027, MMDC_P0_BASE_ADDR + 0x040); + writel(0xc31a0000, MMDC_P0_BASE_ADDR + 0x000); + /* MR2 */ + writel(0x04008032, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x0400803a, MMDC_P0_BASE_ADDR + 0x01c); + /* MR3 */ + writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x0000803b, MMDC_P0_BASE_ADDR + 0x01c); + /* MR1 */ + writel(0x00428031, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x00428039, MMDC_P0_BASE_ADDR + 0x01c); + /* MR0 */ + writel(0x07208030, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x07208038, MMDC_P0_BASE_ADDR + 0x01c); + /* ZQ calibration */ + writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c); + /* final DDR setup */ + writel(0x00005800, MMDC_P0_BASE_ADDR + 0x020); + writel(0x00000007, MMDC_P0_BASE_ADDR + 0x818); + writel(0x00000007, MMDC_P1_BASE_ADDR + 0x818); + writel(0x0002556d, MMDC_P0_BASE_ADDR + 0x004); + writel(0x00011006, MMDC_P1_BASE_ADDR + 0x404); + writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c); +} + +static void spl_dram_init_mx6q_2g(void) +{ + /* i.MX6Q */ + /* DDR IO TYPE */ + writel(0x000C0000, IOMUXC_BASE_ADDR + 0x798); + writel(0x00000000, IOMUXC_BASE_ADDR + 0x758); + /* Clock */ + writel(0x00000030, IOMUXC_BASE_ADDR + 0x588); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x594); + /* Address */ + writel(0x00000030, IOMUXC_BASE_ADDR + 0x56c); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x578); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x74c); + /* Control */ + writel(0x00000030, IOMUXC_BASE_ADDR + 0x57c); + + writel(0x00000000, IOMUXC_BASE_ADDR + 0x58c); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x59c); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x5a0); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x78c); + /* Data Strobe */ + writel(0x00020000, IOMUXC_BASE_ADDR + 0x750); + + writel(0x00000030, IOMUXC_BASE_ADDR + 0x5a8); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x5b0); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x524); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x51c); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x518); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x50c); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x5b8); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x5c0); + /* Data */ + writel(0x00020000, IOMUXC_BASE_ADDR + 0x774); + + writel(0x00000030, IOMUXC_BASE_ADDR + 0x784); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x788); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x794); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x79c); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x7a0); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x7a4); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x7a8); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x748); + + writel(0x00000030, IOMUXC_BASE_ADDR + 0x5ac); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x5b4); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x528); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x520); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x514); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x510); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x5bc); + writel(0x00000030, IOMUXC_BASE_ADDR + 0x5c4); + + /* Calibrations */ + /* ZQ */ + writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800); + /* write leveling */ + writel(0x001F001F, MMDC_P0_BASE_ADDR + 0x80c); + writel(0x001F001F, MMDC_P0_BASE_ADDR + 0x810); + writel(0x001F001F, MMDC_P1_BASE_ADDR + 0x80c); + writel(0x001F001F, MMDC_P1_BASE_ADDR + 0x810); + /* DQS gating, read delay, write delay calibration values */ + /* based on calibration compare of 0x00ffff00 */ + writel(0x4301030D, MMDC_P0_BASE_ADDR + 0x83c); + writel(0x03020277, MMDC_P0_BASE_ADDR + 0x840); + writel(0x4300030A, MMDC_P1_BASE_ADDR + 0x83c); + writel(0x02780248, MMDC_P1_BASE_ADDR + 0x840); + + writel(0x4536393B, MMDC_P0_BASE_ADDR + 0x848); + writel(0x36353441, MMDC_P1_BASE_ADDR + 0x848); + + writel(0x41414743, MMDC_P0_BASE_ADDR + 0x850); + writel(0x462F453F, MMDC_P1_BASE_ADDR + 0x850); + + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c); + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820); + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824); + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828); + + writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8); + writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8); + /* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated: */ + writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004); + writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008); + writel(0x555A7975, MMDC_P0_BASE_ADDR + 0x00c); + writel(0xFF538F64, MMDC_P0_BASE_ADDR + 0x010); + writel(0x01FF00DB, MMDC_P0_BASE_ADDR + 0x014); + writel(0x00001740, MMDC_P0_BASE_ADDR + 0x018); + + writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c); + writel(0x005A1023, MMDC_P0_BASE_ADDR + 0x030); + + /* 2G */ + writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040); + writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000); + + writel(0x04088032, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x09408030, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c); + + writel(0x00005800, MMDC_P0_BASE_ADDR + 0x020); + + writel(0x00011117, MMDC_P0_BASE_ADDR + 0x818); + writel(0x00011117, MMDC_P1_BASE_ADDR + 0x818); + + writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004); + writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404); + writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c); +} + +static void spl_dram_init(void) +{ + u32 cpurev, imxtype; + + cpurev = get_cpu_rev(); + imxtype = (cpurev & 0xFF000) >> 12; + + puts("CPU: Freescale i.MX"); + puts(get_imx_type(imxtype)); + puts("\n"); + + switch (imxtype){ + case MXC_CPU_MX6SOLO: + spl_dram_init_mx6solo_512mb(); + break; + case MXC_CPU_MX6Q: + spl_dram_init_mx6q_2g(); + break; + case MXC_CPU_MX6DL: + default: + spl_dram_init_mx6dl_1g(); + break; + } +} + +void spl_board_init(void) +{ + spl_dram_init(); + setup_boot_device(); +} + +u32 spl_boot_device(void) +{ + puts("Boot Device: "); + switch (get_boot_device()) { + case SD0_BOOT: + printf("SD0\n"); + return BOOT_DEVICE_MMC1; + case SD1_BOOT: + printf("SD1\n"); + return BOOT_DEVICE_MMC2; + case MMC_BOOT: + printf("MMC\n"); + return BOOT_DEVICE_MMC2; + case NAND_BOOT: + printf("NAND\n"); + return BOOT_DEVICE_NAND; + case UNKNOWN_BOOT: + default: + printf("UNKNOWN\n"); + return BOOT_DEVICE_NONE; + } +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: + case BOOT_DEVICE_MMC2_2: +#ifdef CONFIG_SPL_FAT_SUPPORT + return MMCSD_MODE_FAT; +#else + return MMCSD_MODE_RAW; +#endif + break; + case BOOT_DEVICE_NAND: + default: + puts("spl: ERROR: unsupported device\n"); + hang(); + } +} + +void reset_cpu(ulong addr) +{ + +} +#endif diff --git a/board/technexion/edm_cf_imx6/edm_cf_imx6_pins.h b/board/technexion/edm_cf_imx6/edm_cf_imx6_pins.h new file mode 100644 index 0000000..cba5d1c --- /dev/null +++ b/board/technexion/edm_cf_imx6/edm_cf_imx6_pins.h @@ -0,0 +1,44 @@ +#ifndef _EDM_CF_IMX6_PINS_H +#define _EDM_CF_IMX6_PINS_H + +enum { + MX6DL_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0), + MX6DL_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0), + + MX6Q_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0), + MX6Q_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0), + + MX6DL_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, 0), + MX6DL_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6DL_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), + MX6DL_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), + MX6DL_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), + MX6DL_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), + MX6DL_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), + + MX6Q_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0), + MX6Q_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0), + MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0), + MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0), + MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0), + MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0), + MX6Q_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), + + MX6DL_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0), + MX6DL_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), + MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), + MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), + MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), + MX6DL_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0), + + MX6Q_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0), + MX6Q_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0), + MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0), + MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), + MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), + MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), + MX6Q_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0), +}; + +#endif /* _EDM_CF_IMX6_PINS_H */ diff --git a/board/technexion/edm_cf_imx6/imximage.cfg b/board/technexion/edm_cf_imx6/imximage.cfg new file mode 100644 index 0000000..4019d68 --- /dev/null +++ b/board/technexion/edm_cf_imx6/imximage.cfg @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2013 TechNexion Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +IMAGE_VERSION 2 + +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "clocks.cfg" diff --git a/boards.cfg b/boards.cfg index 79d6cd8..b7d66ff 100644 --- a/boards.cfg +++ b/boards.cfg @@ -288,6 +288,7 @@ nitrogen6s1g arm armv7 nitrogen6x boundar wandboard_dl arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 wandboard_quad arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 wandboard_solo arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 +edm_cf_imx6 arm armv7 edm_cf_imx6 technexion mx6 edm_cf_imx6:IMX_CONFIG=board/technexion/edm_cf_imx6/imximage.cfg,SPL omap3_overo arm armv7 overo - omap3 omap3_pandora arm armv7 pandora - omap3 dig297 arm armv7 dig297 comelit omap3 diff --git a/include/configs/edm_cf_imx6.h b/include/configs/edm_cf_imx6.h new file mode 100644 index 0000000..7bfe8e2 --- /dev/null +++ b/include/configs/edm_cf_imx6.h @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for the Wandboard. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> +#include <asm/sizes.h> + +#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define MACH_TYPE_EDM_CF_IMX6 4257 +#define CONFIG_MACH_TYPE MACH_TYPE_EDM_CF_IMX6 + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_REVISION_TAG + +/* SPL magic */ +#ifdef CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x00908400 +#define CONFIG_SPL_PAD_TO 0x400 +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7" +#define CONFIG_SPL_STACK 0x0091FFB8 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 128 /* offset 64KB */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 700 /* 350 KB */ +#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS*512) + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_SPL_MALLOC_START 0x00916000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 +#endif + +/* Memory map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +/* Set to 64k since we should be able to run on both imx6dl and imx6q */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_MXC_GPIO + +/* debug console */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE + +/* Standard command definition */ +#include <config_cmd_default.h> +/* ... exclude what's not yet supported */ +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_NET + +/* MMC Configuration */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +/* Environment settings */ +#define CONFIG_ENV_SIZE (8 << 10) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (8 * 64 * 1024) +#define CONFIG_SYS_NO_FLASH +/* SPL boot reorders mmc devices so that boot device is 0 -- env is in boot dev */ +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_BOOTDELAY 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw video=mxcfb0:dev=hdmi,1920x1080@60,if=BGR32\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev 0; mmc read $loadaddr 0x800 0x1000; bootm" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 384 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMD_BOOTZ + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H * */ -- 1.8.0.3

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