January 2013 - U-Boot

[U-Boot] [PATCH] powerpc/mpc85xx: Add BSC9132/BSC9232 processor support
by Prabhakar Kushwaha 15 Jan '13

15 Jan '13

The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi(a)freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/Makefile | 2 + arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c | 96 +++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc8xxx/cpu.c | 3 + arch/powerpc/include/asm/config_mpc85xx.h | 15 +++++ arch/powerpc/include/asm/immap_85xx.h | 25 +++++++- arch/powerpc/include/asm/processor.h | 3 + 6 files changed, 142 insertions(+), 2 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 4c2b104..cb1f604 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -85,6 +85,7 @@ COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o COBJS-$(CONFIG_PPC_T4240) += ddr-gen3.o COBJS-$(CONFIG_PPC_B4860) += ddr-gen3.o COBJS-$(CONFIG_BSC9131) += ddr-gen3.o +COBJS-$(CONFIG_BSC9132) += ddr-gen3.o COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o @@ -135,6 +136,7 @@ COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o +COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o COBJS-y += cpu.o COBJS-y += cpu_init.o diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c new file mode 100644 index 0000000..300a4db --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c @@ -0,0 +1,96 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * Author: Prabhakar Kushwaha <prabhakar(a)freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0] = {NONE, NONE, NONE, NONE}, + [1] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [2] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [3] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [4] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [5] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [6] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [7] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [8] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [9] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [10] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [11] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2}, + [12] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [13] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [14] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [15] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [16] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [17] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [18] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [19] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [20] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [21] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [22] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [23] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [24] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [25] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [26] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [27] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [28] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [29] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [30] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [31] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [32] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2}, + [33] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [34] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [35] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [36] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [37] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [38] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [39] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [40] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [41] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [42] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [43] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1}, + [44] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1}, + [45] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1}, + [46] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1}, + [47] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index e8613be..03fd2fb 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -86,6 +86,9 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(B4220, B4220, 0), CPU_TYPE_ENTRY(BSC9130, 9130, 1), CPU_TYPE_ENTRY(BSC9131, 9131, 1), + CPU_TYPE_ENTRY(BSC9132, 9132, 2), + CPU_TYPE_ENTRY(BSC9132, 9132_E, 2), + CPU_TYPE_ENTRY(BSC9232, 9232, 2), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 0b9638b..4b6c172 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -493,6 +493,21 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#elif defined(CONFIG_BSC9132) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 +#define CONFIG_FSL_SDHC_V2_3 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" + #elif defined(CONFIG_PPC_T4240) #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 296b549..ab4abc2 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2150,7 +2150,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 #else -#ifdef CONFIG_BSC9131 +#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 #else #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 @@ -2164,6 +2164,11 @@ typedef struct ccsr_gur { u32 porbmsr; /* POR boot mode status */ #define MPC85xx_PORBMSR_HA 0x00070000 #define MPC85xx_PORBMSR_HA_SHIFT 16 +#define MPC85XX_PORBMSR_ROMLOC_SHIFT 24 +#define PORBMSR_ROMLOC_SPI 0x6 +#define PORBMSR_ROMLOC_SDHC 0x7 +#define PORBMSR_ROMLOC_NAND_2K 0x9 +#define PORBMSR_ROMLOC_NOR 0xf u32 porimpscr; /* POR I/O impedance status & control */ u32 pordevsr; /* POR I/O device status regsiter */ #if defined(CONFIG_P1017) || defined(CONFIG_P1023) @@ -2188,6 +2193,9 @@ typedef struct ccsr_gur { #if defined(CONFIG_P1010) #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 +#elif defined(CONFIG_BSC9132) +#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000 +#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17 #else #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 @@ -2345,6 +2353,10 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003 #endif +#ifdef CONFIG_BSC9132 +#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000 +#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000 +#endif u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ #if defined(CONFIG_P1010) || defined(CONFIG_P1014) #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 @@ -2375,6 +2387,7 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 #define MPC85xx_PMUXCR2_USB 0x00150000 #endif +#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) #if defined(CONFIG_BSC9131) #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000 @@ -2418,8 +2431,9 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004 #define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001 #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002 +#endif u32 pmuxcr3; - +#if defined(CONFIG_BSC9131) #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000 @@ -2434,6 +2448,13 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000 #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000 #define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000 +#endif +#ifdef CONFIG_BSC9132 +#define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00 +#define MPC85xx_PMUXCR3_UART2_SEL 0x00005000 +#define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000 +#define MPC85xx_PMUXCR3_UART3_SEL 0x40000000 +#endif u32 pmuxcr4; #else u8 res6[8]; diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 19fe250..ae5e154 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1113,6 +1113,9 @@ #define SVR_9130 0x860001 #define SVR_9131 0x860000 +#define SVR_9132 0x861000 +#define SVR_9132_E 0x861800 +#define SVR_9232 0x861400 #define SVR_Unknown 0xFFFFFF -- 1.7.9.5

2 1

[U-Boot] [PATCH] powerpc/85xx: Add BSC9132QDS support
by Prabhakar Kushwaha 15 Jan '13

15 Jan '13

BSC9132QDS is a Freescale reference design board for BSC9132 SoC. BSC9132 SOC is an integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. BSC9132QDS Overview -------------------- 2Gbyte DDR3 (on board DDR), Dual Ranki 32Mbyte 16bit NOR flash 128Mbyte 2K page size NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory SD slot USB-ULPI eTSEC1: Connected to SGMII PHY eTSEC2: Connected to SGMII PHY PCIe CPRI SerDes I2C RTC DUART interface: supports one UARTs up to 115200 bps for console display Apart from the above it also consists various peripherals to support DSP functionalities. This patch adds support for mainly Power side functionalities and peripherals Signed-off-by: Naveen Burmi <NaveenBurmi(a)freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- MAINTAINERS | 4 + board/freescale/bsc9132qds/Makefile | 52 +++ board/freescale/bsc9132qds/README | 150 +++++++ board/freescale/bsc9132qds/bsc9132qds.c | 406 +++++++++++++++++++ board/freescale/bsc9132qds/ddr.c | 209 ++++++++++ board/freescale/bsc9132qds/law.c | 35 ++ board/freescale/bsc9132qds/tlb.c | 92 +++++ boards.cfg | 6 + include/configs/BSC9132QDS.h | 667 +++++++++++++++++++++++++++++++ 9 files changed, 1621 insertions(+) create mode 100644 board/freescale/bsc9132qds/Makefile create mode 100644 board/freescale/bsc9132qds/README create mode 100644 board/freescale/bsc9132qds/bsc9132qds.c create mode 100644 board/freescale/bsc9132qds/ddr.c create mode 100644 board/freescale/bsc9132qds/law.c create mode 100644 board/freescale/bsc9132qds/tlb.c create mode 100644 include/configs/BSC9132QDS.h diff --git a/MAINTAINERS b/MAINTAINERS index 28c052d..d3ed390 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27,6 +27,10 @@ Poonam Aggrwal <poonam.aggrwal(a)freescale.com> BSC9131RDB BSC9131 +Naveen Burmi <NaveenBurmi(a)freescale.com> + + BSC9132QDS BSC9132 + Greg Allen <gallen(a)arlut.utexas.edu> UTX8245 MPC8245 diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile new file mode 100644 index 0000000..267400b --- /dev/null +++ b/board/freescale/bsc9132qds/Makefile @@ -0,0 +1,52 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/bsc9132qds/README b/board/freescale/bsc9132qds/README new file mode 100644 index 0000000..4a3dbfe --- /dev/null +++ b/board/freescale/bsc9132qds/README @@ -0,0 +1,150 @@ +Overview +-------- + The BSC9132 is a highly integrated device that targets the evolving + Microcell, Picocell, and Enterprise-Femto base station market subsegments. + + The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 + core technologies with MAPLE-B2P baseband acceleration processing elements + to address the need for a high performance, low cost, integrated solution + that handles all required processing layers without the need for an + external device except for an RF transceiver or, in a Micro base station + configuration, a host device that handles the L3/L4 and handover between + sectors. + + The BSC9132 SoC includes the following function and features: + - Power Architecture subsystem including two e500 processors with + 512-Kbyte shared L2 cache + - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 + cache + - 32 Kbyte of shared M3 memory + - The Multi Accelerator Platform Engine for Pico BaseStation Baseband + Processing (MAPLE-B2P) + - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including + ECC), up to 1333 MHz data rate + - Dedicated security engine featuring trusted boot + - Two DMA controllers + - OCNDMA with four bidirectional channels + - SysDMA with sixteen bidirectional channels + - Interfaces + - Four-lane SerDes PHY + - PCI Express controller complies with the PEX Specification-Rev 2.0 + - Two Common Public Radio Interface (CPRI) controller lanes + - High-speed USB 2.0 host and device controller with ULPI interface + - Enhanced secure digital (SD/MMC) host controller (eSDHC) + - Antenna interface controller (AIC), supporting four industry + standard JESD207/four custom ADI RF interfaces + - ADI lanes support both full duplex FDD support & half duplex TDD + - Universal Subscriber Identity Module (USIM) interface that + facilitates communication to SIM cards or Eurochip pre-paid phone + cards + - Two DUART, two eSPI, and two I2C controllers + - Integrated Flash memory controller (IFC) + - GPIO + - Sixteen 32-bit timers + +The SC3850 core subsystem consists of the following: + - 32 KB, 8-way, level 1 instruction cache (L1 ICache) + - 32 KB, 8-way, level 1 data cache (L1 DCache) + - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory) + - Memory management unit (MMU) + - Global interrupt controller ( GIC) + - Debug and profiling unit (DPU) + - Two 32-bit quad timers + +BSC9132QDS board Overview +------------------------- + 2Gbyte DDR3 (on board DDR), Dual Ranki + 32Mbyte 16bit NOR flash + 128Mbyte 2K page size NAND Flash + 256 Kbit M24256 I2C EEPROM + 128 Mbit SPI Flash memory + SD slot + USB-ULPI + eTSEC1: Connected to SGMII PHY + eTSEC2: Connected to SGMII PHY + PCIe + CPRI + SerDes + I2C RTC + DUART interface: supports one UARTs up to 115200 bps for console display + +Frequency Combinations Supported +-------------------------------- +Core MHz/CCB MHz/DDR(MT/s) +1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz + (SYSCLK = 100MHz, DDRCLK = 100MHz) +2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz + (SYSCLK = 100MHz, DDRCLK = 133MHz) + +Boot Methods Supported +----------------------- +1. NOR Flash +2. NAND Flash +3. SD Card +4. SPI flash + +Default Boot Method +-------------------- +NOR boot + +Building U-boot +-------------- +To build the u-boot for BSC9132QDS: +1. NOR Flash + make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK + make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK +2. NAND Flash : It is currently not supported +3. SPI Flash + make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK + make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK +4. SD Card + make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK + make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK + +Memory map +----------- + 0x0000_0000 0x7FFF_FFFF DDR 2G cacheable + 0x8000_0000 0x8FFF_FFFF NOR Flash 256M + 0x9000_0000 0x9FFF_FFFF PCIe Memory 256M + 0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M + 0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M + 0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M + 0xC000_0000 0xC000_7FFF M3 Memory 32K + 0xC001_0000 0xC001_FFFF PCI Express I/O 64K + 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M + 0xC1F0_0000 0xC1F7_FFFF PA SRAM Region 0 512K + 0xC1F8_0000 0xC1FB_FFFF PA SRAM Region 1 512K + 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K + 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K + 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M + 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M + 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M + +Flashing Images +--------------- +To place a new u-boot image in the NAND flash and then boot +with that new image temporarily, use this: + tftp 1000000 u-boot-nand.bin + nand erase 0 100000 + nand write 1000000 0 100000 + reset + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts + +Booting Linux +------------- +Place a linux uImage in the TFTP disk area. + + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp c00000 bsc9132qds.dtb + bootm 1000000 2000000 c00000 diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c new file mode 100644 index 0000000..9f0eaa5 --- /dev/null +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -0,0 +1,406 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/io.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <mmc.h> +#include <netdev.h> +#include <asm/fsl_ifc.h> +#include <hwconfig.h> +#include <i2c.h> +#include <asm/fsl_ddr_sdram.h> + +#ifdef CONFIG_PCI +#include <pci.h> +#include <asm/fsl_pci.h> +#endif + +#include "../common/qixis.h" +DECLARE_GLOBAL_DATA_PTR; + + +int board_early_init_f(void) +{ + struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; + + setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); + + return 0; +} + +void board_config_serdes_mux(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + + switch (srds_cfg) { + /* PEX(1) PEX(2) CPRI 2 CPRI 1 */ + case 1: + case 2: + case 3: + case 4: + case 5: + case 22: + case 23: + case 24: + case 25: + case 26: + QIXIS_WRITE_I2C(brdcfg[4], 0x03); + break; + + /* PEX(1) PEX(2) SGMII1 CPRI 1 */ + case 6: + case 7: + case 8: + case 9: + case 10: + case 27: + case 28: + case 29: + case 30: + case 31: + QIXIS_WRITE_I2C(brdcfg[4], 0x01); + break; + + /* PEX(1) PEX(2) SGMII1 SGMII2 */ + case 11: + case 32: + QIXIS_WRITE_I2C(brdcfg[4], 0x00); + break; + + /* PEX(1) SGMII2 CPRI 2 CPRI 1 */ + case 12: + case 13: + case 14: + case 15: + case 16: + case 33: + case 34: + case 35: + case 36: + case 37: + QIXIS_WRITE_I2C(brdcfg[4], 0x07); + break; + + /* PEX(1) SGMII2 SGMII1 CPRI 1 */ + case 17: + case 18: + case 19: + case 20: + case 21: + case 38: + case 39: + case 40: + case 41: + case 42: + QIXIS_WRITE_I2C(brdcfg[4], 0x05); + break; + + /* SGMII1 SGMII2 CPRI 2 CPRI 1 */ + case 43: + case 44: + case 45: + case 46: + case 47: + QIXIS_WRITE_I2C(brdcfg[4], 0x0F); + break; + + + default: + break; + } +} + +int board_early_init_r(void) +{ +#ifndef CONFIG_SYS_NO_FLASH + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_64M, 1); + + set_tlb(1, flashbase + 0x4000000, + CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel+1, BOOKE_PAGESZ_64M, 1); +#endif + board_config_serdes_mux(); + return 0; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} +#endif /* ifdef CONFIG_PCI */ + +int checkboard(void) +{ + struct cpu_type *cpu; + u8 sw; + + cpu = gd->cpu; + printf("Board: %sQDS\n", cpu->name); + + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n", + QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver)); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + printf("IFC chip select:"); + switch (sw) { + case 0: + printf("NOR\n"); + break; + case 2: + printf("Promjet\n"); + break; + case 4: + printf("NAND\n"); + break; + default: + printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); + break; + } + + return 0; +} + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; + +#endif + +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &mdio_info); + tsec_eth_init(bis, tsec_info, num); + + #ifdef CONFIG_PCI + pci_eth_init(bis); + #endif + + return 0; +} +#endif + +#define USBMUX_SEL_MASK 0xc0 +#define USBMUX_SEL_UART2 0xc0 +#define USBMUX_SEL_USB 0x40 +#define SPIMUX_SEL_UART3 0x80 +#define GPS_MUX_SEL_GPS 0x40 + +#define TSEC_1588_CLKIN_MASK 0x03 +#define CON_XCVR_REF_CLK 0x00 + +int misc_init_r(void) +{ + u8 val; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 porbmsr = in_be32(&gur->porbmsr); + u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf; + + /*Configure 1588 clock-in source from RF Card*/ + val = QIXIS_READ_I2C(brdcfg[5]); + QIXIS_WRITE_I2C(brdcfg[5], + (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK); + + if (hwconfig("uart2") && hwconfig("usb1")) { + printf("UART2 and USB cannot work together on the board\n"); + printf("Remove one from hwconfig and reset\n"); + } else { + if (hwconfig("uart2")) { + val = QIXIS_READ_I2C(brdcfg[5]); + QIXIS_WRITE_I2C(brdcfg[5], + (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2); + clrbits_be32(&gur->pmuxcr3, + MPC85xx_PMUXCR3_USB_SEL_MASK); + setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL); + } else { + /* By default USB should be selected. + * Programming FPGA to select USB. */ + val = QIXIS_READ_I2C(brdcfg[5]); + QIXIS_WRITE_I2C(brdcfg[5], + (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB); + } + + } + + if (hwconfig("sim")) { + if (romloc == PORBMSR_ROMLOC_NAND_2K || + romloc == PORBMSR_ROMLOC_NOR || + romloc == PORBMSR_ROMLOC_SPI) { + + val = QIXIS_READ_I2C(brdcfg[3]); + QIXIS_WRITE_I2C(brdcfg[3], val|0x10); + clrbits_be32(&gur->pmuxcr, + MPC85xx_PMUXCR0_SIM_SEL_MASK); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL); + } + } + + if (hwconfig("uart3")) { + if (romloc == PORBMSR_ROMLOC_NAND_2K || + romloc == PORBMSR_ROMLOC_NOR || + romloc == PORBMSR_ROMLOC_SDHC) { + + /* UART3 and SPI1 (Flashes) are muxed together */ + val = QIXIS_READ_I2C(brdcfg[3]); + QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3)); + clrbits_be32(&gur->pmuxcr3, + MPC85xx_PMUXCR3_UART3_SEL_MASK); + setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL); + + /* MUX to select UART3 connection to J24 header + * or to GPS */ + val = QIXIS_READ_I2C(brdcfg[6]); + if (hwconfig("gps")) + QIXIS_WRITE_I2C(brdcfg[6], + (val | GPS_MUX_SEL_GPS)); + else + QIXIS_WRITE_I2C(brdcfg[6], + (val & ~(GPS_MUX_SEL_GPS))); + } + } + return 0; +} + +void fdt_del_node_compat(void *blob, const char *compatible) +{ + int err; + int off = fdt_node_offset_by_compatible(blob, -1, compatible); + if (off < 0) { + printf("WARNING: could not find compatible node %s: %s.\n", + compatible, fdt_strerror(off)); + return; + } + err = fdt_del_node(blob, off); + if (err < 0) { + printf("WARNING: could not remove %s: %s.\n", + compatible, fdt_strerror(err)); + } +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + struct cpu_type *cpu; + + cpu = gd->cpu; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + #if defined(CONFIG_PCI) + FT_FSL_PCI_SETUP; + #endif + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 porbmsr = in_be32(&gur->porbmsr); + u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf; + + if (!(hwconfig("uart2") && hwconfig("usb1"))) { + /* If uart2 is there in hwconfig remove usb node from + * device tree */ + + if (hwconfig("uart2")) { + /* remove dts usb node */ + fdt_del_node_compat(blob, "fsl-usb2-dr"); + } else { + fdt_fixup_dr_usb(blob, bd); + fdt_del_node_and_alias(blob, "serial2"); + } + } + + if (hwconfig("uart3")) { + if (romloc == PORBMSR_ROMLOC_NAND_2K || + romloc == PORBMSR_ROMLOC_NOR || + romloc == PORBMSR_ROMLOC_SDHC) + /* Delete SPI node from the device tree */ + fdt_del_node_and_alias(blob, "spi1"); + } else + fdt_del_node_and_alias(blob, "serial3"); + + if (hwconfig("sim")) { + if (romloc == PORBMSR_ROMLOC_NAND_2K || + romloc == PORBMSR_ROMLOC_NOR || + romloc == PORBMSR_ROMLOC_SPI) { + + /* remove dts sdhc node */ + fdt_del_node_compat(blob, "fsl,esdhc"); + } else if (romloc == PORBMSR_ROMLOC_SDHC) { + + /* remove dts sim node */ + fdt_del_node_compat(blob, "fsl,sim-v1.0"); + printf("SIM & SDHC can't work together on the board"); + printf("\nRemove sim from hwconfig and reset\n"); + } + } +} +#endif diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c new file mode 100644 index 0000000..946ad19 --- /dev/null +++ b/board/freescale/bsc9132qds/ddr.c @@ -0,0 +1,209 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/processor.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include <asm/io.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_DDR_RAW_TIMING + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {750, 850, &ddr_cfg_regs_800}, + {1060, 1333, &ddr_cfg_regs_1333}, + {0, 0, NULL} +}; + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +phys_size_t fixed_sdram(void) +{ + int i; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + ulong ddr_freq, ddr_freq_mhz; + + ddr_freq = get_ddr_freq(0); + ddr_freq_mhz = ddr_freq / 1000000; + + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { + if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && + (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { + memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, + sizeof(ddr_cfg_regs)); + break; + } + } + + if (fixed_ddr_parm_0[i].max_freq == 0) + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, + LAW_TRGT_IF_DDR_1) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + + return ddr_size; +} + +#else /* CONFIG_SYS_DDR_RAW_TIMING */ +/* Micron MT41J512M8_187E */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1870, + .caslat_X = 0x1e << 4, /* 5,6,7,8 */ + .tAA_ps = 13125, + .tWR_ps = 15000, + .tRCD_ps = 13125, + .tRRD_ps = 7500, + .tRP_ps = 13125, + .tRAS_ps = 37500, + .tRC_ps = 50625, + .tRFC_ps = 160000, + .tWTR_ps = 7500, + .tRTP_ps = 7500, + .refresh_rate_ps = 7800000, + .tFAW_ps = 37500, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + int i; + popts->clk_adjust = 6; + popts->cpo_override = 0x1f; + popts->write_data_delay = 2; + popts->half_strength_driver_enable = 1; + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x8; + popts->trwt_override = 1; + popts->trwt = 0; + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} + +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ diff --git a/board/freescale/bsc9132qds/law.c b/board/freescale/bsc9132qds/law.c new file mode 100644 index 0000000..dc23658 --- /dev/null +++ b/board/freescale/bsc9132qds/law.c @@ -0,0 +1,35 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { +#ifndef CONFIG_SYS_NO_FLASH + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC), +#endif + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c new file mode 100644 index 0000000..0e4545f --- /dev/null +++ b/board/freescale/bsc9132qds/tlb.c @@ -0,0 +1,92 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR (PA) */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 3, BOOKE_PAGESZ_64M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000, + CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 4, BOOKE_PAGESZ_64M, 1), + +#if defined(CONFIG_SYS_RAMBOOT) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), +#endif + +#ifdef CONFIG_PCI + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_64K, 1), +#endif + + /* *I*G - Board FPGA */ + SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_256K, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_1M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 91504c0..4691a2a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -854,6 +854,12 @@ P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 P5040DS powerpc mpc85xx corenet_ds freescale BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH +BSC9132QDS_NOR_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100 +BSC9132QDS_NOR_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133 +BSC9132QDS_SDCARD_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100 +BSC9132QDS_SDCARD_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133 +BSC9132QDS_SPIFLASH_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 +BSC9132QDS_SPIFLASH_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h new file mode 100644 index 0000000..431c686 --- /dev/null +++ b/include/configs/BSC9132QDS.h @@ -0,0 +1,667 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * BSC9132 QDS board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_BSC9132QDS +#define CONFIG_BSC9132 +#endif + +#define CONFIG_MISC_INIT_R + +#ifdef CONFIG_SDCARD +#define CONFIG_RAMBOOT_SDCARD +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif +#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x8ff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + + +/* High Level Configuration Options */ +#define CONFIG_BOOKE /* BOOKE */ +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_MPC85xx +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ + +#define CONFIG_PCI /* Enable PCI/PCIE */ +#if defined(CONFIG_PCI) +#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI + +#define CONFIG_E1000 /* E1000 pci Ethernet card*/ + +/* + * PCI Windows + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "PCIe Slot" +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif + +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_TSEC_ENET /* ethernet */ + +#if defined(CONFIG_SYS_CLK_100_DDR_100) +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#elif defined(CONFIG_SYS_CLK_100_DDR_133) +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 133000000 +#endif + +#define CONFIG_MP + +#define CONFIG_HWCONFIG +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* enable branch predition */ + +#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x01ffffff + +/* DDR Setup */ +#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ +#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ +#define CONFIG_FSL_DDR_INTERACTIVE + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_SYS_SDRAM_SIZE (1024) +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +/* DDR3 Controller Settings */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F +#define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 +#define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 +#define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F + +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 +#define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 +#define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 +#define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 + +#define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 +#define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 +#define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 +#define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 + +#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 +#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 +#define CONFIG_SYS_DDR_MODE_1_800 0x40461520 +#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 +#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 + +#define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 +#define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 +#define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 +#define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 +#define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 +#define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 +#define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 +#define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 +#define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 + +/*FIXME: the following params are constant w.r.t diff freq +combinations. this should be removed later +*/ +#if CONFIG_DDR_CLK_FREQ == 100000000 +#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 +#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 +#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 +#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 +#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 +#elif CONFIG_DDR_CLK_FREQ == 133000000 +#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 +#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 +#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 +#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 +#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 +#else +#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 +#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 +#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 +#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 +#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 +#endif + + +/* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT + +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR + +/* + * IFC Definitions + */ +/* NOR Flash on IFC */ +#define CONFIG_SYS_FLASH_BASE 0x88000000 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ + +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_NOR_CSPR 0x88000101 +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) +/* NOR Flash Timing Params */ + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ + | FTIM0_NOR_TEADC(0x03) \ + | FTIM0_NOR_TAVDS(0x00) \ + | FTIM0_NOR_TEAHC(0x0f)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ + | FTIM1_NOR_TRAD_NOR(0x09) \ + | FTIM1_NOR_TSEQRAD_NOR(0x09)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ + | FTIM2_NOR_TCH(0x4) \ + | FTIM2_NOR_TWPH(0x7) \ + | FTIM2_NOR_TWP(0x1e)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* CFI for NOR Flash */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +/* NAND Flash on IFC */ +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +/* NAND Flash Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ + | FTIM0_NAND_TWP(0x05) \ + | FTIM0_NAND_TWCHT(0x02) \ + | FTIM0_NAND_TWH(0x04)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ + | FTIM1_NAND_TWBE(0x1e) \ + | FTIM1_NAND_TRR(0x07) \ + | FTIM1_NAND_TRP(0x05)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ + | FTIM2_NAND_TREH(0x04) \ + | FTIM2_NAND_TWHRE(0x11)) +#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) + +#define CONFIG_SYS_NAND_DDR_LAW 11 + +/* NAND */ +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#define CONFIG_FSL_QIXIS +#ifdef CONFIG_FSL_QIXIS +#define CONFIG_SYS_FPGA_BASE 0xffb00000 +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_BASE CONFIG_SYS_FPGA_BASE +#define QIXIS_LBMAP_SWITCH 9 +#define QIXIS_LBMAP_MASK 0x07 +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_RST_CTL_RESET 0x83 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 + +#define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE + +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR2 0x0 +/* CPLD Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS2_FTIM3 0x0 +#endif + +/* Set up IFC registers for boot location NOR/NAND */ +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER /* hush parser */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400800 /* I2C speed and slave address*/ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* I2C EEPROM */ +#define CONFIG_ID_EEPROM +#ifdef CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#endif +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_BUS_NUM 0 + +/* enable read and write access to EEPROM */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* I2C FPGA */ +#define CONFIG_I2C_FPGA +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 + +#define CONFIG_RTC_DS3231 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * SPI interface will not be available in case of NAND boot SPI CS0 will be + * used for SLIC + */ +/* eSPI - Enhanced SPI */ +#define CONFIG_FSL_ESPI /* SPI */ +#ifdef CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +/* TBI PHY configuration for SGMII mode */ +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + +#endif /* CONFIG_TSEC_ENET */ + +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_FSL_ESDHC +#define CONFIG_GENERIC_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#endif + +#define CONFIG_USB_EHCI /* USB */ +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#define CONFIG_HAS_FSL_DR_USB +#endif + +/* + * Environment + */ +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif +#else +#define CONFIG_ENV_IS_IN_FLASH +#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 +#define CONFIG_ENV_ADDR 0xfff80000 +#else +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#endif +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq:1ms ticks */ + + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_HOSTNAME BSC9132qds +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" + +#define CONFIG_BAUDRATE 115200 + +#ifdef CONFIG_SDCARD +#define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" +#else +#define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ + "loadaddr=1000000\0" \ + "bootfile=uImage\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=rootfs.ext2.gz.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=bsc9132qds.dtb\0" \ + "bdev=sda1\0" \ + CONFIG_DEF_HWCONFIG\ + "othbootargs=mem=880M ramdisk_size=600000 " \ + "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ + "isolcpus=0\0" \ + "usbext2boot=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "usb start;" \ + "ext2load usb 0:4 $loadaddr $bootfile;" \ + "ext2load usb 0:4 $fdtaddr $fdtfile;" \ + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + "debug_halt_off=mw ff7e0e30 0xf0000000;" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "usb start;" \ + "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ + "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#endif /* __CONFIG_H */ -- 1.7.9.5

1 0

[U-Boot] [PATCH 1/3] pxa: Add support for board specific reset function
by Lukasz Dalek 15 Jan '13

15 Jan '13

Some boards have its own way to reset board. This patch adds support for board_reset() function which is called from reset_cpu() to do board specific actions before/instead main reset_cpu() actions. Signed-off-by: Lukasz Dalek <luk0104(a)gmail.com> --- arch/arm/cpu/pxa/pxa2xx.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c index 09e8177..5520f4f 100644 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -284,12 +284,19 @@ void i2c_clk_enable(void) writel(readl(CKEN) | CKEN14_I2C, CKEN); } +void __attribute__((weak)) board_reset(void) +{ + /* do nothing */ +} + void reset_cpu(ulong ignored) __attribute__((noreturn)); void reset_cpu(ulong ignored) { uint32_t tmp; + board_reset(); + setbits_le32(OWER, OWER_WME); tmp = readl(OSCR); -- 1.7.8.6

4 9

[U-Boot] [RFC PATCH 0/4] RFC: FIT images and device tree on x86
by Simon Glass 15 Jan '13

15 Jan '13

This little series adds support for booting FITs on x86. A FIT is a single file that can contain a kernel, device tree and ramdisk. This is a bit of an experiment, and is work in progress. I would like to get feedback on the approach. x86 kernels require a setup.bin file to boot. Rather than try to pack this into the image in a clever way, this series just adds it as another image in the FIT. At present compression is not supported for the setup binary. The kernel image can be compressed using FIT's normal compression options, such as bzip2 and lzo. U-Boot will decompress it as part of the 'bootm' command. More work is needed to make this implementation also support a zImage (which contains a setup.bin and a compressed kernel in a single image), and to pass the correct device tree binary to the kernel. This series builds on the image and FIT code improvements that were done for verified boot. The full series is available at: http://git.denx.de/u-boot-x86.git in branch 'setup'. Simon Glass (4): x86: Enable LMB and RAMDISK_HIGH by default x86: Rewrite bootm.c to make it similar to ARM x86: Allow cmdline setup in setup_zimage() to be optional x86: Support loading kernel setup from a FIT arch/x86/include/asm/bootm.h | 24 +++++ arch/x86/include/asm/config.h | 2 + arch/x86/lib/bootm.c | 152 +++++++++++++++++++++++++-------- arch/x86/lib/zimage.c | 37 +++----- common/cmd_bootm.c | 22 +++++- common/image-fit.c | 20 +++++ common/image.c | 11 +++ doc/uImage.FIT/kernel.its | 50 +++++++++++ doc/uImage.FIT/source_file_format.txt | 23 +++-- include/bootstage.h | 3 + include/image.h | 13 +++ 11 files changed, 285 insertions(+), 72 deletions(-) create mode 100644 arch/x86/include/asm/bootm.h -- 1.7.7.3

2 5

[U-Boot] Pull request: u-boot-arm/master
by Albert ARIBAUD 15 Jan '13

15 Jan '13

Hello Tom, The following changes since commit fd70aa41468be4324275910f85578cb5be6a0439: m68k/lib: fix serial driver relocation (2013-01-11 14:41:14 -0700) are available in the git repository at: git://git.denx.de/u-boot-arm.git master for you to fetch changes up to a17617d6553369ba72c080128ed8d0b0c33dfc89: Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' (2013-01-14 17:00:02 +0100) ---------------------------------------------------------------- Ajay Kumar (8): EXYNOS5: Add support for FIMD and DP EXYNOS5: Change parent clock of FIMD to MPLL EXYNOS: Add dummy definition to fix compilation dependency on CONFIG_EXYNOS_MIPI_DSIM video: Modify exynos_fimd driver to support LCD console EXYNOS5: Make all display related code dependent on CONFIG_LCD EXYNOS5: Enable console multiplexing in u-boot video: exynos_dp: Remove unused variable disp_info video: exynos_fb: Make a call to draw_logo only when CONFIG_CMD_BMP is selected Albert ARIBAUD (2): Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' Bo Shen (1): arm: at91sam9x5: add dataflash boot support Chander Kashyap (4): EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12 EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12 EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequency Fabio Estevam (4): mx6: Add workaround for ARM errata mx53loco: Add support for SEIKO 4.3'' WVGA panel mx6qsabresd: Fix booting the kernel from SDHC3 mx51evk: Add DVI output support Hatim RV (5): EXYNOS5: FDT: add initial dts file for EXYNOS5250, SMDK5250 fdt: exynos5: Add DT node definition for SROM and SMSC9215 exynos5: Add DT based driver for SMC911X ethernet exynos5: config: Rename the smdk5250.h to exynos5250-dt.h SMDK5250: config: Add configuration file for SMDK5250 board Jaehoon Chung (2): Exynos: clock: support get_mmc_clk for exynos Exynos: clock: add CLK_DIV_FSYS3 at set_mmc_clk Otavio Salvador (6): mx6qsabrelite: Use tabs to environment setting mx28evk: We shouldn't hardcode a rootfs filesystem type mx28evk: Add support to dynamically choose between fdt use or not mx53loco: Add support to dynamically choose between fdt use or not mx6qsabrelite: Add support to dynamically choose between fdt use or not mx6qsabre{auto, sd}: Add support to dynamically choose between fdt use or not Piotr Wilczek (1): arm:exynos4:pinmux: Modify the gpio function for mmc Rajeshwari Shinde (23): EXYNOS5: FDT: Add I2C device node data EXYNOS5 : FDT: Add Aliases for I2C device FDT: Add compatible string for I2C EXYNOS5: FDT : Decode peripheral id I2C: Driver changes for FDT support SMDK5250: Initialise I2C using FDT EXYNOS5: FDT: Add sound device node data EXYNOS5: FDT: Add sound and codec device node EXYNOS5: FDT: Add compatible strings for sound Sound: Add FDT support to driver Sound: WM8994: Add FDT support to codec Sound: Add FDT support to CMD. EXYNOS5: FDT: Add compatible strings for SPI EXYNOS5 : FDT: Add Aliases for SPI device EXYNOS5: FDT: Add SPI device node data SPI: EXYNOS: Add FDT support to driver. EHCI: Exynos: Add fdt support EXYNOS5: Add device node for USB. EXYNOS5: FDT: Add compatible strings for USB EXYNOS5: FDT: Add compatible strings for PMIC EXYNOS5: Add device node for PMIC PMIC: MAX77686: Add FDT Support I2C: S3C24X0: Resolve build error for VCMA9 Troy Kisky (1): mx31/mx35/mx51/mx53/mx6: add watchdog Vivek Gautam (1): SMDK5250: Enable VBus for USB 2.0 controller Łukasz Majewski (2): spl:falcon:trats Update Trats default board configuration file to support FALCON MODE video:cache:fix: Enable dcache flush at LCD subsystem for Exynos based boards arch/arm/cpu/arm1136/mx31/timer.c | 39 ---- arch/arm/cpu/arm1136/mx35/generic.c | 6 - arch/arm/cpu/armv7/exynos/clock.c | 272 +++++++++++++++++++++- arch/arm/cpu/armv7/exynos/pinmux.c | 74 ++++++ arch/arm/cpu/armv7/mx6/lowlevel_init.S | 10 + arch/arm/dts/exynos5250.dtsi | 154 ++++++++++++ arch/arm/imx-common/cpu.c | 5 - arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/clock.h | 276 ++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 48 +++- arch/arm/include/asm/arch-exynos/dp_info.h | 2 + arch/arm/include/asm/arch-exynos/gpio.h | 85 +++++++ arch/arm/include/asm/arch-exynos/mipi_dsim.h | 7 + arch/arm/include/asm/arch-exynos/periph.h | 33 +-- arch/arm/include/asm/arch-exynos/pinmux.h | 8 + arch/arm/include/asm/arch-exynos/sromc.h | 18 ++ arch/arm/include/asm/arch-mx31/clock.h | 2 - arch/arm/include/asm/arch-mx31/imx-regs.h | 13 +- arch/arm/include/asm/arch-mx35/imx-regs.h | 11 +- arch/arm/include/asm/arch-mx5/imx-regs.h | 10 - board/davedenx/qong/qong.c | 9 +- board/freescale/mx31pdk/mx31pdk.c | 9 +- board/freescale/mx51evk/mx51evk.c | 2 - board/freescale/mx51evk/mx51evk_video.c | 39 +++- board/freescale/mx53loco/mx53loco.c | 2 - board/freescale/mx53loco/mx53loco_video.c | 38 ++- board/hale/tt01/tt01.c | 2 +- board/samsung/dts/exynos5250-smdk5250.dts | 69 ++++++ board/samsung/smdk5250/smdk5250.c | 237 +++++++++++++++---- board/samsung/trats/trats.c | 2 +- boards.cfg | 1 + common/cmd_sound.c | 2 +- doc/README.watchdog | 29 +++ doc/device-tree-bindings/exynos/isp-spi.txt | 22 ++ doc/device-tree-bindings/exynos/sound.txt | 27 +++ drivers/i2c/s3c24x0_i2c.c | 85 ++++++- drivers/i2c/s3c24x0_i2c.h | 7 + drivers/power/pmic/pmic_max77686.c | 37 ++- drivers/sound/sound.c | 171 ++++++++------ drivers/sound/wm8994.c | 74 +++++- drivers/sound/wm8994.h | 6 +- drivers/spi/exynos_spi.c | 96 +++++++- drivers/usb/host/ehci-exynos.c | 92 +++++++- drivers/video/exynos_dp.c | 2 - drivers/video/exynos_fb.c | 7 + drivers/video/exynos_fimd.c | 12 +- drivers/watchdog/Makefile | 3 + drivers/watchdog/imx_watchdog.c | 66 ++++++ include/configs/at91sam9x5ek.h | 10 + include/configs/exynos5250-dt.h | 321 ++++++++++++++++++++++++++ include/configs/mx28evk.h | 47 +++- include/configs/mx31pdk.h | 1 + include/configs/mx53loco.h | 44 +++- include/configs/mx6qsabre_common.h | 43 +++- include/configs/mx6qsabreauto.h | 1 + include/configs/mx6qsabrelite.h | 101 +++++--- include/configs/mx6qsabresd.h | 3 +- include/configs/qong.h | 1 + include/configs/smdk5250.h | 278 +--------------------- include/configs/trats.h | 45 +++- include/fdtdec.h | 9 + include/i2c.h | 26 +++ include/sound.h | 4 +- include/watchdog.h | 1 + lib/fdtdec.c | 9 + 65 files changed, 2558 insertions(+), 608 deletions(-) create mode 100644 arch/arm/dts/exynos5250.dtsi create mode 100644 board/samsung/dts/exynos5250-smdk5250.dts create mode 100644 doc/README.watchdog create mode 100644 doc/device-tree-bindings/exynos/isp-spi.txt create mode 100644 doc/device-tree-bindings/exynos/sound.txt create mode 100644 drivers/watchdog/imx_watchdog.c create mode 100644 include/configs/exynos5250-dt.h Amicalement, -- Albert.

2 2

[U-Boot] Pull request: u-boot-video/master
by Anatolij Gustschin 14 Jan '13

14 Jan '13

Hello Tom, The following changes since commit fd70aa41468be4324275910f85578cb5be6a0439: m68k/lib: fix serial driver relocation (2013-01-11 14:41:14 -0700) are available in the git repository at: git://git.denx.de/u-boot-video.git master Nikita Kiryanov (1): lcd: restore ability to display 8 bpp BMPs on 16 bpp LCDs Wolfgang Denk (1): VIDEO: better document the correct use of CONFIG_FB_ADDR README | 11 +++++++---- common/lcd.c | 2 +- 2 files changed, 8 insertions(+), 5 deletions(-) Please pull. Thanks! Anatolij

2 1

[U-Boot] Pull request: u-boot-staging
by Anatolij Gustschin 14 Jan '13

14 Jan '13

Hello Tom, The following changes since commit fd70aa41468be4324275910f85578cb5be6a0439: m68k/lib: fix serial driver relocation (2013-01-11 14:41:14 -0700) are available in the git repository at: git://git.denx.de/u-boot-staging.git agust(a)denx.de Peter Meerwald (1): twl4030: fix 'could could' in error messages drivers/power/twl4030.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Please pull. Thanks! Anatolij

2 1

[U-Boot] Limit on length of U_BOOT_VERSION_STRING for mpc85xx
by Steve Heckman 14 Jan '13

14 Jan '13

I was wondering if there was a limit on the size of the version string U_BOOT_VERSION_STRING in start.S. There are 256 bytes available for the Magic Number, version_string (U_BOOT_VERSION_STRING) and _start_cont code. We want to put clearcase build view information in as part of the version_string, but were wondering if there were length restrictions. Thanks, Steve Heckman Google/Motorola

1 1

[U-Boot] [RFC]: always relocate u-boot before the framebuffer
by Jeroen Hofstee 14 Jan '13

14 Jan '13

Hi All, Currently CONFIG_FB_ADDR can be set to specify the location of the frame buffer. Since Linux places the frame buffer at the end of the RAM, it is nice to place it at the same position so the u-boot to linux transition can be made flicker free, by preserving the frame buffer. However u-boot and it's heap prefer to locate themselves at the end of the RAM as well and there is nothing which prevents them to overlap. While this can be set/calculated manually, it would be nicer if the relocation would never take place to the region occupied by the frame buffer. A simple way to do so is to locate u-boot before the frame buffer, like it is already done when the frame buffer address is not set. Currently there are 2 boards using the CONFIG_FB_ADDR and CONFIG_LCD on arm (trats, mimc200). Would it cause any problem to relocate u-boot below the frame buffer on these boards? Regards, Jeroen proposed patch: diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index e0cb635..4d0fc3c 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -371,9 +371,10 @@ void board_init_f(ulong bootflag) gd->fb_base = CONFIG_FB_ADDR; #else /* reserve memory for LCD display (always full pages) */ - addr = lcd_setmem(addr); - gd->fb_base = addr; + gd->fb_base = lcd_setmem(addr); #endif /* CONFIG_FB_ADDR */ + /* always continue placement below the frame buffer to not overlap */

6 16

[U-Boot] [PATCH] lcd: restore ability to display 8 bpp BMPs on 16 bpp LCDs
by Nikita Kiryanov 14 Jan '13

14 Jan '13

Commit fb6a9aab7ae78c (LCD: display 32bpp decompressed bitmap image) broke the check that allowed U-Boot to display 8 bpp BMPs on a 16 bpp LCD screen, effectively turning this feature off. Restore this feature by changing the check back to the same meaning it originally had. To avoid future confusion, the check has also been rephrased to make its meaning clear. Signed-off-by: Nikita Kiryanov <nikita(a)compulab.co.il> Signed-off-by: Igor Grinberg <grinberg(a)compulab.co.il> --- common/lcd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/lcd.c b/common/lcd.c index 4c83a8b..cfa1134 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -834,7 +834,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) } /* We support displaying 8bpp BMPs on 16bpp LCDs */ - if (bpix != bmp_bpix && (bmp_bpix != 8 || bpix != 16 || bpix != 32)) { + if (bpix != bmp_bpix && !(bmp_bpix == 8 && bpix == 16)) { printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n", bpix, le16_to_cpu(bmp->header.bit_count)); -- 1.7.10.4

2 1