January 2013 - U-Boot

[U-Boot] [PATCH 01/10] arm: Compile cache_disable() with -O2 to avoid failure
by Simon Glass 18 Jan '13

18 Jan '13

It is good to have these functions written in C instead of assembler, but with -O0 the cache_disable() function doesn't return. Rather than revert to assembler, this fix just forces this to be built with -O2. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- arch/arm/lib/cache-cp15.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 939de10..8f8385d 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -110,6 +110,16 @@ static void cache_enable(uint32_t cache_bit) set_cr(reg | cache_bit); } +/* + * Big hack warning! + * + * Devs like to compile with -O0 to get a nice debugging illusion. But this + * function does not survive that since -O0 causes the compiler to read the + * PC back from the stack after the dcache flush. Might it be possible to fix + * this by flushing the write buffer? + */ +static void cache_disable(uint32_t cache_bit) __attribute__ ((optimize(2))); + /* cache_bit must be either CR_I or CR_C */ static void cache_disable(uint32_t cache_bit) { -- 1.7.7.3

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[U-Boot] [PATCH][v2] powerpc/p5040: enable NAND/SD/SPI boot support
by Shaohui Xie 18 Jan '13

18 Jan '13

Also update README.pblimage for p5040. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- changes for v2: 1. merge NAND/SD/SPI to one patch; 2. update README.pblimage for p5040; boards.cfg | 3 +++ doc/README.pblimage | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/boards.cfg b/boards.cfg index e4b0d44..710942f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -855,6 +855,9 @@ P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freesca P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 P5040DS powerpc mpc85xx corenet_ds freescale +P5040DS_NAND powerpc mpc85xx corenet_ds freescale - P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 +P5040DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 +P5040DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa diff --git a/doc/README.pblimage b/doc/README.pblimage index 2b9bb5c..bbf7658 100644 --- a/doc/README.pblimage +++ b/doc/README.pblimage @@ -14,17 +14,17 @@ Building PBL Boot Image and boot steps 1. Building PBL Boot Image. The default Image is u-boot.pbl. - For eSPI boot(available on P3041/P4080/P5020): + For eSPI boot(available on P3041/P4080/P5020/P5040): To build the eSPI boot image: make <board_name>_SPIFLASH_config make u-boot.pbl - For SD boot(available on P3041/P4080/P5020): + For SD boot(available on P3041/P4080/P5020/P5040): To build the SD boot image: make <board_name>_SDCARD_config make u-boot.pbl - For Nand boot(available on P3041/P5020): + For Nand boot(available on P3041/P5020/P5040): To build the NAND boot image: make <board_name>_NAND_config make u-boot.pbl -- 1.6.4

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[U-Boot] [PATCH] MPC8308: Fixup clocks in PCI Host configuration
by Barry Grussling 18 Jan '13

18 Jan '13

While trying to bring up a custom MPC8308 based board I found that the clocking was wrong. The comment in include/configs/mpc8308_p1m.h led me to believe setting HRCWH_PCI_HOST and HRCWH_PCI1_ARBITER_ENABLE in the CONFIG_SYS_HRCW_HIGH should allow the system to work, but on my newer version of the 8308 this is not working. Setting the HRCWH_PCI_HOST bit (which doesn't exist according to the manual) doesn't latch, and as such the im->reset.rcwh & HRCWH_PCI_HOST test in speed.c fails. Since this board is running off the CONFIG_83XX_CLKIN and is not a PCI client, I end up with 0xdeadbeef and hosed clock values. This patch allows for proper clocks on the 8308 as a workaround for the lack of HRCWH_PCI_HOST support. Signed-off-by: Barry Grussling <barry(a)grussling.com> --- arch/powerpc/cpu/mpc83xx/speed.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index b8c05d1..6f715ea 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -160,6 +160,10 @@ int get_clocks(void) } else { #if defined(CONFIG_83XX_PCICLK) pci_sync_in = CONFIG_83XX_PCICLK; +#elif defined(CONFIG_83XX_CLKIN) && defined(CONFIG_MPC8308) + /* 8308 doesn't have the HRCWH_PCI_HOST, but should + * run off the CONFIG_83XX_CLKIN */ + pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div); #else pci_sync_in = 0xDEADBEEF; #endif -- 1.7.9.5

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[U-Boot] designing a firmware update mechanism
by John Stile 17 Jan '13

17 Jan '13

I have an embedded project using an atmel arm processor, primary bootloader at91BootStrap on NOR to call uboot (and the reset of the system) on NAND. I am trying to devise a way to partition NAND redundantly, with 2 copies of (uboot + uboot-env + kernel + roofs). At91bootstrap will have to decide which uboot to start some how. I have not determined this yet, but I think reading something out of the two uboot-env areas might be a good start. Will I need to compile 2 versions of uboot, differing only in where to look for the uboot-env, or is there another way? I don't think giving one copy of uboot 2 uboot-env will do the trick. Could anyone share a firmware update strategy with me that uses uboot, or is that outside the scope of this list?

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[U-Boot] [PATCH v3 0/7] tegra: SPI drivers
by Allen Martin 17 Jan '13

17 Jan '13

This series updates the tegra20 SPI driver to add fdt support and adds a new tegra30 SPI driver. Testing was done on trimslice (tegra20) and cardhu (tegra30). Changes in v3: -Dropped some fdt patches from the series that were picked up in u-boot-tegra/next already -Removed SPI node from seaboard, added to trimslice -Incorporated feedback from Simon Glass and Stephen Warren to slink driver Changes in v2: -Added new patch to sort dts files prior to adding new nodes -Moved "max-spi-frequency" out to board dts files -Moved tegra20 SFLASH fdt changes out to separate patch -Added valid flag to slink driver controller structure Allen Martin (7): tegra20: fdt: add SPI SFLASH node tegra: spi: add fdt support to tegra SPI SFLASH driver tegra30: add SBC1 to periph id mapping table tegra30: fdt: add SPI SLINK nodes tegra: add addresses of SPI SLINK controllers tegra: add SPI SLINK driver tegra: cardhu: config: enable SPI arch/arm/cpu/tegra30-common/clock.c | 2 +- arch/arm/dts/tegra20.dtsi | 12 + arch/arm/dts/tegra30.dtsi | 72 ++++++ arch/arm/include/asm/arch-tegra/tegra.h | 6 + arch/arm/include/asm/arch-tegra/tegra_slink.h | 84 +++++++ board/compulab/dts/tegra20-trimslice.dts | 4 + board/nvidia/common/board.c | 3 +- board/nvidia/dts/tegra30-cardhu.dts | 4 + drivers/spi/Makefile | 1 + drivers/spi/tegra_slink.c | 332 +++++++++++++++++++++++++ drivers/spi/tegra_spi.c | 42 +++- include/configs/cardhu.h | 11 + include/fdtdec.h | 2 + lib/fdtdec.c | 2 + 14 files changed, 574 insertions(+), 3 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra/tegra_slink.h create mode 100644 drivers/spi/tegra_slink.c -- 1.7.10.4

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[U-Boot] Irq handler code is not working in u-boot
by VISWANADHULA BALAJI 17 Jan '13

17 Jan '13

Hi, In start.S file irq_handler code is used for handling the irq interrupts though iam able to handle the interrupt, iam not able to restore the previous state. irq_restore_user_regs label is given generally in all u-boots for restoring the state but not happens. Please do needful how i come out from this. Thanks balaji

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[U-Boot] USB3.0 support snacs 0 storage device
by Satendra... 17 Jan '13

17 Jan '13

Hi , I had ported usb3.0 xHCI driver code (not merged yet in the U-Boot : http://patchwork.ozlabs.org/patch/193477/ ) from U-Boot to Barebox. Using that I was able to detect the Controller and hub but not the usb storage devices. So I thought porting usb3.0 xHCI driver code as is (not integrating in barebox usb driver framework) from U-Boot to barebox and also ported the Barebox's usb core and command code just to test whether original code works fine. But still code not able to detect any storage device device but controller and hub. I get as shown below: "usb_storage_probe:1237:Probing Storage Devices...... 0 Storage Device(s) found" Below is the complete log : -------------------------------------------------- Barebox-C2K >/ Barebox-C2K >/ usb start do_usb:405: .......... argv[0]=usb argv[1]=start (Re)start USB... USB0: usb_lowlevel_init:3343........ ### comcerto_start_xhci ### comcerto_usb3_phy_init USB3.0 clock selected: internal init hccr 9f000000 and hcor 9f000020 hc_length 32 Halt the HC // Reset the HC Register 2000110 NbrPorts 2 Starting the controller USB XHCI 1.00 scanning bus 0 for devices... New Device 0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 0x40 USB_DT_DEVICE request scrlen = 18 req->length = 64 , length = 64 set address 1 usb_control_msg: request: 0x5, requesttype: 0x0, value 0x1 index 0x0 length 0x0 scrlen = 0 req->length = 0 , length = 0 Len is 0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 0x12 USB_DT_DEVICE request scrlen = 18 req->length = 18 , length = 18 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 0x9 USB_DT_CONFIG config scrlen = 25 req->length = 9 , length = 9 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 0x19 USB_DT_CONFIG config scrlen = 25 req->length = 25 , length = 25 get_conf_no 0 Result 25, wLength 25 if 0, ep 0 ##EP epmaxpacketin[1] = 8 set configuration 1 usb_control_msg: request: 0x9, requesttype: 0x0, value 0x1 index 0x0 length 0x0 new device strings: Mfr=1, Product=2, SerialNumber=0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x300 index 0x0 length 0xFF USB_DT_STRING config scrlen = 4 req->length = 255 , length = 255 USB device number 1 default language ID 0x1 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x301 index 0x1 length 0xFF USB_DT_STRING config scrlen = 14 req->length = 255 , length = 255 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x302 index 0x1 length 0xFF USB_DT_STRING config scrlen = 42 req->length = 255 , length = 255 Manufacturer u-boot Product XHCI Host Controller SerialNumber USB hub found usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2900 index 0x0 length 0x4 USB_DT_HUB config scrlen = 8 req->length = 4 , length = 4 usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2900 index 0x0 length 0xC USB_DT_HUB config scrlen = 8 req->length = 12 , length = 12 2 ports detected unknown reserved power switching mode standalone hub individual port over-current protection power on to power good time: 20ms hub controller current requirement: 0mA port 1 is removable port 2 is removable usb_control_msg: request: 0x0, requesttype: 0xA0, value 0x0 index 0x0 length 0x4 scrlen = 2 req->length = 4 , length = 4 get_hub_status returned status 1, change 8A02 local power source is lost (inactive) no over-current condition exists enabling power on all ports usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x1 length 0x0 scrlen = 0 req->length = 0 , length = 0 Len is 0 port 1 returns 0 usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x2 length 0x0 scrlen = 0 req->length = 0 , length = 0 Len is 0 port 2 returns 0 Waiting 16991886 msec to enable power on all ports. enabling power on all ports done. usb_hub_configure:usb_hub_power_on() done usb_hub_configure:430 get_timer() get_timer:68: cur = 15899899126 get_timer:72: cur=15899899126 cur>>19=30326 usb_hub_configure:433 get_timer() done. usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 scrlen = 4 req->length = 4 , length = 4 usb_hub_configure:456:portchange = 0x0 Port 1 Status 0 Change 0 usb_hub_configure:430 get_timer() get_timer:68: cur = 15946928539 get_timer:72: cur=15946928539 cur>>19=30416 usb_hub_configure:433 get_timer() done. usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x2 length 0x4 scrlen = 4 req->length = 4 , length = 4 usb_hub_configure:456:portchange = 0x0 Port 2 Status 200 Change 0 usb_hub_configure: done usb_new_device done. 1 USB Device(s) found scan end do_usb:started USB with ret = 0... scanning usb for storage devices... usb_stor_scan:256: Create usb_dev_desc[0] usb_stor_scan:256: Create usb_dev_desc[1] usb_stor_scan:256: Create usb_dev_desc[2] usb_stor_scan:256: Create usb_dev_desc[3] usb_stor_scan:256: Create usb_dev_desc[4] i=0 dev=0x104b940 i=0, dev_num=1 usb_storage_probe:1237:Probing Storage Devices...... iVendor 0 iProduct 0 usb_storage_probe:1261:Not a USB Mass Storage device. dev->descriptor.bDeviceClass=0x9 iface->desc.bInterfaceClass=0x9 iface->desc.bInterfaceSubClass=0x0 iface->desc.bInterfaceSubClass=0x0 i=1 dev=0x0 0 Storage Device(s) found do_usb:(Re)started USB with ret = 0... Barebox-C2K >/ Barebox-C2K >/ Barebox-C2K >/ usb tree do_usb:405: .......... argv[0]=usb argv[1]=tree USB device tree: 1 Hub (5 Gb/s, 0mA) u-boot XHCI Host Controller Barebox-C2K >/ Barebox-C2K >/ Barebox-C2K >/ usb info do_usb:405: .......... argv[0]=usb argv[1]=info 1: Hub, USB Revision 3.0 - u-boot XHCI Host Controller - Class: Hub - PacketSize: 9 Configurations: 1 - Vendor: 0x0000 Product 0x0000 Version 1.0 Configuration: 1 - Interfaces: 1 Self Powered 0mA Interface: 0 - Alternate Setting 0, Endpoints: 1 - Class Hub - Endpoint 1 In Interrupt MaxPacket 8 Interval 255ms Barebox-C2K >/ Barebox-C2K >/ --------------------------------------------------------- Any help is appreciated. Thanks, Satendra

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[U-Boot] Flash Not Erased for M29W128GL
by Ramesh K Khokhani 17 Jan '13

17 Jan '13

Hi Angelo, I am having problem with 16MB M29W128GL Flash. I am getting Flash Not Erased when i try to use saveenv command at u-boot command prompt. I have tried manually Byte by Byte wise writing to NOR Flash location so for that i have use following command and getting 2 same byte write on consecutive location. We have our custom board which uses MCF5329 Coldfire freescale's processor and 16MB M29W128GL NOR Flash. We have one M5329EVB evaluation board which has same processor but 2MB LHF00F31 NOR Flash (16bit x 16bit). For this evaluation board we have LTIB packege provided by freescale and which has u-boot-2011.09 version. This LTIB package we are using with some CFI CONFIG parameter changes. i.e. sector size, env offset add etc. And when i have try to write word using mw.w then it writes correct. Before use command: -> md 0x50000 00050000: ffffffff ffffffff ffffffff ffffffff ................ 00050010: ffffffff ffffffff ffffffff ffffffff ................ 00050020: ffffffff ffffffff ffffffff ffffffff ................ 00050030: ffffffff ffffffff ffffffff ffffffff ................ 00050040: ffffffff ffffffff ffffffff ffffffff ................ 00050050: ffffffff ffffffff ffffffff ffffffff ................ 00050060: ffffffff ffffffff ffffffff ffffffff ................ 00050070: ffffffff ffffffff ffffffff ffffffff ................ 00050080: ffffffff ffffffff ffffffff ffffffff ................ 00050090: ffffffff ffffffff ffffffff ffffffff ................ 000500a0: ffffffff ffffffff ffffffff ffffffff ................ 000500b0: ffffffff ffffffff ffffffff ffffffff ................ 000500c0: ffffffff ffffffff ffffffff ffffffff ................ 000500d0: ffffffff ffffffff ffffffff ffffffff ................ 000500e0: ffffffff ffffffff ffffffff ffffffff ................ 000500f0: ffffffff ffffffff ffffffff ffffffff ................ After use command: (Here i have try to write 0x12 on 0x50000 location but it writes two same bytes on 0x50000 & 0x50001) -> mw.b 0x?50?aaa 0xaa -> mw.b 0x50554 0x55 -> mw.b 0x50aaa 0xa0 -> mw.b 0x50000 0x12 -> md 0x50000 00050000: 1212ffff ffffffff ffffffff ffffffff ................ 00050010: ffffffff ffffffff ffffffff ffffffff ................ 00050020: ffffffff ffffffff ffffffff ffffffff ................ 00050030: ffffffff ffffffff ffffffff ffffffff ................ 00050040: ffffffff ffffffff ffffffff ffffffff ................ 00050050: ffffffff ffffffff ffffffff ffffffff ................ 00050060: ffffffff ffffffff ffffffff ffffffff ................ 00050070: ffffffff ffffffff ffffffff ffffffff ................ 00050080: ffffffff ffffffff ffffffff ffffffff ................ 00050090: ffffffff ffffffff ffffffff ffffffff ................ 000500a0: ffffffff ffffffff ffffffff ffffffff ................ 000500b0: ffffffff ffffffff ffffffff ffffffff ................ 000500c0: ffffffff ffffffff ffffffff ffffffff ................ 000500d0: ffffffff ffffffff ffffffff ffffffff ................ 000500e0: ffffffff ffffffff ffffffff ffffffff ................ 000500f0: ffffffff ffffffff ffffffff ffffffff ................ When try to write word using mw.w then it writes correct: -> md? ?w.w 0x50?aaa 0xaa -> mw.w 0x50554 0x55 -> mw.w 0x50aaa ??xa0? ? -> mw.w 0x500?10 0x1234 -> md 50000 00050000: 1212ffff ffffffff ffffffff ffffffff ................ 00050010: 1234ffff ffffffff ffffffff ffffffff .4.............. 00050020: ffffffff ffffffff ffffffff ffffffff ................ 00050030: ffffffff ffffffff ffffffff ffffffff ................ 00050040: ffffffff ffffffff ffffffff ffffffff ................ 00050050: ffffffff ffffffff ffffffff ffffffff ................ 00050060: ffffffff ffffffff ffffffff ffffffff ................ 00050070: ffffffff ffffffff ffffffff ffffffff ................ 00050080: ffffffff ffffffff ffffffff ffffffff ................ 00050090: ffffffff ffffffff ffffffff ffffffff ................ 000500a0: ffffffff ffffffff ffffffff ffffffff ................ 000500b0: ffffffff ffffffff ffffffff ffffffff ................ 000500c0: ffffffff ffffffff ffffffff ffffffff ................ 000500d0: ffffffff ffffffff ffffffff ffffffff ................ 000500e0: ffffffff ffffffff ffffffff ffffffff ................ 000500f0: ffffffff ffffffff ffffffff ffffffff ................ So what may be problem? Internally it uses following command (8bit x b bit). Is it problem? it should be 16bit x 8 bit? fwc addr 00040aaa cmd aa aa 8bit x 8 bit fwc addr 00040554 cmd 55 55 8bit x 8 bit fwc addr 00040aaa cmd a0 a0 8bit x 8 bit Thanks & Warm Regards, Ramesh Khokhani Senior Software Engineer [%20] ................................................................................................................................................... ramesh.khokhani(a)igatepatni.com ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Disclaimer~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Information contained and transmitted by this e-mail is confidential and proprietary to iGATE and its affiliates and is intended for use only by the recipient. If you are not the intended recipient, you are hereby notified that any dissemination, distribution, copying or use of this e-mail is strictly prohibited and you are requested to delete this e-mail immediately and notify the originator or mailadmin(a)igate.com <mailto:mailadmin@igate.com>. iGATE does not enter into any agreement with any party by e-mail. Any views expressed by an individual do not necessarily reflect the view of iGATE. iGATE is not responsible for the consequences of any actions taken on the basis of information provided, through this email. The contents of an attachment to this e-mail may contain software viruses, which could damage your own computer system. While iGATE has taken every reasonable precaution to minimise this risk, we cannot accept liability for any damage which you sustain as a result of software viruses. You should carry out your own virus checks before opening an attachment. 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[U-Boot] Divide uboot into two parts
by terryhuang 17 Jan '13

17 Jan '13

Hi, Are there any ways to divide uboot into two parts, and burn into SPI NOR Flash at different address? Limitation: first part of uboot will less than 128KB. Thanks. -Terry -- View this message in context: http://u-boot.10912.n7.nabble.com/Divide-uboot-into-two-parts-tp144917.html Sent from the U-Boot mailing list archive at Nabble.com.

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[U-Boot] [PATCH] powerpc/p5040: enable PBL tool support
by Shaohui Xie 17 Jan '13

17 Jan '13

Provided a default RCW for P5040, then it can use PBL to build ramboot image. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- board/freescale/corenet_ds/rcw_p5040ds.cfg | 11 +++++++++++ include/configs/corenet_ds.h | 2 ++ 2 files changed, 13 insertions(+), 0 deletions(-) create mode 100644 board/freescale/corenet_ds/rcw_p5040ds.cfg diff --git a/board/freescale/corenet_ds/rcw_p5040ds.cfg b/board/freescale/corenet_ds/rcw_p5040ds.cfg new file mode 100644 index 0000000..82fa741 --- /dev/null +++ b/board/freescale/corenet_ds/rcw_p5040ds.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for P5040DS. +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +0c580000 00000000 22121200 00000000 +089c4400 00283000 58000000 61000000 +00000000 00000000 00000000 10070000 +00000000 00000000 00000000 00000000 diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 3f42cd9..06281c6 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -38,6 +38,8 @@ #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg #elif defined(CONFIG_P5020DS) #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg +#elif defined(CONFIG_P5040DS) +#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg #endif #endif -- 1.6.4

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