August 2012 - U-Boot

[U-Boot] [PATCH 3/4] EXYNOS: additional Exynos4 SoC series support
by snow.jhkim＠gmail.com 10 Oct '12

10 Oct '12

From: Jeong-Hyeon Kim <jhkim(a)insignal.co.kr> - Fixed MPLL register address It's different between Exynos4210 and Exynos4412. - Added pinmux functions for Exynos4 - Added extended gpios for Exynos4412 Exynos4412 has more gpios than Exynos4210. Signed-off-by: Jeong-Hyeon Kim <jhkim(a)insignal.co.kr> --- arch/arm/cpu/armv7/exynos/clock.c | 11 ++ arch/arm/cpu/armv7/exynos/pinmux.c | 241 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clock.h | 27 ++++ arch/arm/include/asm/arch-exynos/cpu.h | 4 + arch/arm/include/asm/arch-exynos/gpio.h | 21 +++- 5 files changed, 303 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 680aeeb..84a6725 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -79,14 +79,25 @@ static unsigned long exynos4_get_pll_clk(int pllreg) /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ fout = (m + k / 65536) * (freq / (p * (1 << s))); } else if (pllreg == VPLL) { +#ifdef CONFIG_EXYNOS4210 k = k & 0xfff; /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */ fout = (m + k / 1024) * (freq / (p * (1 << s))); +#else + k = k & 0xffff; + /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ + fout = (m + k / 65536) * (freq / (p * (1 << s))); +#endif } else { +#ifdef CONFIG_EXYNOS4210 if (s < 1) s = 1; /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */ fout = m * (freq / (p * (1 << (s - 1)))); +#else + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */ + fout = m * (freq / (p * (1 << s))); +#endif } return fout; diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 7776add..0746878 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -26,6 +26,245 @@ #include <asm/arch/pinmux.h> #include <asm/arch/sromc.h> +static void exynos4_uart_config(int peripheral) +{ + struct exynos4_gpio_part1 *gpio1 = + (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1(); + struct s5p_gpio_bank *bank; + int i, start, count; + + switch (peripheral) { + case PERIPH_ID_UART0: + bank = &gpio1->a0; + start = 0; + count = 4; + break; + case PERIPH_ID_UART1: + bank = &gpio1->a0; + start = 4; + count = 4; + break; + case PERIPH_ID_UART2: + bank = &gpio1->a1; + start = 0; + count = 4; + break; + case PERIPH_ID_UART3: + bank = &gpio1->a1; + start = 4; + count = 2; + break; + } + for (i = start; i < start + count; i++) { + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + } +} + +static int exynos4_mmc_config(int peripheral, int flags) +{ + struct exynos4_gpio_part2 *gpio2 = + (struct exynos4_gpio_part2 *) samsung_get_base_gpio_part2(); + struct s5p_gpio_bank *bank, *bank_ext; + int i, start = 0, gpio_func = 0; + + switch (peripheral) { + case PERIPH_ID_SDMMC0: + bank = &gpio2->k0; + bank_ext = &gpio2->k1; + start = 3; + gpio_func = GPIO_FUNC(0x2); + break; + case PERIPH_ID_SDMMC1: + bank = &gpio2->k1; + bank_ext = NULL; + break; + case PERIPH_ID_SDMMC2: + bank = &gpio2->k2; + bank_ext = &gpio2->k3; + start = 3; + gpio_func = GPIO_FUNC(0x3); + break; + case PERIPH_ID_SDMMC3: + bank = &gpio2->k3; + bank_ext = NULL; + break; + } + if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + debug("SDMMC device %d does not support 8bit mode", + peripheral); + return -1; + } + if (flags & PINMUX_FLAG_8BIT_MODE) { + for (i = start; i <= (start + 3); i++) { + s5p_gpio_cfg_pin(bank_ext, i, gpio_func); + s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + } + } + for (i = 0; i < 2; i++) { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + for (i = 3; i <= 6; i++) { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + return 0; +} + +static void exynos4_sromc_config(int flags) +{ + struct exynos4_gpio_part2 *gpio2 = + (struct exynos4_gpio_part2 *) samsung_get_base_gpio_part2(); + int i; + + /* + * SROM:CS1 and EBI + * + * GPY0[0] SROM_CSn[0] + * GPY0[1] SROM_CSn[1](2) + * GPY0[2] SROM_CSn[2] + * GPY0[3] SROM_CSn[3] + * GPY0[4] EBI_OEn(2) + * GPY0[5] EBI_EEn(2) + * + * GPY1[0] EBI_BEn[0](2) + * GPY1[1] EBI_BEn[1](2) + * GPY1[2] SROM_WAIT(2) + * GPY1[3] EBI_DATA_RDn(2) + */ + s5p_gpio_cfg_pin(&gpio2->y0, (flags & PINMUX_FLAG_BANK), + GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio2->y0, 4, GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio2->y0, 5, GPIO_FUNC(2)); + + for (i = 0; i < 4; i++) + s5p_gpio_cfg_pin(&gpio2->y1, i, GPIO_FUNC(2)); + + /* + * EBI: 8 Addrss Lines + * + * GPY3[0] EBI_ADDR[0](2) + * GPY3[1] EBI_ADDR[1](2) + * GPY3[2] EBI_ADDR[2](2) + * GPY3[3] EBI_ADDR[3](2) + * GPY3[4] EBI_ADDR[4](2) + * GPY3[5] EBI_ADDR[5](2) + * GPY3[6] EBI_ADDR[6](2) + * GPY3[7] EBI_ADDR[7](2) + * + * EBI: 16 Data Lines + * + * GPY5[0] EBI_DATA[0](2) + * GPY5[1] EBI_DATA[1](2) + * GPY5[2] EBI_DATA[2](2) + * GPY5[3] EBI_DATA[3](2) + * GPY5[4] EBI_DATA[4](2) + * GPY5[5] EBI_DATA[5](2) + * GPY5[6] EBI_DATA[6](2) + * GPY5[7] EBI_DATA[7](2) + * + * GPY6[0] EBI_DATA[8](2) + * GPY6[1] EBI_DATA[9](2) + * GPY6[2] EBI_DATA[10](2) + * GPY6[3] EBI_DATA[11](2) + * GPY6[4] EBI_DATA[12](2) + * GPY6[5] EBI_DATA[13](2) + * GPY6[6] EBI_DATA[14](2) + * GPY6[7] EBI_DATA[15](2) + */ + for (i = 0; i < 8; i++) { + s5p_gpio_cfg_pin(&gpio2->y3, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio2->y3, i, GPIO_PULL_UP); + + s5p_gpio_cfg_pin(&gpio2->y5, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio2->y5, i, GPIO_PULL_UP); + + s5p_gpio_cfg_pin(&gpio2->y6, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio2->y6, i, GPIO_PULL_UP); + } +} + +static void exynos4_i2c_config(int peripheral, int flags) +{ + + struct exynos4_gpio_part1 *gpio1 = + (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1(); + + switch (peripheral) { + case PERIPH_ID_I2C0: + s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + s5p_gpio_cfg_pin(&gpio1->b, 0, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b, 1, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3)); + break; + } +} + +static int exynos4_pinmux_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + exynos4_uart_config(peripheral); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + return exynos4_mmc_config(peripheral, flags); + case PERIPH_ID_SROMC: + exynos4_sromc_config(flags); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + exynos4_i2c_config(peripheral, flags); + break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + return 0; +} + static void exynos5_uart_config(int peripheral) { struct exynos5_gpio_part1 *gpio1 = @@ -269,6 +508,8 @@ int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) return exynos5_pinmux_config(peripheral, flags); + else if (cpu_is_exynos4()) + return exynos4_pinmux_config(peripheral, flags); else { debug("pinmux functionality not supported\n"); return -1; diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index fce38ef..e238810 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -57,10 +57,20 @@ struct exynos4_clock { unsigned char res16[0xec]; unsigned int epll_con0; unsigned int epll_con1; +#ifdef CONFIG_EXYNOS4210 unsigned char res17[0x8]; +#else + unsigned int epll_con2; + unsigned char res17[0x4]; +#endif unsigned int vpll_con0; unsigned int vpll_con1; +#ifdef CONFIG_EXYNOS4210 unsigned char res18[0xe8]; +#else + unsigned int vpll_con2; + unsigned char res18[0xe4]; +#endif unsigned int src_top0; unsigned int src_top1; unsigned char res19[0x8]; @@ -161,7 +171,16 @@ struct exynos4_clock { unsigned char res38[0x8c]; unsigned int clkout_cmu_top; unsigned int clkout_cmu_top_div_stat; +#ifdef CONFIG_EXYNOS4210 unsigned char res39[0x37f8]; +#else + unsigned char res39[0x3600]; + unsigned int mpll_lock; + unsigned char res3a[0xfc]; + unsigned int mpll_con0; + unsigned int mpll_con1; + unsigned char res3b[0xf0]; +#endif unsigned int src_dmc; unsigned char res40[0xfc]; unsigned int src_mask_dmc; @@ -195,14 +214,22 @@ struct exynos4_clock { unsigned int maxperf; unsigned char res51[0x2f78]; unsigned int apll_lock; +#ifdef CONFIG_EXYNOS4210 unsigned char res52[0x4]; unsigned int mpll_lock; +#else + unsigned char res52[0x8]; +#endif unsigned char res53[0xf4]; unsigned int apll_con0; unsigned int apll_con1; +#ifdef CONFIG_EXYNOS4210 unsigned int mpll_con0; unsigned int mpll_con1; unsigned char res54[0xf0]; +#else + unsigned char res54[0xf8]; +#endif unsigned int src_cpu; unsigned char res55[0x1fc]; unsigned int mux_stat_cpu; diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 2cd4ae1..d1117c0 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -55,7 +55,11 @@ #define EXYNOS4_MODEM_BASE 0x13A00000 #define EXYNOS4_USBPHY_CONTROL 0x10020704 +#ifdef CONFIG_EXYNOS4412 +#define EXYNOS4_GPIO_PART4_BASE 0x106E0000 +#else #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE +#endif #define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE /* EXYNOS5 */ diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 97be4ea..9539aa0 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -49,6 +49,9 @@ struct exynos4_gpio_part1 { struct s5p_gpio_bank f1; struct s5p_gpio_bank f2; struct s5p_gpio_bank f3; + struct s5p_gpio_bank res1[2]; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; }; struct exynos4_gpio_part2 { @@ -68,7 +71,13 @@ struct exynos4_gpio_part2 { struct s5p_gpio_bank y4; struct s5p_gpio_bank y5; struct s5p_gpio_bank y6; - struct s5p_gpio_bank res1[80]; + struct s5p_gpio_bank res1[3]; + struct s5p_gpio_bank m0; + struct s5p_gpio_bank m1; + struct s5p_gpio_bank m2; + struct s5p_gpio_bank m3; + struct s5p_gpio_bank m4; + struct s5p_gpio_bank res2[72]; struct s5p_gpio_bank x0; struct s5p_gpio_bank x1; struct s5p_gpio_bank x2; @@ -79,6 +88,16 @@ struct exynos4_gpio_part3 { struct s5p_gpio_bank z; }; +struct exynos4_gpio_part4 { + struct s5p_gpio_bank v0; + struct s5p_gpio_bank v1; + struct s5p_gpio_bank res1[1]; + struct s5p_gpio_bank v2; + struct s5p_gpio_bank v3; + struct s5p_gpio_bank res2[1]; + struct s5p_gpio_bank v4; +}; + struct exynos5_gpio_part1 { struct s5p_gpio_bank a0; struct s5p_gpio_bank a1; -- 1.7.1

3 5

[U-Boot] [PATCH] fix IDE_BUS(dev) macro
by Luka Perkov 08 Oct '12

08 Oct '12

IDE_BUS assumes that each bus has two devices and thus returns the first bus even when the second one should be probed. Signed-off-by: Simon Baatz <gmbnomis(a)gmail.com> Tested-by: Luka Perkov <uboot(a)lukaperkov.net> --- Simon discovered this while adding support for new board IB NAS6210. More info can be found here: http://lists.denx.de/pipermail/u-boot/2012-April/122525.html When this is commited I will do a coding style cleanup. There are tabs after few "#define" parts in include/ide.h. include/ide.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/ide.h b/include/ide.h index 8ecc9dd..385e909 100644 --- a/include/ide.h +++ b/include/ide.h @@ -24,7 +24,7 @@ #ifndef _IDE_H #define _IDE_H -#define IDE_BUS(dev) (dev >> 1) +#define IDE_BUS(dev) (dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS)) #define ATA_CURR_BASE(dev) (CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])

11 23

[U-Boot] [PATCH v3 0/23] tegra: warmboot (suspend / resume) support
by Simon Glass 06 Oct '12

06 Oct '12

This series adds support for warm boot, allowing the device to suspend and resume. U-Boot sets up some 'warm boot' code in a special area such that the SOC can find it on a resume. This code is responsible for setting up memory and clocked and then allowing the OS to continue where it left off. Also included here is support for the EMC, which allows setting the memory timings correctly in U-Boot for maximum speed operation. Note: sign-offs are needed from Jimmy Zhang, Wei Ni and Yen Lin. Changes in v2: - Add check of undocumented values in hidrev register - Add debug() output to EMC - Add new fdtdec_locate_array() function - Add patch to find DVC bus number - Check error return from pmu_set_nominal() in debug mode - Move EMC tables to device tree - Move structs shared between A9 and AVP into warmboot.h header file - New patch to add low-level clock functions - Rely on compiler to optimise out debug_print_vector() - Remove unused crypto code - Remove unused crypto code from crypto.c - Removed check for nominal voltage (not needed as it is done just before) - Split PMU code into separate TPS6586X driver - Tidy SDRAM range check in warmboot_prepare_code() - Tidy whitespace problems - Use const for sbox arrays - Use low-level clock functions in warmboot code instead of register access Changes in v3: - Add apb_misc.h header file in new patch - Add better error reporting when EMC setup fails - Add new fdtdec_next_compatible_subnode() patch - Add new patch to put abs() in common.h - Fix CONFIG_TEGRA_I2C define - Move abs() macro into common.h - Support nvidia,use-ram-code binding option for EMC - Try to return a useful error code when EMC config fails Jimmy Zhang (3): tegra: Add EMC support for optimal memory timings tegra: Add PMU to manage power supplies tegra: Add EMC settings for Seaboard Simon Glass (14): fdt: Add function to locate an array in the device tree fdt: Add function to return next compatible subnode Add abs() macro to return absolute value i2c: Add TPS6586X driver tegra: Move ap20.h header into arch location tegra: Add functions to access low-level Osc/PLL details tegra: Add tegra_get_chip_type() to detect SKU tegra: Add header file for APB_MISC register tegra: Set up PMU for Nvidia boards tegra: Set up warmboot code on Nvidia boards fdt: tegra: Add EMC node to device tree tegra: i2c: Add function to find DVC bus tegra: fdt: Add EMC data for Tegra2 Seaboard tegra: Enable LP0 on Seaboard Wei Ni (1): tegra: Turn off power detect in board init Yen Lin (5): Add AES crypto library tegra: Add crypto library for warmboot code tegra: Add flow, gp_padctl, fuse, sdram headers tegra: Add warmboot implementation tegra: Setup PMC scratch info from ap20 setup arch/arm/cpu/armv7/tegra2/Makefile | 4 + arch/arm/cpu/armv7/tegra2/ap20.c | 44 ++- arch/arm/cpu/armv7/tegra2/board.c | 4 +- arch/arm/cpu/armv7/tegra2/clock.c | 32 + arch/arm/cpu/armv7/tegra2/crypto.c | 230 ++++++++ arch/arm/cpu/armv7/tegra2/crypto.h | 36 ++ arch/arm/cpu/armv7/tegra2/emc.c | 286 ++++++++++ arch/arm/cpu/armv7/tegra2/pmu.c | 70 +++ arch/arm/cpu/armv7/tegra2/warmboot.c | 382 +++++++++++++ arch/arm/cpu/armv7/tegra2/warmboot_avp.c | 250 ++++++++ arch/arm/cpu/armv7/tegra2/warmboot_avp.h | 81 +++ arch/arm/dts/tegra20.dtsi | 7 + .../tegra2 => include/asm/arch-tegra2}/ap20.h | 7 + arch/arm/include/asm/arch-tegra2/apb_misc.h | 36 ++ arch/arm/include/asm/arch-tegra2/clk_rst.h | 3 + arch/arm/include/asm/arch-tegra2/clock.h | 22 + arch/arm/include/asm/arch-tegra2/emc.h | 113 ++++ arch/arm/include/asm/arch-tegra2/flow.h | 36 ++ arch/arm/include/asm/arch-tegra2/fuse.h | 39 ++ arch/arm/include/asm/arch-tegra2/gp_padctrl.h | 73 +++ arch/arm/include/asm/arch-tegra2/pmu.h | 30 + arch/arm/include/asm/arch-tegra2/sdram_param.h | 148 +++++ arch/arm/include/asm/arch-tegra2/tegra2.h | 25 + arch/arm/include/asm/arch-tegra2/tegra_i2c.h | 7 + arch/arm/include/asm/arch-tegra2/warmboot.h | 150 +++++ board/nvidia/common/Makefile | 1 + board/nvidia/common/board.c | 41 ++- board/nvidia/common/emc.c | 53 ++ board/nvidia/common/emc.h | 29 + board/nvidia/dts/tegra2-seaboard.dts | 72 +++ drivers/i2c/tegra_i2c.c | 14 + drivers/power/Makefile | 1 + drivers/power/tps6586x.c | 280 +++++++++ include/aes.h | 70 +++ include/common.h | 13 + include/configs/seaboard.h | 8 + include/configs/tegra2-common.h | 17 + include/fdtdec.h | 38 ++ include/tps6586x.h | 68 +++ lib/Makefile | 1 + lib/aes.c | 598 ++++++++++++++++++++ lib/fdtdec.c | 28 + 42 files changed, 3443 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/crypto.c create mode 100644 arch/arm/cpu/armv7/tegra2/crypto.h create mode 100644 arch/arm/cpu/armv7/tegra2/emc.c create mode 100644 arch/arm/cpu/armv7/tegra2/pmu.c create mode 100644 arch/arm/cpu/armv7/tegra2/warmboot.c create mode 100644 arch/arm/cpu/armv7/tegra2/warmboot_avp.c create mode 100644 arch/arm/cpu/armv7/tegra2/warmboot_avp.h rename arch/arm/{cpu/armv7/tegra2 => include/asm/arch-tegra2}/ap20.h (96%) create mode 100644 arch/arm/include/asm/arch-tegra2/apb_misc.h create mode 100644 arch/arm/include/asm/arch-tegra2/emc.h create mode 100644 arch/arm/include/asm/arch-tegra2/flow.h create mode 100644 arch/arm/include/asm/arch-tegra2/fuse.h create mode 100644 arch/arm/include/asm/arch-tegra2/gp_padctrl.h create mode 100644 arch/arm/include/asm/arch-tegra2/pmu.h create mode 100644 arch/arm/include/asm/arch-tegra2/sdram_param.h create mode 100644 arch/arm/include/asm/arch-tegra2/warmboot.h create mode 100644 board/nvidia/common/emc.c create mode 100644 board/nvidia/common/emc.h create mode 100644 drivers/power/tps6586x.c create mode 100644 include/aes.h create mode 100644 include/tps6586x.h create mode 100644 lib/aes.c -- 1.7.7.3

8 53

[U-Boot] [PATCH] Add a new "ini" command
by Joe Hershberger 06 Oct '12

06 Oct '12

This allows you to read ini-formatted data from anywhere and then import one of the sections into the environment This is based on rev 16 at http://code.google.com/p/inih/ Signed-off-by: Joe Hershberger <joe.hershberger(a)ni.com> --- common/Makefile | 1 + common/cmd_ini.c | 256 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 257 insertions(+) create mode 100644 common/cmd_ini.c diff --git a/common/Makefile b/common/Makefile index 3d62775..e296368 100644 --- a/common/Makefile +++ b/common/Makefile @@ -100,6 +100,7 @@ COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o +COBJS-$(CONFIG_CMD_INI) += cmd_ini.o COBJS-$(CONFIG_CMD_IRQ) += cmd_irq.o COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o diff --git a/common/cmd_ini.c b/common/cmd_ini.c new file mode 100644 index 0000000..0f0e5cd --- /dev/null +++ b/common/cmd_ini.c @@ -0,0 +1,256 @@ +/* + * inih -- simple .INI file parser + * + * inih is released under the New BSD license (see LICENSE.txt). Go to the + * project home page for more info: + * + * http://code.google.com/p/inih/ + */ + +#include <common.h> +#include <command.h> +#include <environment.h> +#include <linux/ctype.h> +#include <linux/string.h> + +#ifdef CONFIG_INI_MAX_LINE +#define MAX_LINE CONFIG_INI_MAX_LINE +#else +#define MAX_LINE 200 +#endif + +#ifdef CONFIG_INI_MAX_SECTION +#define MAX_SECTION CONFIG_INI_MAX_SECTION +#else +#define MAX_SECTION 50 +#endif + +#ifdef CONFIG_INI_MAX_NAME +#define MAX_NAME CONFIG_INI_MAX_NAME +#else +#define MAX_NAME 50 +#endif + +/* Strip whitespace chars off end of given string, in place. Return s. */ +static char *rstrip(char *s) +{ + char *p = s + strlen(s); + + while (p > s && isspace(*--p)) + *p = '\0'; + return s; +} + +/* Return pointer to first non-whitespace char in given string. */ +static char *lskip(const char *s) +{ + while (*s && isspace(*s)) + s++; + return (char *)s; +} + +/* Return pointer to first char c or ';' comment in given string, or pointer to + null at end of string if neither found. ';' must be prefixed by a whitespace + character to register as a comment. */ +static char *find_char_or_comment(const char *s, char c) +{ + int was_whitespace = 0; + + while (*s && *s != c && !(was_whitespace && *s == ';')) { + was_whitespace = isspace(*s); + s++; + } + return (char *)s; +} + +/* Version of strncpy that ensures dest (size bytes) is null-terminated. */ +static char *strncpy0(char *dest, const char *src, size_t size) +{ + strncpy(dest, src, size); + dest[size - 1] = '\0'; + return dest; +} + +/* Emulate the behavior of fgets but on memory */ +static char *memgets(char *str, int num, char **mem, size_t *memsize) +{ + char *end; + int len; + int newline = 1; + + end = memchr(*mem, '\n', *memsize); + if (end == NULL) { + if (*memsize == 0) + return NULL; + end = *mem + *memsize; + newline = 0; + } + len = min((end - *mem) + newline, num); + memcpy(str, *mem, len); + if (len < num) + str[len] = '\0'; + + /* prepare the mem vars for the next call */ + *memsize -= (end - *mem) + newline; + *mem += (end - *mem) + newline; + + return str; +} + +/* Parse given INI-style file. May have [section]s, name=value pairs + (whitespace stripped), and comments starting with ';' (semicolon). Section + is "" if name=value pair parsed before any section heading. name:value + pairs are also supported as a concession to Python's ConfigParser. + + For each name=value pair parsed, call handler function with given user + pointer as well as section, name, and value (data only valid for duration + of handler call). Handler should return nonzero on success, zero on error. + + Returns 0 on success, line number of first error on parse error (doesn't + stop on first error). +*/ +int ini_parse(char *filestart, size_t filelen, + int (*handler)(void *, char *, char *, char *), void *user) +{ + /* Uses a fair bit of stack (use heap instead if you need to) */ + char line[MAX_LINE]; + char section[MAX_SECTION] = ""; + char prev_name[MAX_NAME] = ""; + + char *curmem = filestart; + char *start; + char *end; + char *name; + char *value; + size_t memleft = filelen; + int lineno = 0; + int error = 0; + + /* Scan through file line by line */ + while (memgets(line, sizeof(line), &curmem, &memleft) != NULL) { + lineno++; + start = lskip(rstrip(line)); + + if (*start == ';' || *start == '#') { + /* + * Per Python ConfigParser, allow '#' comments at start + * of line + */ + } +#if CONFIG_INI_ALLOW_MULTILINE + else if (*prev_name && *start && start > line) { + /* + * Non-blank line with leading whitespace, treat as + * continuation of previous name's value (as per Python + * ConfigParser). + */ + if (!handler(user, section, prev_name, start) && !error) + error = lineno; + } +#endif + else if (*start == '[') { + /* A "[section]" line */ + end = find_char_or_comment(start + 1, ']'); + if (*end == ']') { + *end = '\0'; + strncpy0(section, start + 1, sizeof(section)); + *prev_name = '\0'; + } else if (!error) { + /* No ']' found on section line */ + error = lineno; + } + } else if (*start && *start != ';') { + /* Not a comment, must be a name[=:]value pair */ + end = find_char_or_comment(start, '='); + if (*end != '=') + end = find_char_or_comment(start, ':'); + if (*end == '=' || *end == ':') { + *end = '\0'; + name = rstrip(start); + value = lskip(end + 1); + end = find_char_or_comment(value, '\0'); + if (*end == ';') + *end = '\0'; + rstrip(value); + /* Strip double-quotes */ + if (value[0] == '"' && + value[strlen(value)-1] == '"') { + value[strlen(value)-1] = '\0'; + value += 1; + } + + /* + * Valid name[=:]value pair found, call handler + */ + strncpy0(prev_name, name, sizeof(prev_name)); + if (!handler(user, section, name, value) && + !error) + error = lineno; + } else if (!error) + /* No '=' or ':' found on name[=:]value line */ + error = lineno; + } + } + + return error; +} + +static int ini_handler(void *user, char *section, char *name, char *value) +{ + char *requested_section = (char *)user; +#ifdef CONFIG_INI_CASE_INSENSITIVE + int i; + + for (i = 0; i < strlen(requested_section); i++) + requested_section[i] = tolower(requested_section[i]); + for (i = 0; i < strlen(section); i++) + section[i] = tolower(section[i]); +#endif + + if (!strcmp(section, requested_section)) { +#ifdef CONFIG_INI_CASE_INSENSITIVE + for (i = 0; i < strlen(name); i++) + name[i] = tolower(name[i]); + for (i = 0; i < strlen(value); i++) + value[i] = tolower(value[i]); +#endif + setenv(name, value); + printf("ini: Imported %s as %s\n", name, value); + } + + /* success */ + return 1; +} + +int do_ini(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const char *section; + char *file_address; + size_t file_size; + + if (argc == 1) + return CMD_RET_USAGE; + + section = argv[1]; + if (argc < 3) + file_address = (char *)simple_strtoul(getenv("loadaddr"), + NULL, 16); + else + file_address = (char *)simple_strtoul(argv[2], NULL, 16); + if (argc < 4) + file_size = (size_t)simple_strtoul(getenv("filesize"), + NULL, 16); + else + file_size = (size_t)simple_strtoul(argv[3], NULL, 16); + + ini_parse(file_address, file_size, ini_handler, (void *)section); + + /* success */ + return 0; +} + +U_BOOT_CMD( + ini, 4, 0, do_ini, + "parse an ini file in memory and merge the specified section into the env", + "section [[file-address] file-size]" +); -- 1.7.11.5

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[U-Boot] [PATCH 1/2] GPIO: pca953x: fix spelling in help
by Laurence Withers 06 Oct '12

06 Oct '12

Signed-off-by: Laurence Withers <lwithers(a)guralp.com> --- drivers/gpio/pca953x.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index 359fdee..64c7797 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -287,7 +287,7 @@ U_BOOT_CMD( " - set pin as output and drive low or high\n" "pca953x invert pin 0|1\n" " - disable/enable polarity inversion for reads\n" - "pca953x intput pin\n" + "pca953x input pin\n" " - set pin as input and read value" ); -- 1.7.2.5

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[U-Boot] [PATCH] arm: rmobile: kzm9g: Adjust hardware setting in lowlevel_init.S
by Tetsuyuki Kobayashi 05 Oct '12

05 Oct '12

This patch depends on Nobuhiro Iwamatsu's arm: rmobile: Add supoprt for KMC KZM-A9-GT board Tetsuyuki Kobayashi's arm: rmobile: kzm9g: Modify sdram area Adjust hardware setting in lowlevel_init.S. After this patch U-boot can boot Linux kernel (without DTB) on KZM-A9-GT board successfully. Signed-off-by: Tetsuyuki Kobayashi <koba(a)kmckk.co.jp> --- arch/arm/include/asm/arch-rmobile/sh73a0.h | 1 + board/kmc/kzm/lowlevel_init.S | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/include/asm/arch-rmobile/sh73a0.h b/arch/arm/include/asm/arch-rmobile/sh73a0.h index 07824ab..bb66d20 100644 --- a/arch/arm/include/asm/arch-rmobile/sh73a0.h +++ b/arch/arm/include/asm/arch-rmobile/sh73a0.h @@ -191,6 +191,7 @@ #define SMSTPCR3 (CPG_BASE + 0x013C) #define SMSTPCR4 (CPG_BASE + 0x0140) #define SMSTPCR5 (CPG_BASE + 0x0144) +#define CPGXXCR4 (CPG_BASE + 0x0150) #define SRCR0 (CPG_BASE + 0x80A0) #define SRCR1 (CPG_BASE + 0x80A8) #define SRCR2 (CPG_BASE + 0x80B0) diff --git a/board/kmc/kzm/lowlevel_init.S b/board/kmc/kzm/lowlevel_init.S index 5221611..be3d203 100644 --- a/board/kmc/kzm/lowlevel_init.S +++ b/board/kmc/kzm/lowlevel_init.S @@ -111,6 +111,7 @@ loop0: and_write32 LIFEC_SEC_SRC, 0xFFFFFFE7 + and_write32 SMSTPCR3,0xFFFF7FFF and_write32 SRCR3, 0xFFFF7FFF and_write32 SMSTPCR2,0xFFFBFFFF and_write32 SRCR2, 0xFFFBFFFF @@ -302,6 +303,8 @@ loop0: write32 FRQCRD, 0x00000B0B cmp_loop FRQCRD, 0x80000000, 0x00000000 + write32 CPGXXCR4, 0xfffffffc + bx lr .pool -- 1.7.9.5

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[U-Boot] [PATCH] arm: Add CONFIG_OF_BOARD_SETUP support to bootm
by Joe Hershberger 04 Oct '12

04 Oct '12

ARM boards need to change device tree settings as well Signed-off-by: Joe Hershberger <joe.hershberger(a)ni.com> --- arch/arm/lib/bootm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 599547d..2e0b0c1 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -258,6 +258,9 @@ static int create_fdt(bootm_headers_t *images) fixup_memory_node(*of_flat_tree); fdt_fixup_ethernet(*of_flat_tree); fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1); +#ifdef CONFIG_OF_BOARD_SETUP + ft_board_setup(*of_flat_tree, gd->bd); +#endif return 0; } -- 1.7.11.5

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Re: [U-Boot] [PATCH] mtest: Disable dcache during test
by Benoît Thébaudeau 04 Oct '12

04 Oct '12

On 08/11/2012 21:47, Andrew Dyer wrote: > I agree with Mike, use the current dcache settings. U-boot has always > assumed the user knew what they were doing. > If you want to print a small message with the dcache setting that > makes sense to me, but no big warning. Then, something like the following at runtime in the first lines printed my mtest? dcache state: on Best regards, Benoît

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[U-Boot] [PATCH] armv7 cpu_init_crit: Simplify code
by Benoît Thébaudeau 04 Oct '12

04 Oct '12

We don't need to return to cpu_init_crit after calling lowlevel_init, so lowlevel_init can directly return to the caller of cpu_init_crit. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau(a)advansee.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> --- .../arch/arm/cpu/armv7/start.S | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/start.S u-boot-4d3c95f/arch/arm/cpu/armv7/start.S index aee27fd..e8e533e 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/start.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/start.S @@ -357,10 +357,7 @@ ENTRY(cpu_init_crit) * basic memory. Go here to bump up clock rate and handle * wake up conditions. */ - mov ip, lr @ persevere link reg across call - bl lowlevel_init @ go setup pll,mux,memory - mov lr, ip @ restore link - mov pc, lr @ back to my caller + b lowlevel_init @ go setup pll,mux,memory ENDPROC(cpu_init_crit) #endif

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[U-Boot] [PATCH v4 1/2] tools, config.mk: add binutils-version
by Allen Martin 04 Oct '12

04 Oct '12

Modeled after gcc-version, add function to get binutils version. Signed-off-by: Allen Martin <amartin(a)nvidia.com> --- config.mk | 1 + tools/binutils-version.sh | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100755 tools/binutils-version.sh diff --git a/config.mk b/config.mk index 3dcea6a..919b77d 100644 --- a/config.mk +++ b/config.mk @@ -128,6 +128,7 @@ endif # cc-version # Usage gcc-ver := $(call cc-version) cc-version = $(shell $(SHELL) $(SRCTREE)/tools/gcc-version.sh $(CC)) +binutils-version = $(shell $(SHELL) $(SRCTREE)/tools/binutils-version.sh $(AS)) # # Include the make variables (CC, etc...) diff --git a/tools/binutils-version.sh b/tools/binutils-version.sh new file mode 100755 index 0000000..d4d9eb4 --- /dev/null +++ b/tools/binutils-version.sh @@ -0,0 +1,20 @@ +#!/bin/sh +# +# binutils-version [-p] gas-command +# +# Prints the binutils version of `gas-command' in a canonical 4-digit form +# such as `0222' for binutils 2.22 +# + +gas="$*" + +if [ ${#gas} -eq 0 ]; then + echo "Error: No assembler specified." + printf "Usage:\n\t$0 <gas-command>\n" + exit 1 +fi + +MAJOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 1) +MINOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 2) + +printf "%02d%02d\\n" $MAJOR $MINOR -- 1.7.9.5

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