August 2012 - U-Boot

[U-Boot] [PATCH] powerpc/mpc85xx:Add new ext fields to Freescale's IFC
by Prabhakar Kushwaha 16 Aug '12

16 Aug '12

Freescale's Integrated Flash controller(IFC) v1.1.0 supports 40 bit address bus width. In case more than 32 bit address is used, the new ext registers should be set. Add support of ext registers. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> Signed-off-by: York Sun <yorksun(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot.git (branch master) arch/powerpc/include/asm/fsl_ifc.h | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h index 7d95eb4..9aaa398 100644 --- a/arch/powerpc/include/asm/fsl_ifc.h +++ b/arch/powerpc/include/asm/fsl_ifc.h @@ -909,22 +909,24 @@ struct fsl_ifc_gpcm { */ struct fsl_ifc { u32 ifc_rev; - u32 res1[0x3]; + u32 res1[0x2]; struct { + u32 cspr_ext; u32 cspr; - u32 res2[0x2]; + u32 res2; } cspr_cs[FSL_IFC_BANK_COUNT]; - u32 res3[0x18]; + u32 res3[0x19]; struct { u32 amask; u32 res4[0x2]; } amask_cs[FSL_IFC_BANK_COUNT]; - u32 res5[0x18]; + u32 res5[0x17]; struct { + u32 csor_ext; u32 csor; - u32 res6[0x2]; + u32 res6; } csor_cs[FSL_IFC_BANK_COUNT]; - u32 res7[0x18]; + u32 res7[0x19]; struct { u32 ftim[4]; u32 res8[0x8]; -- 1.7.9.5

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[U-Boot] [Patch 15/16] add standalone link script
by Zhi-zhou Zhang 16 Aug '12

16 Aug '12

diff --git a/examples/standalone/mips64.lds b/examples/standalone/mips64.lds new file mode 100644 index 0000000..00b96da --- /dev/null +++ b/examples/standalone/mips64.lds @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, <wd(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +*/ +OUTPUT_FORMAT("elf64-tradlittlemips", "elf64-tradlittlemips", "elf64-tradlittlemips") +OUTPUT_ARCH(mips) +SECTIONS +{ + .text : + { + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data*) } + + . = .; + _gp = ALIGN(16) + 0x7ff0; + + .got : { + __got_start = .; + *(.got) + __got_end = .; + } + + .sdata : { *(.sdata*) } + + . = ALIGN(4); + __bss_start = .; + .sbss (NOLOAD) : { *(.sbss*) } + .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); } + + _end = .; +} -- Regards, Zhizhou Zhang

2 1

[U-Boot] [Patch 11/16] make size_t equal to unsigned int
by Zhi-zhou Zhang 16 Aug '12

16 Aug '12

err.. maybe a bug of gcc? In my memory, size_t is equaled to unsigned int. diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h index 879aae2..86a866a 100644 --- a/arch/mips/include/asm/posix_types.h +++ b/arch/mips/include/asm/posix_types.h @@ -24,7 +24,11 @@ typedef int __kernel_pid_t; typedef int __kernel_ipc_pid_t; typedef int __kernel_uid_t; typedef int __kernel_gid_t; +#ifndef CONFIG_MIPS64 typedef unsigned int __kernel_size_t; +#else +typedef unsigned long __kernel_size_t; +#endif typedef int __kernel_ssize_t; typedef int __kernel_ptrdiff_t; typedef long __kernel_time_t; -- Regards, Zhizhou Zhang

2 1

[U-Boot] [Patch 12/16] add config about mips64
by Zhi-zhou Zhang 16 Aug '12

16 Aug '12

diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk index 27cd34a..6a3d7a7 100644 --- a/board/qemu-mips/config.mk +++ b/board/qemu-mips/config.mk @@ -2,9 +2,16 @@ # Qemu -M mips system emulator # See http://fabrice.bellard.free.fr/qemu # +ifeq "$(CPU)" "mips64" +# ROM version +#CONFIG_SYS_TEXT_BASE = 0xFfffFfffbfc00000 +# RAM version +CONFIG_SYS_TEXT_BASE = 0xffffffff80200000 +else # ROM version CONFIG_SYS_TEXT_BASE = 0xbfc00000 # RAM version #CONFIG_SYS_TEXT_BASE = 0x80001000 +endif -- Regards, Zhizhou Zhang

2 1

[U-Boot] [Patch 5/16] add mips64/cpu.h
by Zhi-zhou Zhang 16 Aug '12

16 Aug '12

diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c new file mode 100644 index 0000000..1ead349 --- /dev/null +++ b/arch/mips/cpu/mips64/cpu.c @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, <wd(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <asm/mipsregs.h> +#include <asm/cacheops.h> +#include <asm/reboot.h> + +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips64\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +void __attribute__((weak)) _machine_restart(void) +{ +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + _machine_restart(); + + fprintf(stderr, "*** reset failed ***\n"); + return 0; +} + +void flush_cache(ulong start_addr, ulong size) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + + /* aend will be miscalculated when size is zero, so we return here */ + if (size == 0) + return; + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); + if (addr == aend) + break; + addr += lsize; + } +} + +void flush_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (stop - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + if (addr == aend) + break; + addr += lsize; + } +} + +void invalidate_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (stop - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Invalidate_D, addr); + if (addr == aend) + break; + addr += lsize; + } +} + +void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) +{ + write_c0_entrylo0(low0); + write_c0_pagemask(pagemask); + write_c0_entrylo1(low1); + write_c0_entryhi(hi); + write_c0_index(index); + tlb_write_indexed(); +} + +int cpu_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SOC_AU1X00 + au1x00_enet_initialize(bis); +#endif + return 0; +} -- Regards, Zhizhou Zhang

2 1

[U-Boot] [Patch 4/16] add mips64/config.mk
by Zhi-zhou Zhang 16 Aug '12

16 Aug '12

diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk new file mode 100644 index 0000000..cec250a --- /dev/null +++ b/arch/mips/cpu/mips64/config.mk @@ -0,0 +1,36 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, <wd(a)denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Default optimization level for MIPS32 +# +# Note: Toolchains with binutils prior to v2.16 +# are no longer supported by U-Boot MIPS tree! +# +MIPSFLAGS = -march=mips64 + +ENDIANNESS = -EL + +MIPSFLAGS += $(ENDIANNESS) + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) -- Regards, Zhizhou Zhang

2 1

[U-Boot] [Patch 1/17] add mips64 build configuration in mips/config.mk
by Zhi-zhou Zhang 15 Aug '12

15 Aug '12

diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 6ab8acd..12df150 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -23,9 +23,13 @@ CROSS_COMPILE ?= mips_4KC- +ifeq "$(CPU)" "mips64" +CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff80200000 -T mips64.lds +PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ -DCONFIG_64BIT +else CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds - PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ +endif # # From Linux arch/mips/Makefile @@ -47,8 +51,16 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ # On the other hand, we want PIC in the U-Boot code to relocate it from ROM # to RAM. $28 is always used as gp. # +ifeq "$(CPU)" "mips64" +PLATFORM_CPPFLAGS += -G 0 -mabicalls -mabi=64 -fpic +PLATFORM_CPPFLAGS += -msoft-float +PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib -m elf64ltsmip +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +LDFLAGS_FINAL += --gc-sections +else PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic PLATFORM_CPPFLAGS += -msoft-float PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections LDFLAGS_FINAL += --gc-sections +endif -- Regards, Zhizhou Zhang

2 1

[U-Boot] [PATCH] mkconfig: add support for SPL CPU
by Allen Martin 15 Aug '12

15 Aug '12

Add support for specifying a differnt CPU for main u-boot and SPL u-boot builds. This is done by adding an optional SPL CPU after the main CPU in boards.cfg as follows: normal_cpu:spl_cpu This this case CPU will be set to "normal_cpu" during the main u-boot build and "spl_cpu" during the SPL build. Signed-off-by: Allen Martin <amartin(a)nvidia.com> --- This is part of my patch series to move all armv4t code out of tegra u-boot to an SPL. I haven't heard any suggestions on how to resolve having a different CPU for the SPL build, so this is my suggestion as a possible solution. boards.cfg | 5 +++++ doc/README.SPL | 12 ++++++++++++ mkconfig | 15 ++++++++++++++- 3 files changed, 31 insertions(+), 1 deletions(-) diff --git a/boards.cfg b/boards.cfg index 3cf75c3..a58cd02 100644 --- a/boards.cfg +++ b/boards.cfg @@ -11,6 +11,11 @@ # Lines starting with '#' are comments. # Blank lines are ignored. # +# The CPU field takes the form: +# cpu[:spl_cpu] +# If spl_cpu is specified the make variable CPU will be set to this +# during the SPL build. +# # The options field takes the form: # <board config name>[:comma separated config options] # Each config option has the form (value defaults to "1"): diff --git a/doc/README.SPL b/doc/README.SPL index 0276953..e4a5ac3 100644 --- a/doc/README.SPL +++ b/doc/README.SPL @@ -66,3 +66,15 @@ CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o) CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o) CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o) CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o) + + +Normally CPU is assumed to be the same between the SPL and normal +u-boot build. However it is possible to specify a different CPU for +the SPL build for cases where the SPL is expected to run on a +different CPU model from the main u-boot. This is done by specifying +an SPL CPU in boards.cfg as follows: + + normal_cpu:spl_cpu + +This this case CPU will be set to "normal_cpu" during the main u-boot +build and "spl_cpu" during the SPL build. diff --git a/mkconfig b/mkconfig index 438530b..82660a6 100755 --- a/mkconfig +++ b/mkconfig @@ -60,6 +60,11 @@ CONFIG_NAME="${1%_config}" arch="$2" cpu="$3" +tmp="${cpu#*:}" +if [ "$tmp" != "$cpu" ] ; then + spl_cpu=$tmp + cpu="${cpu%:*}" +fi if [ "$4" = "-" ] ; then board=${BOARD_NAME} else @@ -131,7 +136,15 @@ fi # Create include file for Make # echo "ARCH = ${arch}" > config.mk -echo "CPU = ${cpu}" >> config.mk +if [ ! -z "$spl_cpu" ] ; then + echo 'ifeq ($(CONFIG_SPL_BUILD),y)' >> config.mk + echo "CPU = ${spl_cpu}" >> config.mk + echo "else" >> config.mk + echo "CPU = ${cpu}" >> config.mk + echo "endif" >> config.mk +else + echo "CPU = ${cpu}" >> config.mk +fi echo "BOARD = ${board}" >> config.mk [ "${vendor}" ] && echo "VENDOR = ${vendor}" >> config.mk -- 1.7.5.4

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[U-Boot] [PATCH v8 00/15] split tegra20 arm7 code into separate SPL
by Allen Martin 15 Aug '12

15 Aug '12

This patch series fixes a long standing problem with the tegra20 u-boot build. Tegra20 contains an ARM7TDMI boot processor and a Cortex A9 main processor. Prior to this patch series this was accomplished by #ifdefing out any armv7 code from the early boot sequence and creating a single binary that runs on both both the ARM7TDMI and A9. This was very fragile as changes to compiler options or any additions or rearranging of the early boot code could add additional armv7 specific code causing it to fail on the ARM7TDMI. This patch series pulls all the armv4t code out into a separate SPL that does nothing more than initialize the A9 and transfer control to it. The resultint SPL and armv7 u-boot are concatenated together into a single image. This patch series is also available from: git://github.com/arm000/u-boot.git branch: tegra-spl-v8 Changes: v8: - rebased to u-boot-tegra/master - added changes to work with "arm: Provide lowlevel_init C function wrapper for v7" - Moved JTAG init in SPL to earlier - fixed TEXT_BASE in SPL to use SPL TEXT_BASE not main u-boot TEXT_BASE - pad exception handlers in arm720t to 64 bytes with 0x12345678 to match armv7 v7: - rebased to u-boot-tegra/next - added Acks and Tested-Bys v6: - changed combined SPL/u-boot target names to u-boot-dtb-tegra.bin and u-boot-nodtb-tegra.bin - fixed regression introduced in v5 that caused git bisect to fail to build at one of the patches - fix USE_PRIVATE_LIBGCC for SPL build and enable it - fix libtegra20-common.so link so it works if building with out of tree OBJDIR v5: - added missing mkdir rules in all tegra20 board Makefiles that include common code and changed them to be unconditional - make new u-boot-dtb-t2.bin rule default for tegra20 and copy resulting binary over u-boot.bin v4: - rebased to u-boot-tegra/next - reordered entire patch series to preserve git bisect, verified build and boot at each patch - merged patches that add SPL config defines and removes duplicate code from u-boot init, these have to go in atomically to preserve building at each patch - fixed compiler warnings introduced - fixed blank line at end of file on cpu.c - renamed u-boot.t2 to u-boot-t2.bin - cleaned up config.mk generation in mkconfig to make it more readable - added some text to clarify using arm720t code for arm7tdmi - rearranged SPL memory map to make resulting SPL + u-boot image much smaller - removed separate PAD_TO define in favor of just using CONFIG_SYS_TEXT_BASE - moved warmboot_save_sdram_params() from dram_init() to board_init() v3: - git bisect still does not work across this series, I'm saving that for the next revision, but I had enough changes that I wanted to get this out for review - expanded the tegra2 -> tegra20 rename to include functions/variables/ defines - rebased to u-boot-tegra/next - removed some extra -march=armv4t flags, kept armv4t flags on warmboot_avp since it's special - removed bashisms from mkconfig - renamed CONFIG_MACH_TEGRA_GENERIC to CONFIG_TEGRA - moved SPL overrides to tegra2-common-post.h - changed SPL base address to 0x108000, u-boot goes to 0x208000 - moved warboot_save_sdram_params fix to separate patch - remove USE_PRIVATE_LIBGCC from non SPL build - expanded SPL support to all tegra20 boards, not just seaboard v2: - renamed tegra2 to tegra20 to match kernel and devicetree naming policy - pulled all SPL related config overrides to a separate file to clean up ifdefs from seabard.h - rebased to TOT u-boot/master and fixed a bug related to init sequence changes between this patch series and new EMC code - made u-boot.t2 target work even if CONFIG_OF is disabled - added back USE_PRIVATE_LIBGCC Allen Martin (15): tegra20: rename tegra2 -> tegra20 tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-common tegra20: rename CONFIG_MACH_TEGRA_GENERIC tegra20: tec: add tegra20-common-post.h tegra20: make board mkdir commands unconditional mkconfig: add support for SPL CPU ARM: Fix arm720t SPL build tegra20: remove timer_init from SPL build ARM: add tegra20 support to arm720t tegra20: add u-boot-*-tegra.bin targets tegra20: move SDRAM param save to later in boot tegra20: enable SPL for tegra20 boards arm: enable libgcc build for SPL spl: fix SPL build of private libgcc tegra20: Remove armv4t build flags MAINTAINERS | 18 +-- Makefile | 26 ++++ arch/arm/cpu/arm720t/cpu.c | 2 + arch/arm/cpu/arm720t/interrupts.c | 5 + arch/arm/cpu/arm720t/start.S | 25 +++- arch/arm/cpu/{armv7 => arm720t/tegra20}/Makefile | 27 ++-- .../arch-tegra2 => cpu/arm720t/tegra20}/board.h | 11 +- .../{armv7/tegra2 => arm720t/tegra20}/config.mk | 12 -- .../{armv7/tegra2/ap20.c => arm720t/tegra20/cpu.c} | 148 ++------------------ .../ap20.h => cpu/arm720t/tegra20/cpu.h} | 15 +- arch/arm/cpu/arm720t/tegra20/spl.c | 133 ++++++++++++++++++ arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/start.S | 6 +- arch/arm/cpu/armv7/{tegra2 => tegra20}/Makefile | 15 +- .../cpu/armv7/{tegra2 => tegra20}/cmd_enterrcm.c | 4 +- arch/arm/cpu/armv7/{tegra2 => tegra20}/config.mk | 12 -- arch/arm/cpu/armv7/{tegra2 => tegra20}/usb.c | 2 +- .../cpu/{armv7/tegra2 => tegra20-common}/Makefile | 29 ++-- arch/arm/cpu/tegra20-common/ap20.c | 131 +++++++++++++++++ .../cpu/{armv7/tegra2 => tegra20-common}/board.c | 39 ++---- .../cpu/{armv7/tegra2 => tegra20-common}/clock.c | 10 +- .../cpu/{armv7/tegra2 => tegra20-common}/crypto.c | 0 .../cpu/{armv7/tegra2 => tegra20-common}/crypto.h | 0 .../arm/cpu/{armv7/tegra2 => tegra20-common}/emc.c | 2 +- .../cpu/{armv7/tegra2 => tegra20-common}/funcmux.c | 2 +- .../tegra2 => tegra20-common}/lowlevel_init.S | 0 .../cpu/{armv7/tegra2 => tegra20-common}/pinmux.c | 4 +- .../arm/cpu/{armv7/tegra2 => tegra20-common}/pmu.c | 2 +- .../{armv7/tegra2 => tegra20-common}/sys_info.c | 2 +- .../cpu/{armv7/tegra2 => tegra20-common}/timer.c | 2 +- .../{armv7/tegra2 => tegra20-common}/warmboot.c | 18 +-- .../tegra2 => tegra20-common}/warmboot_avp.c | 4 +- .../tegra2 => tegra20-common}/warmboot_avp.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/ap20.h | 4 +- .../asm/{arch-tegra2 => arch-tegra20}/apb_misc.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/board.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/clk_rst.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/clock.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/emc.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/flow.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/funcmux.h | 2 +- .../asm/{arch-tegra2 => arch-tegra20}/fuse.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/gp_padctrl.h | 2 +- .../asm/{arch-tegra2 => arch-tegra20}/gpio.h | 2 +- arch/arm/include/asm/arch-tegra20/hardware.h | 29 ++++ .../asm/{arch-tegra2 => arch-tegra20}/mmc.h | 8 +- .../asm/{arch-tegra2 => arch-tegra20}/pinmux.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/pmc.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/pmu.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/scu.h | 0 .../{arch-tegra2 => arch-tegra20}/sdram_param.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/sys_proto.h | 4 +- .../tegra2.h => arch-tegra20/tegra20.h} | 18 +-- .../asm/{arch-tegra2 => arch-tegra20}/tegra_i2c.h | 2 +- .../asm/{arch-tegra2 => arch-tegra20}/tegra_spi.h | 4 +- .../asm/{arch-tegra2 => arch-tegra20}/timer.h | 6 +- .../uart-spi-switch.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/uart.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/usb.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/warmboot.h | 0 arch/arm/lib/Makefile | 2 +- board/avionic-design/common/tamonten.c | 4 +- .../dts/{tegra2-medcom.dts => tegra20-medcom.dts} | 0 .../dts/{tegra2-plutux.dts => tegra20-plutux.dts} | 0 .../dts/{tegra2-tec.dts => tegra20-tec.dts} | 0 board/avionic-design/medcom/Makefile | 2 - board/avionic-design/plutux/Makefile | 2 - board/avionic-design/tec/Makefile | 2 - .../dts/{tegra2-paz00.dts => tegra20-paz00.dts} | 0 board/compal/paz00/Makefile | 2 - board/compal/paz00/paz00.c | 6 +- ...{tegra2-trimslice.dts => tegra20-trimslice.dts} | 0 board/compulab/trimslice/Makefile | 2 - board/compulab/trimslice/trimslice.c | 6 +- board/nvidia/common/board.c | 17 ++- board/nvidia/common/emc.c | 2 +- board/nvidia/common/uart-spi-switch.c | 2 +- .../{tegra2-harmony.dts => tegra20-harmony.dts} | 2 +- .../{tegra2-seaboard.dts => tegra20-seaboard.dts} | 0 .../{tegra2-ventana.dts => tegra20-ventana.dts} | 2 +- .../{tegra2-whistler.dts => tegra20-whistler.dts} | 2 +- board/nvidia/harmony/harmony.c | 6 +- board/nvidia/seaboard/seaboard.c | 6 +- board/nvidia/whistler/whistler.c | 6 +- boards.cfg | 23 +-- doc/README.SPL | 12 ++ drivers/gpio/tegra_gpio.c | 12 +- drivers/i2c/tegra_i2c.c | 12 +- drivers/input/Makefile | 2 +- drivers/mmc/tegra_mmc.c | 32 ++--- drivers/mmc/tegra_mmc.h | 12 +- drivers/spi/tegra_spi.c | 10 +- include/configs/harmony.h | 14 +- include/configs/medcom.h | 12 +- include/configs/paz00.h | 12 +- include/configs/plutux.h | 12 +- include/configs/seaboard.h | 20 +-- include/configs/tec.h | 12 +- ...{tegra2-common-post.h => tegra20-common-post.h} | 73 +++++++++- .../configs/{tegra2-common.h => tegra20-common.h} | 44 +++--- include/configs/trimslice.h | 14 +- include/configs/ventana.h | 12 +- include/configs/whistler.h | 14 +- include/fdtdec.h | 12 +- include/serial.h | 2 +- mkconfig | 25 ++-- spl/Makefile | 10 ++ 107 files changed, 755 insertions(+), 510 deletions(-) copy arch/arm/cpu/{armv7 => arm720t/tegra20}/Makefile (71%) copy arch/arm/{include/asm/arch-tegra2 => cpu/arm720t/tegra20}/board.h (81%) copy arch/arm/cpu/{armv7/tegra2 => arm720t/tegra20}/config.mk (73%) rename arch/arm/cpu/{armv7/tegra2/ap20.c => arm720t/tegra20/cpu.c} (63%) copy arch/arm/{include/asm/arch-tegra2/ap20.h => cpu/arm720t/tegra20/cpu.h} (93%) create mode 100644 arch/arm/cpu/arm720t/tegra20/spl.c copy arch/arm/cpu/armv7/{tegra2 => tegra20}/Makefile (69%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/cmd_enterrcm.c (94%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/config.mk (74%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/usb.c (99%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/Makefile (66%) create mode 100644 arch/arm/cpu/tegra20-common/ap20.c rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/board.c (79%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/clock.c (99%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/crypto.c (100%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/crypto.h (100%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/emc.c (99%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/funcmux.c (99%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/lowlevel_init.S (100%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/pinmux.c (99%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/pmu.c (98%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/sys_info.c (98%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/timer.c (98%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/warmboot.c (95%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/warmboot_avp.c (98%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/warmboot_avp.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/ap20.h (98%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/apb_misc.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/board.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/clk_rst.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/clock.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/emc.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/flow.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/funcmux.h (97%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/fuse.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/gp_padctrl.h (98%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/gpio.h (99%) create mode 100644 arch/arm/include/asm/arch-tegra20/hardware.h rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/mmc.h (84%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/pinmux.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/pmc.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/pmu.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/scu.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/sdram_param.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/sys_proto.h (93%) rename arch/arm/include/asm/{arch-tegra2/tegra2.h => arch-tegra20/tegra20.h} (87%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/tegra_i2c.h (99%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/tegra_spi.h (96%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/timer.h (92%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/uart-spi-switch.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/uart.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/usb.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/warmboot.h (100%) rename board/avionic-design/dts/{tegra2-medcom.dts => tegra20-medcom.dts} (100%) rename board/avionic-design/dts/{tegra2-plutux.dts => tegra20-plutux.dts} (100%) rename board/avionic-design/dts/{tegra2-tec.dts => tegra20-tec.dts} (100%) rename board/compal/dts/{tegra2-paz00.dts => tegra20-paz00.dts} (100%) rename board/compulab/dts/{tegra2-trimslice.dts => tegra20-trimslice.dts} (100%) rename board/nvidia/dts/{tegra2-harmony.dts => tegra20-harmony.dts} (92%) rename board/nvidia/dts/{tegra2-seaboard.dts => tegra20-seaboard.dts} (100%) rename board/nvidia/dts/{tegra2-ventana.dts => tegra20-ventana.dts} (92%) rename board/nvidia/dts/{tegra2-whistler.dts => tegra20-whistler.dts} (94%) rename include/configs/{tegra2-common-post.h => tegra20-common-post.h} (74%) rename include/configs/{tegra2-common.h => tegra20-common.h} (84%) -- 1.7.9.5

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[U-Boot] [PATCH 0/2]: arm: Provide lowlevel_init C function wrapper for v7
by Tom Rini 15 Aug '12

15 Aug '12

Hey all, As Allen Martin noted, on tegra platforms a bug is exposed when using certain toolchains that currently calls to lowlevel_init must be calls to another assembly function as the stack is not explicitly setup / saved and thus register corruption can occur. Over in TI-land Aneesh V wrote a lowlevel_init that sets up the stack and calls s_init which is a C function that does what lowlevel_init does on other platforms. The code is generic to at least v7, so this series moves it to arch/arm/cpu/armv7. The initial version of the code made use of LOW_LEVEL_SRAM_STACK as the stack to be setup. This define is essentially another name for CONFIG_SYS_INIT_SP_ADDR without taking GENERATED_GBL_DATA_SIZE into consideration. So we switch to that instead. Finally, Wolfgang question me as to if the stack really only needed the alignment that we had been giving it. To be safe, I grabbed the alignmnet that we do when setting up the initial stack for real and placed it into lowlevel_init as well. Tested on AM335x GP EVM and OMAP4 Pandaboard ES2. -- Tom

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