August 2012 - U-Boot

[U-Boot] [PATCH] net/phy: support the mv88e6352 switch
by Valentin Longchamp 28 Sep '12

28 Sep '12

This patch add support for the configuration of an external switch from the 88E6xxx series from Marvell trough an MDIO link using indirect adressing. This can be used if we do not want to use an EEPROM for the configuration. This driver is not generic and was not tested on other switches than the 88e6352. This is proposed as a first implementation that is somewhat limited but works and that can be used as a basis for further developments for this switch family. Signed-off-by: Valentin Longchamp <valentin.longchamp(a)keymile.com> cc: Holger Brunck <holger.brunck(a)keymile.com> cc: Prafulla Wadaskar <prafulla(a)marvell.com> cc: Joe Hershberger <joe.hershberger(a)gmail.com> --- drivers/net/phy/Makefile | 1 + drivers/net/phy/mv88e6352.c | 318 +++++++++++++++++++++++++++++++++++++++++++ include/mv88e6352.h | 92 +++++++++++++ 3 files changed, 411 insertions(+), 0 deletions(-) create mode 100644 drivers/net/phy/mv88e6352.c create mode 100644 include/mv88e6352.h diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index feced39..5e90d70 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libphy.o COBJS-$(CONFIG_BITBANGMII) += miiphybb.o COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o +COBJS-$(CONFIG_MV88E6352_SWITCH) += mv88e6352.o COBJS-$(CONFIG_PHYLIB) += phy.o COBJS-$(CONFIG_PHYLIB_10G) += generic_10g.o diff --git a/drivers/net/phy/mv88e6352.c b/drivers/net/phy/mv88e6352.c new file mode 100644 index 0000000..7269a6a --- /dev/null +++ b/drivers/net/phy/mv88e6352.c @@ -0,0 +1,318 @@ +/* + * (C) Copyright 2012 + * Valentin Lontgchamp, Keymile AG, valentin.longchamp(a)keymile.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/errno.h> +#include <mv88e6352.h> + +#define SMI_HDR ((0x8 | 0x1) << 12) +#define SMI_BUSY_MASK (0x8000) +#define SMIRD_OP (0x2 << 10) +#define SMIWR_OP (0x1 << 10) +#define SMI_MASK 0x1f +#define PORT_SHIFT 5 + +#define COMMAND_REG 0 +#define DATA_REG 1 + +/* global registers */ +#define GLOBAL 0x1b + +#define GLOBAL_STATUS 0x00 +#define PPU_STATE 0x8000 + +#define GLOBAL_CTRL 0x04 +#define SW_RESET 0x8000 +#define PPU_ENABLE 0x4000 + +static int sw_wait_rdy(const char *devname, u8 phy_addr) +{ + u16 command; + u32 timeout = 100; + int ret; + + /* wait till the SMI is not busy */ + do { + /* read command register */ + ret = miiphy_read(devname, phy_addr, COMMAND_REG, &command); + if (ret < 0) { + printf("%s: Error reading command register\n", + __func__); + return ret; + } + if (timeout-- == 0) { + printf("Err..(%s) SMI busy timeout\n", __func__); + return -EFAULT; + } + } while (command & SMI_BUSY_MASK); + + return 0; +} + +static int sw_reg_read(const char *devname, u8 phy_addr, u8 port, + u8 reg, u16 *data) +{ + int ret; + u16 command; + + ret = sw_wait_rdy(devname, phy_addr); + if (ret) + return ret; + + command = SMI_HDR | SMIRD_OP | ((port&SMI_MASK) << PORT_SHIFT) | + (reg & SMI_MASK); + debug("%s: write to command: %#x\n", __func__, command); + ret = miiphy_write(devname, phy_addr, COMMAND_REG, command); + if (ret) + return ret; + + ret = sw_wait_rdy(devname, phy_addr); + if (ret) + return ret; + + ret = miiphy_read(devname, phy_addr, DATA_REG, data); + + return ret; +} + +static int sw_reg_write(const char *devname, u8 phy_addr, u8 port, + u8 reg, u16 data) +{ + int ret; + u16 value; + + ret = sw_wait_rdy(devname, phy_addr); + if (ret) + return ret; + + debug("%s: write to data: %#x\n", __func__, data); + ret = miiphy_write(devname, phy_addr, DATA_REG, data); + if (ret) + return ret; + + value = SMI_HDR | SMIWR_OP | ((port & SMI_MASK) << PORT_SHIFT) | + (reg & SMI_MASK); + debug("%s: write to command: %#x\n", __func__, value); + ret = miiphy_write(devname, phy_addr, COMMAND_REG, value); + if (ret) + return ret; + + ret = sw_wait_rdy(devname, phy_addr); + if (ret) + return ret; + + return 0; +} + +static int ppu_enable(const char *devname, u8 phy_addr) +{ + int i, ret = 0; + u16 reg; + + ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, &reg); + if (ret) { + printf("%s: Error reading global ctrl reg\n", __func__); + return ret; + } + + reg |= PPU_ENABLE; + + ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg); + if (ret) { + printf("%s: Error writing global ctrl reg\n", __func__); + return ret; + } + + for (i = 0; i < 1000; i++) { + sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS, + &reg); + if ((reg & 0xc000) == 0xc000) + return 0; + udelay(1000); + } + + return -ETIMEDOUT; +} + +static int ppu_disable(const char *devname, u8 phy_addr) +{ + int i, ret = 0; + u16 reg; + + ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, &reg); + if (ret) { + printf("%s: Error reading global ctrl reg\n", __func__); + return ret; + } + + reg &= ~PPU_ENABLE; + + ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg); + if (ret) { + printf("%s: Error writing global ctrl reg\n", __func__); + return ret; + } + + for (i = 0; i < 1000; i++) { + sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS, + &reg); + if ((reg & 0xc000) != 0xc000) + return 0; + udelay(1000); + } + + return -ETIMEDOUT; +} + +int mv88e_sw_program(const char *devname, u8 phy_addr, + struct mv88e_sw_reg *regs, int regs_nb) +{ + int i, ret = 0; + + /* first we need to disable the PPU */ + ret = ppu_disable(devname, phy_addr); + if (ret) { + printf("%s: Error disabling PPU\n", __func__); + return ret; + } + + for (i = 0; i < regs_nb; i++) { + ret = sw_reg_write(devname, phy_addr, regs[i].port, + regs[i].reg, regs[i].value); + if (ret) { + printf("%s: Error configuring switch\n", __func__); + ppu_enable(devname, phy_addr); + return ret; + } + } + + /* re-enable the PPU */ + ret = ppu_enable(devname, phy_addr); + if (ret) { + printf("%s: Error enabling PPU\n", __func__); + return ret; + } + + return 0; +} + +int mv88e_sw_reset(const char *devname, u8 phy_addr) +{ + int i, ret = 0; + u16 reg; + + ret = sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, &reg); + if (ret) { + printf("%s: Error reading global ctrl reg\n", __func__); + return ret; + } + + reg = SW_RESET | PPU_ENABLE | 0x0400; + + ret = sw_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg); + if (ret) { + printf("%s: Error writing global ctrl reg\n", __func__); + return ret; + } + + for (i = 0; i < 1000; i++) { + sw_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS, + &reg); + if ((reg & 0xc800) != 0xc800) + return 0; + udelay(1000); + } + + return -ETIMEDOUT; +} + +int do_mvsw_reg_read(const char *name, int argc, char * const argv[]) +{ + u16 value = 0, phyaddr, reg, port; + int ret; + + phyaddr = simple_strtoul(argv[1], NULL, 10); + port = simple_strtoul(argv[2], NULL, 10); + reg = simple_strtoul(argv[3], NULL, 10); + + ret = sw_reg_read(name, phyaddr, port, reg, &value); + printf("%#x\n", value); + + return ret; +} + +int do_mvsw_reg_write(const char *name, int argc, char * const argv[]) +{ + u16 value = 0, phyaddr, reg, port; + int ret; + + phyaddr = simple_strtoul(argv[1], NULL, 10); + port = simple_strtoul(argv[2], NULL, 10); + reg = simple_strtoul(argv[3], NULL, 10); + value = simple_strtoul(argv[4], NULL, 16); + + ret = sw_reg_write(name, phyaddr, port, reg, value); + + return ret; +} + + +int do_mvsw_reg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int ret; + const char *cmd, *ethname; + + if (argc < 2) + return cmd_usage(cmdtp); + + cmd = argv[1]; + --argc; + ++argv; + + if (strcmp(cmd, "read") == 0) { + if (argc < 5) + return cmd_usage(cmdtp); + ethname = argv[1]; + --argc; + ++argv; + ret = do_mvsw_reg_read(ethname, argc, argv); + } else if (strcmp(cmd, "write") == 0) { + if (argc < 6) + return cmd_usage(cmdtp); + ethname = argv[1]; + --argc; + ++argv; + ret = do_mvsw_reg_write(ethname, argc, argv); + } else + return cmd_usage(cmdtp); + + return ret; +} + +U_BOOT_CMD( + mvsw_reg, 7, 1, do_mvsw_reg, + "marvell 88e6352 switch register access", + "write ethname phyaddr port reg value\n" + "mvsw_reg read ethname phyaddr port reg\n" + ); diff --git a/include/mv88e6352.h b/include/mv88e6352.h new file mode 100644 index 0000000..cdc4db7 --- /dev/null +++ b/include/mv88e6352.h @@ -0,0 +1,92 @@ +/* + * (C) Copyright 2012 + * Valentin Lontgchamp, Keymile AG, valentin.longchamp(a)keymile.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __MV886352_H +#define __MV886352_H + +#include <common.h> + +/* PHY registers */ +#define PHY(itf) (itf) + +#define PHY_CTRL 0x00 +#define PHY_100_MBPS 0x2000 +#define PHY_1_GBPS 0x0040 +#define AUTONEG_EN 0x1000 +#define AUTONEG_RST 0x0200 +#define FULL_DUPLEX 0x0100 +#define PHY_PWR_DOWN 0x0800 + +#define PHY_STATUS 0x01 +#define AN1000FIX 0x0001 + +#define PHY_SPEC_CTRL 0x10 +#define SPEC_PWR_DOWN 0x0004 +#define AUTO_MDIX_EN 0x0060 + +#define PHY_1000_CTRL 0x9 + +#define NO_ADV 0x0000 +#define ADV_1000_FDPX 0x0200 +#define ADV_1000_HDPX 0x0100 + +#define PHY_PAGE 0x16 + +#define AN1000FIX_PAGE 0x00fc + +/* PORT or MAC registers */ +#define PORT(itf) (itf+0x10) + +#define PORT_STATUS 0x00 +#define NO_PHY_DETECT 0x0000 + +#define PORT_PHY 0x01 +#define RX_RGMII_TIM 0x8000 +#define TX_RGMII_TIM 0x4000 +#define FLOW_CTRL_EN 0x0080 +#define FLOW_CTRL_FOR 0x0040 +#define LINK_VAL 0x0020 +#define LINK_FOR 0x0010 +#define FULL_DPX 0x0008 +#define FULL_DPX_FOR 0x0004 +#define NO_SPEED_FOR 0x0003 +#define SPEED_1000_FOR 0x0002 +#define SPEED_100_FOR 0x0001 +#define SPEED_10_FOR 0x0000 + +#define PORT_CTRL 0x04 +#define FORWARDING 0x0003 +#define EGRS_FLD_ALL 0x000c +#define PORT_DIS 0x0000 + +struct mv88e_sw_reg { + u8 port; + u8 reg; + u16 value; +}; + +int mv88e_sw_reset(const char *devname, u8 phy_addr); +int mv88e_sw_program(const char *devname, u8 phy_addr, + struct mv88e_sw_reg *regs, int regs_nb); + +#endif -- 1.7.1

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[U-Boot] [PATCH] eth_write_hwaddr: Return error for invalid MACs
by Benoît Thébaudeau 28 Sep '12

28 Sep '12

If dev->enetaddr was supposed to be set with dev->write_hwaddr() but the MAC address was not valid, return an error. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau(a)advansee.com> Cc: Joe Hershberger <joe.hershberger(a)gmail.com> --- {u-boot-4d3c95f.orig => u-boot-4d3c95f}/net/eth.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git u-boot-4d3c95f.orig/net/eth.c u-boot-4d3c95f/net/eth.c index 1a11ce1..174361f 100644 --- u-boot-4d3c95f.orig/net/eth.c +++ u-boot-4d3c95f/net/eth.c @@ -222,9 +222,12 @@ int eth_write_hwaddr(struct eth_device *dev, const char *base_name, } if (dev->write_hwaddr && - !eth_mac_skip(eth_number) && - is_valid_ether_addr(dev->enetaddr)) + !eth_mac_skip(eth_number)) { + if (!is_valid_ether_addr(dev->enetaddr)) + return -1; + ret = dev->write_hwaddr(dev); + } return ret; }

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[U-Boot] [PATCHv2 0/5] net: ASIX AX88772B enablement
by Lucas Stach 28 Sep '12

28 Sep '12

Hi all, This series supersedes the earlier posted patches to support the AX88772B chip. I've split this up into a series as what started as a small patch to get the chip working turned into a journey through the usbeth stack and now not only reworks a lot of the ASIX code, but also touches other parts of the stack. I want to thank Marek, Joe and Mike for their review, valueable feedback and guidance. I've verified that we are now actually able to override the MAC address from the environment. All review feedback so far has been incorporated. v2: Hopefully last round of this patches. - drop patch 2 - it's not a good idea - use correct malloc includes - introduce flags in the correct patches - now really constify asix_dongles[] Lucas Stach (5): net: introduce transparent driver private in ueth_data net: asix: split out basic reset function net: asix: add write_hwaddr function net: asix: add read_mac function net: asix: add AX88772B support drivers/usb/eth/asix.c | 180 ++++++++++++++++++++++++++++++++------------- drivers/usb/eth/smsc95xx.c | 48 ++++++++---- include/usb_ether.h | 8 +- 3 files changed, 165 insertions(+), 71 deletions(-) -- 1.7.11.4

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[U-Boot] [PATCH] net: sh_eth: Add support R8A7740 of rmobile (arm core)
by Nobuhiro Iwamatsu 28 Sep '12

28 Sep '12

R8A7740 of rmobile has ethernet device, and this is same IP of sh-ether. This support R8A7740 of rmobile. Signed-off-by: Hideyuki Sano <hideyuki.sano.dn(a)renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> --- drivers/net/sh_eth.c | 2 +- drivers/net/sh_eth.h | 14 ++++++++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 09af860..2d9cc32 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -394,7 +394,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER); #endif -#if defined(CONFIG_CPU_SH7734) +#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); #endif /* Configure phy */ diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 3703c55..61d2df9 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -1,8 +1,8 @@ /* * sh_eth.h - Driver for Renesas SuperH ethernet controler. * - * Copyright (C) 2008, 2011 Renesas Solutions Corp. - * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu + * Copyright (C) 2008 - 2012 Renesas Solutions Corp. + * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu * Copyright (c) 2007 Carlos Munoz <carlos(a)kenati.com> * * This program is free software; you can redistribute it and/or modify @@ -25,6 +25,7 @@ #define SHETHER_NAME "sh_eth" +#if defined(CONFIG_SH) /* Malloc returns addresses in the P1 area (cacheable). However we need to use area P2 (non-cacheable) */ #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000)) @@ -35,6 +36,12 @@ #else #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000) #endif +#elif defined(CONFIG_ARM) +#define inl readl +#define outl writel +#define ADDR_TO_PHY(addr) ((int)(addr)) +#define ADDR_TO_P2(addr) (addr) +#endif /* defined(CONFIG_SH) */ /* Number of supported ports */ #define MAX_PORT_NUM 2 @@ -292,6 +299,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { #elif defined(CONFIG_CPU_SH7724) #define SH_ETH_TYPE_ETHER #define BASE_IO_ADDR 0xA4600000 +#elif defined(CONFIG_R8A7740) +#define SH_ETH_TYPE_GETHER +#define BASE_IO_ADDR 0xE9A00000 #endif /* -- 1.7.10

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[U-Boot] [PATCH] dm: net: Fixup the armada100 FEC driver
by Marek Vasut 28 Sep '12

28 Sep '12

Apply the following questionable adjustment to silence GCC. armada100_fec.c: In function ‘armdfec_send’: armada100_fec.c:589:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Joe Hershberger <joe.hershberger(a)ni.com> --- drivers/net/armada100_fec.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c index d318a36..ed7cf20 100644 --- a/drivers/net/armada100_fec.c +++ b/drivers/net/armada100_fec.c @@ -565,7 +565,7 @@ static int armdfec_send(struct eth_device *dev, void *dataptr, int datasize) struct tx_desc *p_txdesc = darmdfec->p_txdesc; void *p = (void *)dataptr; int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS; - u32 cmd_sts; + u32 cmd_sts, temp; /* Copy buffer if it's misaligned */ if ((u32)dataptr & 0x07) { @@ -586,7 +586,8 @@ static int armdfec_send(struct eth_device *dev, void *dataptr, int datasize) p_txdesc->byte_cnt = datasize; /* Apply send command using high priority TX queue */ - writel((u32)p_txdesc, &regs->txcdp[TXQ]); + temp = (u32)&regs->txcdp[TXQ]; + writel((u32)p_txdesc, temp); writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, &regs->sdma_cmd); /* -- 1.7.10.4

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[U-Boot] [PATCH 1/5] microblaze: Add gpio.h
by Michal Simek 28 Sep '12

28 Sep '12

Gpio support is not implemented yet. Adding it because of fdtdec. Signed-off-by: Michal Simek <monstr(a)monstr.eu> --- arch/microblaze/include/asm/gpio.h | 41 ++++++++++++++++++++++++++++++++++++ 1 files changed, 41 insertions(+), 0 deletions(-) create mode 100644 arch/microblaze/include/asm/gpio.h diff --git a/arch/microblaze/include/asm/gpio.h b/arch/microblaze/include/asm/gpio.h new file mode 100644 index 0000000..883f4d4 --- /dev/null +++ b/arch/microblaze/include/asm/gpio.h @@ -0,0 +1,41 @@ +#ifndef _ASM_MICROBLAZE_GPIO_H_ +#define _ASM_MICROBLAZE_GPIO_H_ + +#include <asm/io.h> + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +static inline int gpio_free(unsigned gpio) +{ + return 0; +} + +static inline int gpio_direction_input(unsigned gpio) +{ + return 0; +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + return 0; +} + +static inline int gpio_get_value(unsigned gpio) +{ + return 0; +} + +static inline int gpio_set_value(unsigned gpio, int value) +{ + return 0; +} + +static inline int gpio_is_valid(int number) +{ + return 0; +} +#endif + -- 1.7.0.4

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[U-Boot] [PATCH] net: bugfix: NetSetTimeout assumes CONFIG_SYS_HZ=1000
by Tetsuyuki Kobayashi 28 Sep '12

28 Sep '12

NetSetTimeout sets incorrect value to timeDelta when CONFIG_SYS_HZ != 1000. Signed-off-by: Tetsuyuki Kobayashi <koba(a)kmckk.co.jp> --- net/net.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/net.c b/net/net.c index 9de7d92..ac9c2c8 100644 --- a/net/net.c +++ b/net/net.c @@ -653,7 +653,7 @@ NetSetTimeout(ulong iv, thand_f *f) "--- NetLoop timeout handler set (%p)\n", f); timeHandler = f; timeStart = get_timer(0); - timeDelta = iv; + timeDelta = iv * CONFIG_SYS_HZ / 1000; } } -- 1.7.9.5

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[U-Boot] [PATCH] api: net: fix length check in eth_receive()
by Michael Walle 28 Sep '12

28 Sep '12

If the requested length is too small to hold the received packet, eth_receive() will return -1 and will leave the packet in the receive buffers. Instead of returning an error in this case, we return the first portion of the received packet and remove it from the receive buffers. This fixes FreeBSD's ubldr. Without this patch it will just stop receiving packets if the NIC receives more than PKTBUFSRX too large packets. Signed-off-by: Michael Walle <michael(a)walle.cc> Cc: Joe Hershberger <joe.hershberger(a)gmail.com> Cc: Rafal Jaworowski <raj(a)semihalf.com> Cc: Piotr Kruszynski <ppk(a)semihalf.com> --- net/eth.c | 5 +---- 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/net/eth.c b/net/eth.c index d526264..09249c9 100644 --- a/net/eth.c +++ b/net/eth.c @@ -486,10 +486,7 @@ int eth_receive(void *packet, int length) return -1; } - if (length < eth_rcv_bufs[eth_rcv_current].length) - return -1; - - length = eth_rcv_bufs[eth_rcv_current].length; + length = min(eth_rcv_bufs[eth_rcv_current].length, length); for (i = 0; i < length; i++) p[i] = eth_rcv_bufs[eth_rcv_current].data[i]; -- 1.7.2.5

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[U-Boot] [PATCH 0/4] arm:samsung: Cleanup code for trats and universal boards
by Piotr Wilczek 28 Sep '12

28 Sep '12

This patch fixes SDRAM configuration and size visibility for trats board. Common code is set for trats and universal boards. Low level initialisation in U-boot is eliminated for universal_c210 board. Piotr Wilczek (4): arm:exynos4:trats: Correct SDRAM configuration for trats arm:exynos4:trats: Fix SDRAM size arm:exynos4:trats&universal_c210: Set common code for trats and universal_c210 boards arm:exynos4:universal_c210: Eliminate low level initialisation board/samsung/exynos4_common/exynos4_common.c | 139 +++++++++ board/samsung/trats/trats.c | 98 +------ board/samsung/universal_c210/Makefile | 1 - board/samsung/universal_c210/lowlevel_init.S | 395 ------------------------- board/samsung/universal_c210/universal.c | 105 +------ include/configs/s5pc210_universal.h | 2 + include/configs/trats.h | 17 +- 7 files changed, 163 insertions(+), 594 deletions(-) create mode 100644 board/samsung/exynos4_common/exynos4_common.c delete mode 100644 board/samsung/universal_c210/lowlevel_init.S -- 1.7.5.4

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[U-Boot] [PATCH 0/2] arm/km: configuration of the mv88e6352 switch on kmnusa
by Valentin Longchamp 28 Sep '12

28 Sep '12

This series adds supoort for the configuration of the mv88e6352 external switch on kmnusa. It has a clear dependancy to the minimal mv88e6352 net/phy driver: http://patchwork.ozlabs.org/patch/177953/ Valentin Longchamp (2): arm/km: add mv88e6352 configuration for kmnusa km_kirkwood: enable MV88E6352_SWITCH support for kmnusa board/keymile/km_arm/km_arm.c | 63 +++++++++++++++++++++++++++++++++++++++++ include/configs/km_kirkwood.h | 2 + 2 files changed, 65 insertions(+), 0 deletions(-)

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