July 2012 - U-Boot

[U-Boot] [PATCH u-boot-arm/next 1/2] OMAP3: igep00x0: Add config option to choose flash storage memory
by Javier Martinez Canillas 17 Jul '12

17 Jul '12

IGEP-based boards can have two different flash memories, a OneNAND or a NAND device. Add a configuration option for to choose which memory to use. Signed-off-by: Javier Martinez Canillas <javier(a)dowhile0.org> --- board/isee/igep0020/igep0020.h | 4 ++++ board/isee/igep0030/igep0030.h | 4 ++++ boards.cfg | 6 ++++-- include/configs/igep00x0.h | 19 +++++++++++++++++++ 4 files changed, 31 insertions(+), 2 deletions(-) diff --git a/board/isee/igep0020/igep0020.h b/board/isee/igep0020/igep0020.h index 3d6e15f..3335ecc 100644 --- a/board/isee/igep0020/igep0020.h +++ b/board/isee/igep0020/igep0020.h @@ -26,7 +26,11 @@ const omap3_sysinfo sysinfo = { DDR_STACKED, "IGEP v2 board", +#if defined(CONFIG_ENV_IS_IN_ONENAND) "ONENAND", +#else + "NAND", +#endif }; static void setup_net_chip(void); diff --git a/board/isee/igep0030/igep0030.h b/board/isee/igep0030/igep0030.h index b7ce5aa..a93339d 100644 --- a/board/isee/igep0030/igep0030.h +++ b/board/isee/igep0030/igep0030.h @@ -26,7 +26,11 @@ const omap3_sysinfo sysinfo = { DDR_STACKED, "OMAP3 IGEP module", +#if defined(CONFIG_ENV_IS_IN_ONENAND) "ONENAND", +#else + "NAND", +#endif }; /* diff --git a/boards.cfg b/boards.cfg index 9efdc6d..7463896 100644 --- a/boards.cfg +++ b/boards.cfg @@ -224,8 +224,10 @@ cm_t35 arm armv7 cm_t35 - omap3_overo arm armv7 overo - omap3 omap3_pandora arm armv7 pandora - omap3 dig297 arm armv7 dig297 comelit omap3 -igep0020 arm armv7 igep0020 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020 -igep0030 arm armv7 igep0030 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030 +igep0020 arm armv7 igep0020 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND +igep0020_nand arm armv7 igep0020 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND +igep0030 arm armv7 igep0030 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND +igep0030_nand arm armv7 igep0030 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND am3517_evm arm armv7 am3517evm logicpd omap3 mt_ventoux arm armv7 mt_ventoux teejet omap3 omap3_zoom1 arm armv7 zoom1 logicpd omap3 diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index a0a23a7..d8e87c3 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -105,7 +105,12 @@ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_I2C /* I2C serial bus support */ #define CONFIG_CMD_MMC /* MMC support */ +#ifdef CONFIG_BOOT_ONENAND #define CONFIG_CMD_ONENAND /* ONENAND support */ +#endif +#ifdef CONFIG_BOOT_NAND +#define CONFIG_CMD_NAND +#endif #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING @@ -244,6 +249,7 @@ * FLASH and environment organization */ +#ifdef CONFIG_BOOT_ONENAND #define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */ #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP @@ -253,6 +259,19 @@ #define CONFIG_ENV_IS_IN_ONENAND 1 #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ #define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET +#endif + +#ifdef CONFIG_BOOT_NAND +#define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_BASE NAND_BASE +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ +#define CONFIG_ENV_ADDR NAND_ENV_OFFSET +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#endif /* * Size of malloc() pool -- 1.7.7.6

2 3

[U-Boot] [PATCH] fsl: board EEPROM has the CRC in the wrong location
by Timur Tabi 17 Jul '12

17 Jul '12

The NXID v1 EEPROM format has the CRC at offset 0xFC, but for some reason it was placed at address 0xCC instead. To retain compatibility with existing boards, we check the CRC in the old location if necessary. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- board/freescale/common/sys_eeprom.c | 28 ++++++++++++++++++++++++++-- 1 files changed, 26 insertions(+), 2 deletions(-) diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index d2ed036..2541dd2 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -34,8 +34,16 @@ #endif #ifdef CONFIG_SYS_I2C_EEPROM_NXID -#define MAX_NUM_PORTS 23 +#define MAX_NUM_PORTS 31 #define NXID_VERSION 1 + +/* + * Older versions of this code incorrectly placed the CRC at offset 0xCC, + * when it should have been at 0xFC. To maintain compatibility with boards + * that have the CRC at 0xCC, we check for the CRC at 0xCC if it's not in + * 0xFC. + */ +#define BROKEN_CRC_OFFSET 0xCC #endif /** @@ -71,7 +79,7 @@ static struct __attribute__ ((__packed__)) eeprom { u8 mac_count; /* 0x40 Number of MAC addresses */ u8 mac_flag; /* 0x41 MAC table flags */ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */ - u32 crc; /* x+1 CRC32 checksum */ + u32 crc; /* 0xFC CRC32 checksum */ #endif } e; @@ -457,6 +465,22 @@ int mac_read_from_eeprom(void) crc = crc32(0, (void *)&e, crc_offset); crcp = (void *)&e + crc_offset; +#ifdef BROKEN_CRC_OFFSET + /* + * If the CRC is wrong, then check the old location. If it contains a + * valid CRC, then assume that this is an older EEPROM. We update the + * real CRC so that the EEPROM looks valid. + */ + if ((e.version == NXID_VERSION) && (crc != be32_to_cpup(crcp))) { + u32 crc2 = crc32(0, (void *)&e, BROKEN_CRC_OFFSET); + void *crcp2 = (void *)&e + BROKEN_CRC_OFFSET; + + if (crc2 == be32_to_cpup(crcp2)) { + debug("Broken NXID v1 CRC found and corrected\n"); + update_crc(); + } + } +#endif if (crc != be32_to_cpu(*crcp)) { printf("CRC mismatch (%08x != %08x)\n", crc, be32_to_cpu(e.crc)); return -1; -- 1.7.3.4

7 30

[U-Boot] [PATCH v2] i.MX28: Check if we are using a valid VBUS for power initialization
by Otavio Salvador 16 Jul '12

16 Jul '12

Signed-off-by: Otavio Salvador <otavio(a)ossystems.com.br> --- Changes in v2: - add comments - fix when we have vbus OR vdd5v - improve patch short description arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c index 4b09b0c..fdf810c 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c @@ -564,6 +564,15 @@ void mx28_batt_boot(void) 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); } +static int mx28_valid_vbus(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* iMX23 uses POWER_STS_VBUSVALID_STATUS at same offset */ + return readl(&power_regs->hw_power_sts) & POWER_STS_VBUSVALID0_STATUS; +} + void mx28_handle_5v_conflict(void) { struct mx28_power_regs *power_regs = @@ -577,14 +586,19 @@ void mx28_handle_5v_conflict(void) tmp = readl(&power_regs->hw_power_sts); if (tmp & POWER_STS_VDDIO_BO) { + /* + * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes + * unreliable + */ mx28_powerdown(); break; } - if (tmp & POWER_STS_VDD5V_GT_VDDIO) { + if (mx28_valid_vbus() || (tmp & POWER_STS_VDD5V_GT_VDDIO)) { mx28_boot_valid_5v(); break; } else { + /* Neither 5v sees 5v so we power down */ mx28_powerdown(); break; } @@ -601,17 +615,15 @@ void mx28_5v_boot(void) struct mx28_power_regs *power_regs = (struct mx28_power_regs *)MXS_POWER_BASE; - /* - * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID, - * but their implementation always returns 1 so we omit it here. - */ - if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + if (mx28_valid_vbus() && + (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO)) { mx28_boot_valid_5v(); return; } early_delay(1000); - if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + if (mx28_valid_vbus() && + (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO)) { mx28_boot_valid_5v(); return; } -- 1.7.10.4

2 2

[U-Boot] DaVinci PHYs
by Marek Vasut 16 Jul '12

16 Jul '12

Hi guys, is there any hope the ad-hoc implementation of davinci emac PHYs will ever be flipped to phylib ? Thanks! Best regards, Marek Vasut

3 5

[U-Boot] [PATCH 00/20] updates for Keymile Marvell boards
by Valentin Longchamp 16 Jul '12

16 Jul '12

This series adds support for 2 new Kirkwood boards at Keymile: kmnusa and kmcoge5un. All the previously supported boards that had a proper config file now are all supported by the generic km_kirkwood.h config file. This series also adds support for the environment variables in the SPI NOR Flash, for a skippable FPGA download through the BOCO2 CPLD, and for the configuration of a managed Marvell switch that is used on kmnusa. This series also corrects a bug caused by accessing global static tables in board_early_init_f that is called before relocation which must be avoided. Holger Brunck (6): arm/km: add kmnusa board support arm/km: add kmcoge5un board support arm/km: convert mgcoge3un target to km_kirkwood arm/km: remove portl2.h and use km_kirkwood instead arm/km: cleanup km_kirkwood boards arm/km: remove spi toggle command Thomas Herzmann (2): arm/km: add implementation for read_dip_switch arm/km: fix testpin detection for kmcoge5un Valentin Longchamp (12): arm/km: enable spi claim bus arm/km: use correct kw_gpio function for NAND/SPI switching arm/kirkwood: protect the ENV_SPI #defines arm/km: correct init of 88e6352 switch in the reset_phy function arm/km: enable BOCO2 FPGA download support arm/km: redefine piggy 4 reg names to avoid conflicts arm/km: add support for external switch configuration arm/km: enable external switch configuration for kmnusa arm/km: skip FPGA config when already configured arm/km: support the 2 PCIe fpga resets arm/km: implement weak function board_spi_clam_bus/release arm/km: remove calls to kw_gpio_* in board_early_init_f MAINTAINERS | 2 + arch/arm/include/asm/arch-kirkwood/config.h | 12 +- board/keymile/common/common.h | 5 + board/keymile/km_arm/128M16-1.cfg | 294 +++++++++++++++++++++++++ board/keymile/km_arm/256M8-1.cfg | 296 +++++++++++++++++++++++++ board/keymile/km_arm/Makefile | 8 + board/keymile/km_arm/fpga_config.c | 256 ++++++++++++++++++++++ board/keymile/km_arm/km_arm.c | 169 +++++++++------ board/keymile/km_arm/managed_switch.c | 316 +++++++++++++++++++++++++++ board/keymile/km_arm/managed_switch.h | 106 +++++++++ boards.cfg | 10 +- include/configs/km/km_arm.h | 57 ++++- include/configs/km_kirkwood.h | 154 ++++++++++++- include/configs/mgcoge3un.h | 87 -------- include/configs/portl2.h | 85 ------- 15 files changed, 1583 insertions(+), 274 deletions(-) create mode 100644 board/keymile/km_arm/128M16-1.cfg create mode 100644 board/keymile/km_arm/256M8-1.cfg create mode 100644 board/keymile/km_arm/fpga_config.c create mode 100644 board/keymile/km_arm/managed_switch.c create mode 100644 board/keymile/km_arm/managed_switch.h delete mode 100644 include/configs/mgcoge3un.h delete mode 100644 include/configs/portl2.h

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[U-Boot] [PATCH 1/3 V2] MX28: SPI: Refactor spi_xfer a bit
by Marek Vasut 16 Jul '12

16 Jul '12

This makes it easier to adapt for addition of DMA support. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Otavio Salvador <otavio(a)ossystems.com.br> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Wolfgang Denk <wd(a)denx.de> --- drivers/spi/mxs_spi.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) V2: Kill the if-elseif-elseif-else chain diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 7859536..a21b02b 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -146,21 +146,33 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); struct mx28_ssp_regs *ssp_regs = mxs_slave->regs; int len = bitlen / 8; - const char *tx = dout; - char *rx = din; char dummy; + int write = 0; + char *data = NULL; if (bitlen == 0) { if (flags & SPI_XFER_END) { - rx = &dummy; + din = (void *)&dummy; len = 1; } else return 0; } - if (!rx && !tx) + /* Half-duplex only */ + if (din && dout) + return -EINVAL; + /* No data */ + if (!din && !dout) return 0; + if (dout) { + data = (char *)dout; + write = 1; + } else if (din) { + data = (char *)din; + write = 0; + } + if (flags & SPI_XFER_BEGIN) mxs_spi_start_xfer(ssp_regs); @@ -171,7 +183,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, if ((flags & SPI_XFER_END) && !len) mxs_spi_end_xfer(ssp_regs); - if (tx) + if (write) writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr); else writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set); @@ -184,20 +196,20 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, return -ETIMEDOUT; } - if (tx) - writel(*tx++, &ssp_regs->hw_ssp_data); + if (write) + writel(*data++, &ssp_regs->hw_ssp_data); writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set); - if (rx) { + if (!write) { if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_status_reg, SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) { printf("MXS SPI: Timeout waiting for data\n"); return -ETIMEDOUT; } - *rx = readl(&ssp_regs->hw_ssp_data); - rx++; + *data = readl(&ssp_regs->hw_ssp_data); + data++; } if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg, -- 1.7.10.4

2 5

[U-Boot] [PATCH v2 1/2] imx: Use a clear identification of an unidentified CPU type
by Otavio Salvador 16 Jul '12

16 Jul '12

In case an unidentified CPU type is detected it now returns i.MX??, in a const char. Signed-off-by: Otavio Salvador <otavio(a)ossystems.com.br> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes for v2: * use i.MX?? for unidentified CPU type arch/arm/cpu/armv7/imx-common/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c index b3195dd..e7bd0bf 100644 --- a/arch/arm/cpu/armv7/imx-common/cpu.c +++ b/arch/arm/cpu/armv7/imx-common/cpu.c @@ -66,7 +66,7 @@ char *get_reset_cause(void) #if defined(CONFIG_DISPLAY_CPUINFO) -static char *get_imx_type(u32 imxtype) +static const char *get_imx_type(u32 imxtype) { switch (imxtype) { case 0x63: @@ -80,7 +80,7 @@ static char *get_imx_type(u32 imxtype) case 0x53: return "53"; default: - return "unknown"; + return "??"; } } -- 1.7.10

2 4

[U-Boot] [PATCH] kirkwood: add support for Iomega iConnect board
by Luka Perkov 16 Jul '12

16 Jul '12

Add support for new board iConnect from Iomega. More information about the device can be found here: http://go.iomega.com/en/products/network-storage-desktop/wireless-data-stat… Signed-off-by: Luka Perkov <uboot(a)lukaperkov.net> Tested-by: Wojciech Dubowik <wojciech.dubowik(a)neratec.com> Tested-by: Tim Fletcher <tim(a)night-shade.org.uk> --- MAINTAINERS | 1 + board/iomega/iconnect/Makefile | 43 ++++++++++ board/iomega/iconnect/iconnect.c | 107 +++++++++++++++++++++++ board/iomega/iconnect/iconnect.h | 39 +++++++++ board/iomega/iconnect/kwbimage.cfg | 165 ++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/iconnect.h | 131 ++++++++++++++++++++++++++++ 7 files changed, 487 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fd0c65c..9e9d8d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -787,6 +787,7 @@ Linus Walleij <linus.walleij(a)linaro.org> Luka Perkov <uboot(a)lukaperkov.net> ib62x0 ARM926EJS + iconnect ARM926EJS Dave Peverley <dpeverley(a)mpc-data.co.uk> diff --git a/board/iomega/iconnect/Makefile b/board/iomega/iconnect/Makefile new file mode 100644 index 0000000..f77fcfb --- /dev/null +++ b/board/iomega/iconnect/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := iconnect.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c new file mode 100644 index 0000000..6ee3b84 --- /dev/null +++ b/board/iomega/iconnect/iconnect.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2009-2012 + * Wojciech Dubowik <wojciech.dubowik(a)neratec.com> + * Luka Perkov <uboot(a)lukaperkov.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include "iconnect.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(ICONNECT_OE_VAL_LOW, + ICONNECT_OE_VAL_HIGH, + ICONNECT_OE_LOW, ICONNECT_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GE1_14, + MPP35_GPIO, + MPP36_AUDIO_SPDIFI, + MPP37_AUDIO_SPDIFO, + MPP38_GPIO, + MPP39_TDM_SPI_CS0, + MPP40_TDM_SPI_SCK, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} diff --git a/board/iomega/iconnect/iconnect.h b/board/iomega/iconnect/iconnect.h new file mode 100644 index 0000000..2fb3e5e --- /dev/null +++ b/board/iomega/iconnect/iconnect.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2009-2012 + * Wojciech Dubowik <wojciech.dubowik(a)neratec.com> + * Luka Perkov <uboot(a)lukaperkov.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __ICONNECT_H +#define __ICONNECT_H + +#define ICONNECT_OE_LOW (~(1 << 7)) +#define ICONNECT_OE_HIGH (~(1 << 10)) +#define ICONNECT_OE_VAL_LOW (0) +#define ICONNECT_OE_VAL_HIGH (1 << 10) + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __ICONNECT_H */ diff --git a/board/iomega/iconnect/kwbimage.cfg b/board/iomega/iconnect/kwbimage.cfg new file mode 100644 index 0000000..6c9dfe3 --- /dev/null +++ b/board/iomega/iconnect/kwbimage.cfg @@ -0,0 +1,165 @@ +# +# (C) Copyright 2009-2012 +# Wojciech Dubowik <wojciech.dubowik(a)neratec.com> +# Luka Perkov <uboot(a)lukaperkov.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xffd100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xffd01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30, (3120 DDR2 clks refresh rate) +# bit23-14: 0x0, +# bit24: 0x1, enable exit self refresh mode on DDR access +# bit25: 0x1, required +# bit29-26: 0x0, +# bit31-30: 0x1, + +DATA 0xffd01404 0x37543000 # DDR Controller Control Low +# bit4: 0x0, addr/cmd in smame cycle +# bit5: 0x0, clk is driven during self refresh, we don't care for APX +# bit6: 0x0, use recommended falling edge of clk for addr/cmd +# bit14: 0x0, input buffer always powered up +# bit18: 0x1, cpu lock transaction enabled +# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 0x3, required +# bit31: 0x0, no additional STARTBURST delay + +DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11-8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xffd0140c 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: 0x0, required + +DATA 0xffd01410 0x000000cc # DDR Address Control +# bit1-0: 00, Cs0width (x8) +# bit3-2: 11, Cs0size (1Gb) +# bit5-4: 00, Cs1width (x8) +# bit7-6: 11, Cs1size (1Gb) +# bit9-8: 00, Cs2width (nonexistent) +# bit11-10: 00, Cs2size (nonexistent) +# bit13-12: 00, Cs3width (nonexistent) +# bit15-14: 00, Cs3size (nonexistent) +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0x0, required + +DATA 0xffd01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0x0, required + +DATA 0xffd01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0x0, required + +DATA 0xffd0141c 0x00000c52 # DDR Mode +# bit2-0: 0x2, BurstLen=2 required +# bit3: 0x0, BurstType=0 required +# bit6-4: 0x4, CL=5 +# bit7: 0x0, TestMode=0 normal +# bit8: 0x0, DLL reset=0 normal +# bit11-9: 0x6, auto-precharge write recovery ???????????? +# bit12: 0x0, PD must be zero +# bit31-13: 0x0, required + +DATA 0xffd01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 0x0, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 0x0, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0x0, required + +DATA 0xffd01424 0x0000f17f # DDR Controller Control High +# bit2-0: 0x7, required +# bit3: 0x1, MBUS Burst Chop disabled +# bit6-4: 0x7, required +# bit7: 0x0, +# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9: 0x0, no half clock cycle addition to dataout +# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh +# bit15-12: 0xf, required +# bit31-16: 0x0, required + +DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xffd01504 0x0ffffff1 # CS[0]n Size +# bit0: 0x1, Window enabled +# bit1: 0x0, Write Protect disabled +# bit3-2: 0x0, CS0 hit selected +# bit23-4: 0xfffff, required +# bit31-24: 0x0f, Size (i.e. 256MB) + +DATA 0xffd01508 0x00000000 # CS[1]n Base address to 256Mb +DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled + +DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled + +DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) +# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1 +# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xffd01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above +# bit3-2: 0x1, ODT1 active NEVER! +# bit31-4: 0x0, required + +DATA 0xffd0149c 0x0000e803 # CPU ODT Control +DATA 0xffd01480 0x00000001 # DDR Initialization Control +# bit0: 0x1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/boards.cfg b/boards.cfg index 2d36d83..6dd8a05 100644 --- a/boards.cfg +++ b/boards.cfg @@ -140,6 +140,7 @@ enbw_cmc arm arm926ejs enbw_cmc enbw calimain arm arm926ejs calimain omicron davinci pogo_e02 arm arm926ejs - cloudengines kirkwood dns325 arm arm926ejs - d-link kirkwood +iconnect arm arm926ejs - iomega kirkwood lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2 lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h new file mode 100644 index 0000000..c75e751 --- /dev/null +++ b/include/configs/iconnect.h @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2009-2012 + * Wojciech Dubowik <wojciech.dubowik(a)neratec.com> + * Luka Perkov <uboot(a)lukaperkov.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _CONFIG_ICONNECT_H +#define _CONFIG_ICONNECT_H + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING " Iomega iConnect Wireless" + +/* + * High level configuration options + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Machine type + */ +#define CONFIG_MACH_TYPE MACH_TYPE_ICONNECT + + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS +#include <config_cmd_default.h> +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "iconnect => " + +/* + * Environment variables configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x80000 + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part rootfs; " \ + "ubifsmount rootfs; " \ + "ubifsload 0x800000 ${kernel}; " \ + "bootm 0x800000" + +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:" \ + "0x80000@0x0(uboot)," \ + "0x20000@0x80000(uboot_env)," \ + "-@0xa0000(rootfs)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS \ + "kernel=/boot/uImage\0" \ + "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" + +/* + * Ethernet driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 11 +#undef CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +/* + * SATA driver configuration + */ +#ifdef CONFIG_CMD_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /* CONFIG_CMD_IDE */ + +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS + +#endif /* _CONFIG_ICONNECT_H */

1 0

[U-Boot] [PATCH 1/3] mxc_i2c: specify i2c base address in config file
by Troy Kisky 16 Jul '12

16 Jul '12

The following platforms had their config files changed flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd Signed-off-by: Troy Kisky <troy.kisky(a)boundarydevices.com> --- arch/arm/include/asm/arch-mx31/imx-regs.h | 7 +++++++ arch/arm/include/asm/arch-mx35/imx-regs.h | 2 +- drivers/i2c/mxc_i2c.c | 25 ++++--------------------- include/configs/flea3.h | 2 +- include/configs/imx31_phycore.h | 3 ++- include/configs/mx35pdk.h | 2 +- include/configs/mx53ard.h | 2 +- include/configs/mx53evk.h | 2 +- include/configs/mx53smd.h | 2 +- 9 files changed, 19 insertions(+), 28 deletions(-) diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 6454acb..7ddbbd6 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -606,6 +606,13 @@ struct esdc_regs { #define UART4_BASE 0x43FB0000 #define UART5_BASE 0x43FB4000 +#define I2C1_BASE_ADDR 0x43f80000 +#define I2C1_CLK_OFFSET 26 +#define I2C2_BASE_ADDR 0x43F98000 +#define I2C2_CLK_OFFSET 28 +#define I2C3_BASE_ADDR 0x43f84000 +#define I2C3_CLK_OFFSET 30 + #define ESDCTL_SDE (1 << 31) #define ESDCTL_CMD_RW (0 << 28) #define ESDCTL_CMD_PRECHARGE (1 << 28) diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index e570ad1..3146006 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -39,7 +39,7 @@ #define MAX_BASE_ADDR 0x43F04000 #define EVTMON_BASE_ADDR 0x43F08000 #define CLKCTL_BASE_ADDR 0x43F0C000 -#define I2C_BASE_ADDR 0x43F80000 +#define I2C1_BASE_ADDR 0x43F80000 #define I2C3_BASE_ADDR 0x43F84000 #define ATA_BASE_ADDR 0x43F8C000 #define UART1_BASE 0x43F90000 diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index c88ac7c..416ffee 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -59,27 +59,10 @@ struct mxc_i2c_regs { #define I2SR_IIF (1 << 1) #define I2SR_RX_NO_AK (1 << 0) -#if defined(CONFIG_SYS_I2C_MX31_PORT1) -#define I2C_BASE 0x43f80000 -#define I2C_CLK_OFFSET 26 -#elif defined (CONFIG_SYS_I2C_MX31_PORT2) -#define I2C_BASE 0x43f98000 -#define I2C_CLK_OFFSET 28 -#elif defined (CONFIG_SYS_I2C_MX31_PORT3) -#define I2C_BASE 0x43f84000 -#define I2C_CLK_OFFSET 30 -#elif defined(CONFIG_SYS_I2C_MX53_PORT1) -#define I2C_BASE I2C1_BASE_ADDR -#elif defined(CONFIG_SYS_I2C_MX53_PORT2) -#define I2C_BASE I2C2_BASE_ADDR -#elif defined(CONFIG_SYS_I2C_MX35_PORT1) -#define I2C_BASE I2C_BASE_ADDR -#elif defined(CONFIG_SYS_I2C_MX35_PORT2) -#define I2C_BASE I2C2_BASE_ADDR -#elif defined(CONFIG_SYS_I2C_MX35_PORT3) -#define I2C_BASE I2C3_BASE_ADDR +#ifdef CONFIG_SYS_I2C_BASE +#define I2C_BASE CONFIG_SYS_I2C_BASE #else -#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver" +#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" #endif #define I2C_MAX_TIMEOUT 10000 @@ -114,7 +97,7 @@ static uint8_t i2c_imx_get_clk(unsigned int rate) (struct clock_control_regs *)CCM_BASE; /* start the required I2C clock */ - writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET), + writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), &sc_regs->cgr0); #endif diff --git a/include/configs/flea3.h b/include/configs/flea3.h index f046a58..75330c4 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -68,7 +68,7 @@ */ #define CONFIG_HARD_I2C #define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_MX35_PORT3 +#define CONFIG_SYS_I2C_BASE I2C3_BASE_ADDR #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0xfe #define CONFIG_MXC_SPI diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 3153eb5..197cefa 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -54,7 +54,8 @@ #define CONFIG_HARD_I2C #define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_MX31_PORT2 +#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR +#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0xfe diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index de4b954..dfe39b8 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -59,7 +59,7 @@ */ #define CONFIG_HARD_I2C #define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_MX35_PORT1 +#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0xfe #define CONFIG_MXC_SPI diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index f48a41e..0bdf6a3 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -50,7 +50,7 @@ #define CONFIG_CMD_I2C #define CONFIG_HARD_I2C #define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_MX53_PORT2 +#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0xfe diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index a77e5b2..3c7c329 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -53,7 +53,7 @@ #define CONFIG_CMD_I2C #define CONFIG_HARD_I2C #define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_MX53_PORT2 1 +#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0xfe diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index a04db3f..a904130 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -50,7 +50,7 @@ #define CONFIG_CMD_I2C #define CONFIG_HARD_I2C #define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_MX53_PORT2 +#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0xfe -- 1.7.5.4

7 19

[U-Boot] [PATCH v2 0/4] mmc: Support designWare Controller
by Jaehoon Chung 16 Jul '12

16 Jul '12

Include mmc:dw-mmc:support DesignWare MMC controller at this patchset. dw-mmc.c is generic interface.(like sdhci.c) For using dw-mmc controller, need to add the some samsung specific code. Exynos specific code should be presented into exynos_dw_mmc.c If want to use with exynos5, must enable the dw-mmc.c. Changelog v2: - Fixed the wrong argument for exynos_dwmci_init() - Added CONFIG_DWMMC/CONFIG_EXYNOS_DWMMC at Makefile - Changed host->mmc_clk instead of host->get_mmc_clk - removed hard-coding value : if need, we can set to host->fifoth_val Jaehoon Chung (4): mmc: dw-mmc: support DesignWare MMC Controller EXYNOS: clock: add the get_mmc_clk function EXYNOS: mmc: support DesignWare Controller for Samsung-SoC mmc: dw-mmc: add dw-mmc's confiuration at Makefile arch/arm/cpu/armv7/exynos/clock.c | 78 ++++++ arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/dwmmc.h | 36 +++ drivers/mmc/Makefile | 3 + drivers/mmc/dw_mmc.c | 400 ++++++++++++++++++++++++++++++ drivers/mmc/exynos_dw_mmc.c | 58 +++++ include/dwmmc.h | 186 ++++++++++++++ 7 files changed, 762 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/dwmmc.h create mode 100644 drivers/mmc/dw_mmc.c create mode 100644 drivers/mmc/exynos_dw_mmc.c create mode 100644 include/dwmmc.h

2 2